From bfe4dd60330cc498a865f759417cf416e1cefe68 Mon Sep 17 00:00:00 2001 From: Dmitry Akimov Date: Mon, 6 Jul 2026 14:31:59 +0300 Subject: [PATCH] # Phase 5 - alpha-pyinstaller packed version of service-tui (Win tested) --- ...3bd2c585b0f4821__mypyc.cp313-win_amd64.pyd | Bin 0 -> 218624 bytes .../service_tui/_internal/_asyncio.pyd | Bin 0 -> 72928 bytes .../service_tui/_internal/_bz2.pyd | Bin 0 -> 86752 bytes .../_cffi_backend.cp313-win_amd64.pyd | Bin 0 -> 180224 bytes .../service_tui/_internal/_ctypes.pyd | Bin 0 -> 134368 bytes .../service_tui/_internal/_decimal.pyd | Bin 0 -> 286432 bytes .../service_tui/_internal/_hashlib.pyd | Bin 0 -> 69344 bytes .../service_tui/_internal/_lzma.pyd | Bin 0 -> 159456 bytes .../_internal/_multiprocessing.pyd | Bin 0 -> 38112 bytes .../service_tui/_internal/_overlapped.pyd | Bin 0 -> 57568 bytes .../service_tui/_internal/_queue.pyd | Bin 0 -> 35552 bytes .../_ruamel_yaml.cp313-win_amd64.pyd | Bin 0 -> 266240 bytes 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+AppFrame { + width: 100%; + height: 100%; + max-width: 112; + max-height: 40; + border: heavy $primary; + background: $surface; + padding: 1 2; +} + +/* ── WaitingScreen ──────────────────────────────────────── */ + +#waiting-frame { + align: center top; +} + +#waiting-logo-row { + width: 100%; + height: auto; + margin-top: 1; +} + +#waiting-logo-art { + width: auto; +} + +#waiting-version-row { + width: 100%; + height: auto; + margin-top: 1; +} + +#waiting-version { + color: $warning; + text-style: bold; + text-align: center; + margin-bottom: 1; +} +#waiting-reason { + margin-top: 1; + padding: 1 2; + border: round $warning; + color: $warning; + text-style: bold; + content-align: center middle; +} + +#waiting-reason.hidden { + display: none; +} + +#waiting-hint { + margin-top: 2; + color: $text-muted; + content-align: center middle; +} + +#waiting-spinner { + margin-top: 1; + color: $accent; + content-align: center middle; +} + +/* ── FlashScreen ────────────────────────────────────────── */ + +#flash-title { + text-style: bold; + color: $warning; + margin-bottom: 1; +} + +#flash-target-group { + border: round $panel; + padding: 1 2; + margin-bottom: 1; + height: auto; + max-height: 18; + overflow-y: auto; +} + +#flash-target-group .section-title { + text-style: bold; + color: $text-muted; + padding: 0 0 1 0; +} + +#flash-custom-group { + margin-top: 1; + height: auto; +} + +#flash-custom-group.hidden { + display: none; +} + +#flash-custom-select, +#flash-fcb-select { + width: 1fr; + margin-bottom: 1; +} + +#flash-dcd-row { + height: auto; + align: left middle; + margin-top: 1; +} + +#flash-dcd-switch { + margin-right: 1; +} + +#flash-btn-row { + height: auto; + margin-top: 1; + align: left middle; +} + +#flash-btn-flash, +#flash-btn-erase { + margin-right: 2; +} + +#flash-btn-flash:disabled, +#flash-btn-erase:disabled, +#flash-btn-quit:disabled { + background: $panel; + color: $text-muted; +} + +#flash-progress-bar { + margin-top: 1; +} + +#flash-progress-bar.hidden { + display: none; +} + +#flash-log { + height: 1fr; + min-height: 6; + margin-top: 1; + border: round $panel; + background: $surface-darken-1; + overflow-y: auto; +} + +/* ── PostFlashScreen ────────────────────────────────────── */ + +#post-flash-frame { + align: center middle; +} + +#post-flash-title { + text-style: bold; + color: $success; + content-align: center middle; + margin-bottom: 2; +} + +#post-flash-instruction { + border: round $warning; + padding: 1 3; + color: $text; + text-style: bold; + content-align: center middle; + width: auto; +} + +#post-flash-countdown { + margin-top: 2; + color: $text-muted; + content-align: center middle; +} + +#post-flash-btn-row { + margin-top: 2; + height: auto; + align: center middle; +} + +#post-flash-btn-ok { + margin-right: 2; +} + +#post-flash-title-row, +#post-flash-instruction-row { + width: 100%; + height: auto; +} +/* ── DiagScreen ─────────────────────────────────────────── */ + +#diag-frame { + layout: vertical; + padding: 0; +} + +#diag-header { + height: 3; + background: $panel; + padding: 0 2; + align: left middle; +} + +#diag-header-fw { + width: auto; + min-width: 14; + color: $text-muted; + margin-right: 3; +} + +#diag-header-uid { + width: auto; + min-width: 28; + color: $text-muted; + margin-right: 3; +} + +#diag-header-m5 { + width: auto; + color: $success; +} + +#diag-header-m5.m5-absent { + color: $text-muted; +} + +#diag-main { + height: 1fr; + min-height: 10; +} + +#diag-progress-row { + height: auto; + padding: 0 2; +} + +#diag-progress-row.hidden { + display: none; +} + +#diag-progress-bar { + height: 1; + margin-top: 1; +} + +#diag-progress-label { + height: 1; + color: $text-muted; +} + +#diag-btn-row { + height: 3; + align: left middle; + padding: 0 2; + background: $panel; +} + +#diag-btn-run-selected, +#diag-btn-run-all { + margin-right: 2; +} + +#diag-btn-run-selected:disabled, +#diag-btn-run-all:disabled { + background: $panel; + color: $text-muted; +} + +/* ── TestListPanel ──────────────────────────────────────── */ + +TestListPanel { + width: 38; + border-right: solid $panel; + padding: 1 1; + overflow-y: auto; +} + +TestListPanel .section-title { + text-style: bold; + color: $text-muted; + padding: 0 0 1 0; +} + +#test-list-select-row { + height: auto; + margin-bottom: 1; +} + +#test-list-select-row Button { + margin-right: 1; + min-width: 12; +} + +.test-row { + height: auto; + align: left middle; +} + +.test-row-hil-badge { + width: 6; + color: $accent; +} + +.test-row-hil-badge.hil-disabled { + color: $text-muted; +} + +/* ── ResultsPanel ───────────────────────────────────────── */ + +ResultsPanel { + width: 70; + padding: 1 2; + overflow-y: auto; +} + +ResultsPanel .section-title { + text-style: bold; + color: $text-muted; + padding: 0 0 1 0; +} + +#results-empty { + height: 1fr; + width: 100%; +} + +#results-empty.hidden { + display: none; +} + +#results-empty-text { + color: $text-muted; + text-align: center; +} + +#results-table { + height: auto; + max-height: 100%; +} + +#results-table.hidden { + display: none; +} + +/* ── ConfirmPanel ───────────────────────────────────────── */ + +ConfirmPanel { + height: auto; + background: $warning 15%; + border-top: solid $warning; + padding: 1 2; + align: left middle; +} + +ConfirmPanel.hidden { + display: none; +} + +#confirm-prompt { + width: 1fr; + color: $warning; + text-style: bold; +} + +#confirm-countdown { + color: $text-muted; + margin-right: 2; +} + +#confirm-btn-ok { + margin-right: 1; +} + +#confirm-btn-ok.hidden, +#confirm-btn-fail.hidden { + display: none; +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/base_library.zip b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/base_library.zip new file mode 100644 index 0000000000000000000000000000000000000000..7ff415b1f5584634c5ad359f15eb7f61a742004d GIT binary patch literal 1409329 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z#W~>3fC*IUs~7N~i5~)#@N*&Ya{;SNoZuZM-UPVC#0frZ;*S9S7Ih)+3IrXvw2~cy z6(&wFYT^o@j!Hf=+72i%U@2%I3k83_CU;9uZQ zbr1OXe!yNujR0r3SJ6GP12{pt2Ufs7LAoOnPLS?*gcGE@*a6@KccD7S&i{C^h`T+) z&^6UG?tfr7e+M5wxH675x|csZRY_1)%Q}Jq`$jn$!vR{oU{R@afn5&y!mT*9s~4 +Requires-Python: >=3.10 +Description-Content-Type: text/markdown +License-Expression: BSD-3-Clause +Classifier: Development Status :: 5 - Production/Stable +Classifier: Intended Audience :: Developers +Classifier: Operating System :: OS Independent +Classifier: Programming Language :: Python +Classifier: Typing :: Typed +License-File: LICENSE.txt +Requires-Dist: colorama; platform_system == 'Windows' +Project-URL: Changes, https://click.palletsprojects.com/page/changes/ +Project-URL: Chat, https://discord.gg/pallets +Project-URL: Documentation, https://click.palletsprojects.com/ +Project-URL: Donate, https://palletsprojects.com/donate +Project-URL: Source, https://github.com/pallets/click/ + +

+ +# Click + +Click is a Python package for creating beautiful command line interfaces +in a composable way with as little code as necessary. It's the "Command +Line Interface Creation Kit". It's highly configurable but comes with +sensible defaults out of the box. + +It aims to make the process of writing command line tools quick and fun +while also preventing any frustration caused by the inability to +implement an intended CLI API. + +Click in three points: + +- Arbitrary nesting of commands +- Automatic help page generation +- Supports lazy loading of subcommands at runtime + + +## A Simple Example + +```python +import click + +@click.command() +@click.option("--count", default=1, help="Number of greetings.") +@click.option("--name", prompt="Your name", help="The person to greet.") +def hello(count, name): + """Simple program that greets NAME for a total of COUNT times.""" + for _ in range(count): + click.echo(f"Hello, {name}!") + +if __name__ == '__main__': + hello() +``` + +``` +$ python hello.py --count=3 +Your name: Click +Hello, Click! +Hello, Click! +Hello, Click! +``` + + +## Donate + +The Pallets organization develops and supports Click and other popular +packages. In order to grow the community of contributors and users, and +allow the maintainers to devote more time to the projects, [please +donate today][]. + +[please donate today]: https://palletsprojects.com/donate + +## Contributing + +See our [detailed contributing documentation][contrib] for many ways to +contribute, including reporting issues, requesting features, asking or answering +questions, and making PRs. + +[contrib]: https://palletsprojects.com/contributing/ + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/RECORD new file mode 100644 index 0000000..3746bb1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/RECORD @@ -0,0 +1,24 @@ +click-8.4.2.dist-info/INSTALLER,sha256=5hhM4Q4mYTT9z6QB6PGpUAW81PGNFrYrdXMj4oM_6ak,2 +click-8.4.2.dist-info/METADATA,sha256=GUyd2B1Wf5CB8CbH5AEGD7r6e8FHyOClizZotApkwDE,2621 +click-8.4.2.dist-info/RECORD,, +click-8.4.2.dist-info/REQUESTED,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 +click-8.4.2.dist-info/WHEEL,sha256=G2gURzTEtmeR8nrdXUJfNiB3VYVxigPQ-bEQujpNiNs,82 +click-8.4.2.dist-info/licenses/LICENSE.txt,sha256=morRBqOU6FO_4h9C9OctWSgZoigF2ZG18ydQKSkrZY0,1475 +click/__init__.py,sha256=FId2fXCSJB3yeWD-e2uON-mBhFa2Yc9MvXGmHu8OXG0,4634 +click/_compat.py,sha256=gPNtXQ9q-G6Qil2b-MC5CsHsGGcQ4u6YSWy9_tlmuhc,18879 +click/_termui_impl.py,sha256=CGdg24AeXijeGSzbu0Z7x3c4aaahVFjVBpEbbjhQ5K4,31730 +click/_textwrap.py,sha256=7Z0N7Vmn-66TNSTUwp6OXJbcUXRmYET9h9c2ucD8oQQ,6270 +click/_utils.py,sha256=eCZCtwJtsYD5QYkkNWJ8MY_8ABIjy8MczgMMyVY32rQ,996 +click/_winconsole.py,sha256=KSxfNbMlYRa6GOJuCLgsg2Pb3dVkgJNPqLJPae-Pa10,8543 +click/core.py,sha256=rZz76ihNTFV4Y2sxp3H-m93GxL2acD5Pqs0IobEvmuk,140616 +click/decorators.py,sha256=9e1Ndu4jhGAcP6RGdNPAwAWtuP9hEs4ETp1u3lKmH1o,19709 +click/exceptions.py,sha256=HvSY34G4auj_bYRR8-T8CU8Jwq_1-OcsRU4ezfozeEk,11862 +click/formatting.py,sha256=8SW2KGkvjfz9Q1NbeojMHuZBN0cfnQJDs4mqDP6oXms,10444 +click/globals.py,sha256=gM-Nh6A4M0HB_SgkaF5M4ncGGMDHc_flHXu9_oh4GEU,1923 +click/parser.py,sha256=oJ-fU_3mvxugIuNtHaCATZ56lgEmHRggjJiSqEgYrjA,19052 +click/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 +click/shell_completion.py,sha256=5tGGY5pV3mAZ17xT23OnuKrWqzEyyLVtrJ30npUxjkU,22618 +click/termui.py,sha256=Vn9ehmrQl92z2_6R4bVZOsHUI6j8LrT8u0RzNZUpCvY,33213 +click/testing.py,sha256=S9I-pspAlJH3RvZJWDQoJXb-M0nrAEJzXcUzrVXsT34,26458 +click/types.py,sha256=9G4DB-nBj-omA_XWsYwbQ3H9BkpH82wJj-kxIPScKmA,44788 +click/utils.py,sha256=XwrDxOzU__rnHn-rvJmJcD7ecbypUKMeDJQRjN2F-OA,20942 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/REQUESTED b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/REQUESTED new file mode 100644 index 0000000..e69de29 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/WHEEL b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/WHEEL new file mode 100644 index 0000000..d8b9936 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/WHEEL @@ -0,0 +1,4 @@ +Wheel-Version: 1.0 +Generator: flit 3.12.0 +Root-Is-Purelib: true +Tag: py3-none-any diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/licenses/LICENSE.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/licenses/LICENSE.txt new file mode 100644 index 0000000..d12a849 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/click-8.4.2.dist-info/licenses/LICENSE.txt @@ -0,0 +1,28 @@ +Copyright 2014 Pallets + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. 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+Classifier: Intended Audience :: Developers +Classifier: Natural Language :: English +Classifier: Operating System :: MacOS :: MacOS X +Classifier: Operating System :: POSIX +Classifier: Operating System :: POSIX :: BSD +Classifier: Operating System :: POSIX :: Linux +Classifier: Operating System :: Microsoft :: Windows +Classifier: Programming Language :: Python +Classifier: Programming Language :: Python :: 3 +Classifier: Programming Language :: Python :: 3 :: Only +Classifier: Programming Language :: Python :: 3.8 +Classifier: Programming Language :: Python :: 3.9 +Classifier: Programming Language :: Python :: 3.10 +Classifier: Programming Language :: Python :: 3.11 +Classifier: Programming Language :: Python :: 3.12 +Classifier: Programming Language :: Python :: 3.13 +Classifier: Programming Language :: Python :: 3.14 +Classifier: Programming Language :: Python :: Implementation :: CPython +Classifier: Programming Language :: Python :: Implementation :: PyPy +Classifier: Programming Language :: Python :: Free Threading :: 3 - Stable +Classifier: Topic :: Security :: Cryptography +Requires-Dist: cffi>=1.14 ; python_full_version == '3.8.*' and platform_python_implementation != 'PyPy' +Requires-Dist: cffi>=2.0.0 ; python_full_version >= '3.9' and platform_python_implementation != 'PyPy' +Requires-Dist: typing-extensions>=4.13.2 ; python_full_version < '3.11' +Requires-Dist: bcrypt>=3.1.5 ; extra == 'ssh' +Requires-Dist: nox[uv]>=2024.4.15 ; extra == 'nox' +Requires-Dist: cryptography-vectors==46.0.7 ; extra == 'test' +Requires-Dist: pytest>=7.4.0 ; extra == 'test' +Requires-Dist: pytest-benchmark>=4.0 ; extra == 'test' +Requires-Dist: pytest-cov>=2.10.1 ; extra == 'test' +Requires-Dist: pytest-xdist>=3.5.0 ; extra == 'test' +Requires-Dist: pretend>=0.7 ; extra == 'test' +Requires-Dist: certifi>=2024 ; extra == 'test' +Requires-Dist: pytest-randomly ; extra == 'test-randomorder' +Requires-Dist: sphinx>=5.3.0 ; extra == 'docs' +Requires-Dist: sphinx-rtd-theme>=3.0.0 ; extra == 'docs' +Requires-Dist: sphinx-inline-tabs ; extra == 'docs' +Requires-Dist: pyenchant>=3 ; extra == 'docstest' +Requires-Dist: readme-renderer>=30.0 ; extra == 'docstest' +Requires-Dist: sphinxcontrib-spelling>=7.3.1 ; extra == 'docstest' +Requires-Dist: build>=1.0.0 ; extra == 'sdist' +Requires-Dist: ruff>=0.11.11 ; extra == 'pep8test' +Requires-Dist: mypy>=1.14 ; extra == 'pep8test' +Requires-Dist: check-sdist ; extra == 'pep8test' +Requires-Dist: click>=8.0.1 ; extra == 'pep8test' +Provides-Extra: ssh +Provides-Extra: nox +Provides-Extra: test +Provides-Extra: test-randomorder +Provides-Extra: docs +Provides-Extra: docstest +Provides-Extra: sdist +Provides-Extra: pep8test +License-File: LICENSE +License-File: LICENSE.APACHE +License-File: LICENSE.BSD +Summary: cryptography is a package which provides cryptographic recipes and primitives to Python developers. +Author-email: The Python Cryptographic Authority and individual contributors +License-Expression: Apache-2.0 OR BSD-3-Clause +Requires-Python: >=3.8, !=3.9.0, !=3.9.1 +Description-Content-Type: text/x-rst; charset=UTF-8 +Project-URL: homepage, https://github.com/pyca/cryptography +Project-URL: documentation, https://cryptography.io/ +Project-URL: source, https://github.com/pyca/cryptography/ +Project-URL: issues, https://github.com/pyca/cryptography/issues +Project-URL: changelog, https://cryptography.io/en/latest/changelog/ + +pyca/cryptography +================= + +.. image:: https://img.shields.io/pypi/v/cryptography.svg + :target: https://pypi.org/project/cryptography/ + :alt: Latest Version + +.. image:: https://readthedocs.org/projects/cryptography/badge/?version=latest + :target: https://cryptography.io + :alt: Latest Docs + +.. image:: https://github.com/pyca/cryptography/actions/workflows/ci.yml/badge.svg + :target: https://github.com/pyca/cryptography/actions/workflows/ci.yml?query=branch%3Amain + +``cryptography`` is a package which provides cryptographic recipes and +primitives to Python developers. Our goal is for it to be your "cryptographic +standard library". It supports Python 3.8+ and PyPy3 7.3.11+. + +``cryptography`` includes both high level recipes and low level interfaces to +common cryptographic algorithms such as symmetric ciphers, message digests, and +key derivation functions. For example, to encrypt something with +``cryptography``'s high level symmetric encryption recipe: + +.. code-block:: pycon + + >>> from cryptography.fernet import Fernet + >>> # Put this somewhere safe! + >>> key = Fernet.generate_key() + >>> f = Fernet(key) + >>> token = f.encrypt(b"A really secret message. Not for prying eyes.") + >>> token + b'...' + >>> f.decrypt(token) + b'A really secret message. Not for prying eyes.' + +You can find more information in the `documentation`_. + +You can install ``cryptography`` with: + +.. code-block:: console + + $ pip install cryptography + +For full details see `the installation documentation`_. + +Discussion +~~~~~~~~~~ + +If you run into bugs, you can file them in our `issue tracker`_. + +We maintain a `cryptography-dev`_ mailing list for development discussion. + +You can also join ``#pyca`` on ``irc.libera.chat`` to ask questions or get +involved. + +Security +~~~~~~~~ + +Need to report a security issue? Please consult our `security reporting`_ +documentation. + + +.. _`documentation`: https://cryptography.io/ +.. _`the installation documentation`: https://cryptography.io/en/latest/installation/ +.. _`issue tracker`: https://github.com/pyca/cryptography/issues +.. _`cryptography-dev`: https://mail.python.org/mailman/listinfo/cryptography-dev +.. _`security reporting`: https://cryptography.io/en/latest/security/ + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/cryptography-46.0.7.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/cryptography-46.0.7.dist-info/RECORD new file mode 100644 index 0000000..8d6b112 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/cryptography-46.0.7.dist-info/RECORD @@ -0,0 +1,109 @@ +cryptography-46.0.7.dist-info/INSTALLER,sha256=5hhM4Q4mYTT9z6QB6PGpUAW81PGNFrYrdXMj4oM_6ak,2 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Python packages +Author-email: "Jason R. Coombs" +License-Expression: Apache-2.0 +Project-URL: Source, https://github.com/python/importlib_metadata +Classifier: Development Status :: 5 - Production/Stable +Classifier: Intended Audience :: Developers +Classifier: Programming Language :: Python :: 3 +Classifier: Programming Language :: Python :: 3 :: Only +Requires-Python: >=3.10 +Description-Content-Type: text/x-rst +License-File: LICENSE +Requires-Dist: zipp>=3.20 +Provides-Extra: test +Requires-Dist: pytest!=8.1.*,>=6; extra == "test" +Requires-Dist: packaging; extra == "test" +Requires-Dist: pyfakefs; extra == "test" +Requires-Dist: pytest-perf>=0.9.2; extra == "test" +Provides-Extra: doc +Requires-Dist: sphinx>=3.5; extra == "doc" +Requires-Dist: jaraco.packaging>=9.3; extra == "doc" +Requires-Dist: rst.linker>=1.9; extra == "doc" +Requires-Dist: furo; extra == "doc" +Requires-Dist: sphinx-lint; extra == "doc" +Requires-Dist: jaraco.tidelift>=1.4; extra == "doc" +Provides-Extra: perf +Requires-Dist: ipython; extra == "perf" +Provides-Extra: check +Requires-Dist: pytest-checkdocs>=2.14; extra == "check" +Requires-Dist: pytest-ruff>=0.2.1; sys_platform != "cygwin" and extra == "check" +Provides-Extra: cover +Requires-Dist: pytest-cov; extra == "cover" +Provides-Extra: enabler +Requires-Dist: pytest-enabler>=3.4; extra == "enabler" +Provides-Extra: type +Requires-Dist: pytest-mypy>=1.0.1; platform_python_implementation != "PyPy" and extra == "type" +Dynamic: license-file + +.. image:: https://img.shields.io/pypi/v/importlib_metadata.svg + :target: https://pypi.org/project/importlib_metadata + +.. image:: https://img.shields.io/pypi/pyversions/importlib_metadata.svg + +.. image:: https://github.com/python/importlib_metadata/actions/workflows/main.yml/badge.svg + :target: https://github.com/python/importlib_metadata/actions?query=workflow%3A%22tests%22 + :alt: tests + +.. image:: https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/astral-sh/ruff/main/assets/badge/v2.json + :target: https://github.com/astral-sh/ruff + :alt: Ruff + +.. image:: https://readthedocs.org/projects/importlib-metadata/badge/?version=latest + :target: https://importlib-metadata.readthedocs.io/en/latest/?badge=latest + +.. image:: https://img.shields.io/badge/skeleton-2025-informational + :target: https://blog.jaraco.com/skeleton + +.. image:: https://tidelift.com/badges/package/pypi/importlib-metadata + :target: https://tidelift.com/subscription/pkg/pypi-importlib-metadata?utm_source=pypi-importlib-metadata&utm_medium=readme + +Library to access the metadata for a Python package. + +This package supplies third-party access to the functionality of +`importlib.metadata `_ +including improvements added to subsequent Python versions. + + +Compatibility +============= + +New features are introduced in this third-party library and later merged +into CPython. The following table indicates which versions of this library +were contributed to different versions in the standard library: + +.. list-table:: + :header-rows: 1 + + * - importlib_metadata + - stdlib + * - 7.0 + - 3.13 + * - 6.5 + - 3.12 + * - 4.13 + - 3.11 + * - 4.6 + - 3.10 + * - 1.4 + - 3.8 + + +Usage +===== + +See the `online documentation `_ +for usage details. + +`Finder authors +`_ can +also add support for custom package installers. See the above documentation +for details. + + +Caveats +======= + +This project primarily supports third-party packages installed by PyPA +tools (or other conforming packages). It does not support: + +- Packages in the stdlib. +- Packages installed without metadata. + +Project details +=============== + + * Project home: https://github.com/python/importlib_metadata + * Report bugs at: https://github.com/python/importlib_metadata/issues + * Code hosting: https://github.com/python/importlib_metadata + * Documentation: https://importlib-metadata.readthedocs.io/ + +For Enterprise +============== + +Available as part of the Tidelift Subscription. + +This project and the maintainers of thousands of other packages are working with Tidelift to deliver one enterprise subscription that covers all of the open source you use. + +`Learn more `_. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/RECORD new file mode 100644 index 0000000..6f83192 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/RECORD @@ -0,0 +1,20 @@ +importlib_metadata-8.9.0.dist-info/INSTALLER,sha256=5hhM4Q4mYTT9z6QB6PGpUAW81PGNFrYrdXMj4oM_6ak,2 +importlib_metadata-8.9.0.dist-info/METADATA,sha256=571mC1BVj1cZB0nBrwPCK51LVhroM9pG20A8Ulo3y88,4536 +importlib_metadata-8.9.0.dist-info/RECORD,, +importlib_metadata-8.9.0.dist-info/REQUESTED,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 +importlib_metadata-8.9.0.dist-info/WHEEL,sha256=aeYiig01lYGDzBgS8HxWXOg3uV61G9ijOsup-k9o1sk,91 +importlib_metadata-8.9.0.dist-info/licenses/LICENSE,sha256=4ve7BVfno4FJnxW6p8HXdtg9ZhZZkXnXHTEJuOOfeyU,10278 +importlib_metadata-8.9.0.dist-info/top_level.txt,sha256=CO3fD9yylANiXkrMo4qHLV_mqXL2sC5JFKgt1yWAT-A,19 +importlib_metadata/__init__.py,sha256=l0bUNX8-gg5_malNOySP8DLhB1VH5pZnhrQ2kA6I2xc,38000 +importlib_metadata/_adapters.py,sha256=r5i8XLrKT6xmrpoREZhZrfczOYDmrVZeJBW5u0HzIGU,3797 +importlib_metadata/_collections.py,sha256=CxAhzlF3g1rwu_fMiB53JtRQiUFh0RgiMpoOvmK_ocg,760 +importlib_metadata/_compat.py,sha256=VC5ZDLlT-BcshauCShdFJvMNLntJJfZzNK1meGa-enw,1313 +importlib_metadata/_functools.py,sha256=hVPD-xQZF68JXAhQOzDqpsD-gav28Ga0p1T_wDzLuwc,3537 +importlib_metadata/_itertools.py,sha256=nMvp9SfHAQ_JYwK4L2i64lr3GRXGlYlikGTVzWbys_E,5351 +importlib_metadata/_meta.py,sha256=EtHyiJ5kGzWFDfKyQ2XQp6Vu113CeadKW1Vf6aGc1B4,1765 +importlib_metadata/_text.py,sha256=HCsFksZpJLeTP3NEk_ngrAeXVRRtTrtyh9eOABoRP4A,2166 +importlib_metadata/_typing.py,sha256=EQKhhsEgz_Sa-FnePI-faC72rNOOQwopjA1i5pG8FDU,367 +importlib_metadata/compat/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 +importlib_metadata/compat/py311.py,sha256=uqm-K-uohyj1042TH4a9Er_I5o7667DvulcD-gC_fSA,608 +importlib_metadata/diagnose.py,sha256=nkSRMiowlmkhLYhKhvCg9glmt_11Cox-EmLzEbqYTa8,379 +importlib_metadata/py.typed,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/REQUESTED b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/REQUESTED new file mode 100644 index 0000000..e69de29 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/WHEEL b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/WHEEL new file mode 100644 index 0000000..14a883f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/WHEEL @@ -0,0 +1,5 @@ +Wheel-Version: 1.0 +Generator: setuptools (82.0.1) +Root-Is-Purelib: true +Tag: py3-none-any + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/licenses/LICENSE b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/licenses/LICENSE new file mode 100644 index 0000000..7b25cfb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/importlib_metadata-8.9.0.dist-info/licenses/LICENSE @@ -0,0 +1,73 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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0000000..b2c8f31 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyproject.toml @@ -0,0 +1,26 @@ +[project] +name = "service-tui" +version = "0.2.0" +description = "TUI сервисного инженера для диагностики платы MIMXRT1052" +requires-python = ">=3.11" +dependencies = [ + "textual>=0.80.0", + "pyserial>=3.5", + "python-dotenv>=1.0.0", + "pyinstaller>=6.0.0", + "pyusb>=1.0.0", + "spsdk==3.7.0", +] + +[project.scripts] +service-tui = "main:main" + +[tool.uv] +package = false + +[dependency-groups] +dev = ["pytest>=8.0.0"] + +[build-system] +requires = ["hatchling"] +build-backend = "hatchling.build" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/INSTALLER b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/INSTALLER new file mode 100644 index 0000000..5c69047 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/INSTALLER @@ -0,0 +1 @@ +uv \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/METADATA b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/METADATA new file mode 100644 index 0000000..466684c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/METADATA @@ -0,0 +1,110 @@ +Metadata-Version: 2.4 +Name: pyreadline3 +Version: 3.5.6 +Summary: A python implementation of GNU readline. +Author-email: Bassem Girgis , Jorgen Stenarson , Gary Bishop , Jack Trainor +Maintainer-email: Bassem Girgis +License: BSD +Project-URL: Homepage, https://github.com/pyreadline3/pyreadline3 +Project-URL: Documentation, https://github.com/pyreadline3/pyreadline3 +Project-URL: Repository, https://github.com/pyreadline3/pyreadline3.git +Project-URL: Issues, https://github.com/pyreadline3/pyreadline3/issues +Project-URL: Changelog, https://github.com/pyreadline3/pyreadline3/blob/master/doc/ChangeLog +Keywords: readline,pyreadline,pyreadline3 +Classifier: Development Status :: 5 - Production/Stable +Classifier: Environment :: Console +Classifier: Operating System :: Microsoft :: Windows +Classifier: License :: OSI Approved :: BSD License +Classifier: Programming Language :: Python :: 3.8 +Classifier: Programming Language :: Python :: 3.9 +Classifier: Programming Language :: Python :: 3.10 +Classifier: Programming Language :: Python :: 3.11 +Classifier: Programming Language :: Python :: 3.12 +Requires-Python: >=3.8 +Description-Content-Type: text/markdown +License-File: LICENSE.md +Provides-Extra: dev +Requires-Dist: build; extra == "dev" +Requires-Dist: flake8; extra == "dev" +Requires-Dist: mypy; extra == "dev" +Requires-Dist: pytest; extra == "dev" +Requires-Dist: twine; extra == "dev" +Dynamic: license-file + +# pyreadline3 + +[![PyPi Badge](https://img.shields.io/pypi/v/pyreadline3)](https://pypi.org/project/pyreadline3/) +![Publish](https://github.com/pyreadline3/pyreadline3/workflows/Publish/badge.svg) +![Test](https://github.com/pyreadline3/pyreadline3/workflows/Test/badge.svg) +[![Downloads](https://static.pepy.tech/personalized-badge/pyreadline3?period=week&units=international_system&left_color=black&right_color=orange&left_text=Last%20Week)](https://pepy.tech/project/pyreadline3) +[![Downloads](https://static.pepy.tech/personalized-badge/pyreadline3?period=month&units=international_system&left_color=black&right_color=orange&left_text=Month)](https://pepy.tech/project/pyreadline3) +[![Downloads](https://static.pepy.tech/personalized-badge/pyreadline3?period=total&units=international_system&left_color=black&right_color=orange&left_text=Total)](https://pepy.tech/project/pyreadline3) + +The `pyreadline3` package is based on the stale package `pyreadline` located +[here](https://github.com/pyreadline/pyreadline). +The original `pyreadline` package is a Python implementation of GNU `readline` +functionality. +It is based on the `ctypes` based UNC `readline` package by Gary Bishop. +It is not complete. +It has been tested for use with Windows 10. + +Version 3.4+ of pyreadline3 runs on Python 3.8+. + +`pyreadline3` is available on PyPI and can be installed with + + pip install pyreadline3 + +## Features + +- keyboard text selection and copy/paste +- Shift-arrowkeys for text selection +- Control-c can be used for copy activate with allow_ctrl_c(True) in config file +- Double tapping ctrl-c will raise a KeyboardInterrupt, use ctrl_c_tap_time_interval(x) +- where x is your preferred tap time window, default 0.3 s. +- paste pastes first line of content on clipboard. +- ipython_paste, pastes tab-separated data as list of lists or numpy array if all data is numeric +- paste_mulitline_code pastes multi line code, removing any empty lines. + +The latest development version is always available at the project git +[repository](https://github.com/pyreadline3/pyreadline3) + +## Development + +To clone the library for development: + + git clone git@github.com:pyreadline3/pyreadline3.git + +or + + git clone https://github.com/pyreadline3/pyreadline3.git + +### Build The Virtual Environment + +The current earliest Python version supported is `3.8`. You need to be able to create a virtual environment at this version to make sure any changes you make is combatible. + +If you are using `conda`: + + conda create --prefix=.venv python=3.8 --yes + +If you are using `venv`, make sure you have the right base package: + + >> python --version + Python 3.8.x + +Once you verify your base Python, you can then create a virtual environment using: + + virtualenv -p py3.8 .venv + +### Setup + +Once you have created your virtual environment and made sure it is active in your current command line: + + pip install -e .[dev] + +This should all the dependencies you need for developing into the library and also allow you to run the unit tests: + + pytest + +### Debugging + + WIP diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/RECORD new file mode 100644 index 0000000..7e09eaf --- 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mode 100644 index 0000000..14a883f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/WHEEL @@ -0,0 +1,5 @@ +Wheel-Version: 1.0 +Generator: setuptools (82.0.1) +Root-Is-Purelib: true +Tag: py3-none-any + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/licenses/LICENSE.md b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/licenses/LICENSE.md new file mode 100644 index 0000000..73c4548 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/licenses/LICENSE.md @@ -0,0 +1,53 @@ +# LICENSE + +## pyreadline3 copyright and licensing notes + +Unless indicated otherwise, files in this project are covered by a BSD-type +license, included below. + +Individual authors are the holders of the copyright for their code and are +listed in each file. + +Some files may be licensed under different conditions. Ultimately each file +indicates clearly the conditions under which its author/authors have +decided to publish the code. + +## pyreadline3 license + +pyreadline3 is released under a BSD-type license. + +Copyright (c) 2020 Bassem Girgis . + +Copyright (c) 2006-2020 J�rgen Stenarson . + +Copyright (c) 2003-2006 Gary Bishop + +Copyright (c) 2003-2006 Jack Trainor + +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +a. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +b. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +c. Neither the name of the copyright holders nor the names of any + contributors to this software may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +DAMAGE. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/top_level.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/top_level.txt new file mode 100644 index 0000000..437aaa5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/pyreadline3-3.5.6.dist-info/top_level.txt @@ -0,0 +1,2 @@ +pyreadline3 +readline diff --git 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https://img.shields.io/readthedocs/setuptools/latest.svg + :target: https://setuptools.pypa.io + +.. |skeleton-badge| image:: https://img.shields.io/badge/skeleton-2025-informational + :target: https://blog.jaraco.com/skeleton + +.. |codecov-badge| image:: https://img.shields.io/codecov/c/github/pypa/setuptools/master.svg?logo=codecov&logoColor=white + :target: https://codecov.io/gh/pypa/setuptools + +.. |tidelift-badge| image:: https://tidelift.com/badges/github/pypa/setuptools?style=flat + :target: https://tidelift.com/subscription/pkg/pypi-setuptools?utm_source=pypi-setuptools&utm_medium=readme + +.. |discord-badge| image:: https://img.shields.io/discord/803025117553754132 + :target: https://discord.com/channels/803025117553754132/815945031150993468 + :alt: Discord + +|pypi-version| |py-version| |test-badge| |ruff-badge| |docs-badge| |skeleton-badge| |codecov-badge| |discord-badge| + +See the `Quickstart `_ +and the `User's Guide `_ for +instructions on how to use Setuptools. + +Questions and comments should be directed to `GitHub Discussions +`_. +Bug reports and especially tested patches may be +submitted directly to the `bug tracker +`_. + + +Code of Conduct +=============== + +Everyone interacting in the setuptools project's codebases, issue trackers, +chat rooms, and fora is expected to follow the +`PSF Code of Conduct `_. + + +For Enterprise +============== + +Available as part of the Tidelift Subscription. + +Setuptools and the maintainers of thousands of other packages are working with Tidelift to deliver one enterprise subscription that covers all of the open source you use. + +`Learn more `_. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/RECORD new file mode 100644 index 0000000..7b3e150 --- /dev/null +++ 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-0,0 +1,5 @@ +Wheel-Version: 1.0 +Generator: setuptools (80.10.2) +Root-Is-Purelib: true +Tag: py3-none-any + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/entry_points.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/entry_points.txt new file mode 100644 index 0000000..0db0a6c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/entry_points.txt @@ -0,0 +1,51 @@ +[distutils.commands] +alias = setuptools.command.alias:alias +bdist_egg = setuptools.command.bdist_egg:bdist_egg +bdist_rpm = setuptools.command.bdist_rpm:bdist_rpm +bdist_wheel = setuptools.command.bdist_wheel:bdist_wheel +build = setuptools.command.build:build +build_clib = setuptools.command.build_clib:build_clib +build_ext = setuptools.command.build_ext:build_ext +build_py = setuptools.command.build_py:build_py +develop = setuptools.command.develop:develop +dist_info = setuptools.command.dist_info:dist_info +easy_install = setuptools.command.easy_install:easy_install +editable_wheel = setuptools.command.editable_wheel:editable_wheel +egg_info = setuptools.command.egg_info:egg_info +install = setuptools.command.install:install +install_egg_info = setuptools.command.install_egg_info:install_egg_info +install_lib = setuptools.command.install_lib:install_lib +install_scripts = setuptools.command.install_scripts:install_scripts +rotate = setuptools.command.rotate:rotate +saveopts = setuptools.command.saveopts:saveopts +sdist = setuptools.command.sdist:sdist +setopt = setuptools.command.setopt:setopt + +[distutils.setup_keywords] +dependency_links = setuptools.dist:assert_string_list +eager_resources = setuptools.dist:assert_string_list +entry_points = setuptools.dist:check_entry_points +exclude_package_data = setuptools.dist:check_package_data +extras_require = setuptools.dist:check_extras +include_package_data = setuptools.dist:assert_bool +install_requires = setuptools.dist:check_requirements +namespace_packages = setuptools.dist:check_nsp +package_data = setuptools.dist:check_package_data +packages = setuptools.dist:check_packages +python_requires = setuptools.dist:check_specifier +setup_requires = setuptools.dist:check_requirements +use_2to3 = setuptools.dist:invalid_unless_false +zip_safe = setuptools.dist:assert_bool + +[egg_info.writers] +PKG-INFO = setuptools.command.egg_info:write_pkg_info +dependency_links.txt = setuptools.command.egg_info:overwrite_arg +eager_resources.txt = setuptools.command.egg_info:overwrite_arg +entry_points.txt = setuptools.command.egg_info:write_entries +namespace_packages.txt = setuptools.command.egg_info:overwrite_arg +requires.txt = setuptools.command.egg_info:write_requirements +top_level.txt = setuptools.command.egg_info:write_toplevel_names + +[setuptools.finalize_distribution_options] +keywords = setuptools.dist:Distribution._finalize_setup_keywords +parent_finalize = setuptools.dist:_Distribution.finalize_options diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/licenses/LICENSE b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/licenses/LICENSE new file mode 100644 index 0000000..1bb5a44 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/licenses/LICENSE @@ -0,0 +1,17 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to +deal in the Software without restriction, including without limitation the +rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +sell copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +IN THE SOFTWARE. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/top_level.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/top_level.txt new file mode 100644 index 0000000..b5ac107 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools-80.10.2.dist-info/top_level.txt @@ -0,0 +1,3 @@ +_distutils_hack +pkg_resources +setuptools diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools/_vendor/jaraco/text/Lorem ipsum.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools/_vendor/jaraco/text/Lorem ipsum.txt new file mode 100644 index 0000000..986f944 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/setuptools/_vendor/jaraco/text/Lorem ipsum.txt @@ -0,0 +1,2 @@ +Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui officia deserunt mollit anim id est laborum. +Curabitur pretium tincidunt lacus. Nulla gravida orci a odio. Nullam varius, turpis et commodo pharetra, est eros bibendum elit, nec luctus magna felis sollicitudin mauris. Integer in mauris eu nibh euismod gravida. Duis ac tellus et risus vulputate vehicula. Donec lobortis risus a elit. Etiam tempor. Ut ullamcorper, ligula eu tempor congue, eros est euismod turpis, id tincidunt sapien risus a quam. Maecenas fermentum consequat mi. Donec fermentum. Pellentesque malesuada nulla a mi. Duis sapien sem, aliquet nec, commodo eget, consequat quis, neque. Aliquam faucibus, elit ut dictum aliquet, felis nisl adipiscing sapien, sed malesuada diam lacus eget erat. Cras mollis scelerisque nunc. Nullam arcu. Aliquam consequat. Curabitur augue lorem, dapibus quis, laoreet et, pretium ac, nisi. Aenean magna nisl, mollis quis, molestie eu, feugiat in, orci. In hac habitasse platea dictumst. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/apps/README.md b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/apps/README.md new file mode 100644 index 0000000..e97e639 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/apps/README.md @@ -0,0 +1,26 @@ +# SPSDK Applications + +After installing SPSDK, several applications are present directly on PATH as executables. + +- [spsdk](spsdk_apps.py) - entry point for all available applications. +- [blhost](blhost.py) - console script for MBoot module. +- [dk6prog](dk6prog.py) - utility for DK6 Programming tool. +- [nxpcrypto](nxpcrypto.py) - utility for generating/verifying RSA/ECC key pairs, and converting key file format (PEM/DER/RAW). +- [nxpdebugmbox](nxpdebugmbox.py) - utility for performing the Debug Authentication. +- [nxpdevhsm](nxpdevhsm.py) - utility for generating initialization SB file. +- [nxpdevscan](nxpdevscan.py) - utility for listing all connected NXP USB and UART devices. +- [nxpele](nxpele.py) - utility for communication with NXP EdgeLock Enclave. +- [nxpimage](nxpimage.py) - utility for generating TrustZone, MasterBootImage and SecureBinary images. +- [pfr](pfr.py) - simple utility for creation and analysis of protected regions(PFR /IFR) - CMPA, CFPA, ROMCFG and CMACTABLE. +- [sdphost](sdphost.py) - console script for SDP module. +- [sdpshost](sdpshost.py) - console script for SDPS module. +- [shadowregs](shadowregs.py) - utility for Shadow Registers controlling. +- [tpconfig](tpconfig.py) - utility for Trust provisioning config application. +- [tphost](tphost.py) - utility for Trust provisioning host application. + + +`` spsdk --help`` - lists all available commands. + +`` spsdk --help`` - print help for given application. + +`` spsdk --help `` - print help for given command. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/certgen_config.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/certgen_config.yaml new file mode 100644 index 0000000..cf33de8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/certgen_config.yaml @@ -0,0 +1,65 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# This is template for configuration file used for generating certificates + +# ============================================== +# Issuer identification fields +# ============================================== +# All available option can be found within class NameOID in +# cryptography/src/cryptography/x509/oid.py at https://github.com/pyca/cryptography + +issuer: + COMMON_NAME: NXP + COUNTRY_NAME: CZ + LOCALITY_NAME: Roznov pod Radhostem + STATE_OR_PROVINCE_NAME: Morava + STREET_ADDRESS: 1.maje 1009 + ORGANIZATION_NAME: SPSDK Team + +# ============================================== +# Subject identification fields +# ============================================== +# All available option can be found within class NameOID in +# cryptography/src/cryptography/x509/oid.py at https://github.com/pyca/cryptography +subject: + COMMON_NAME: NXP - SPSDK + COUNTRY_NAME: CZ + LOCALITY_NAME: Roznov pod Radhostem + STATE_OR_PROVINCE_NAME: Morava + STREET_ADDRESS: 1.maje 1009 + ORGANIZATION_NAME: SPSDK Team + POSTAL_CODE: 756 61 + +# ============================================== +# The certificate settings +# ============================================== + +# Path, where issuer private key is stored +# If the issuer_private_key is encrypted, the interactive prompt will ask for password +# For loading the password in non-interactive way, the configuration parameter 'issuer_private_key_password' can be used. +# There are multiple formats of issuer_private_key_password values: +# 1. If the value is an existing path, first line of file is read and returned +# 2. If the value has format '$ENV_VAR', the value of environment variable ENV_VAR is returned +# 3. If the value has format '$ENV_VAR' and the value contains a valid path to a file, the first line of a file is returned +# 4. If the value does not match any options above, the input value itself is returned +issuer_private_key: issuer_key.pem +# Use PSS padding in case of RSA private key +pss_padding: false +# Path, where subject public key is stored +subject_public_key: subject_key.pub +# Serial number of certificate +serial_number: 12346578 +# Validity duration in days +duration: 3650 + +# ============================================== +# Certificate basic extensions +# ============================================== +extensions: + BASIC_CONSTRAINTS: + # Delegate certificate as a signing authority to create an intermediate certificates. + ca: false # Valid values true|false + # Integer length of the path of certificate signature from a given certificate, back to the root certificate + path_length: diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/oscca.asn b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/oscca.asn new file mode 100644 index 0000000..1c513cf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/oscca.asn @@ -0,0 +1,27 @@ +-- Definition derived from openssl 3.0 + +OSCCA DEFINITIONS ::= BEGIN + + Signature ::= SEQUENCE { + r INTEGER, + s INTEGER + } + + KeySet ::= SEQUENCE { + number INTEGER, + prk OCTET STRING, + puk [1] EXPLICIT BIT STRING + } + + Private ::= SEQUENCE { + number INTEGER, + ids SEQUENCE OF OBJECT IDENTIFIER, + keyset OCTET STRING + } + + Public ::= SEQUENCE { + ids SEQUENCE OF OBJECT IDENTIFIER, + puk BIT STRING + } + +END diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/ultimaco_puk.asn b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/ultimaco_puk.asn new file mode 100644 index 0000000..ecff837 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/crypto/ultimaco_puk.asn @@ -0,0 +1,25 @@ +-- Definition based on OTPS HSM implementation +-- To generate Python code use 'asn1ate' with pyparsing<3 + +OTPS DEFINITIONS ::= BEGIN + + AlgorithmIdentifier ::= SEQUENCE { + algorithm OBJECT IDENTIFIER, + parameters ANY DEFINED BY algorithm OPTIONAL + } + + SubjectPublicKeyInfo ::= SEQUENCE { + algorithm AlgorithmIdentifier, + subjectPublicKey BIT STRING + } + + IdentifiedSubjectPublicKeyInfo ::= SEQUENCE { + identifier [0] IMPLICIT IA5String, + version [1] IMPLICIT INTEGER, + typeName [2] IMPLICIT IA5String, + owner [3] IMPLICIT IA5String OPTIONAL, + usage [4] IMPLICIT INTEGER, + subjectPublicKeyInfo SubjectPublicKeyInfo + } + +END diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/database_defaults.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/database_defaults.yaml new file mode 100644 index 0000000..126b571 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/database_defaults.yaml @@ -0,0 +1,480 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: {} +latest: latest + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: General Purpose Processor + # Web page of MCU representative + web: https://www.nxp.com + memory_map: {} # Memory map basic info + isp: + rom: + protocol: mboot # Possible options:[mboot, sdps, sdp] + interfaces: ["uart", "usb", "spi", "i2c"] + flashloader: {} + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + tool: blhost + + # ======== Fuses description section ======== + fuses: + tool: blhost + reg_spec: fuses.json + grouped_registers: [] + + # ======== Blhost section ======== + blhost: {} + # properties: + # 0: list-properties + # 1: current-version + # 2: available-peripherals + # 3: flash-start-address + # 4: flash-size-in-bytes + # 5: flash-sector-size + # 6: flash-block-count + # 7: available-commands + # 8: check-status + # 9: reserved + # 10: verify-writes + # 11: max-packet-size + # 12: reserved-regions + # 13: reserved_1 + # 14: ram-start-address + # 15: ram-size-in-bytes + # 16: system-device-id + # 17: security-state + # 18: unique-device-id + # 19: flash-fac-support + # 20: flash-access-segment-size + # 21: flash-access-segment-count + # 22: flash-read-margin + # 23: qspi/otfad-init-status + # 24: target-version + # 25: external-memory-attributes + # 26: reliable-update-status + # 27: flash-page-size + # 28: irq-notify-pin + # 29: pfr-keystore-update-opt + # 30: byte-write-timeout-ms + # 31: fuse-locked-status + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + isk_data_alignment: 4 + isk_data_limit: 96 + + # ======== DAT section ======== + dat: + socc: 0 # SOCC identification + based_on_ele: False # Flag if the implementation of DAT is based on EdgeLock Enclave + # famode_cert: [] # List of Fault analysis Mode certificates (names of MBI classes) + # famode_cfg_defaults: {} # Dictionary of default values of standard MBI members for FAmode image + used_beacons_on_ele: False # The DAT ELE implementation is using certificate and authentication beacons + auth_beacon_length: 2 # The length in bytes of authentication beacon + + dmbox_ap_ix: -1 # Typical Index of debug mailbox access port is 2 + mem_ap_ix: -1 # Typical Index of debug mailbox access port is 0 + # non_standard_statuses: # dictionary of non standard return statuses from various commands + # 2: # Command get_crp_level + # 0xFFFF_FFFF: ROP_LEVEL0 + # 0xEEBA_04C3: ROP_LEVEL1 + # 0x4939_8D8B: ROP_LEVEL2 + # 0xB0AB_B703: ROP_LEVEL3 + dac_rot_type: default # Default type is full RKTH/SRK value + + command_delays: # Additional standard command delays per individual DM commands + ERASE_FLASH: 0.5 + + # Memory addresses for SSF certificate data + ssf_cert_memory: + ecdsa_puk_address: 0x0 # Default address for ECDSA PUK (will be overridden by device-specific values) + ecdsa_puk_size: 0x0 # Default size for ECDSA PUK + hybrid_puk_address: 0x0 # Default address for Hybrid PUK + hybrid_puk_size: 0x0 # Default size for Hybrid PUK + + # ======== MBI section ======== + mbi: + mbi_classes: {} + images: {} + + # ======== HABv4 section ======== + hab: {} + + # ======== AHAB section ======== + ahab: + sub_features: [ahab_image] + containers_max_cnt: 2 + oem_images_max_cnt: 8 + valid_offset_minimal_alignment: 4 + container_types: [1] # Supported container types + certificate_type: standard # The standard certificate + iae_has_signed_offsets: False # There is a special cases when the Container is after images + core_ids: {} + image_types: {} + image_types_mapping: {} + allow_empty_hash: False # Some chips allow empty image hash in OEM Open LC + # image_types: Keep it here as a template for new NPI + # CSF: [0x01, csf, CSF Image] + # SCD: [0x02, scd, SCD Image] + # EXECUTABLE: [0x03, executable, Executable Image] + # DATA: [0x04, data, Data Image] + # DCD_IMAGE: [0x05, dcd_image, DCD Image] + # ELE: [0x06, ele, EdgeLock Enclave Image] + # PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + # DEK_VALIDATION_FCB_CHK: [0x08, dek_validation_fcb_chk, DEK validation FCB check Image] + # PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + # EXECUTABLE_FAST_BOOT_IMAGE: [0x0A, executable_fast_boot_image, Executable fast boot Image] + # V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + # V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + # V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + # V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + + double_authentication_load_address: 0 + double_authentication_core_id: 0 + double_authentication_image_type: 0 + + extra_containers: [] + fuses: + _name: "AHAB SRK" + srkh: "__srk_hash" # SRK hash fuse + + # ======== PFR section ======== + pfr: + sub_features: [cmpa, cfpa] + cmpa: + erase_method: write_memory + additional_data: # extra data defined by customer + enabled: False + offset: -1 + max_size: 0 + cfpa: + additional_data: # extra data defined by customer + enabled: False + offset: -1 + max_size: 0 + requires_reset: False + requires_scratch_erase: False + + # ======== Bootable image section ======== + bootable_image: + mem_types: {} + + # ======== FCB section ======== + fcb: + mem_types: {} + + # ======== XMCD section ======== + xmcd: + header: + reg_spec: ../../common/xmcd/flexspi_ram_header.json + mem_types: {} + fuses: {} + + # ======== BEE section ======== + bee: {} + + # ======== IEE section ======== + iee: + key_blob_rec_size: 96 + key_blob_max_cnt: 4 + key_blob_min_cnt: 4 + has_kek_fuses: False + additional_template: [] + additional_template_text: "" + generate_keyblob: True + + # ======== OTFAD section ======== + otfad: + key_blob_rec_size: 64 + key_blob_max_cnt: 4 + key_blob_min_cnt: 4 + byte_swap: false + keyblob_byte_swap_cnt: 0 + sb_21_supported: True + has_kek_fuses: False + additional_template: [] + additional_template_text: "" + supports_key_scrambling: False + reversed_scramble_key: False + + # ======== Secure binary v2.1 section ======== + sb21: + keyblobs: true + supported_commands: [] + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: [] + key_wraps_version: 1 + variable_block_length: false + commands_block_length: 256 + supports_compression: false + command_rules: [] + + # ======== Secure binary v4.0 section ======== + sb40: + supported_commands: [] + key_wraps_version: 2 + variable_block_length: true + commands_block_length: 4096 + supports_compression: true + + # ======== Secure binary vX section ======== + sbx: + commands_block_length: 256 + variable_block_length: false + supported_commands: [] + + # ======== Secure binary c section ======== + sbc: + commands_block_length: 256 + key_wraps_version: 2 + variable_block_length: false + supported_commands: [] + + # ======== Shadow registers section ======== + shadow_regs: + inverted_regs: {} + computed_fields: {} + reset_type: hw_reset # possible options: [hw_reset, nvic_reset] + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsm] + supported_commands: + - erase + - load + - programFuses + - programIFR + - copy + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + flag: 0x1 + key_blob_offset: 0x4 + key_blob_command_position: -1 + devbuff_wrapped_cust_mk_sk_key_size: 0x30 + + # ======== Trust Zone section ======== + tz: + version: v1 # TrustZone configuration version v1.0 + reg_spec: tz.json + + # ======== EdgeLock Enclave section ======== + ele: + ele_device: uboot_fastboot + + # ======== Memory configuration ======== + memcfg: + data_file: ../../common/memcfg/memcfg_data.yaml + peripherals: + flexspi_nor: + reg_spec: ../../common/memcfg/opt_word_flexspi_nor.json + region_number: 0x09 + ow_counts_rule: OptionSize + runtime_instance: True + mem_type: nor + interfaces: [octal_spi, quad_spi, hyper_flash] + instances: [] + xspi_nor: + reg_spec: ../../common/memcfg/opt_word_xspi_nor.json + region_number: 0x0b + ow_counts_rule: OptionSize + runtime_instance: True + mem_type: nor + interfaces: [octal_spi, quad_spi] + instances: [] + flexspi_nand: + reg_spec: ../../common/memcfg/opt_word_flexspi_nand.json + region_number: 0x101 + ow_counts_rule: OptionSize + runtime_instance: True + mem_type: nand + interfaces: [quad_spi] + instances: [] + semc_nor: + reg_spec: ../../common/memcfg/opt_word_semc_nor.json + region_number: 0x08 + ow_counts_rule: AcTimingMode + mem_type: nor + interfaces: [parallel] + instances: [] + semc_nand: + reg_spec: ../../common/memcfg/opt_word_semc_nand.json + region_number: 0x100 + ow_counts_rule: All + mem_type: nand + interfaces: [parallel] + instances: [] + spi_nor: + reg_spec: ../../common/memcfg/opt_word_spi_nor.json + region_number: 0x110 + ow_counts_rule: OptionSize + mem_type: nor + interfaces: [spi] + instances: [] + # spi_nand: + # region_number: 0x101 + # instances: [] + mmc: + reg_spec: ../../common/memcfg/opt_word_mmc.json + region_number: 0x121 + ow_counts_rule: All + mem_type: sd + interfaces: [instance_0, instance_1, instance_2, instance_3] + instances: [] + emmc: + reg_spec: ../../common/memcfg/opt_word_emmc.json + region_number: 0x121 + ow_counts_rule: All + mem_type: sd + interfaces: [instance_0, instance_1, instance_2, instance_3] + instances: [] + sd: + reg_spec: ../../common/memcfg/opt_word_sd.json + region_number: 0x120 + ow_counts_rule: All + mem_type: sd + interfaces: [instance_0, instance_1, instance_2, instance_3] + instances: [] + # XIP Memories in internal memory address range + # mem_region_internal = 0x0 # Internal memory (include all on chip memory) + # mem_region_quad_spi0 = 0x1 # Quad SPI memory 0 + # mem_region_ifr0_fuse = 0x4 # Nonvolatile information register 0. Only used by SB loader. + # mem_region_semc_nor = 0x8 # SEMC Nor memory + # mem_region_flexspi_nor = 0x9 # Flex SPI Nor memory + # mem_region_spifi_nor = 0xA # SPIFI Nor memory + # mem_region_flash_execute_only = 0x10 # Execute-only region on internal Flash + + # # NON-XIP Memories in external memory address range + # mem_region_semc_nand = 0x100 + 0x0 # SEMC NAND memory + # mem_region_spi_nand = 0x100 + 0x1 # SPI NAND memory + # mem_region_spi_nor_eeprom = 0x100 + 0x10 # SPI NOR/EEPROM memory + # mem_region_i2c_nor_eeprom = 0x100 + 0x11 # I2C NOR/EEPROM memory + # mem_region_sd = 0x100 + 0x20 # eSD, SD, SDHC, SDXC memory Card + # mem_region_mmc = 0x100 + 0x21 # MMC, eMMC memory Card + + # ======== Wireless Power section ======== + wpc: + insert_puc_only: false + need_reset: false + need_address_adjust: false + check_lifecycle: 0 + + # ======== Misc signing section ======== + signing: + pss_padding: false + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_interface: mboot + el2go_name: null + prov_method: null + use_additional_data: false + fw_load_address: -1 + fw_read_address: -1 + user_data_address: -1 + ignored_otp: [] # format: index of a fuse (not uid, just the number) + ignored_otp_ranges: [] # format: [range1_start, range1_end, range2_start, range2_end,...] + clean_method: "none" + # format: "method1=value1[,value2];method2=value3;..." or "none" (default) + # methods are in secure_object.py:ValidationMethod + validation_method: "none" + uuid_fuse_index: "6 0 4" + use_prov_report: false + + # ======== LPCPROG section ======== + lpcprog: + part_ids: {} + buffer_address: 0x1000_0800 + buffer_size: 0x400 + page_size: 0x40 + sector_size: 0x400 + + # ======== DICE configuration ======== + dice: + had_length: 48 + had_members: + [ + ELS_AS_CFG0, + ELS_AS_CFG1, + ELS_AS_CFG2, + ELS_AS_ST0, + ELS_AS_ST1, + ELS_AS_ST2, + ELS_AS_FLAG0, + ] + critical_had_members: [ELS_AS_CFG0, ELS_AS_CFG1, ELS_AS_CFG2] + rtf_length: 32 + ca_puk_length: 64 + rkth_length: 32 + rkth_truncated_length: 32 + need_reset: false + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: + boot_devices: + emmc: + script: ../../common/uuu/emmc_burn_loader.lst + arguments: [_flash.bin, _image] + emmc_all: + script: ../../common/uuu/emmc_burn_all.lst + arguments: [_flash.bin, _image] + fat_write: + script: ../../common/uuu/fat_write.lst + arguments: [_image, _device, _partition, _filename] + nand: + script: ../../common/uuu/nand_burn_loader.lst + arguments: [_flash.bin, _image] + nvme_all: + script: ../../common/uuu/nvme_burn_all.lst + arguments: [_flash.bin, _image] + qspi: + script: ../../common/uuu/qspi_burn_loader.lst + arguments: [_flash.bin, _image] + sd: + script: ../../common/uuu/sd_burn_loader.lst + arguments: [_flash.bin, _image] + sd_all: + script: ../../common/uuu/sd_burn_all.lst + arguments: [_flash.bin, _image] + spi_nand: + script: ../../common/uuu/fspinand_burn_loader.lst + arguments: [_flash.bin, _image] + spl: + script: ../../common/uuu/spl_boot.lst + arguments: [_flash.bin] + + # ======== BCA section ======== + bca: + reg_spec: bca.json + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + + # ======== SHE section ======== + she_scec: {} + + # ===== TLV ===== + tlv_blob: {} + + # ======== Hardware Security Engine section ======== + hse: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/fmc_template.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/fmc_template.yaml new file mode 100644 index 0000000..1f27715 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/fmc_template.yaml @@ -0,0 +1,28 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# issuer common name; required +issuer_name: NXP DICE 2.0 - IDevID +# subject common name; required +subject_name: NXP DICE 2.0 - FMC Alias + +# Include Customer TCB Table; optional (default=false) +include_cust_table: true +# Customer SVN for Customer TCB Table; required if include_cust_table = true +cust_svn: 0xabcd + +# Include NXP TCB Table; optional (default=false) +include_nxp_table: true + +# ECDSA/MLDSA mode; optional (default=ecdsa) +mode: ecdsa +# Template key; optional (if omitted a new temporary key will be generated each time) +template_key: idevid_ecc384.pem + +# Where to store the FMC Alias certificate; optional +template_output: alias_fmc.der +# Where to store the FMC Alias certificate offset descriptor; optional +descriptor_output: descriptor.bin +# Where to store the final FMC Alias certificate container; required +container_output: container.bin diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/tcg_dice.asn b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/tcg_dice.asn new file mode 100644 index 0000000..665bb30 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/dice/tcg_dice.asn @@ -0,0 +1,65 @@ +TCG DEFINITIONS ::= BEGIN + + tcg OBJECT IDENTIFIER ::= { 2 23 133 } + tcg-dice OBJECT IDENTIFIER ::= { tcg platformClass(5) 4 } + + FWID ::= SEQUENCE { + hashAlg OBJECT IDENTIFIER, + digest OCTET STRING + } + + FWIDLIST ::= SEQUENCE SIZE (1..10) OF FWID + + OperationalFlags ::= BIT STRING { + notConfigured (0), + notSecure (1), + recovery (2), + debug (3), + notReplayProtected (4), + notIntegrityProtected (5), + notRuntimeMeasured (6), + notImmutable (7), + notTcb (8), + fixedWidth (31) + } + + OperationalFlagsMask ::= BIT STRING { + notConfigured (0), + notSecure (1), + recovery (2), + debug (3), + notReplayProtected (4), + notIntegrityProtected (5), + notRuntimeMeasured (6), + notImmutable (7), + notTcb (8), + fixedWidth (31) + } + + tcg-dice-TcbInfo OBJECT IDENTIFIER ::= { tcg-dice 1 } + + DiceTcbInfo ::= SEQUENCE { + vendor [0] IMPLICIT UTF8String OPTIONAL, + model [1] IMPLICIT UTF8String OPTIONAL, + version [2] IMPLICIT UTF8String OPTIONAL, + svn [3] IMPLICIT INTEGER OPTIONAL, + layer [4] IMPLICIT INTEGER OPTIONAL, + index [5] IMPLICIT INTEGER OPTIONAL, + fwids [6] IMPLICIT FWIDLIST OPTIONAL, + flags [7] IMPLICIT OperationalFlags OPTIONAL, + vendorInfo [8] IMPLICIT OCTET STRING OPTIONAL, + type [9] IMPLICIT OCTET STRING OPTIONAL, + flagsMask [10]IMPLICIT OperationalFlagsMask OPTIONAL + } + + tcg-dice-MultiTcbInfo OBJECT IDENTIFIER ::= { tcg-dice 5 } + + DiceTcbInfoSeq ::= SEQUENCE SIZE (1..3) OF DiceTcbInfo + + tcg-dice-Ueid OBJECT IDENTIFIER ::= { tcg-dice 4 } + + TcgUeid ::= SEQUENCE { + ueid OCTET STRING + } + +END diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/fcb_flexspi_nor_modification.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/fcb_flexspi_nor_modification.yaml new file mode 100644 index 0000000..ef82d92 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/fcb_flexspi_nor_modification.yaml @@ -0,0 +1,508 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +field082: + bitfields: + field082-bits-0-7: + no_yaml_comments: true + field082-bits-10-15: + no_yaml_comments: true + field082-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field084: + bitfields: + field084-bits-0-7: + no_yaml_comments: true + field084-bits-10-15: + no_yaml_comments: true + field084-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field086: + bitfields: + field086-bits-0-7: + no_yaml_comments: true + field086-bits-10-15: + no_yaml_comments: true + field086-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field088: + bitfields: + field088-bits-0-7: + no_yaml_comments: true + field088-bits-10-15: + no_yaml_comments: true + field088-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field08A: + bitfields: + field08A-bits-0-7: + no_yaml_comments: true + field08A-bits-10-15: + no_yaml_comments: true + field08A-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field08C: + bitfields: + field08C-bits-0-7: + no_yaml_comments: true + field08C-bits-10-15: + no_yaml_comments: true + field08C-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field08E: + bitfields: + field08E-bits-0-7: + no_yaml_comments: true + field08E-bits-10-15: + no_yaml_comments: true + field08E-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field092: + bitfields: + field092-bits-0-7: + no_yaml_comments: true + field092-bits-10-15: + no_yaml_comments: true + field092-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field094: + bitfields: + field094-bits-0-7: + no_yaml_comments: true + field094-bits-10-15: + no_yaml_comments: true + field094-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field096: + bitfields: + field096-bits-0-7: + no_yaml_comments: true + field096-bits-10-15: + no_yaml_comments: true + field096-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field098: + bitfields: + field098-bits-0-7: + no_yaml_comments: true + field098-bits-10-15: + no_yaml_comments: true + field098-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field09A: + bitfields: + field09A-bits-0-7: + no_yaml_comments: true + field09A-bits-10-15: + no_yaml_comments: true + field09A-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field09C: + bitfields: + field09C-bits-0-7: + no_yaml_comments: true + field09C-bits-10-15: + no_yaml_comments: true + field09C-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field09E: + bitfields: + field09E-bits-0-7: + no_yaml_comments: true + field09E-bits-10-15: + no_yaml_comments: true + field09E-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0A2: + bitfields: + field0A2-bits-0-7: + no_yaml_comments: true + field0A2-bits-10-15: + no_yaml_comments: true + field0A2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0A4: + bitfields: + field0A4-bits-0-7: + no_yaml_comments: true + field0A4-bits-10-15: + no_yaml_comments: true + field0A4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0A6: + bitfields: + field0A6-bits-0-7: + no_yaml_comments: true + field0A6-bits-10-15: + no_yaml_comments: true + field0A6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0A8: + bitfields: + field0A8-bits-0-7: + no_yaml_comments: true + field0A8-bits-10-15: + no_yaml_comments: true + field0A8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0AA: + bitfields: + field0AA-bits-0-7: + no_yaml_comments: true + field0AA-bits-10-15: + no_yaml_comments: true + field0AA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0AC: + bitfields: + field0AC-bits-0-7: + no_yaml_comments: true + field0AC-bits-10-15: + no_yaml_comments: true + field0AC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0AE: + bitfields: + field0AE-bits-0-7: + no_yaml_comments: true + field0AE-bits-10-15: + no_yaml_comments: true + field0AE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0B2: + bitfields: + field0B2-bits-0-7: + no_yaml_comments: true + field0B2-bits-10-15: + no_yaml_comments: true + field0B2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0B4: + bitfields: + field0B4-bits-0-7: + no_yaml_comments: true + field0B4-bits-10-15: + no_yaml_comments: true + field0B4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0B6: + bitfields: + field0B6-bits-0-7: + no_yaml_comments: true + field0B6-bits-10-15: + no_yaml_comments: true + field0B6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0B8: + bitfields: + field0B8-bits-0-7: + no_yaml_comments: true + field0B8-bits-10-15: + no_yaml_comments: true + field0B8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0BA: + bitfields: + field0BA-bits-0-7: + no_yaml_comments: true + field0BA-bits-10-15: + no_yaml_comments: true + field0BA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0BC: + bitfields: + field0BC-bits-0-7: + no_yaml_comments: true + field0BC-bits-10-15: + no_yaml_comments: true + field0BC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0BE: + bitfields: + field0BE-bits-0-7: + no_yaml_comments: true + field0BE-bits-10-15: + no_yaml_comments: true + field0BE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0C2: + bitfields: + field0C2-bits-0-7: + no_yaml_comments: true + field0C2-bits-10-15: + no_yaml_comments: true + field0C2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0C4: + bitfields: + field0C4-bits-0-7: + no_yaml_comments: true + field0C4-bits-10-15: + no_yaml_comments: true + field0C4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0C6: + bitfields: + field0C6-bits-0-7: + no_yaml_comments: true + field0C6-bits-10-15: + no_yaml_comments: true + field0C6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0C8: + bitfields: + field0C8-bits-0-7: + no_yaml_comments: true + field0C8-bits-10-15: + no_yaml_comments: true + field0C8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0CA: + bitfields: + field0CA-bits-0-7: + no_yaml_comments: true + field0CA-bits-10-15: + no_yaml_comments: true + field0CA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0CC: + bitfields: + field0CC-bits-0-7: + no_yaml_comments: true + field0CC-bits-10-15: + no_yaml_comments: true + field0CC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0CE: + bitfields: + field0CE-bits-0-7: + no_yaml_comments: true + field0CE-bits-10-15: + no_yaml_comments: true + field0CE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0D2: + bitfields: + field0D2-bits-0-7: + no_yaml_comments: true + field0D2-bits-10-15: + no_yaml_comments: true + field0D2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0D4: + bitfields: + field0D4-bits-0-7: + no_yaml_comments: true + field0D4-bits-10-15: + no_yaml_comments: true + field0D4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0D6: + bitfields: + field0D6-bits-0-7: + no_yaml_comments: true + field0D6-bits-10-15: + no_yaml_comments: true + field0D6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0D8: + bitfields: + field0D8-bits-0-7: + no_yaml_comments: true + field0D8-bits-10-15: + no_yaml_comments: true + field0D8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0DA: + bitfields: + field0DA-bits-0-7: + no_yaml_comments: true + field0DA-bits-10-15: + no_yaml_comments: true + field0DA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0DC: + bitfields: + field0DC-bits-0-7: + no_yaml_comments: true + field0DC-bits-10-15: + no_yaml_comments: true + field0DC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0DE: + bitfields: + field0DE-bits-0-7: + no_yaml_comments: true + field0DE-bits-10-15: + no_yaml_comments: true + field0DE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0E2: + bitfields: + field0E2-bits-0-7: + no_yaml_comments: true + field0E2-bits-10-15: + no_yaml_comments: true + field0E2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0E4: + bitfields: + field0E4-bits-0-7: + no_yaml_comments: true + field0E4-bits-10-15: + no_yaml_comments: true + field0E4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0E6: + bitfields: + field0E6-bits-0-7: + no_yaml_comments: true + field0E6-bits-10-15: + no_yaml_comments: true + field0E6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0E8: + bitfields: + field0E8-bits-0-7: + no_yaml_comments: true + field0E8-bits-10-15: + no_yaml_comments: true + field0E8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0EA: + bitfields: + field0EA-bits-0-7: + no_yaml_comments: true + field0EA-bits-10-15: + no_yaml_comments: true + field0EA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0EC: + bitfields: + field0EC-bits-0-7: + no_yaml_comments: true + field0EC-bits-10-15: + no_yaml_comments: true + field0EC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0EE: + bitfields: + field0EE-bits-0-7: + no_yaml_comments: true + field0EE-bits-10-15: + no_yaml_comments: true + field0EE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0F2: + bitfields: + field0F2-bits-0-7: + no_yaml_comments: true + field0F2-bits-10-15: + no_yaml_comments: true + field0F2-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0F4: + bitfields: + field0F4-bits-0-7: + no_yaml_comments: true + field0F4-bits-10-15: + no_yaml_comments: true + field0F4-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0F6: + bitfields: + field0F6-bits-0-7: + no_yaml_comments: true + field0F6-bits-10-15: + no_yaml_comments: true + field0F6-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0F8: + bitfields: + field0F8-bits-0-7: + no_yaml_comments: true + field0F8-bits-10-15: + no_yaml_comments: true + field0F8-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0FA: + bitfields: + field0FA-bits-0-7: + no_yaml_comments: true + field0FA-bits-10-15: + no_yaml_comments: true + field0FA-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0FC: + bitfields: + field0FC-bits-0-7: + no_yaml_comments: true + field0FC-bits-10-15: + no_yaml_comments: true + field0FC-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true +field0FE: + bitfields: + field0FE-bits-0-7: + no_yaml_comments: true + field0FE-bits-10-15: + no_yaml_comments: true + field0FE-bits-8-9: + no_yaml_comments: true + no_yaml_comments: true diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/memcfg_data.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/memcfg_data.yaml new file mode 100644 index 0000000..5220642 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/memcfg_data.yaml @@ -0,0 +1,380 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +# ======== Flash memories configuration ======== + +# *********************************************************************** +# NOR +# *********************************************************************** + +# Winbond +W25QxxxJV: + manufacturer: Winbond + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] + tested: True +W35T51NW: + manufacturer: Winbond + type: nor + interfaces: + octal_spi: + option_words: [0xc0603005] +# Macronix +MX25Uxxx32F: + manufacturer: Macronix + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] + tested: True +MX25Lxxx45G: + manufacturer: Macronix + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] + tested: True +MX25UMxxx45G: + manufacturer: Macronix + type: nor + interfaces: + octal_spi: + option_words: [0xc0403007] +MX66UMxxx45G: + manufacturer: Macronix + type: nor + interfaces: + octal_spi: + option_words: [0xc0403007] +MX25LMxxx45G: + manufacturer: Macronix + type: nor + interfaces: + octal_spi: + option_words: [0xc0403007] +MX25UM51345G: + manufacturer: Macronix + type: nor + interfaces: + octal_spi: + option_words: [0xc0403007] +# GigaDevice +GD25QxxxC: + manufacturer: GigaDevice + type: nor + interfaces: + quad_spi: + option_words: [0xc0000406] +GD25LBxxxE: + manufacturer: GigaDevice + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +GD25LTxxxE: + manufacturer: GigaDevice + type: nor + interfaces: + quad_spi: + option_words: [0xc0000008] +GD25LXxxxE: + manufacturer: GigaDevice + type: nor + interfaces: + quad_spi: + option_words: [0xc0603008] +# ISSI +IS25LPxxxA: + manufacturer: ISSI + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +IS25WPxxxA: + manufacturer: ISSI + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +IS25LXxxx: + manufacturer: ISSI + type: nor + interfaces: + octal_spi: + option_words: [0xC0603005] +IS25WXxxx: + manufacturer: ISSI + type: nor + interfaces: + octal_spi: + option_words: [0xC0603005] +IS26KSxxxS: + manufacturer: ISSI + type: nor + interfaces: + hyper_flash: + option_words: [0xc0233007] +IS26KLxxxS: + manufacturer: ISSI + type: nor + interfaces: + hyper_flash: + option_words: [0xc0233007] +# Micron +MT25QLxxxA: + manufacturer: Micron + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +MT35XUxxxABA1G: + manufacturer: Micron + type: nor + interfaces: + octal_spi: + option_words: [0xC0703005] +MT35XUxxxABA2G: + manufacturer: Micron + type: nor + interfaces: + octal_spi: + option_words: [0xC0633005] + tested: True +MT28EW128ABA: + manufacturer: Micron + type: nor + interfaces: + parallel: + option_words: [0xD0000600] +MT28UG128ABA: + manufacturer: Micron + type: nor + interfaces: + parallel: + option_words: [0xD0000601] +# Adesto +AT25SFxxxA: + manufacturer: Adesto + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +ATXPxxx: + manufacturer: Adesto + type: nor + interfaces: + octal_spi: + option_words: [0xc0803007] +# Cypress +S25FSxxxS: + manufacturer: Cypress + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +S25FLxxxS: + manufacturer: Cypress + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +S26KSxxxS: + manufacturer: Cypress + type: nor + interfaces: + hyper_flash: + option_words: [0xc0233007] +S26KLxxxS: + manufacturer: Cypress + type: nor + interfaces: + hyper_flash: + option_words: [0xc0233007] +# Microchip +SST26VFxxxB: + manufacturer: Microchip + type: nor + interfaces: + quad_spi: + option_words: [0xc0000005] +# FudanMicro +FM25Qxxx: + manufacturer: FudanMicro + type: nor + interfaces: + quad_spi: + option_words: [0xc0000205] +# BoyaMicro +BY25QxxxBS: + manufacturer: BoyaMicro + type: nor + interfaces: + quad_spi: + option_words: [0xc0000405] +# XMC +XM25QHxxxB: + manufacturer: XMC + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +XM25QUxxxB: + manufacturer: XMC + type: nor + interfaces: + quad_spi: + option_words: [0xc0000007] +# XTXtech +X25FxxxB: + manufacturer: XTXtech + type: nor + interfaces: + quad_spi: + option_words: [0xc0000407] +X25QxxxD: + manufacturer: XTXtech + type: nor + interfaces: + quad_spi: + option_words: [0xc0000407] +# Puya +P25QxxxLE: + manufacturer: Puya + type: nor + interfaces: + quad_spi: + option_words: [0xc0000405] +P25QxxxH: + manufacturer: Puya + type: nor + interfaces: + quad_spi: + option_words: [0xc0000405] +P25QxxxU: + manufacturer: Puya + type: nor + interfaces: + quad_spi: + option_words: [0xc0000405] +# AMIC +A25LQxxx: + manufacturer: AMIC + type: nor + interfaces: + quad_spi: + option_words: [0xc0000105] + +# *********************************************************************** +# NAND +# *********************************************************************** + +# Winbond +W25N01G: + manufacturer: Winbond + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000ef] +W25N02K: + manufacturer: Winbond + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000ef] +# Macronix +MX35UF1G: + manufacturer: Macronix + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000c2] +MX35LF1G: + manufacturer: Macronix + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000c2] +MX35UF2G: + manufacturer: Macronix + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000c2] +MX35LF2G: + manufacturer: Macronix + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000c2] +# GigaDevice +GD5F1GQ5: + manufacturer: GigaDevice + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000c8] +GD5F2GQ5: + manufacturer: GigaDevice + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000c8] +# Micron +MT29F1G01AA: + manufacturer: Micron + type: nand + interfaces: + quad_spi: + option_words: [0xC1011022, 0x0000002c] +MT29F2G01AA: + manufacturer: Micron + type: nand + interfaces: + quad_spi: + option_words: [0xC1021022, 0x0000002c] +# Paragon +PN26Q01A: + manufacturer: Paragon + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000a1] +PN26G01A: + manufacturer: Paragon + type: nand + interfaces: + quad_spi: + option_words: [0xC1010026, 0x000000a1] +PN26Q02A: + manufacturer: Paragon + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000a1] +PN26G02A: + manufacturer: Paragon + type: nand + interfaces: + quad_spi: + option_words: [0xC1020026, 0x000000a1] + +# *********************************************************************** +# SD +# *********************************************************************** + +# General +1bit_sdr12: + manufacturer: General + type: sd + interfaces: + instance_0: + option_words: [0xD0000000] + instance_1: + option_words: [0xD0000001] + instance_2: + option_words: [0xD0000002] + instance_3: + option_words: [0xD0000003] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_emmc.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_emmc.json new file mode 100644 index 0000000..57c0ea3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_emmc.json @@ -0,0 +1,395 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "eMMC card Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bit0", + "width": 1, + "name": "BootConfigEnable", + "access": "RW", + "description": "Boot configuration", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Boot configuration disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Boot configuration enabled" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bit2", + "width": 1, + "name": "BootAcknowledge", + "access": "RW", + "description": "Boot acknowledge", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Boot acknowledge disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Boot acknowledge enabled" + } + ] + }, + { + "id": "field000-bit3", + "width": 1, + "name": "ResetBootBusConditions", + "access": "RW", + "description": "Reset boot BUS conditions", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Don't change BUS conditions" + }, + { + "name": "Enabled", + "value": 1, + "description": "Reset boot BUS conditions" + } + ] + }, + { + "id": "field000-bits4-5", + "width": 2, + "name": "BootMode", + "access": "RW", + "description": "Boot mode configuration", + "values": [ + { + "name": "SDRWithDefaultTiming", + "value": 0, + "description": "Single data rate with backward compatible timings" + }, + { + "name": "SDRWithHighSpeedTiming", + "value": 1, + "description": "Single data rate with high speed timing" + }, + { + "name": "DDRTiming", + "value": 2, + "description": "Dual date rate" + } + ] + }, + { + "width": 2 + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "BusWidth", + "access": "RW", + "description": "eMMC card data bus width(BUS_WIDTH in Extended CSD)", + "values": [ + { + "name": "1bit", + "value": 0, + "description": "eMMC data bus width is 1 bit" + }, + { + "name": "4bit", + "value": 1, + "description": "eMMC data bus width is 4 bits" + }, + { + "name": "8bit", + "value": 2, + "description": "eMMC data bus width is 8 bits" + }, + { + "name": "4bitDDR", + "value": 5, + "description": "eMMC data bus width is 4 bits ddr" + }, + { + "name": "8bitDDR", + "value": 6, + "description": "eMMC data bus width is 8 bits ddr" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "TimingMode", + "access": "RW", + "description": "Select the bus timing when accesses eMMC memory", + "values": [ + { + "name": "HighSpeedTimingNormal", + "value": 0, + "description": "eMMC card using none high-speed timing" + }, + { + "name": "HighSpeedTiming", + "value": 1, + "description": "eMMC card using high-speed timing" + }, + { + "name": "HighSpeed200Timing", + "value": 2, + "description": "eMMC card high speed 200 timing" + }, + { + "name": "HighSpeed400Timing", + "value": 3, + "description": "eMMC card high speed 400 timing" + } + ] + }, + { + "id": "field000-bits16-17", + "width": 2, + "name": "BootBusWidth", + "access": "RW", + "description": "eMMC card boot bus width(BOOT_BUS_WIDTH in Extended CSD)", + "values": [ + { + "name": "1bitSDR4bitDDR", + "value": 0, + "description": "x1 (sdr) or x4 (ddr) bus width in boot operation mode(default)" + }, + { + "name": "4bitSDR4bitDDR", + "value": 1, + "description": "x4 (sdr/ddr) bus width in boot operation mode" + }, + { + "name": "8bitSDR8bitDDR", + "value": 2, + "description": "x8 (sdr/ddr) bus width in boot operation mode" + } + ] + }, + { + "width": 2 + }, + { + "id": "field000-bits20-22", + "width": 3, + "name": "BootPartitionEnabled", + "access": "RW", + "description": "eMMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD)", + "values": [ + { + "name": "Not", + "value": 0, + "description": "Device not boot enabled (default)" + }, + { + "name": "Partition1", + "value": 1, + "description": "Boot partition 1 enabled for boot" + }, + { + "name": "Partition2", + "value": 2, + "description": "Boot partition 2 enabled for boot" + }, + { + "name": "UserAera", + "value": 7, + "description": "User area enabled for boot" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bits24-26", + "width": 3, + "name": "PartitionAccess", + "access": "RW", + "description": "eMMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD)", + "values": [ + { + "name": "PartitionUserAera", + "value": 0, + "description": "No access to boot partition (default), normal partition" + }, + { + "name": "PartitionBoot1", + "value": 1, + "description": "Read/Write boot partition 1" + }, + { + "name": "PartitionBoot2", + "value": 2, + "description": "Read/Write boot partition 2" + }, + { + "name": "RPMB", + "value": 3, + "description": "Replay protected mem block" + }, + { + "name": "GeneralPurposePartition1", + "value": 4, + "description": "access to general purpose partition 1" + }, + { + "name": "GeneralPurposePartition2", + "value": 5, + "description": "access to general purpose partition 2" + }, + { + "name": "GeneralPurposePartition3", + "value": 6, + "description": "access to general purpose partition 3" + }, + { + "name": "GeneralPurposePartition4", + "value": 7, + "description": "access to general purpose partition 4" + } + ] + }, + { + "width": 1 + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "eMMC card Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 19 + }, + { + "id": "field004-bit19", + "width": 1, + "name": "EnablePowerCycle", + "access": "RW", + "description": "Execute power cycle before initialization", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Power cycle disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Execute power cycle before initialization" + } + ] + }, + { + "id": "field004-bit20", + "width": 1, + "name": "PowerUpDelay", + "access": "RW", + "description": "Set power up delay", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "width": 2 + }, + { + "id": "field004-bit23", + "width": 1, + "name": "PowerUpPolarity", + "access": "RW", + "description": "eMMC power control polarity. Only valid when PWR_CYCLE_ENABLE is enabled", + "values": [ + { + "name": "Low", + "value": 0, + "description": "Power down when uSDHC.RST set low" + }, + { + "name": "High", + "value": 1, + "description": "Power down when uSDHC.RST set high" + } + ] + }, + { + "id": "field004-bits24-25", + "width": 2, + "name": "PowerDownTime", + "access": "RW", + "description": "Set power down time", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "Power up delay 20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "Power up delay 10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "width": 2 + }, + { + "width": 4 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nand.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nand.json new file mode 100644 index 0000000..c39dc3c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nand.json @@ -0,0 +1,276 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NAND Configuration Option 0", + "default_value_int": "0xc0000020", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "MaxFreq", + "access": "RW", + "description": "The maximum work frequency for specified Flash device", + "values": [ + { + "name": "NoChange", + "value": 0, + "description": "Don't change FlexSPI clock setting" + }, + { + "name": "30Mhz", + "value": 1, + "description": "30MHz" + }, + { + "name": "50Mhz", + "value": 2, + "description": "50MHz" + }, + { + "name": "60Mhz", + "value": 3, + "description": "60MHz" + }, + { + "name": "80Mhz", + "value": 4, + "description": "80MHz" + }, + { + "name": "100Mhz", + "value": 5, + "description": "100MHz" + }, + { + "name": "120Mhz", + "value": 6, + "description": "120MHz" + }, + { + "name": "133Mhz", + "value": 7, + "description": "133MHz" + }, + { + "name": "166Mhz", + "value": 8, + "description": "166MHz" + } + ] + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "PageSize", + "access": "RW", + "description": "Specify page size in KB.", + "values": [ + { + "name": "2KB", + "value": 2, + "description": "NAND is using 2KB pages" + }, + { + "name": "4KB", + "value": 4, + "description": "NAND is using 4KB pages" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "PagesPerBlock", + "access": "RW", + "description": "Specify the count of pages per one block", + "values": [ + { + "name": "64", + "value": 0, + "description": "64 pages per one block" + }, + { + "name": "128", + "value": 1, + "description": "128 pages per one block" + }, + { + "name": "256", + "value": 2, + "description": "256 pages per one block" + }, + { + "name": "32", + "value": 3, + "description": "32 pages per one block" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "HasMultiPlanes", + "access": "RW", + "description": "Has or no multiplanes", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "NAND memory has not multiplanes" + }, + { + "name": "Enabled", + "value": 1, + "description": "NAND memory has multiplanes" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "FlashSize", + "access": "RW", + "description": "Overall flash size", + "values": [ + { + "name": "512Mbit", + "value": 0, + "description": "Memory size is 512Mbit" + }, + { + "name": "1Gbit", + "value": 1, + "description": "Memory size is 1Gbit" + }, + { + "name": "2Gbit", + "value": 2, + "description": "Memory size is 2Gbit" + }, + { + "name": "4Gbit", + "value": 4, + "description": "Memory size is 4Gbit" + }, + { + "name": "8Gbit", + "value": 8, + "description": "Memory size is 8Gbit" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "DeviceType", + "access": "RW", + "description": "Device type of NAND.", + "values": [ + { + "name": "QuadSpi", + "value": 0, + "description": "QuadSPI NAND" + }, + { + "name": "Octal", + "value": 1, + "description": "OctalSPI NAND" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "OptionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OptionSize1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OptionSize2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "FlexSPI NAND flash Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "ManufacturerId", + "access": "RW", + "description": "Manufacture ID" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "EccFailureMask", + "access": "RW", + "description": "ECC Failure mask" + }, + { + "id": "field004-bits16-23", + "width": 8, + "name": "EccCheckMask", + "access": "RW", + "description": "ECC Check Mask" + }, + { + "id": "field004-bits24-27", + "width": 4, + "name": "PinMuxGroup", + "access": "RW", + "description": "Select the FlexSPI Pin MUx group" + }, + { + "id": "field004-bits28-31", + "width": 4, + "name": "FlashConnection", + "access": "RW", + "description": "Select the FlexSPI Port A/B", + "values": [ + { + "name": "SingleFlashPort_A", + "value": 0, + "description": "Single Flash connected to port A" + }, + { + "name": "SingleFlashPort_B", + "value": 2, + "description": "Single Flash connected to port B" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor.json new file mode 100644 index 0000000..daf5ec2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor.json @@ -0,0 +1,338 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NOR Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "MaxFreq", + "access": "RW", + "description": "The maximum work frequency for specified Flash device", + "values": [ + { + "name": "NoChange", + "value": 0, + "description": "Don't change FlexSPI clock setting" + }, + { + "name": "30Mhz", + "value": 1, + "description": "30MHz" + }, + { + "name": "50Mhz", + "value": 2, + "description": "50MHz" + }, + { + "name": "60Mhz", + "value": 3, + "description": "60MHz" + }, + { + "name": "75Mhz", + "value": 4, + "description": "75MHz" + }, + { + "name": "80Mhz", + "value": 5, + "description": "80MHz" + }, + { + "name": "100Mhz", + "value": 6, + "description": "100MHz" + }, + { + "name": "133Mhz", + "value": 7, + "description": "133MHz" + }, + { + "name": "166Mhz", + "value": 8, + "description": "166MHz" + } + ] + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "Misc", + "access": "RW", + "description": "Specify miscellaneous mode for selected flash type; Experimental feature, do not use in products, keep it as 0.", + "values": [ + { + "name": "NotEnabled", + "value": 0, + "description": "Miscellaneous mode is not enabled" + }, + { + "name": "Mode0-4-4", + "value": 1, + "description": "Enable 0-4-4 mode for High Random Read performance" + }, + { + "name": "SwappedMode", + "value": 3, + "description": " Data Order Swapped mode (for MXIC OctaFlash only)" + }, + { + "name": "InternalLoopBack", + "value": 5, + "description": " Select the FlexSPI data sample source as internal loop back, more details please refer FlexSPI usage" + }, + { + "name": "StandSpiMode", + "value": 6, + "description": " Config the FlexSPI NOR flash running at stand SPI mode" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "QuadEnableType", + "access": "RW", + "description": "Specify the Quad Enable sequence, only applicable for device that only JESD216 compliant, this field is ignored if device support JESD216A or later version. This field will be effective only if device is compliant with JESD216 only (9 longword SDFP table)", + "values": [ + { + "name": "NotConfigure", + "value": 0, + "description": "Not Configured" + }, + { + "name": "Bit6InSR1", + "value": 1, + "description": "QE bit is bit6 in StatusReg1" + }, + { + "name": "Bit1InSR2", + "value": 2, + "description": "QE bit is bit1 in StatusReg2" + }, + { + "name": "Bit7InSR2", + "value": 3, + "description": "QE bit is bit7 in StatusReg2" + }, + { + "name": "Bit1InSR2EnableCmdIs0x31", + "value": 4, + "description": "QE bit is bit1 in StatusReg2, enable command is 0x31" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "CMDPad(s)", + "access": "RW", + "description": "Commands pads for the Flash device (1/4/8), for device that works under 1-1-4,1-4-4,1-1-8 or 1-8-8 mode, CMD pad(s) value is always 0x0, for devices that only support 4-4-4 mode for high performance, CMD pads value is 2, for devices that only support 8-8-8 mode for high performance, CMD pads value is 3", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "Query CMDPad(s)", + "access": "RW", + "description": "Command pads (1/4/8) for the SFDP command", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "Device Detection Type", + "access": "RW", + "description": "SW defined device types used for config block autodetection", + "values": [ + { + "name": "QuadSPI_SDR", + "value": 0, + "description": "QuadSPI SDR" + }, + { + "name": "QuadSPI_DDR", + "value": 1, + "description": "QuadSPI DDR" + }, + { + "name": "HyperFLASH_1V8", + "value": 2, + "description": "HyperFLASH 1V8" + }, + { + "name": "HyperFLASH_3V", + "value": 3, + "description": "HyperFLASH 3V" + }, + { + "name": "MXICOPI_DDR", + "value": 4, + "description": "MXICOPI DDR" + }, + { + "name": "MicronOPI_DDR", + "value": 6, + "description": "MicronOPI DDR" + }, + { + "name": "MicronOPI_SDR", + "value": 7, + "description": "MicronOPI SDR" + }, + { + "name": "AdestoOPI_DDR", + "value": 8, + "description": "AdestoOPI DDR" + }, + { + "name": "AdestoOPI_SDR", + "value": 9, + "description": "AdestoOPI SDR" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "OptionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OptionSize1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OptionSize2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "FlexSPI NOR Flash Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "DummyCycles", + "access": "RW", + "description": "User provided dummy cycles for SDR/DDR read command: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "StatusOverride", + "access": "RW", + "description": "Override status register value during device mode configuration" + }, + { + "id": "field004-bits16-19", + "width": 4, + "name": "PinMuxGroup", + "access": "RW", + "description": "Pin multiplexer group selection" + }, + { + "id": "field004-bits20-23", + "width": 4, + "name": "DqsPinMuxGroup", + "access": "RW", + "description": "DQS Pin multiplexer group selection" + }, + { + "id": "field004-bits24-27", + "width": 4, + "name": "PinDriveStrength", + "access": "RW", + "description": "The Drive Strength of FlexSPI Pads" + }, + { + "id": "field004-bits28-31", + "width": 4, + "name": "FlashConnection", + "access": "RW", + "description": "Select the FlexSPI Port A/B", + "values": [ + { + "name": "SingleFlashPort_A", + "value": 0, + "description": "Single Flash connected to port A" + }, + { + "name": "ParallelMode", + "value": 1, + "description": "Parallel mode" + }, + { + "name": "SingleFlashPort_B", + "value": 2, + "description": "Single Flash connected to port B" + } + ] + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor_legacy.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor_legacy.json new file mode 100644 index 0000000..b7d0544 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_flexspi_nor_legacy.json @@ -0,0 +1,273 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NOR Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "MaxFreq", + "access": "RW", + "description": "The maximum work frequency for specified Flash device; 0 - Don't change FlexSPI clock setting" + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "Misc", + "access": "RW", + "description": "Specify miscellaneous mode for selected flash type; Experimental feature, do not use in products, keep it as 0.", + "values": [ + { + "name": "NotEnabled", + "value": 0, + "description": "Miscellaneous mode is not enabled" + }, + { + "name": "Mode0-4-4", + "value": 1, + "description": "Enable 0-4-4 mode for High Random Read performance" + }, + { + "name": "SwappedMode", + "value": 3, + "description": " Data Order Swapped mode (for MXIC OctaFlash only)" + }, + { + "name": "InternalLoopBack", + "value": 5, + "description": " Select the FlexSPI data sample source as internal loop back, more details please refer FlexSPI usage" + }, + { + "name": "StandSpiMode", + "value": 6, + "description": " Config the FlexSPI NOR flash running at stand SPI mode" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "QuadEnableType", + "access": "RW", + "description": "Specify the Quad Enable sequence, only applicable for device that only JESD216 compliant, this field is ignored if device support JESD216A or later version. This field will be effective only if device is compliant with JESD216 only (9 longword SDFP table)", + "values": [ + { + "name": "NotConfigure", + "value": 0, + "description": "Not Configured" + }, + { + "name": "Bit6InSR1", + "value": 1, + "description": "QE bit is bit6 in StatusReg1" + }, + { + "name": "Bit1InSR2", + "value": 2, + "description": "QE bit is bit1 in StatusReg2" + }, + { + "name": "Bit7InSR2", + "value": 3, + "description": "QE bit is bit7 in StatusReg2" + }, + { + "name": "Bit1InSR2EnableCmdIs0x31", + "value": 4, + "description": "QE bit is bit1 in StatusReg2, enable command is 0x31" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "CMDPad(s)", + "access": "RW", + "description": "Commands pads for the Flash device (1/4/8), for device that works under 1-1-4,1-4-4,1-1-8 or 1-8-8 mode, CMD pad(s) value is always 0x0, for devices that only support 4-4-4 mode for high performance, CMD pads value is 2, for devices that only support 8-8-8 mode for high performance, CMD pads value is 3", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "QueryCMDPad(s)", + "access": "RW", + "description": "Command pads (1/4/8) for the SFDP command", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "DeviceDetectionType", + "access": "RW", + "description": "SW defined device types used for config block autodetection", + "values": [ + { + "name": "QuadSPI_SDR", + "value": 0, + "description": "QuadSPI SDR" + }, + { + "name": "QuadSPI_DDR", + "value": 1, + "description": "QuadSPI DDR" + }, + { + "name": "HyperFLASH_1V8", + "value": 2, + "description": "HyperFLASH 1V8" + }, + { + "name": "HyperFLASH_3V", + "value": 3, + "description": "HyperFLASH 3V" + }, + { + "name": "MXICOPI_DDR", + "value": 4, + "description": "MXICOPI DDR" + }, + { + "name": "MicronOPI_DDR", + "value": 6, + "description": "MicronOPI DDR" + }, + { + "name": "MicronOPI_SDR", + "value": 7, + "description": "MicronOPI SDR" + }, + { + "name": "AdestoOPI_DDR", + "value": 8, + "description": "AdestoOPI DDR" + }, + { + "name": "AdestoOPI_SDR", + "value": 9, + "description": "AdestoOPI SDR" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "OptionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OptionSize1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OptionSize2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "FlexSPI NOR Flash Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "DummyCycles", + "access": "RW", + "description": "User provided dummy cycles for SDR/DDR read command: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "StatusOverride", + "access": "RW", + "description": "Override status register value during device mode configuration" + }, + { + "width": 8 + }, + { + "id": "field004-bits24-31", + "width": 8, + "name": "FlashConnection", + "access": "RW", + "description": "Select the FlexSPI Port A/B", + "values": [ + { + "name": "SingleFlashPort_A", + "value": 0, + "description": "Single Flash connected to port A" + }, + { + "name": "ParallelMode", + "value": 1, + "description": "Parallel mode" + }, + { + "name": "SingleFlashPort_B", + "value": 2, + "description": "Single Flash connected to port B" + } + ] + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_mmc.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_mmc.json new file mode 100644 index 0000000..c306f94 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_mmc.json @@ -0,0 +1,430 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "MMC card Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bit0", + "width": 1, + "name": "BootConfigEnable", + "access": "RW", + "description": "Boot configuration", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Boot configuration disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Boot configuration enabled" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bit2", + "width": 1, + "name": "BootAcknowledge", + "access": "RW", + "description": "Boot acknowledge", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Boot acknowledge disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Boot acknowledge enabled" + } + ] + }, + { + "id": "field000-bit3", + "width": 1, + "name": "ResetBootBusConditions", + "access": "RW", + "description": "Reset boot BUS conditions", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Don't change BUS conditions" + }, + { + "name": "Enabled", + "value": 1, + "description": "Reset boot BUS conditions" + } + ] + }, + { + "id": "field000-bits4-5", + "width": 2, + "name": "BootMode", + "access": "RW", + "description": "Boot mode configuration", + "values": [ + { + "name": "SDRWithDefaultTiming", + "value": 0, + "description": "Single data rate with backward compatible timings" + }, + { + "name": "SDRWithHighSpeedTiming", + "value": 1, + "description": "Single data rate with high speed timing" + }, + { + "name": "DDRTiming", + "value": 2, + "description": "Dual date rate" + } + ] + }, + { + "width": 2 + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "BusWidth", + "access": "RW", + "description": "MMC card data bus width(BUS_WIDTH in Extended CSD)", + "values": [ + { + "name": "1bit", + "value": 0, + "description": "MMC data bus width is 1 bit" + }, + { + "name": "4bit", + "value": 1, + "description": "MMC data bus width is 4 bits" + }, + { + "name": "8bit", + "value": 2, + "description": "MMC data bus width is 8 bits" + }, + { + "name": "4bitDDR", + "value": 5, + "description": "MMC data bus width is 4 bits ddr" + }, + { + "name": "8bitDDR", + "value": 6, + "description": "MMC data bus width is 8 bits ddr" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "TimingMode", + "access": "RW", + "description": "MMC card high-speed timing(HS_TIMING in Extended CSD)", + "values": [ + { + "name": "HighSpeedTimingNone", + "value": 0, + "description": "MMC card using none high-speed timing" + }, + { + "name": "HighSpeedTiming", + "value": 1, + "description": "MMC card using high-speed timing" + }, + { + "name": "HighSpeed200Timing", + "value": 2, + "description": "MMC card high speed 200 timing" + }, + { + "name": "HighSpeed400Timing", + "value": 3, + "description": "MMC card high speed 400 timing" + }, + { + "name": "HighSpeed26MHZTiming", + "value": 4, + "description": "MMC high speed 26MHZ timing" + }, + { + "name": "HighSpeed52MHZTiming", + "value": 5, + "description": "MMC high speed 52MHZ timing" + }, + { + "name": "HighSpeedDDR52Timing", + "value": 6, + "description": "MMC high speed timing DDR52 1.8V" + } + ] + }, + { + "id": "field000-bits16-17", + "width": 2, + "name": "BootBusWidth", + "access": "RW", + "description": "MMC card boot bus width(BOOT_BUS_WIDTH in Extended CSD)", + "values": [ + { + "name": "1bitSDR4bitDDR", + "value": 0, + "description": "x1 (sdr) or x4 (ddr) bus width in boot operation mode(default)" + }, + { + "name": "4bitSDR4bitDDR", + "value": 1, + "description": "x4 (sdr/ddr) bus width in boot operation mode" + }, + { + "name": "8bitSDR8bitDDR", + "value": 2, + "description": "x8 (sdr/ddr) bus width in boot operation mode" + } + ] + }, + { + "width": 2 + }, + { + "id": "field000-bits20-22", + "width": 3, + "name": "BootPartitionEnabled", + "access": "RW", + "description": "MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD)", + "values": [ + { + "name": "Not", + "value": 0, + "description": "Device not boot enabled (default)" + }, + { + "name": "Partition1", + "value": 1, + "description": "Boot partition 1 enabled for boot" + }, + { + "name": "Partition2", + "value": 2, + "description": "Boot partition 2 enabled for boot" + }, + { + "name": "UserAera", + "value": 7, + "description": "User area enabled for boot" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bits24-26", + "width": 3, + "name": "PartitionAccess", + "access": "RW", + "description": "MMC card partition to be accessed(BOOT_PARTITION_ACCESS in Extended CSD)", + "values": [ + { + "name": "PartitionUserAera", + "value": 0, + "description": "No access to boot partition (default), normal partition" + }, + { + "name": "PartitionBoot1", + "value": 1, + "description": "Read/Write boot partition 1" + }, + { + "name": "PartitionBoot2", + "value": 2, + "description": "Read/Write boot partition 2" + }, + { + "name": "RPMB", + "value": 3, + "description": "Replay protected mem block" + }, + { + "name": "GeneralPurposePartition1", + "value": 4, + "description": "access to general purpose partition 1" + }, + { + "name": "GeneralPurposePartition2", + "value": 5, + "description": "access to general purpose partition 2" + }, + { + "name": "GeneralPurposePartition3", + "value": 6, + "description": "access to general purpose partition 3" + }, + { + "name": "GeneralPurposePartition4", + "value": 7, + "description": "access to general purpose partition 4" + } + ] + }, + { + "width": 1 + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "MMC card Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-3", + "width": 4, + "name": "Instance", + "access": "RW", + "description": "MMC peripheral instance" + }, + { + "width": 2 + }, + { + "width": 10 + }, + { + "width": 2 + }, + { + "id": "field004-bit18", + "width": 1, + "name": "1V8", + "access": "RW", + "description": "MMC interface BUS use 1V8", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "1V8 disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1V8 enabled" + } + ] + }, + { + "id": "field004-bit19", + "width": 1, + "name": "EnablePowerCycle", + "access": "RW", + "description": "Execute power cycle before initialization", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Power cycle disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Execute power cycle before initialization" + } + ] + }, + { + "id": "field004-bit20", + "width": 1, + "name": "PowerUpDelay", + "access": "RW", + "description": "Set power up delay", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "width": 2 + }, + { + "id": "field004-bit23", + "width": 1, + "name": "PowerUpPolarity", + "access": "RW", + "description": "Power up polarity - May vary on different devices" + }, + { + "id": "field004-bits24-25", + "width": 2, + "name": "PowerDownTime", + "access": "RW", + "description": "Set power down time", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "Power up delay 20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "Power up delay 10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "width": 2 + }, + { + "width": 4 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_sd.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_sd.json new file mode 100644 index 0000000..a7994bf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_sd.json @@ -0,0 +1,183 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "SD card Configuration Option 0", + "default_value_int": "0xd0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "Instance", + "access": "RW", + "description": "SD peripheral instance" + }, + { + "width": 4 + }, + { + "id": "field000-bit8", + "width": 1, + "name": "BusWidth", + "access": "RW", + "description": "SD interface BUS width", + "values": [ + { + "name": "1bit", + "value": 0, + "description": "BUS width 1 bit" + }, + { + "name": "4bit", + "value": 1, + "description": "BUS width 4 bit" + } + ] + }, + { + "id": "field000-bits9-11", + "width": 3, + "name": "TunningStart", + "access": "RW", + "description": "Tunning start - the final value will be multiplicated by 32" + }, + { + "id": "field000-bits12-14", + "width": 3, + "name": "TimingMode", + "access": "RW", + "description": "SD card timing mode flags", + "values": [ + { + "name": "SDR12DefaultMode", + "value": 0, + "description": "Identification mode and SDR12" + }, + { + "name": "SDR25HighSpeedMode", + "value": 1, + "description": "High speed mode and SDR25" + }, + { + "name": "SDR50Mode", + "value": 2, + "description": "SDR50 mode" + }, + { + "name": "SDR104Mode", + "value": 3, + "description": "SDR104 mode" + }, + { + "name": "DDR50Mode", + "value": 4, + "description": "DDR50 mode" + } + ] + }, + { + "width": 4 + }, + { + "id": "field000-bit19", + "width": 1, + "name": "EnablePowerCycle", + "access": "RW", + "description": "Execute power cycle before initialization", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Power cycle disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Execute power cycle before initialization" + } + ] + }, + { + "id": "field000-bit20", + "width": 1, + "name": "PowerUpDelay", + "access": "RW", + "description": "Set power up delay", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "id": "field000-bits21-22", + "width": 2, + "name": "TunningStep", + "access": "RW", + "description": "Tunning step - the final value will be multiplicated by 2. In case of zero it used value 1" + }, + { + "id": "field000-bit23", + "width": 1, + "name": "PowerUpPolarity", + "access": "RW", + "description": "Power up polarity - May vary on different devices" + }, + { + "id": "field000-bits24-25", + "width": 2, + "name": "PowerDownTime", + "access": "RW", + "description": "Set power down time", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "Power up delay 20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "Power up delay 10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "Power up delay 5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "Power up delay 2.5ms" + } + ] + }, + { + "width": 2 + }, + { + "width": 4 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nand.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nand.json new file mode 100644 index 0000000..1daa119 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nand.json @@ -0,0 +1,195 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "SEMC NAND Configuration Option 0", + "default_value_int": "0xd0000100", + "bitfields": [ + { + "id": "field000-bits0-2", + "width": 3, + "name": "OnfiVersion", + "access": "RW", + "description": "ONFI version" + }, + { + "id": "field000-bit3", + "width": 1, + "name": "EdoMode", + "access": "RW", + "description": "EDO mode", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "EDO mode disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "EDO mode enabled" + } + ] + }, + { + "id": "field000-bits4-6", + "width": 3, + "name": "OnfiTimingMode", + "access": "RW", + "description": "ONFI Timing mode", + "values": [ + { + "name": "10MHz", + "value": 0, + "description": "Mode 0, 10MHz" + }, + { + "name": "20MHz", + "value": 1, + "description": "Mode 1, 20MHz" + }, + { + "name": "28MHz", + "value": 2, + "description": "Mode 2, 28MHz" + }, + { + "name": "33MHz", + "value": 3, + "description": "Mode 3, 33MHz" + }, + { + "name": "40MHz", + "value": 4, + "description": "Mode 4, 40MHz" + }, + { + "name": "50MHz", + "value": 5, + "description": "Mode 5, 50MHz" + }, + { + "name": "Fastest0", + "value": 6, + "description": "Mode 6, Fastest mode 0" + }, + { + "name": "Fastest1", + "value": 7, + "description": "Mode 7, Fastest mode 1" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bits8-9", + "width": 2, + "name": "IoPortDiv8", + "access": "RW", + "description": "IO port size, Minimum is 1" + }, + { + "width": 2 + }, + { + "id": "field000-bits12-14", + "width": 3, + "name": "PcsSelection", + "access": "RW", + "description": "SEMC NAND PCS selection", + "values": [ + { + "name": "CSX0", + "value": 0, + "description": "SEMC NAND CSX0" + }, + { + "name": "CSX1", + "value": 1, + "description": "SEMC NAND CSX1" + }, + { + "name": "CSX2", + "value": 2, + "description": "SEMC NAND CSX2" + }, + { + "name": "CSX3", + "value": 3, + "description": "SEMC NAND CSX3" + }, + { + "name": "A8", + "value": 4, + "description": "SEMC NAND A8" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bit16", + "width": 1, + "name": "EccType", + "access": "RW", + "description": "ECC type", + "values": [ + { + "name": "SW", + "value": 0, + "description": "Software ECC" + }, + { + "name": "HW", + "value": 1, + "description": "Hardware ECC" + } + ] + }, + { + "id": "field000-bit17", + "width": 1, + "name": "EccStatus", + "access": "RW", + "description": "ECC status", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "ECC enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "ECC disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nor.json new file mode 100644 index 0000000..cd0f2ba --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_semc_nor.json @@ -0,0 +1,289 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "SEMC NOR Configuration Option 0", + "default_value_int": "0xd0000100", + "bitfields": [ + { + "id": "field000-bits0-1", + "width": 2, + "name": "CommandSet", + "access": "RW", + "description": "SEMC Parallel NOR Flash command set", + "values": [ + { + "name": "EPSCD", + "value": 0, + "description": "As Micron MT28EW Embedded Parallel NOR Standard Command Definitions" + }, + { + "name": "SFMCD", + "value": 1, + "description": "As Micron MT28GU StrataFlash Memory Command Definitions" + } + ] + }, + { + "id": "field000-bits2-3", + "width": 2, + "name": "AcTimingMode", + "access": "RW", + "description": "SEMC Parallel NOR AC timing mode (Async read mode)", + "values": [ + { + "name": "DefaultSafe", + "value": 0, + "description": "Timing default safe" + }, + { + "name": "DefaultSast", + "value": 1, + "description": "Timing default fast" + }, + { + "name": "UserDefined", + "value": 2, + "description": "Timing user defined. The definition (next 6 option words) MUST follow this option word" + } + ] + }, + { + "width": 4 + }, + { + "id": "field000-bits8-9", + "width": 2, + "name": "IoPortDiv8", + "access": "RW", + "description": "IO port size, Minimum is 1" + }, + { + "id": "field000-bit10", + "width": 1, + "name": "AdvPortPolarity", + "access": "RW", + "description": "ADV# polarity", + "values": [ + { + "name": "Low", + "value": 0, + "description": "ADV polarity low" + }, + { + "name": "High", + "value": 1, + "description": "ADV polarity high" + } + ] + }, + { + "width": 1 + }, + { + "id": "field000-bits12-14", + "width": 3, + "name": "PcsSelection", + "access": "RW", + "description": "SEMC NOR PCS selection", + "values": [ + { + "name": "CSX0", + "value": 0, + "description": "SEMC NOR CSX0" + }, + { + "name": "CSX1", + "value": 1, + "description": "SEMC NOR CSX1" + }, + { + "name": "CSX2", + "value": 2, + "description": "SEMC NOR CSX2" + }, + { + "name": "CSX3", + "value": 3, + "description": "SEMC NOR CSX3" + }, + { + "name": "A8", + "value": 4, + "description": "SEMC NOR A8" + }, + { + "name": "RDY", + "value": 5, + "description": "SEMC NOR RDY" + } + ] + }, + { + "width": 1 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "SEMC NOR Configuration Option 1 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-15", + "width": 16, + "name": "min_tCEH_ns", + "access": "RW", + "description": "User definition min_tCEH_ns" + }, + { + "id": "field004-bits16-31", + "width": 16, + "name": "min_tCES_ns", + "access": "RW", + "description": "User definition min_tCES_ns" + } + ] + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "ConfigOption2", + "description": "SEMC NOR Configuration Option 2 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field008-bits0-15", + "width": 16, + "name": "min_tAS_ns", + "access": "RW", + "description": "User definition min_tAS_ns" + }, + { + "id": "field008-bits16-31", + "width": 16, + "name": "min_tCEITV_ns", + "access": "RW", + "description": "User definition min_tCEITV_ns" + } + ] + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "ConfigOption3", + "description": "SEMC NOR Configuration Option 3 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field00C-bits0-15", + "width": 16, + "name": "min_tTA_ns", + "access": "RW", + "description": "User definition min_tTA_ns" + }, + { + "id": "field00C-bits16-31", + "width": 16, + "name": "min_tAH_ns", + "access": "RW", + "description": "User definition min_tAH_ns" + } + ] + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "ConfigOption4", + "description": "SEMC NOR Configuration Option 4 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field010-bits0-15", + "width": 16, + "name": "min_tWEH_ns", + "access": "RW", + "description": "User definition min_tWEH_ns" + }, + { + "id": "field010-bits16-31", + "width": 16, + "name": "min_tWEL_ns", + "access": "RW", + "description": "User definition min_tWEL_ns" + } + ] + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "ConfigOption5", + "description": "SEMC NOR Configuration Option 5 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-15", + "width": 16, + "name": "min_tREL_ns", + "access": "RW", + "description": "User definition min_tREL_ns" + }, + { + "id": "field014-bits16-31", + "width": 16, + "name": "min_tAWDH_ns", + "access": "RW", + "description": "User definition min_tAWDH_ns" + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "ConfigOption6", + "description": "SEMC NOR Configuration Option 6 - User definition - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 16 + }, + { + "id": "field018-bits16-31", + "width": 16, + "name": "max_tREH_ns", + "access": "RW", + "description": "User definition max_tREH_ns" + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor.json new file mode 100644 index 0000000..263a16d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor.json @@ -0,0 +1,356 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NOR Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "PageSize", + "access": "RW", + "description": "Page size of the NOR flash device", + "values": [ + { + "name": "256B", + "value": 0, + "description": "Page size 256B" + }, + { + "name": "512B", + "value": 1, + "description": "Page size 512B" + }, + { + "name": "1MB", + "value": 2, + "description": "Page size 1MB" + }, + { + "name": "32B", + "value": 3, + "description": "Page size 32B" + }, + { + "name": "64B", + "value": 4, + "description": "Page size 64B" + }, + { + "name": "128B", + "value": 5, + "description": "Page size 128B" + } + ] + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "SectorSize", + "access": "RW", + "description": "Sector size of the NOR flash device", + "values": [ + { + "name": "4KB", + "value": 0, + "description": "Page size 4KB" + }, + { + "name": "8KB", + "value": 1, + "description": "Page size 8KB" + }, + { + "name": "32KB", + "value": 2, + "description": "Page size 32KB" + }, + { + "name": "64KB", + "value": 3, + "description": "Page size 64KB" + }, + { + "name": "128KB", + "value": 4, + "description": "Page size 128KB" + }, + { + "name": "256KB", + "value": 5, + "description": "Page size 256KB" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "MemorySize", + "access": "RW", + "description": "Memory capacity of the NOR flash device", + "values": [ + { + "name": "512KB", + "value": 0, + "description": "Page size 512KB" + }, + { + "name": "1MB", + "value": 1, + "description": "Page size 1MB" + }, + { + "name": "2MB", + "value": 2, + "description": "Page size 2MB" + }, + { + "name": "4MB", + "value": 3, + "description": "Page size 4MB" + }, + { + "name": "8MB", + "value": 4, + "description": "Page size 8MB" + }, + { + "name": "16MB", + "value": 5, + "description": "Page size 16MB" + }, + { + "name": "32MB", + "value": 6, + "description": "Page size 32MB" + }, + { + "name": "64MB", + "value": 7, + "description": "Page size 64MB" + }, + { + "name": "128MB", + "value": 8, + "description": "Page size 128MB" + }, + { + "name": "256MB", + "value": 9, + "description": "Page size 256MB" + }, + { + "name": "512MB", + "value": 10, + "description": "Page size 512MB" + }, + { + "name": "1GB", + "value": 11, + "description": "Page size 1GB" + }, + { + "name": "32KB", + "value": 12, + "description": "Page size 32KB" + }, + { + "name": "64KB", + "value": 13, + "description": "Page size 64KB" + }, + { + "name": "128KB", + "value": 14, + "description": "Page size 128KB" + }, + { + "name": "256KB", + "value": 15, + "description": "Page size 256KB" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "MemoryType", + "access": "RW", + "description": "Memory type used to configure and access the NOR flash", + "values": [ + { + "name": "NorFlash", + "value": 0, + "description": "SPI NOR FLASH" + }, + { + "name": "EEPROM", + "value": 1, + "description": "SPI EEPROM" + }, + { + "name": "Terminator", + "value": 2, + "description": "Terminator" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "PcsIndex", + "access": "RW", + "description": "PCS index used by SPI to access serial NOR flash", + "values": [ + { + "name": "PCS0", + "value": 0, + "description": "Use SPIx PCS0" + }, + { + "name": "PCS1", + "value": 1, + "description": "Use SPIx PCS1" + }, + { + "name": "PCS2", + "value": 2, + "description": "Use SPIx PCS2" + }, + { + "name": "PCS3", + "value": 3, + "description": "Use SPIx PCS3" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "SpiIndex", + "access": "RW", + "description": "SPI interface used to access serial NOR flash", + "values": [ + { + "name": "SPI0", + "value": 0, + "description": "Use SPI0" + }, + { + "name": "SPI1", + "value": 1, + "description": "Use SPI1" + }, + { + "name": "SPI2", + "value": 2, + "description": "Use SPI2" + }, + { + "name": "SPI3", + "value": 3, + "description": "Use SPI3" + }, + { + "name": "SPI4", + "value": 4, + "description": "Use SPI4" + }, + { + "name": "SPI5", + "value": 5, + "description": "Use SPI5" + }, + { + "name": "SPI6", + "value": 6, + "description": "Use SPI6" + }, + { + "name": "SPI7", + "value": 7, + "description": "Use SPI7" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "OptionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OptionSize1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OptionSize2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "SPI NOR flash Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-3", + "width": 4, + "name": "SpiSpeed", + "access": "RW", + "description": "Spi NOR/EEPROM module clock freq", + "values": [ + { + "name": "20MHz", + "value": 0, + "description": "SPI Clock set to 20MHz" + }, + { + "name": "10MHz", + "value": 1, + "description": "SPI Clock set to 10MHz" + }, + { + "name": "5MHz", + "value": 2, + "description": "SPI Clock set to 5MHz" + }, + { + "name": "2MHz", + "value": 3, + "description": "SPI Clock set to 2MHz" + } + ] + }, + { + "width": 28 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor_legacy.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor_legacy.json new file mode 100644 index 0000000..dc90949 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_spi_nor_legacy.json @@ -0,0 +1,267 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NOR Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "PageSize", + "access": "RW", + "description": "Page size of the NOR flash device", + "values": [ + { + "name": "256B", + "value": 0, + "description": "Page size 256B" + }, + { + "name": "512B", + "value": 1, + "description": "Page size 512B" + }, + { + "name": "1MB", + "value": 2, + "description": "Page size 1MB" + }, + { + "name": "32B", + "value": 3, + "description": "Page size 32B" + }, + { + "name": "64B", + "value": 4, + "description": "Page size 64B" + }, + { + "name": "128B", + "value": 5, + "description": "Page size 128B" + } + ] + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "SectorSize", + "access": "RW", + "description": "Sector size of the NOR flash device", + "values": [ + { + "name": "4KB", + "value": 0, + "description": "Page size 4KB" + }, + { + "name": "8KB", + "value": 1, + "description": "Page size 8KB" + }, + { + "name": "32KB", + "value": 2, + "description": "Page size 32KB" + }, + { + "name": "64KB", + "value": 3, + "description": "Page size 64KB" + }, + { + "name": "128KB", + "value": 4, + "description": "Page size 128KB" + }, + { + "name": "256KB", + "value": 5, + "description": "Page size 256KB" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "MemorySize", + "access": "RW", + "description": "Memory capacity of the NOR flash device", + "values": [ + { + "name": "512KB", + "value": 0, + "description": "Page size 512KB" + }, + { + "name": "1MB", + "value": 1, + "description": "Page size 1MB" + }, + { + "name": "2MB", + "value": 2, + "description": "Page size 2MB" + }, + { + "name": "4MB", + "value": 3, + "description": "Page size 4MB" + }, + { + "name": "8MB", + "value": 4, + "description": "Page size 8MB" + }, + { + "name": "16MB", + "value": 5, + "description": "Page size 16MB" + }, + { + "name": "32MB", + "value": 6, + "description": "Page size 32MB" + }, + { + "name": "64MB", + "value": 7, + "description": "Page size 64MB" + }, + { + "name": "128MB", + "value": 8, + "description": "Page size 128MB" + }, + { + "name": "256MB", + "value": 9, + "description": "Page size 256MB" + }, + { + "name": "512MB", + "value": 10, + "description": "Page size 512MB" + }, + { + "name": "1GB", + "value": 11, + "description": "Page size 1GB" + }, + { + "name": "32KB", + "value": 12, + "description": "Page size 32KB" + }, + { + "name": "64KB", + "value": 13, + "description": "Page size 64KB" + }, + { + "name": "128KB", + "value": 14, + "description": "Page size 128KB" + }, + { + "name": "256KB", + "value": 15, + "description": "Page size 256KB" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "MemoryType", + "access": "RW", + "description": "Memory type used to configure and access the NOR flash", + "values": [ + { + "name": "Manual", + "value": 0, + "description": "Configure manually based on configure option block" + }, + { + "name": "Auto", + "value": 2, + "description": "AutoConfigure the Nor flash via SFDP info" + } + ] + }, + { + "width": 4 + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "SpiIndex", + "access": "RW", + "description": "SPI interface used to access serial NOR flash", + "values": [ + { + "name": "SPI0", + "value": 0, + "description": "Use SPI0" + }, + { + "name": "SPI1", + "value": 1, + "description": "Use SPI1" + }, + { + "name": "SPI2", + "value": 2, + "description": "Use SPI2" + }, + { + "name": "SPI3", + "value": 3, + "description": "Use SPI3" + }, + { + "name": "SPI4", + "value": 4, + "description": "Use SPI4" + }, + { + "name": "SPI5", + "value": 5, + "description": "Use SPI5" + }, + { + "name": "SPI6", + "value": 6, + "description": "Use SPI6" + }, + { + "name": "SPI7", + "value": 7, + "description": "Use SPI7" + } + ] + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_xspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_xspi_nor.json new file mode 100644 index 0000000..12a4c16 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/memcfg/opt_word_xspi_nor.json @@ -0,0 +1,318 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "ConfigOption0", + "description": "FlexSPI NOR Configuration Option 0", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-3", + "width": 4, + "name": "MaxFreq", + "access": "RW", + "description": "The maximum work frequency for specified Flash device", + "values": [ + { + "name": "NoChange", + "value": 0, + "description": "Don't change FlexSPI clock setting" + }, + { + "name": "30Mhz", + "value": 1, + "description": "30MHz" + }, + { + "name": "50Mhz", + "value": 2, + "description": "50MHz" + }, + { + "name": "60Mhz", + "value": 3, + "description": "60MHz" + }, + { + "name": "80Mhz", + "value": 4, + "description": "80MHz" + }, + { + "name": "100Mhz", + "value": 5, + "description": "100MHz" + }, + { + "name": "120Mhz", + "value": 6, + "description": "120MHz" + }, + { + "name": "133Mhz", + "value": 7, + "description": "133MHz" + }, + { + "name": "166Mhz", + "value": 8, + "description": "166MHz" + }, + { + "name": "200Mhz", + "value": 8, + "description": "200MHz" + } + ] + }, + { + "id": "field000-bits4-7", + "width": 4, + "name": "Misc", + "access": "RW", + "description": "Specify miscellaneous mode for selected flash type; Experimental feature, do not use in products, keep it as 0.", + "values": [ + { + "name": "NotEnabled", + "value": 0, + "description": "Miscellaneous mode is not enabled" + }, + { + "name": "Mode0-4-4", + "value": 1, + "description": "Enable 0-4-4 mode for High Random Read performance" + }, + { + "name": "SwappedMode", + "value": 3, + "description": " Data Order Swapped mode (for MXIC OctaFlash only)" + } + ] + }, + { + "id": "field000-bits8-11", + "width": 4, + "name": "QuadEnableType", + "access": "RW", + "description": "Specify the Quad Enable sequence, only applicable for device that only JESD216 compliant, this field is ignored if device support JESD216A or later version. This field will be effective only if device is compliant with JESD216 only (9 longword SDFP table)", + "values": [ + { + "name": "NotConfigure", + "value": 0, + "description": "Not Configured" + }, + { + "name": "Bit6InSR1", + "value": 1, + "description": "QE bit is bit6 in StatusReg1" + }, + { + "name": "Bit1InSR2", + "value": 2, + "description": "QE bit is bit1 in StatusReg2" + }, + { + "name": "Bit7InSR2", + "value": 3, + "description": "QE bit is bit7 in StatusReg2" + }, + { + "name": "Bit1InSR2EnableCmdIs0x31", + "value": 4, + "description": "QE bit is bit1 in StatusReg2, enable command is 0x31" + } + ] + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "CMDPad(s)", + "access": "RW", + "description": "Commands pads for the Flash device (1/4/8), for device that works under 1-1-4,1-4-4,1-1-8 or 1-8-8 mode, CMD pad(s) value is always 0x0, for devices that only support 4-4-4 mode for high performance, CMD pads value is 2, for devices that only support 8-8-8 mode for high performance, CMD pads value is 3", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "Query CMDPad(s)", + "access": "RW", + "description": "Command pads (1/4/8) for the SFDP command", + "values": [ + { + "name": "1", + "value": 0, + "description": "1 bit" + }, + { + "name": "4", + "value": 2, + "description": "4 bits" + }, + { + "name": "8", + "value": 3, + "description": "8 bits" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "Device Detection Type", + "access": "RW", + "description": "SW defined device types used for config block autodetection", + "values": [ + { + "name": "QuadSPI_SDR", + "value": 0, + "description": "QuadSPI SDR" + }, + { + "name": "QuadSPI_DDR", + "value": 1, + "description": "QuadSPI DDR" + }, + { + "name": "HyperFLASH_3V", + "value": 3, + "description": "HyperFLASH 3V" + }, + { + "name": "MXICOPI_DDR", + "value": 4, + "description": "MXICOPI DDR" + }, + { + "name": "MicronOPI_DDR", + "value": 6, + "description": "MicronOPI DDR" + }, + { + "name": "AdestoOPI_DDR", + "value": 8, + "description": "AdestoOPI DDR" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "OptionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OptionSize1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OptionSize2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "ConfigOption1", + "description": "FlexSPI NOR Flash Configuration Option 1 - Optional", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "DummyCycles", + "access": "RW", + "description": "User provided dummy cycles for SDR/DDR read command: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "StatusOverride", + "access": "RW", + "description": "Override status register value during device mode configuration" + }, + { + "id": "field004-bits16-19", + "width": 4, + "name": "PinMuxGroup", + "access": "RW", + "description": "Pin multiplexer group selection" + }, + { + "id": "field004-bits20-23", + "width": 4, + "name": "DqsPinMuxGroup", + "access": "RW", + "description": "DQS Pin multiplexer group selection" + }, + { + "id": "field004-bits24-27", + "width": 4, + "name": "PinDriveStrength", + "access": "RW", + "description": "The Drive Strength of FlexSPI Pads" + }, + { + "id": "field004-bits28-31", + "width": 4, + "name": "FlashConnection", + "access": "RW", + "description": "Select the FlexSPI Port A/B", + "values": [ + { + "name": "SingleFlashPort_A", + "value": 0, + "description": "Single Flash connected to port A" + }, + { + "name": "ParallelMode", + "value": 1, + "description": "Parallel mode" + }, + { + "name": "SingleFlashPort_B", + "value": 2, + "description": "Single Flash connected to port B" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/pfrc_rules.yaml new file mode 100644 index 0000000..c1c8924 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/pfrc_rules.yaml @@ -0,0 +1,77 @@ +# Copyright 2020-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "1.1" + desc: + Never write any non-zero configuration into DCFG_CC_SOCU_NS_PIN before DCFG_CC_SOCU_PIN + contains any valid (non-zero) configuration. + msg: The CMPA.DCFG_CC_SOCU_PIN[0:9] must be set in case the CFPA.DCFG_CC_SOCU_NS_PIN[0:9] is set. + cond: any(True if (((CFPA.DCFG_CC_SOCU_NS_PIN >> index) & 1) and not ((CMPA.DCFG_CC_SOCU_PIN >> index) & 1)) else False for index in range(0, int(10))) + + - req_id: "1.2" + desc: + Never write any non-zero configuration into DCFG_CC_SOCU_NS_DFLT before DCFG_CC_SOCU_DFLT + contains any valid (non-zero) configuration. + msg: The CMPA.DCFG_CC_SOCU_DFLT[0:9] must be set in case the CFPA.DCFG_CC_SOCU_NS_DFLT[0:9] is set. + cond: any(True if (((CFPA.DCFG_CC_SOCU_NS_DFLT >> index) & 1) and not ((CMPA.DCFG_CC_SOCU_DFLT >> index) & 1)) else False for index in range(0, int(10))) + + - req_id: "1.3" + desc: Inverse value (upper 16 bits) of DCFG_CC_SOCU_PIN must be always + valid. Only exception are blank devices where CC_SOCU_PIN contains all + zeros. + msg: Inverse values are generated automatically based on configuration. + cond: CMPA.DCFG_CC_SOCU_PIN != 0 and (~(CMPA.DCFG_CC_SOCU_PIN>>int(16)) & 0xFFFF) != (CMPA.DCFG_CC_SOCU_PIN & 0xFFFF) + + - req_id: "1.4" + desc: Inverse value (upper 16 bits) of DCFG_CC_SOCU_DFLT must be always + valid. Only exception are blank devices where CC_SOCU_DFLT contains all + zeros. + msg: Inverse values are generated automatically based on configuration. + cond: CMPA.DCFG_CC_SOCU_DFLT != 0 and (~(CMPA.DCFG_CC_SOCU_DFLT>>int(16)) & 0xFFFF) != (CMPA.DCFG_CC_SOCU_DFLT & 0xFFFF) + + - req_id: "1.5" + desc: Inverse value (upper 16 bits) of DCFG_CC_SOCU_NS_PIN must be always + valid. Only exception are blank devices where CC_SOCU_xxx contains all + zeros. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.DCFG_CC_SOCU_NS_PIN != 0 and (~(CFPA.DCFG_CC_SOCU_NS_PIN>>int(16)) & 0xFFFF) != (CFPA.DCFG_CC_SOCU_NS_PIN & 0xFFFF) + + - req_id: "1.6" + desc: Inverse value (upper 16 bits) of DCFG_CC_SOCU_NS_DFLT must be always + valid. Only exception are blank devices where CC_SOCU_DFLT contains all + zeros. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.DCFG_CC_SOCU_NS_DFLT != 0 and (~(CFPA.DCFG_CC_SOCU_NS_DFLT>>int(16)) & 0xFFFF) != (CFPA.DCFG_CC_SOCU_NS_DFLT & 0xFFFF) + + - req_id: "1.7" + desc: + Do not write invalid PIN/DFLT configuration in CMPA area. Setting PIN bit + to 0 and DFLT bit to 1 for given feature is not allowed + msg: Invalid bit combination. If CMPA.DCFG_CC_SOCU_PIN[0:9] is 0, CMPA.DCFG_CC_SOCU_DFLT[0:9] can't be set to 1! + cond: any(True if (not ((CMPA.DCFG_CC_SOCU_PIN >> index) & 1) and ((CMPA.DCFG_CC_SOCU_DFLT >> index) & 1)) else False for index in range(0, int(10))) + + - req_id: "1.8" + desc: + Do not write invalid PIN/DFLT configuration in CFPA area. Setting PIN bit + to 0 and DFLT bit to 1 for given feature is not allowed + msg: Invalid bit combination. If CFPA.DCFG_CC_SOCU_NS_PIN[0:9] is 0, CFPA.DCFG_CC_SOCU_NS_DFLT[0:9] can't be set to 1! + cond: any(True if (not ((CFPA.DCFG_CC_SOCU_NS_PIN >> index) & 1) and ((CFPA.DCFG_CC_SOCU_NS_DFLT >> index) & 1)) else False for index in range(0, int(10))) + + - req_id: "1.9" + desc: If CMPA DCFG_CC_SOCU_DFLT is used the DCFG_CC_SOCU_PIN must be used also. + msg: The CMPA DCFG_CC_SOCU_PIN is not set, but the DCFG_CC_SOCU_DFLT is defined. + cond: CMPA.DCFG_CC_SOCU_DFLT != 0 and CMPA.DCFG_CC_SOCU_PIN==0 + + - req_id: "1.10" + desc: If CMPA DCFG_CC_SOCU_PIN is used the DCFG_CC_SOCU_DFLT must be used also. + msg: The CMPA DCFG_CC_SOCU_DFLT is not set, but the DCFG_CC_SOCU_PIN is defined. + cond: CMPA.DCFG_CC_SOCU_PIN != 0 and CMPA.DCFG_CC_SOCU_DFLT==0 + + - req_id: "2.1" + desc: + This CMPA_PROG_IN_PROGRESS must be always 0x00000000. Only ROM bootloader + is allowed to write anything to this field. + msg: The CMPA_PROG_IN_PROGRESS must be set to 0! + cond: CFPA.CMPA_PROG_IN_PROGRESS != 0 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_all.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_all.lst new file mode 100644 index 0000000..d868d05 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_all.lst @@ -0,0 +1,38 @@ +uuu_version 1.4.149 + +# @_flash.bin | bootloader, which can extract from wic image +# @_image [_flash.bin] | wic image burn to emmc. + + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin -scanlimited 0x800000 + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -scanterm -f _flash.bin -scanlimited 0x800000 + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump -scanlimited 0x800000 +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl -scanterm -scanlimited 0x800000 +SDPV: jump -scanlimited 0x800000 +# } + + +FB: ucmd setenv fastboot_dev mmc +FB: ucmd setenv mmcdev ${emmc_dev} +FB: ucmd mmc dev ${emmc_dev} +FB: flash -raw2sparse all _image +FB: flash -scanterm -scanlimited 0x800000 bootloader _flash.bin +FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; +FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_loader.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_loader.lst new file mode 100644 index 0000000..27128fe --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/emmc_burn_loader.lst @@ -0,0 +1,35 @@ +uuu_version 1.2.39 + +# @_flash.bin | bootloader +# @_image [_flash.bin] | image burn to emmc, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -f _flash.bin + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl +SDPV: jump +# } + +FB: ucmd setenv fastboot_dev mmc +FB: ucmd setenv mmcdev ${emmc_dev} +FB: ucmd mmc dev ${emmc_dev} +FB: flash bootloader _image +FB: ucmd if env exists emmc_ack; then ; else setenv emmc_ack 0; fi; +FB: ucmd mmc partconf ${emmc_dev} ${emmc_ack} 1 0 +FB: Done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fat_write.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fat_write.lst new file mode 100644 index 0000000..5949aff --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fat_write.lst @@ -0,0 +1,12 @@ +uuu_version 1.1.4 + +# @_image | image, which cp to fat partition +# @_device | storage device, mmc\sata +# @_partition | fat partition number, like 1:1 +# @_filename [_image] | file name in target fat partition, only support rootdir now + +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: download -f _image +FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi +FB[-t 20000]: ucmd fatwrite _device _partition ${fastboot_buffer} _filename ${fastboot_bytes} +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fspinand_burn_loader.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fspinand_burn_loader.lst new file mode 100644 index 0000000..2a31f63 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/fspinand_burn_loader.lst @@ -0,0 +1,36 @@ +uuu_version 1.2.39 + +# @_flexspi.bin | bootloader +# @_image [_flexspi.bin] | image burn to fspinand, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flexspi.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM, skip QSPI header +SDPS: boot -f _flexspi.bin -skipfhdr + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flexspi.bin -offset 0x10000 -skipfhdr +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flexspi.bin -skipspl -skipfhdr +SDPV: jump +# } + +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: download -f _image + +FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi + +FB[-t 60000]: ucmd fspinand init spi-nand0 ${fastboot_buffer} ${fastboot_bytes} + +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nand_burn_loader.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nand_burn_loader.lst new file mode 100644 index 0000000..d81e3cc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nand_burn_loader.lst @@ -0,0 +1,35 @@ +uuu_version 1.2.39 + +# @_flash.bin | bootloader +# @_image [_flash.bin] | image burn to nand, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -f _flash.bin + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl +SDPV: jump +# } + +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: download -f _image +FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi +# Burn image to nandfit partition if needed +FB: ucmd if env exists nandfit_part; then nand erase.part nandfit; nand write ${fastboot_buffer} nandfit ${fastboot_bytes}; else true; fi; +FB: ucmd nandbcb init ${fastboot_buffer} nandboot ${fastboot_bytes} +FB: Done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nvme_burn_all.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nvme_burn_all.lst new file mode 100644 index 0000000..41e6bff --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/nvme_burn_all.lst @@ -0,0 +1,34 @@ +uuu_version 1.4.149 + +# @_flash.bin | bootloader, which can extract from wic image +# @_image [_flash.bin] | wic image burn to emmc. + + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin -scanlimited 0x800000 + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -scanterm -f _flash.bin -scanlimited 0x800000 + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump -scanlimited 0x800000 +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl -scanterm -scanlimited 0x800000 +SDPV: jump -scanlimited 0x800000 +# } + +FB: ucmd pci +FB: ucmd nvme scan +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: write -format "nvme write ${fastboot_buffer} @off @size" -blksz 512 -f _image +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/qspi_burn_loader.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/qspi_burn_loader.lst new file mode 100644 index 0000000..4028f18 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/qspi_burn_loader.lst @@ -0,0 +1,43 @@ +uuu_version 1.2.39 + +# @_flexspi.bin | bootloader +# @_image [_flexspi.bin] | image burn to flexspi, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flexspi.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM, skip QSPI header +SDPS: boot -f _flexspi.bin -skipfhdr + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flexspi.bin -offset 0x10000 -skipfhdr +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flexspi.bin -skipspl -skipfhdr +SDPV: jump +# } + +FB: ucmd setenv fastboot_buffer ${loadaddr} +FB: download -f _image + +FB: ucmd if test ! -n "$fastboot_bytes"; then setenv fastboot_bytes $filesize; else true; fi + +# Check Image if include flexspi header +FB: ucmd if qspihdr dump ${fastboot_buffer}; then setenv qspihdr_exist yes; else setenv qspihdr_exist no; fi; + +FB[-t 60000]: ucmd if test ${qspihdr_exist} = yes; then qspihdr init ${fastboot_buffer} ${fastboot_bytes} safe; else true; fi; + +#if uboot can't support qspihdr command, use uboot image to write qspi image, which require image include qspi flash header +FB: ucmd if test ${qspihdr_exist} = no; then sf probe; else true; fi; +FB[-t 40000]: ucmd if test ${qspihdr_exist} = no; then sf erase 0 +${fastboot_bytes}; else true; fi; +FB[-t 20000]: ucmd if test ${qspihdr_exist} = no; then sf write ${fastboot_buffer} 0 ${fastboot_bytes}; else true; fi; +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_all.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_all.lst new file mode 100644 index 0000000..ae6ec6d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_all.lst @@ -0,0 +1,35 @@ +uuu_version 1.4.149 + +# @_flash.bin | bootloader, which can extract from wic image +# @_image [_flash.bin] | wic image burn to emmc. + + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin -scanlimited 0x800000 + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -scanterm -f _flash.bin -scanlimited 0x800000 + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 -scanlimited 0x800000 +SDPU: jump -scanlimited 0x800000 +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl -scanterm -scanlimited 0x800000 +SDPV: jump -scanlimited 0x800000 +# } + +FB: ucmd setenv fastboot_dev mmc +FB: ucmd setenv mmcdev ${sd_dev} +FB: ucmd mmc dev ${sd_dev} +FB: flash -raw2sparse all _image +FB: flash -scanterm -scanlimited 0x800000 bootloader _flash.bin +FB: done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_loader.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_loader.lst new file mode 100644 index 0000000..4acb0c7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/sd_burn_loader.lst @@ -0,0 +1,33 @@ +uuu_version 1.2.39 + +# @_flash.bin | bootloader +# @_image [_flash.bin] | image burn to emmc, default is the same as bootloader + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS: boot -f _flash.bin + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl +SDPV: jump +# } + +FB: ucmd setenv fastboot_dev mmc +FB: ucmd setenv mmcdev ${sd_dev} +FB: ucmd mmc dev ${sd_dev} +FB: flash bootloader _image +FB: Done diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/spl_boot.lst b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/spl_boot.lst new file mode 100644 index 0000000..d7f5cec --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/uuu/spl_boot.lst @@ -0,0 +1,26 @@ +uuu_version 1.2.39 + +# This command will be run when i.MX6/7 i.MX8MM, i.MX8MQ +SDP: boot -f _flash.bin + +# This command will be run when ROM support stream mode +# i.MX8QXP, i.MX8QM +SDPS[-t 10000]: boot -f _flash.bin + +# These commands will be run when use SPL and will be skipped if no spl +# SDPU will be deprecated. please use SDPV instead of SDPU +# { +SDPU: delay 1000 +SDPU: write -f _flash.bin -offset 0x57c00 +SDPU: jump +SDPU: done +# } + +# These commands will be run when use SPL and will be skipped if no spl +# if (SPL support SDPV) +# { +SDPV: delay 1000 +SDPV: write -f _flash.bin -skipspl +SDPV: jump +SDPV: done +# } diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_full.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_full.json new file mode 100644 index 0000000..6723146 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_full.json @@ -0,0 +1,2075 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc0011204", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "SIMPLIFIED", + "value": 0, + "description": "Simplified configuration block type" + }, + { + "name": "FULL", + "value": 1, + "description": "Full configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "FLEXSPI", + "value": 0, + "description": "FlexSPI memory interface" + }, + { + "name": "SEMC", + "value": 1, + "description": "SEMC memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RW", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RW", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + }, + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag: fixed value 0x62666366, ascii: 'fcfb'", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version: [31:24] - 'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x100", + "bitfields": [ + { + "id": "field008-bits0-7", + "width": 8, + "name": "bugfix", + "access": "RW", + "description": " bugfix" + }, + { + "id": "field008-bits8-15", + "width": 8, + "name": "major", + "access": "RW", + "description": " major = 1" + }, + { + "id": "field008-bits16-23", + "width": 8, + "name": "minor", + "access": "RW", + "description": " minor" + }, + { + "id": "field008-bits24-31", + "width": 8, + "name": "ascii", + "access": "RW", + "description": " ascii 'V'" + } + ] + }, + { + "id": "Reserved00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field010-bits0-7", + "width": 8, + "name": "readSampleClkSrc", + "access": "RW", + "description": " Read Sample Clock Source", + "values": [ + { + "name": "SAMPLE_CLK_SRC_0", + "value": 0, + "description": "0 - Internal loopback" + }, + { + "name": "SAMPLE_CLK_SRC_1", + "value": 1, + "description": "1 - loopback from DQS pad" + }, + { + "name": "SAMPLE_CLK_SRC_3", + "value": 3, + "description": "3 - Flash provided DQS" + } + ] + } + ] + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x3" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x3" + }, + { + "id": "field013", + "offset_int": "0x13", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address width, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x3" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configuration Enable feature: 1 - Enabled, 0 - Disabled", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "deviceModeCfgEnable", + "access": "RW", + "description": " Device Mode Configuration Enable feature", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "1 - Enabled" + } + ] + } + ] + }, + { + "id": "field015", + "offset_int": "0x15", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type: Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field015-bits0-7", + "width": 8, + "name": "deviceModeType", + "access": "RW", + "description": " Specify the configuration command type", + "values": [ + { + "name": "GENERIC", + "value": 0, + "description": "0 - Generic" + }, + { + "name": "QUAD_ENABLE", + "value": 1, + "description": "1 - Quad Enable" + }, + { + "name": "SPI_TO_XSPI", + "value": 2, + "description": "2 - SPI-to-xSPI Mode" + }, + { + "name": "XSPI_TO_SPI", + "value": 3, + "description": "3 - xSPI-to-SPI Mode" + } + ] + } + ] + }, + { + "id": "field016", + "offset_int": "0x16", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT number of sequences, [15:8] - LUT sequence index, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field018-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field018-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Config Command Enable feature: 1 - Enable, 0 - Disable", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "configCmdEnable", + "access": "RW", + "description": " Config Command Enable feature", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "1 - Enabled" + } + ] + } + ] + }, + { + "id": "field021", + "offset_int": "0x21", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeType, configModeType for configCmdSeq[0]", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field021-bits0-7", + "width": 8, + "name": "configModeType_0", + "access": "RW", + "description": " Specify the configure mode type", + "values": [ + { + "name": "GENERIC", + "value": 0, + "description": "0 - Generic" + }, + { + "name": "QUAD_ENABLE", + "value": 1, + "description": "1 - Quad Enable" + }, + { + "name": "SPI_TO_XSPI", + "value": 2, + "description": "2 - SPI-to-xSPI Mode" + }, + { + "name": "XSPI_TO_SPI", + "value": 3, + "description": "3 - xSPI-to-SPI Mode" + } + ] + } + ] + }, + { + "id": "field022", + "offset_int": "0x22", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeType, configModeType for configCmdSeq[1]", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field022-bits0-7", + "width": 8, + "name": "configModeType_1", + "access": "RW", + "description": " Specify the configure mode type", + "values": [ + { + "name": "GENERIC", + "value": 0, + "description": "0 - Generic" + }, + { + "name": "QUAD_ENABLE", + "value": 1, + "description": "1 - Quad Enable" + }, + { + "name": "SPI_TO_XSPI", + "value": 2, + "description": "2 - SPI-to-xSPI Mode" + }, + { + "name": "XSPI_TO_SPI", + "value": 3, + "description": "3 - xSPI-to-SPI Mode" + } + ] + } + ] + }, + { + "id": "field023", + "offset_int": "0x23", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeType, configModeType for configCmdSeq[2]", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field023-bits0-7", + "width": 8, + "name": "configModeType_2", + "access": "RW", + "description": " Specify the configure mode type", + "values": [ + { + "name": "GENERIC", + "value": 0, + "description": "0 - Generic" + }, + { + "name": "QUAD_ENABLE", + "value": 1, + "description": "1 - Quad Enable" + }, + { + "name": "SPI_TO_XSPI", + "value": 2, + "description": "2 - SPI-to-xSPI Mode" + }, + { + "name": "XSPI_TO_SPI", + "value": 3, + "description": "3 - xSPI-to-SPI Mode" + } + ] + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field02C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field02C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved030", + "offset_int": "0x30", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved040", + "offset_int": "0x40", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Option, see Misc feature bit definitions for more details", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field044-bit0", + "width": 1, + "name": "bit0", + "access": "RW", + "description": " Bit0 - differential clock enable" + }, + { + "id": "field044-bit1", + "width": 1, + "name": "bit1", + "access": "RW", + "description": " Bit1 - CK2 enable" + }, + { + "id": "field044-bit2", + "width": 1, + "name": "bit2", + "access": "RW", + "description": " Bit2 - ParallelModeEnable" + }, + { + "id": "field044-bit3", + "width": 1, + "name": "bit3", + "access": "RW", + "description": " Bit3 - wordAddressableEnable" + }, + { + "id": "field044-bit4", + "width": 1, + "name": "bit4", + "access": "RW", + "description": " Bit4 - Half-Speed access enable" + }, + { + "id": "field044-bit5", + "width": 1, + "name": "bit5", + "access": "RW", + "description": " Bit5 - Pad Settings Override Enable" + }, + { + "id": "field044-bit6", + "width": 1, + "name": "bit6", + "access": "RW", + "description": " Bit6 - DDR Mode Enable" + }, + { + "id": "field044-bit7", + "width": 1, + "name": "bit7", + "access": "RW", + "description": " Bit7 - Pad Settings Override Enable" + }, + { + "id": "field044-bit8", + "width": 1, + "name": "bit8", + "access": "RW", + "description": " Bit8 - Second Pinmux group" + }, + { + "id": "field044-bit9", + "width": 1, + "name": "bit9", + "access": "RW", + "description": " Bit9 - Second DQS pi mux group" + }, + { + "id": "field044-bit10", + "width": 1, + "name": "bit10", + "access": "RW", + "description": " Bit10 - Write Mask Enable" + }, + { + "id": "field044-bit11", + "width": 1, + "name": "bit11", + "access": "RW", + "description": " Bit11 - Write Opt1 Clear" + }, + { + "width": 20 + } + ] + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x3", + "bitfields": [ + { + "id": "field048-bits0-7", + "width": 8, + "name": "deviceType", + "access": "RW", + "description": " Device Type", + "values": [ + { + "name": "SERIAL_NOR", + "value": 1, + "description": "1 - Serial NOR" + }, + { + "name": "SERIAL_NAND", + "value": 2, + "description": "2 - Serial NAND" + }, + { + "name": "SERIAL_RAM", + "value": 3, + "description": "3 - Serial RAM" + } + ] + } + ] + }, + { + "id": "field049", + "offset_int": "0x49", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field049-bits0-7", + "width": 8, + "name": "sflashPadType", + "access": "RW", + "description": " Serial Flash Pad Type", + "values": [ + { + "name": "SINGLE", + "value": 1, + "description": "1 - Single pad" + }, + { + "name": "DUAL", + "value": 2, + "description": "2 - Dual pads" + }, + { + "name": "QUAD", + "value": 3, + "description": "3 - Quad pads" + }, + { + "name": "OCTAL", + "value": 4, + "description": "4 - Octal pads" + } + ] + } + ] + }, + { + "id": "field04A", + "offset_int": "0x4a", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field04B", + "offset_int": "0x4b", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field04B-bits0-7", + "width": 8, + "name": "lutCustomSeqEnable", + "access": "RW", + "description": " LUT customization Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "0 - Use pre-defined LUT sequence index and number" + }, + { + "name": "ENABLED", + "value": 1, + "description": "1 - Use LUT sequence parameters provided in this block" + } + ] + } + ] + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved050", + "offset_int": "0x50", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field082-bits0-7", + "width": 8, + "name": "busyBitPolarity", + "access": "RW", + "description": " Busy flag polarity", + "values": [ + { + "name": "0", + "value": 0, + "description": "0 - 1 represents busy" + }, + { + "name": "1", + "value": 1, + "description": "1 - 0 represents busy" + } + ] + }, + { + "width":8 + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "lookupTable_0", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "lookupTable_1", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "lookupTable_2", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "lookupTable_3", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "lookupTable_4", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "lookupTable_5", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "lookupTable_6", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "lookupTable_7", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "lookupTable_8", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "lookupTable_9", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "lookupTable_10", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "lookupTable_11", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "lookupTable_12", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "lookupTable_13", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "lookupTable_14", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "lookupTable_15", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "lookupTable_16", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "lookupTable_17", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "lookupTable_18", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "lookupTable_19", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "lookupTable_20", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "lookupTable_21", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "lookupTable_22", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "lookupTable_23", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "lookupTable_24", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "lookupTable_25", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "lookupTable_26", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "lookupTable_27", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "lookupTable_28", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "lookupTable_29", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "lookupTable_30", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "lookupTable_31", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "lookupTable_32", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "lookupTable_33", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "lookupTable_34", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "lookupTable_35", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "lookupTable_36", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "lookupTable_37", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "lookupTable_38", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "lookupTable_39", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "lookupTable_40", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "lookupTable_41", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "lookupTable_42", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "lookupTable_43", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "lookupTable_44", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "lookupTable_45", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "lookupTable_46", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "lookupTable_47", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "lookupTable_48", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "lookupTable_49", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "lookupTable_50", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "lookupTable_51", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "lookupTable_52", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "lookupTable_53", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "lookupTable_54", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "lookupTable_55", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "lookupTable_56", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "lookupTable_57", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "lookupTable_58", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "lookupTable_59", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "lookupTable_60", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "lookupTable_61", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "lookupTable_62", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lookupTable_63", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1B0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Number of sequences, valid number: 1-16" + }, + { + "id": "field1B0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved01B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "Reserved01CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "reserved0_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D0-bits0-7", + "width": 8, + "name": "serialNorType", + "access": "RW", + "description": " Serial NOR Flash type", + "values": [ + { + "name": "TYPE_0", + "value": 0, + "description": "0" + }, + { + "name": "TYPE_1", + "value": 1, + "description": "1" + }, + { + "name": "TYPE_2", + "value": 2, + "description": "2" + }, + { + "name": "TYPE_3", + "value": 3, + "description": "3" + } + ] + } + ] + }, + { + "id": "field1D1", + "offset_int": "0x1d1", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1D2", + "offset_int": "0x1d2", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D2-bits0-7", + "width": 8, + "name": "halfClkForNonReadCmd", + "access": "RW", + "description": " Half the Serial Clock for non-read command", + "values": [ + { + "name": "FALSE", + "value": 0, + "description": "0" + }, + { + "name": "TRUE", + "value": 1, + "description": "1" + } + ] + } + ] + }, + { + "id": "field1D3", + "offset_int": "0x1d3", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "Reserved01D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Reserved2_0", + "deprecated_names": ["reserve2_0"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Reserved2_1", + "deprecated_names": ["reserve2_1"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Reserved2_2", + "deprecated_names": ["reserve2_2"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Reserved2_3", + "deprecated_names": ["reserve2_3"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Reserved2_4", + "deprecated_names": ["reserve2_4"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Reserved2_5", + "deprecated_names": ["reserve2_5"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Reserved2_6", + "deprecated_names": ["reserve2_6"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Reserved2_7", + "deprecated_names": ["reserve2_7"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Reserved2_8", + "deprecated_names": ["reserve2_8"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved01FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "Reserved2_9", + "deprecated_names": ["reserve2_9"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved0200", + "offset_int": "0x200", + "reg_width": 32, + "name": "Reserved2_10", + "deprecated_names": ["reserve2_10"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_header.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_header.json new file mode 100644 index 0000000..65fd310 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_header.json @@ -0,0 +1,89 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "Simplified", + "value": 0, + "description": "Simplified configuration block type" + }, + { + "name": "Full", + "value": 1, + "description": "Full configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "FlexSPI", + "value": 0, + "description": "FlexSPI memory interface" + }, + { + "name": "SEMC", + "value": 1, + "description": "SEMC memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_simplified.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_simplified.json new file mode 100644 index 0000000..83238b0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/flexspi_ram_simplified.json @@ -0,0 +1,312 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc001000c", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "Simplified", + "value": 0, + "description": "Simplified configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "FlexSPI", + "value": 0, + "description": "FlexSPI memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + }, + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "configOption0", + "description": "XMCD Configuration Option 0", + "default_value_int": "0xc1000700", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "sizeInMB", + "access": "RW", + "description": "Size in MB: 0 - Auto detection, Others - Size in MB" + }, + { + "id": "field004-bits8-11", + "width": 4, + "name": "maximumFrequency", + "access": "RW", + "description": "Maximum frequency (SoC specific definitions)", + "values": [ + { + "name": "30MHz", + "value": 1, + "description": "Maximum 30MHz" + }, + { + "name": "50MHz", + "value": 2, + "description": "Maximum 50MHz" + }, + { + "name": "60MHz", + "value": 3, + "description": "Maximum 60MHz" + }, + { + "name": "80MHz", + "value": 4, + "description": "Maximum 80MHz" + }, + { + "name": "100MHz", + "value": 5, + "description": "Maximum 100MHz" + }, + { + "name": "120MHz", + "value": 6, + "description": "Maximum 120MHz" + }, + { + "name": "133MHz", + "value": 7, + "description": "Maximum 133MHz" + }, + { + "name": "166MHz", + "value": 8, + "description": "Maximum 166MHz" + }, + { + "name": "200MHz", + "value": 9, + "description": "Maximum 200MHz" + } + ] + }, + { + "id": "field004-bits12-15", + "width": 4, + "name": "misc", + "access": "RW", + "description": "Misc. For HyperRAM: 0 - 1.8V, 1 - 3V", + "values": [ + { + "name": "1.8V", + "value": 0, + "description": "1.8V" + }, + { + "name": "3V", + "value": 1, + "description": "3V" + } + ] + }, + { + "width": 4 + }, + { + "id": "field004-bits20-23", + "width": 4, + "name": "deviceType", + "access": "RW", + "description": "Device type: 0 - HyperRAM, 1 - APMemory", + "values": [ + { + "name": "HYPER_RAM", + "value": 0, + "description": "HyperRAM" + }, + { + "name": "AP_MEMORY", + "value": 1, + "description": "APMemory" + } + ] + }, + { + "id": "field004-bits24-27", + "width": 4, + "name": "optionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "id": "field004-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "configOption1", + "description": "XMCD Configuration Option 1", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field008-bits0-3", + "width": 4, + "name": "readDummyCycles", + "access": "RW", + "description": "Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field008-bits4-7", + "width": 4, + "name": "writeDummyCycles", + "access": "RW", + "description": "Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "width": 8 + }, + { + "id": "field008-bits16-19", + "width": 4, + "name": "pinMuxGroup", + "access": "RW", + "description": "Pin mux group: 0 - Primary Group, 1 - Secondary group", + "values": [ + { + "name": "Primary group", + "value": 0, + "description": "Primary group" + }, + { + "name": "Secondary group", + "value": 1, + "description": "Secondary group" + } + ] + }, + { + "id": "field008-bits20-23", + "width": 4, + "name": "dqsPinmuxGroup", + "access": "RW", + "description": "DQS pin mux group: 0 - Default Group, 1 - Secondary group", + "values": [ + { + "name": "Default group", + "value": 0, + "description": "Default group" + }, + { + "name": "Secondary group", + "value": 1, + "description": "Secondary group" + } + ] + }, + { + "width": 4 + }, + { + "id": "field008-bits28-31", + "width": 4, + "name": "ramConnection", + "access": "RW", + "description": "RAM connection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "PORTA" + }, + { + "name": "PORTB", + "value": 1, + "description": "PORTB" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_full.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_full.json new file mode 100644 index 0000000..3f12ba4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_full.json @@ -0,0 +1,715 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc0101048", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "SIMPLIFIED", + "value": 0, + "description": "Simplified configuration block type" + }, + { + "name": "FULL", + "value": 1, + "description": "Full configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "FLEXSPI", + "value": 0, + "description": "FlexSPI memory interface" + }, + { + "name": "SEMC", + "value": 1, + "description": "SEMC memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RW", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RW", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + }, + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 8, + "name": "magicNumber", + "description": "Fixed to 0xA1", + "default_value_int": "0xa1" + }, + { + "id": "field005", + "offset_int": "0x5", + "reg_width": 8, + "name": "version", + "description": "Set to 1 for this implementation", + "default_value_int": "0x1" + }, + { + "id": "field006", + "offset_int": "0x6", + "reg_width": 8, + "name": "configOption", + "description": "Simplified - 0x00, Full - 0xFF - Must be 0xFF in this case", + "default_value_int": "0xff", + "bitfields": [ + { + "id": "field006-bits0-7", + "width": 8, + "name": "configOption", + "access": "RW", + "description": "Config option", + "values": [ + { + "name": "FULL", + "value": 0, + "description": "Full configuration. Must configure all fields." + } + ] + } + ] + }, + { + "id": "field007", + "offset_int": "0x7", + "reg_width": 8, + "name": "clkMhz", + "description": "Set the working frequency in the unit of MHz", + "default_value_int": "0xA6" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "sdramSizeKb", + "description": "Set the memory size of SDRAM CS0 in the unit of kilobytes. Range: 0x0000_0004~0x0040_0000, i.e. 4~4*1024*1024 kilobytes.", + "default_value_int": "0x10000" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "portSize", + "description": "Port size of SDRAM: 0 - 8-bit, 1 - 16-bit, 2 - 32-bit", + "default_value_int": "0x2", + "bitfields": [ + { + "id": "field00C-bits0-7", + "width": 8, + "name": "portSize", + "access": "RW", + "description": "Port size of SDRAM", + "values": [ + { + "name": "8_BIT", + "value": 0, + "description": "8-bit" + }, + { + "name": "16_BIT", + "value": 1, + "description": "16-bit" + }, + { + "name": "32_BIT", + "value": 2, + "description": "32-bit" + } + ] + } + ] + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "pinConfigPull", + "description": "Pull config of the SDRAM GPIO pin: 0 - Forbidden, 1 - Pull up, 2 - Pull down, 3 - No pull, Others - Invalid value", + "default_value_int": "0x3", + "bitfields": [ + { + "id": "field00D-bits0-7", + "width": 8, + "name": "pinConfigPull", + "access": "RW", + "description": "Pull config of the SDRAM GPIO pin", + "values": [ + { + "name": "FORBIDDEN", + "value": 0, + "description": "Forbidden" + }, + { + "name": "PULL_UP", + "value": 1, + "description": "Pull up" + }, + { + "name": "PULL_DOWN", + "value": 2, + "description": "Pull down" + }, + { + "name": "NO_PULL", + "value": 3, + "description": "No pull" + } + ] + } + ] + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "pinConfigDriveStrength", + "description": "Driver config of SDRAM GPIO pin: 0 - High driver, 1 - Normal driver, Others - Invalid value", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field00E-bits0-7", + "width": 8, + "name": "pinConfigDriveStrength", + "access": "RW", + "description": "Driver config of SDRAM GPIO pin", + "values": [ + { + "name": "DRIVE_STRENGTH_HIGH", + "value": 0, + "description": "High driver" + }, + { + "name": "DRIVE_STRENGTH_NORM", + "value": 1, + "description": "Normal driver" + } + ] + } + ] + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "muxRdy", + "description": "SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field00F-bits0-7", + "width": 8, + "name": "muxRdy", + "access": "RW", + "description": "SDRAM CSn device selection", + "values": [ + { + "name": "CS1", + "value": 1, + "description": "SDRAM CS1" + }, + { + "name": "CS2", + "value": 2, + "description": "SDRAM CS2" + }, + { + "name": "CS3", + "value": 3, + "description": "SDRAM CS3" + } + ] + } + ] + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "muxCsx0", + "description": "SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field010-bits0-7", + "width": 8, + "name": "muxCsx0", + "access": "RW", + "description": "SDRAM CSn device selection", + "values": [ + { + "name": "CSX0_CS1", + "value": 1, + "description": "SDRAM CS1" + }, + { + "name": "CSX0_CS2", + "value": 2, + "description": "SDRAM CS2" + }, + { + "name": "CSX0_CS3", + "value": 3, + "description": "SDRAM CS3" + } + ] + } + ] + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "muxCsx1", + "description": "SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field011-bits0-7", + "width": 8, + "name": "muxCsx1", + "access": "RW", + "description": "SDRAM CSn device selection", + "values": [ + { + "name": "CSX1_CS1", + "value": 1, + "description": "SDRAM CS1" + }, + { + "name": "CSX1_CS2", + "value": 2, + "description": "SDRAM CS2" + }, + { + "name": "CSX1_CS3", + "value": 3, + "description": "SDRAM CS3" + } + ] + } + ] + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 8, + "name": "muxCsx2", + "description": "SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field012-bits0-7", + "width": 8, + "name": "muxCsx2", + "access": "RW", + "description": "SDRAM CSn device selection", + "values": [ + { + "name": "CSX2_CS1", + "value": 1, + "description": "SDRAM CS1" + }, + { + "name": "CSX2_CS2", + "value": 2, + "description": "SDRAM CS2" + }, + { + "name": "CSX2_CS3", + "value": 3, + "description": "SDRAM CS3" + } + ] + } + ] + }, + { + "id": "field013", + "offset_int": "0x13", + "reg_width": 8, + "name": "muxCsx3", + "description": "SDRAM CSn device selection: 1 - SDRAM CS1, 2 - SDRAM CS2, 3 - SDRAM CS3, Others - Invalid for SDRAM, select other external devices", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field013-bits0-7", + "width": 8, + "name": "muxCsx3", + "access": "RW", + "description": "SDRAM CSn device selection", + "values": [ + { + "name": "CSX3_CS1", + "value": 1, + "description": "SDRAM CS1" + }, + { + "name": "CSX3_CS2", + "value": 2, + "description": "SDRAM CS2" + }, + { + "name": "CSX3_CS3", + "value": 3, + "description": "SDRAM CS3" + } + ] + } + ] + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 8, + "name": "bank", + "description": "Bank numbers of SDRAM device: 0 - 4 banks, 1 - 2 banks, Others - Invalid value", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "bank", + "access": "RW", + "description": "Bank numbers of SDRAM device", + "values": [ + { + "name": "BANK_4", + "value": 0, + "description": "4 banks" + }, + { + "name": "BANK_2", + "value": 1, + "description": "2 banks" + } + ] + } + ] + }, + { + "id": "field015", + "offset_int": "0x15", + "reg_width": 8, + "name": "burstLen", + "description": "Burst length: 0 - 1, 1 - 2, 2 - 4, 3 - 8, Others - Invalid value", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field015-bits0-7", + "width": 8, + "name": "burstLen", + "access": "RW", + "description": "Burst length", + "values": [ + { + "name": "BURST_LEN_1", + "value": 0, + "description": "1" + }, + { + "name": "BURST_LEN_2", + "value": 1, + "description": "2" + }, + { + "name": "BURST_LEN_4", + "value": 2, + "description": "4" + }, + { + "name": "BURST_LEN_8", + "value": 3, + "description": "8" + } + ] + } + ] + }, + { + "id": "field016", + "offset_int": "0x16", + "reg_width": 8, + "name": "columnAddrBitNum", + "description": "Column address bit number: 0 - 12 bit, 1 - 11 bit, 2 - 10 bit, 3 - 9 bit, 4 - 8 bit, Others - Invalid value", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field016-bits0-7", + "width": 8, + "name": "columnAddrBitNum", + "access": "RW", + "description": "Column address bit number", + "values": [ + { + "name": "COL_ADDR_BIT_NUM_12", + "value": 0, + "description": "12 bit" + }, + { + "name": "COL_ADDR_BIT_NUM_11", + "value": 1, + "description": "11 bit" + }, + { + "name": "COL_ADDR_BIT_NUM_10", + "value": 2, + "description": "10 bit" + }, + { + "name": "COL_ADDR_BIT_NUM_9", + "value": 3, + "description": "9 bit" + }, + { + "name": "COL_ADDR_BIT_NUM_8", + "value": 4, + "description": "8 bit" + } + ] + } + ] + }, + { + "id": "field017", + "offset_int": "0x17", + "reg_width": 8, + "name": "casLatency", + "description": "CAS Latency: 1 - 1, 2 - 2, 3 - 3, Others - Invalid value", + "default_value_int": "0x1", + "bitfields": [ + { + "id": "field017-bits0-7", + "width": 8, + "name": "casLatency", + "access": "RW", + "description": "CAS Latency", + "values": [ + { + "name": "CAS_LATENCY_1", + "value": 1, + "description": "1" + }, + { + "name": "CAS_LATENCY_2", + "value": 2, + "description": "2" + }, + { + "name": "CAS_LATENCY_3", + "value": 3, + "description": "3" + } + ] + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 8, + "name": "writeRecoveryNs", + "description": "Write recovery time in unit of nanosecond. This could help to meet tWR timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field019", + "offset_int": "0x19", + "reg_width": 8, + "name": "refreshRecoveryNs", + "description": "Refresh recovery time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01A", + "offset_int": "0x1a", + "reg_width": 8, + "name": "act2readwriteNs", + "description": "Act to read/write wait time in unit of nanosecond. This could help to meet tRCD timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01B", + "offset_int": "0x1b", + "reg_width": 8, + "name": "precharge2actNs", + "description": "Precharge to active wait time in unit of nanosecond. This could help to meet tRP timing requirement by SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "act2actBanksNs", + "description": "Active to active wait time between two different banks in unit of nanosecond. This could help to meet tRRD timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "refresh2refreshNs", + "description": "Auto refresh to auto refresh wait time in unit of nanosecond. This could help to meet tRFC timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "selfrefRecoveryNs", + "description": "Self refresh recovery time in unit of nanosecond. This could help to meet tXSR timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "act2prechargeMinNs", + "description": "ACT to Precharge minimum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "act2prechargeMaxNs", + "description": "ACT to Precharge maximum time in unit of nanosecond. This could help to meet tRAS(max) timing requirement by the SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "refreshperiodPerrowNs", + "description": "Refresh timer period in unit of nanosecond. Set to (tREF(ms) * 1000000/rows) value.", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "modeRegister", + "description": "Define the specific mode of operation of SDRAM. Set to the value required by SDRAM device.", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "sdram0Base", + "description": "Base address of SDRAM CS0. Range: 0x8000_0000~0xDFFF_FFFF.", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "sdram1Base", + "description": "Base address of SDRAM CS1. Range: 0x8000_0000~0xDFFF_FFFF. If CS1 is not being used, set the address to 0.", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "sdram2Base", + "description": "Base address of SDRAM CS2. Range: 0x8000_0000~0xDFFF_FFFF. If CS2 is not being used, set the address to 0.", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "sdram3Base", + "description": "Base address of SDRAM CS3. Range: 0x8000_0000~0xDFFF_FFFF. If CS3 is not being used, set the address to 0.", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "sdram1SizeKb", + "description": "Set the memory size of SDRAM CS1 in unit of kbytes. Range: 0x0000_0004~0x0040_0000, i.e. 4~4*1024*1024 kilobytes.", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "sdram2SizeKb", + "description": "Set the memory size of SDRAM CS2 in unit of kbytes. Range: 0x0000_0004~0x0040_0000, i.e. 4~4*1024*1024 kilobytes.", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "sdram3SizeKb", + "description": "Set the memory size of SDRAM CS3 in unit of kbytes. Range: 0x0000_0004~0x0040_0000, i.e. 4~4*1024*1024 kilobytes.", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_header.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_header.json new file mode 100644 index 0000000..a825431 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_header.json @@ -0,0 +1,89 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "SIMPLIFIED", + "value": 0, + "description": "Simplified configuration block type" + }, + { + "name": "FULL", + "value": 1, + "description": "Full configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "FLEXSPI", + "value": 0, + "description": "FlexSPI memory interface" + }, + { + "name": "SEMC", + "value": 1, + "description": "SEMC memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_simplified.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_simplified.json new file mode 100644 index 0000000..eb865ad --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/semc_sdram_simplified.json @@ -0,0 +1,178 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc010000d", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "Simplified", + "value": 0, + "description": "Simplified configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "SoC defined instances" + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - FlexSPI, 1 - SEMC", + "values": [ + { + "name": "SEMC", + "value": 1, + "description": "SEMC memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + }, + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 8, + "access": "RO", + "name": "magicNumber", + "description": "Magic number: Fixed to 0xA1", + "default_value_int": "0xA1" + }, + { + "id": "field005", + "offset_int": "0x5", + "reg_width": 8, + "name": "version", + "description": "Version: Set to 1 for this implementation", + "default_value_int": "0x1" + }, + { + "id": "field006", + "offset_int": "0x6", + "reg_width": 8, + "name": "configOption", + "description": "Config option: Simplified - 0x00, Full - 0xFF; Must be 0x00 in this case", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field006-bits0-7", + "width": 8, + "name": "configOption", + "access": "RW", + "description": "Config option", + "values": [ + { + "name": "Simplified", + "value": 0, + "description": "Simplified configuration" + } + ] + } + ] + }, + { + "id": "field007", + "offset_int": "0x7", + "reg_width": 8, + "name": "clkMhz", + "description": "Set the working frequency in the unit of MHz", + "default_value_int": "0xA6" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "sdramSizeKb", + "description": "Set the memory size of SDRAM CS0 in the unit of kilobytes. Range: 0x0000_0004~0x0040_0000, i.e. 4~4*1024*1024 kilobytes.", + "default_value_int": "0x10000" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "portSize", + "description": "Port size of SDRAM", + "default_value_int": "0x2", + "bitfields": [ + { + "id": "field00C-bits0-7", + "width": 8, + "name": "portSize", + "access": "RW", + "description": "Port size of SDRAM", + "values": [ + { + "name": "8bit", + "value": 0, + "description": "8-bit" + }, + { + "name": "16bit", + "value": 1, + "description": "16-bit" + }, + { + "name": "32bit", + "value": 2, + "description": "32-bit" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_header.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_header.json new file mode 100644 index 0000000..fef92e6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_header.json @@ -0,0 +1,96 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc0000000", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "SIMPLIFIED", + "value": 0, + "description": "Simplified configuration block type" + }, + { + "name": "FULL", + "value": 1, + "description": "Full configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "XSPI instance: 0 - XSPI0, 1 - XSPI1", + "values": [ + { + "name": "XSPI0", + "value": 0, + "description": "XSPI0" + }, + { + "name": "XSPI1", + "value": 1, + "description": "XSPI1" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - XSPI", + "values": [ + { + "name": "XSPI", + "value": 0, + "description": "XSPI memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_simplified.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_simplified.json new file mode 100644 index 0000000..2bca2de --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/common/xmcd/xspi_ram_simplified.json @@ -0,0 +1,310 @@ +{ + "cpu": "General", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "header", + "description": "XMCD Header", + "default_value_int": "0xc000000c", + "bitfields": [ + { + "id": "field000-bits0-11", + "width": 12, + "name": "configurationBlockSize", + "access": "RW", + "description": "Configuration block size including XMCD header itself" + }, + { + "id": "field000-bits12-15", + "width": 4, + "name": "configurationBlockType", + "access": "RW", + "description": "Configuration block type: 0 - Simplified, 1 - Full", + "values": [ + { + "name": "SIMPLIFIED", + "value": 0, + "description": "Simplified configuration block type" + } + ] + }, + { + "id": "field000-bits16-19", + "width": 4, + "name": "instance", + "access": "RW", + "description": "XSPI instance: 0 - XSPI0, 1 - XSPI1", + "values": [ + { + "name": "XSPI0", + "value": 0, + "description": "XSPI0" + }, + { + "name": "XSPI1", + "value": 1, + "description": "XSPI1" + } + ] + }, + { + "id": "field000-bits20-23", + "width": 4, + "name": "memoryInterface", + "access": "RW", + "description": "Memory interface: 0 - XSPI", + "values": [ + { + "name": "XSPI", + "value": 0, + "description": "XSPI memory interface" + } + ] + }, + { + "id": "field000-bits24-27", + "width": 4, + "name": "version", + "access": "RO", + "description": "Version, fixed value 0x0" + }, + { + "id": "field000-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + } + ] + }, + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "configOption0", + "description": "XMCD Configuration Option 0", + "default_value_int": "0xc1000700", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "sizeInMB", + "access": "RW", + "description": "Size in MB: 0 - Auto detection, Others - Size in MB" + }, + { + "id": "field004-bits8-11", + "width": 4, + "name": "maximumFrequency", + "access": "RW", + "description": "Maximum frequency (SoC specific definitions)", + "values": [ + { + "name": "MAX_FREQ_30_MHZ", + "value": 1, + "description": "Maximum 30MHz" + }, + { + "name": "MAX_FREQ_50_MHZ", + "value": 2, + "description": "Maximum 50MHz" + }, + { + "name": "MAX_FREQ_60_MHZ", + "value": 3, + "description": "Maximum 60MHz" + }, + { + "name": "MAX_FREQ_80_MHZ", + "value": 4, + "description": "Maximum 80MHz" + }, + { + "name": "MAX_FREQ_100_MHZ", + "value": 5, + "description": "Maximum 100MHz" + }, + { + "name": "MAX_FREQ_120_MHZ", + "value": 6, + "description": "Maximum 120MHz" + }, + { + "name": "MAX_FREQ_133_MHZ", + "value": 7, + "description": "Maximum 133MHz" + }, + { + "name": "MAX_FREQ_166_MHZ", + "value": 8, + "description": "Maximum 166MHz" + }, + { + "name": "MAX_FREQ_200_MHZ", + "value": 9, + "description": "Maximum 200MHz" + } + ] + }, + { + "id": "field004-bits12-15", + "width": 4, + "name": "misc", + "access": "RW", + "description": "Misc. For HyperRAM: 0 - Differential clock driven, 1 - Single-ended clock driven", + "values": [ + { + "name": "DIFFERENTIAL_CLOCK", + "value": 0, + "description": "Differential clock driven" + }, + { + "name": "SINGLE_ENDED_CLOCK", + "value": 1, + "description": "Single-ended clock driven" + } + ] + }, + { + "width": 4 + }, + { + "id": "field004-bits20-23", + "width": 4, + "name": "deviceType", + "access": "RW", + "description": "Device type: 0 - HyperRAM, 1 - APMemory", + "values": [ + { + "name": "HYPER_RAM", + "value": 0, + "description": "HyperRAM" + }, + { + "name": "AP_MEMORY", + "value": 1, + "description": "APMemory" + } + ] + }, + { + "id": "field004-bits24-27", + "width": 4, + "name": "optionSize", + "access": "RW", + "description": "Option Size", + "values": [ + { + "name": "OPTION_SIZE_1", + "value": 0, + "description": "Option words = 1" + }, + { + "name": "OPTION_SIZE_2", + "value": 1, + "description": "Option words = 2" + } + ] + }, + { + "id": "field004-bits28-31", + "width": 4, + "name": "tag", + "access": "RO", + "description": "Tag, fixed value 0xC" + } + ] + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "configOption1", + "description": "XMCD Configuration Option 1", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field008-bits0-3", + "width": 4, + "name": "readDummyCycles", + "access": "RW", + "description": "Read dummy cycles: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field008-bits4-7", + "width": 4, + "name": "writeDummyCycles", + "access": "RW", + "description": "Write dummy cycles: 0 - Auto detection, Others - Specified dummy cycles" + }, + { + "id": "field008-bits8-14", + "width": 7, + "name": "maxCsLowTime", + "access": "RW", + "description": "Maximum CS Low time - value x 0.1" + }, + { + "id": "field008-bit15", + "width": 1, + "name": "busWidth", + "access": "RW", + "description": "Bus width", + "values": [ + { + "name": "BUS_WIDTH_X8", + "value": 0, + "description": "X8 mode" + }, + { + "name": "BUS_WIDTH_X16", + "value": 1, + "description": "X16 mode" + } + ] + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "id": "field008-bits28-31", + "width": 4, + "name": "ramConnection", + "access": "RW", + "description": "RAM connection configuration", + "values": [ + { + "name": "CONNECTION_PORTA", + "value": 0, + "description": "RAM connection: 0 - PORTA" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/database.yaml new file mode 100644 index 0000000..fbaac4b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/database.yaml @@ -0,0 +1,28 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 + +revisions: + a0: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a0.json + a1: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a1.json +latest: a1 + +# General MCU information +info: + spsdk_predecessor_name: k32w1xx + # Web page of MCU representative + web: https://www.nxp.com/products/wireless/multiprotocol-mcus/tri-core-secure-and-ultra-low-power-mcu-for-matter-over-thread-and-bluetooth-le-5-3:K32W148 + + isp: + rom: + interfaces: ["uart", "spi", "i2c"] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a0.json new file mode 100644 index 0000000..ffd1192 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a0.json @@ -0,0 +1,1347 @@ +{ + "cpu": "K32W148", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "BOOT_CFG_PIN_ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "BOOT_CFG_PIN_DIS", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field084", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x0084", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field088", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0088", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field08C", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x008C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS4", + "description": "Boot Image Base Address 4", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field094", + "name": "BOOT_IMAGE_BASE_ADDRESS5", + "description": "Boot Image Base Address 5", + "offset_int": "0x0094", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field098", + "name": "BOOT_IMAGE_BASE_ADDRESS6", + "description": "Boot Image Base Address 6", + "offset_int": "0x0098", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field09C", + "name": "BOOT_IMAGE_BASE_ADDRESS7", + "description": "Boot Image Base Address 7", + "offset_int": "0x009C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS8", + "description": "Boot Image Base Address 8", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0A4", + "name": "BOOT_IMAGE_BASE_ADDRESS9", + "description": "Boot Image Base Address 9", + "offset_int": "0x00A4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0A8", + "name": "BOOT_IMAGE_BASE_ADDRESS10", + "description": "Boot Image Base Address 10", + "offset_int": "0x00A8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0AC", + "name": "BOOT_IMAGE_BASE_ADDRESS11", + "description": "Boot Image Base Address 11", + "offset_int": "0x00AC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS12", + "description": "Boot Image Base Address 12", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0B4", + "name": "BOOT_IMAGE_BASE_ADDRESS13", + "description": "Boot Image Base Address 13", + "offset_int": "0x00B4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0B8", + "name": "BOOT_IMAGE_BASE_ADDRESS14", + "description": "Boot Image Base Address 14", + "offset_int": "0x00B8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0BC", + "name": "BOOT_IMAGE_BASE_ADDRESS15", + "description": "Boot Image Base Address 15", + "offset_int": "0x00BC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "LPUART1_DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "LUPART1_ENABLED", + "value": 1, + "description": "LUPART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "LPI2C1_DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "LPI2C1_ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "LPSPI1_DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "LPSPI1_ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "SSS_LOADABLE_FW_ENTRY_ADDRESS", + "description": "SSS_Loadable_FW_Entry_Address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a1.json new file mode 100644 index 0000000..4f9a3e7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a1.json @@ -0,0 +1,1422 @@ +{ + "cpu": "K32W148", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "SSS_LOADABLE_FW_ENTRY_ADDRESS", + "description": "SSS_Loadable_FW_Entry_Address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a2.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a2.json new file mode 100644 index 0000000..72a3782 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/k32w148/ifr_romcfg_a2.json @@ -0,0 +1,1422 @@ +{ + "cpu": "K32W148", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_FAILURE_OPTIONS", + "description": "Secure Boot Failure Options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_FAILURE_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "ELE_LOADABLE_FW_ENTRY_ADDRESS", + "description": "ELE loadable firmware resides address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z5/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z5/database.yaml new file mode 100644 index 0000000..b05f2d0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z5/database.yaml @@ -0,0 +1,36 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x80000" + external: false + flash-logical-window_ns: + start_int: "0x1000000" + size_int: "0x80000" + external: false + mirror_of: internal-flash_ns + internal-flash_s: + start_int: "0x10000000" + size_int: "0x80000" + external: false + mirror_of: internal-flash_ns + flash-logical-window_s: + start_int: "0x11000000" + size_int: "0x80000" + external: false + mirror_of: internal-flash_ns + system-tcm: + start_int: "0x20000000" + size_int: "0x1C000" + external: false + code-tcm: + start_int: "0x4000000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/database.yaml new file mode 100644 index 0000000..acc4955 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/database.yaml @@ -0,0 +1,211 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a1.json + a2: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a2.json + +latest: a2 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + spsdk_predecessor_name: kw45xx + # Web page of MCU representative + web: https://www.nxp.com/products/wireless/bluetooth-low-energy/32-bit-bluetooth-5-3-long-range-mcus-with-can-fd-and-lin-bus-options-arm-cortex-m33-core:KW45 + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x100000" + external: false + flash-logical-window_ns: + start_int: "0x1000000" + size_int: "0x100000" + external: false + mirror_of: internal-flash_ns + internal-flash_s: + start_int: "0x10000000" + size_int: "0x100000" + external: false + mirror_of: internal-flash_ns + flash-logical-window_s: + start_int: "0x11000000" + size_int: "0x100000" + external: false + mirror_of: internal-flash_ns + system-tcm: + start_int: "0x20000000" + size_int: "0x1C000" + external: false + code-tcm: + start_int: "0x4000000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "can", "spi", "i2c"] + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x3000_4000 + size: 0x1000 + + # ======== Fuses description section ======== + fuses: + tool: blhost_legacy + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 10: "verify-erase" + 20: "boot-status" + 21: "loadable-fw-version" + 22: "fuse-program-voltage" + + # ======== DAT section ======== + dat: + sub_features: ["famode_cert"] + socc: 5 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + dat_is_using_sha256_always: True + famode_cert: [famode, famode_nxp] # List of Fault analysis Mode certificates (names of MBI classes) + famode_cfg_defaults: # Dictionary of default values of standard MBI members for FAmode image + outputImageExecutionTarget: xip + inputImageFile: generated + outputImageExecutionAddress: 0 + firmwareVersion: 0 + enableTrustZone: false + trustZonePresetFile: null + manifestDigestHashAlgorithm: sha256 + outputImageSubtype: main + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppTrustZone + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + famode: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifest + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + famode_nxp: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifest + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + nxp_signed_xip: + image_type: SIGNED_XIP_NXP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + nxp_signed: nxp_signed_xip + + # ======== PFR section ======== + pfr: + sub_features: [romcfg, cmactable] + romcfg: + address: 0x200_0000 + reg_spec: ifr_romcfg_a0.json + cmactable: + address: 0x0200_4000 + reg_spec: ifr_cmactable_a0.json + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - loadHashLocking + - fillMemory + - checkFwVersion + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: KW + prov_method: fw_data_split + use_additional_data: true + fw_read_address: 0x3001_0000 + ignored_otp_ranges: [31, 32] + validation_method: max_so_size=1024 + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/fuses.json new file mode 100644 index 0000000..6e572e4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/fuses.json @@ -0,0 +1,1015 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Config", + "description": "Miscellaneous security configuration" + }, + "registers": [ + { + "id": "fuse10", + "name": "LIFECYCLE", + "description": "Lifecycle state.", + "index_int": "0x000A", + "default_value_int": "0x0007", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "fuse10-bits-0-7", + "name": "LIFECYCLE", + "description": "Lifecycle state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "OEM_OPEN", + "value": 7, + "description": "OEM Open" + }, + { + "name": "OEM_SEC_CLOSED", + "value": 15, + "description": "OEM Secure World Closed." + }, + { + "name": "OEM_CLOSED", + "value": 31, + "description": "OEM Closed" + }, + { + "name": "OEM_LOCKED", + "value": 159, + "description": "OEM Locked" + }, + { + "name": "OEM_RETURN", + "value": 63, + "description": "OEM Return" + } + ] + } + ] + }, + { + "id": "fuse11", + "name": "DBG_EN_LOCK", + "description": "Debug Enable Lock.", + "index_int": "0x000B", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse11-bit-0", + "name": "DBG_EN_LOCK", + "description": "Debug Enable Lock.", + "values": [ + { + "name": "Open", + "value": 0, + "description": "The debug access control registers remain open when jumping to customer code." + }, + { + "name": "Locked", + "value": 1, + "description": "The debug access control registers are write-locked before jumping to customer code." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse12", + "name": "DBG_AUTH_DIS", + "description": "Debug Authentication Disabled.", + "index_int": "0x000C", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse12-bit-0", + "name": "DBG_AUTH_DIS", + "description": "Debug Authentication Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Debug Authentication enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Debug Authentication disabled" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse13", + "name": "TZM_EN", + "description": "Trust Zone Mode Enable.", + "index_int": "0x000D", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse13-bit-0", + "name": "TZM_EN", + "description": "Trust Zone Mode Enable.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "TZ-M is disabled by default." + }, + { + "name": "Enabled", + "value": 1, + "description": "TZ-M is enabled" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse17", + "name": "SERIAL_DIS", + "description": "Serial Download Disabled.", + "index_int": "0x0011", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse17-bit-0", + "name": "SERIAL_DIS", + "description": "Serial Download Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "ISP path is enabled." + }, + { + "name": "Disabled", + "value": 1, + "description": "ISP path is disabled." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse18", + "name": "WAKEUP_DIS", + "description": "Wakeup Disabled.", + "index_int": "0x0012", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse18-bit-0", + "name": "WAKEUP_DIS", + "description": "Wakeup Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Boot-ROM low power wakeup is enabled." + }, + { + "name": "Disabled", + "value": 1, + "description": "Boot-ROM low power wakeup is disabled." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse19", + "name": "CUST_PROD_OEMFW_AUTH_PUK_REVOKE", + "description": "Key revocation indicators of CUST_PROD_OEMFW_AUTH_PUK.", + "index_int": "0x0013", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse19-bit-0", + "name": "REVOKE_ROTK_1", + "description": "Revokes Root of Trust Key 1.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 1." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 1." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-1", + "name": "REVOKE_ROTK_2", + "description": "Revokes Root of Trust Key 2.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 2." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 2." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-2", + "name": "REVOKE_ROTK_3", + "description": "Revokes Root of Trust Key 3.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 3." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 3." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-3", + "name": "REVOKE_ROTK_4", + "description": "Revokes Root of Trust Key 4.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 4." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 4." + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse21", + "name": "DBG_AUTH_VU", + "description": "These Debug Authentication Vendor Usage fuses are used by customers to restrict debug certificates. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0015", + "reg_width": 16 + }, + { + "id": "fuse22", + "name": "IMG_KEY_REVOKE", + "description": "These fuses are used to revoke image signing keys separately from root keys. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0016", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Keys", + "description": "Authentication and encryption keys" + }, + "registers": [ + { + "id": "fuse31", + "name": "CUST_PROD_OEMFW_AUTH_PUK", + "description": "RoTKTH (customer trusted root key) typically used for CM33 main flash image authentication.", + "index_int": "0x001F", + "individual_write_lock": "implicit", + "reg_width": 256 + }, + { + "id": "fuse32", + "name": "CUST_PROD_OEMFW_ENC_SK", + "description": "256-bit encryption key used to protect confidentiality of OEM firmware. Typically required for firmware updates using sb3 (SB3KDK).", + "index_int": "0x0020", + "access": "WO", + "individual_write_lock": "implicit", + "reg_width": 256 + }, + { + "id": "fuse33", + "name": "OEM_Enablement_Token", + "description": "RoTKTH (root key hash) typically used for radio firmware authentication. (if valid token is intended to be used by programming SECURE_PHANTOM_CONFIG fuse)", + "index_int": "0x0021", + "individual_write_lock": "implicit", + "reg_width": 256 + } + ] + }, + { + "group": { + "name": "DCFG_CC_SOCU", + "description": "Debug authentication configuration" + }, + "registers": [ + { + "id": "fuse34", + "name": "DCFG_CC_SOCU_L1", + "description": "Debug authentication configuration for level 1 customer.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0022", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 1, + "id": "fuse34-bit-0", + "name": "PIN_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-1", + "name": "PIN_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-2", + "name": "PIN_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-3", + "name": "PIN_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-4", + "name": "PIN_NBU_DBGEN", + "description": "Controls debugging of NBU (radio, CM3) core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-5", + "name": "PIN_FA_CMD_EN", + "description": "Controls whether DM-AP command, Set FA Mode (command code: 0x06), can be issued through after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-6", + "name": "PIN_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-7", + "name": "PIN_ME_CMD_EN", + "description": "Controls whether DM-AP command, Bulk Erase (command code: 0x02), can be issued through after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-8", + "name": "DFLT_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-9", + "name": "DFLT_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-11", + "name": "DFLT_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-12", + "name": "DFLT_NBU_DBGEN", + "description": "Controls debugging of NBU (radio, CM3).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-13", + "name": "DFLT_FA_CMD_EN", + "description": "Controls whether DM-AP command, Set FA Mode (command code: 0x06), can be issued through after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-14", + "name": "DFLT_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-15", + "name": "DFLT_ME_CMD_EN", + "description": "Controls whether DM-AP command, Bulk Erase (command code: 0x02), can be issued through after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-16", + "name": "UUID_CHECK", + "description": "UUID matching required flag.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "UUID matching not required." + }, + { + "name": "Enabled", + "value": 1, + "description": "UUID matching required" + } + ] + }, + { + "width": 15 + } + ] + }, + { + "id": "fuse35", + "name": "DCFG_CC_SOCU_L2", + "description": "Debug authentication configuration for level 2 customer.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0023", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 1, + "id": "fuse35-bit-0", + "name": "PIN_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-1", + "name": "PIN_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-2", + "name": "PIN_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-3", + "name": "PIN_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-4", + "name": "PIN_NBU_DBGEN", + "description": "Controls debugging of NBU (radio, CM3) core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-5", + "name": "PIN_FA_CMD_EN", + "description": "Controls whether DM-AP command, Set FA Mode (command code: 0x06), can be issued through after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-6", + "name": "PIN_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-7", + "name": "PIN_ME_CMD_EN", + "description": "Controls whether DM-AP command, Bulk Erase (command code: 0x02), can be issued through after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-8", + "name": "DFLT_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-9", + "name": "DFLT_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-11", + "name": "DFLT_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CM33.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-12", + "name": "DFLT_NBU_DBGEN", + "description": "Controls debugging of NBU (radio, CM3).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-13", + "name": "DFLT_FA_CMD_EN", + "description": "Controls whether DM-AP command, Set FA Mode (command code: 0x06), can be issued through after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-14", + "name": "DFLT_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-15", + "name": "DFLT_ME_CMD_EN", + "description": "Controls whether DM-AP command, Bulk Erase (command code: 0x02), can be issued through after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-16", + "name": "UUID_CHECK", + "description": "UUID matching required flag.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "UUID matching not required." + }, + { + "name": "Enabled", + "value": 1, + "description": "UUID matching required" + } + ] + }, + { + "width": 15 + } + ] + } + ] + }, + { + "group": { + "name": "Versions", + "description": "Version counters for various software components in SoC" + }, + "registers": [ + { + "id": "fuse36", + "name": "SOC_VER_CNT", + "description": "Version counter for various software components in SoC. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0024", + "reg_width": 512 + }, + { + "id": "fuse37", + "name": "CM33_S_VER_CNT", + "description": "Monotonic counter indicating the minimum secure OEM CM33 firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0025", + "reg_width": 64 + }, + { + "id": "fuse38", + "name": "CM33_NS_VER_CNT", + "description": "Monotonic counter indicating the minimum non-secure OEM CM33 firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0026", + "reg_width": 256 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_cmactable_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_cmactable_a0.json new file mode 100644 index 0000000..ea2c352 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_cmactable_a0.json @@ -0,0 +1,188 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "Hash update needed", + "description": "Hash update needed", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field000-bits-0-31", + "name": "Hash update needed", + "description": "Hash update needed", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field016", + "name": "CMAC_APP", + "description": "16 byte CMAC for application image. Hash of main flash primary boot image data at 0x0 OR Hash of Image data at ABASE (if FLW is enabled)", + "offset_int": "0x10", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "field032", + "name": "Hash update needed 1", + "description": "Hash update needed 1", + "offset_int": "0x20", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field032-bits-0-31", + "name": "Hash update needed 1", + "description": "Hash update needed 1", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field048", + "name": "CMAC_FALLBACK", + "description": "16 byte CMAC for fallback image. Hash of fallback image data (if “Image 1 Base Address” field in IFR0 page0 is not 0xFFFFFFFF)", + "offset_int": "0x30", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "field064", + "name": "Hash update needed 2", + "description": "Hash update needed", + "offset_int": "0x40", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field064-bits-0-31", + "name": "Hash update needed", + "description": "Hash update needed", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field0080", + "name": "CMAC_NBU", + "description": "Hash of radio (NBU) flash image data", + "offset_int": "0x50", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "Reserved0096", + "name": "Reserved0096", + "description": "This field is reserved for internal use", + "offset_int": "0x60", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "none", + "is_reserved": true, + "reg_width": 128, + "bitfields": [ + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "Reserved00112", + "name": "Reserved00112", + "description": "This field is reserved for internal use", + "offset_int": "0x70", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "none", + "is_reserved": true, + "reg_width": 128 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a0.json new file mode 100644 index 0000000..3a02368 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a0.json @@ -0,0 +1,1382 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "BOOT_CFG_PIN_ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "BOOT_CFG_PIN_DIS", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field084", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x0084", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field088", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0088", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field08C", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x008C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS4", + "description": "Boot Image Base Address 4", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field094", + "name": "BOOT_IMAGE_BASE_ADDRESS5", + "description": "Boot Image Base Address 5", + "offset_int": "0x0094", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field098", + "name": "BOOT_IMAGE_BASE_ADDRESS6", + "description": "Boot Image Base Address 6", + "offset_int": "0x0098", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field09C", + "name": "BOOT_IMAGE_BASE_ADDRESS7", + "description": "Boot Image Base Address 7", + "offset_int": "0x009C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS8", + "description": "Boot Image Base Address 8", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0A4", + "name": "BOOT_IMAGE_BASE_ADDRESS9", + "description": "Boot Image Base Address 9", + "offset_int": "0x00A4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0A8", + "name": "BOOT_IMAGE_BASE_ADDRESS10", + "description": "Boot Image Base Address 10", + "offset_int": "0x00A8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0AC", + "name": "BOOT_IMAGE_BASE_ADDRESS11", + "description": "Boot Image Base Address 11", + "offset_int": "0x00AC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS12", + "description": "Boot Image Base Address 12", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0B4", + "name": "BOOT_IMAGE_BASE_ADDRESS13", + "description": "Boot Image Base Address 13", + "offset_int": "0x00B4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0B8", + "name": "BOOT_IMAGE_BASE_ADDRESS14", + "description": "Boot Image Base Address 14", + "offset_int": "0x00B8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field0BC", + "name": "BOOT_IMAGE_BASE_ADDRESS15", + "description": "Boot Image Base Address 15", + "offset_int": "0x00BC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "LPUART1_DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "LUPART1_ENABLED", + "value": 1, + "description": "LUPART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "LPI2C1_DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "LPI2C1_ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "LPSPI1_DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "LPSPI1_ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "CAN_DISABLED", + "value": 0, + "description": "CAN disabled" + }, + { + "name": "CAN_ENABLED", + "value": 1, + "description": "CAN enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field109", + "name": "CAN_CONFIG_1", + "description": "CAN config 1", + "offset_int": "0x0109", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field10A", + "name": "CAN_CONFIG_2", + "description": "CAN config 2", + "offset_int": "0x010A", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "Field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "Field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "SSS_LOADABLE_FW_ENTRY_ADDRESS", + "description": "SSS_Loadable_FW_Entry_Address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a1.json new file mode 100644 index 0000000..da295f1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a1.json @@ -0,0 +1,1457 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CAN disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CAN enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field109", + "name": "CAN_CONFIG_1", + "description": "CAN config 1", + "offset_int": "0x0109", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field10A", + "name": "CAN_CONFIG_2", + "description": "CAN config 2", + "offset_int": "0x010A", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "TxID field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "RxID field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "SSS_LOADABLE_FW_ENTRY_ADDRESS", + "description": "SSS_Loadable_FW_Entry_Address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a2.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a2.json new file mode 100644 index 0000000..f34093b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/ifr_romcfg_a2.json @@ -0,0 +1,1457 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_FAILURE_OPTIONS", + "description": "Secure Boot Failure Options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field060-bit0", + "name": "SECURE_BOOT_FAILURE_MODE", + "description": "Secure Boot failure mode", + "values": [ + { + "name": "INFINITE_SLEEP", + "value": 0, + "description": "Infinite sleep" + }, + { + "name": "SERIAL_DOWNLOAD", + "value": 1, + "description": "Serial download" + } + ] + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CAN disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CAN enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field109", + "name": "CAN_CONFIG_1", + "description": "CAN config 1", + "offset_int": "0x0109", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "field10A", + "name": "CAN_CONFIG_2", + "description": "CAN config 2", + "offset_int": "0x010A", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "TxID field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "RxID field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "ELE_LOADABLE_FW_ENTRY_ADDRESS", + "description": "ELE loadable firmware resides address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/tz.json new file mode 100644 index 0000000..ec2d2da --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45b41z8/tz.json @@ -0,0 +1,2213 @@ +{ + "cpu": "kw45b41z8", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "TZM info which data are initialized (tzm_control)", + "description": "TrustZone register - TZM info which data are initialized (tzm_control)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register(cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register(cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register(cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register(cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "TRDC Control Register (cr)", + "description": "TrustZone register - TRDC Control Register (cr)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "TRDC IDAU Control Register (idau_cr)", + "description": "TrustZone register - TRDC IDAU Control Register (idau_cr)", + "default_value_int": "0x8" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "Master 0 Domain Assignment Register (mda_w0_DOM0_dfmt0)", + "description": "TrustZone register - Master 0 Domain Assignment Register (mda_w0_DOM0_dfmt0)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Master 1 Domain Assignment Register (mda_w0_DOM1_dfmt1)", + "description": "TrustZone register - Master 1 Domain Assignment Register (mda_w0_DOM1_dfmt1)", + "default_value_int": "0x20000000" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Master 2 Domain Assignment Register (mda_w0_DOM2_dfmt1)", + "description": "TrustZone register - Master 2 Domain Assignment Register (mda_w0_DOM2_dfmt1)", + "default_value_int": "0x20000000" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Master 3 Domain Assignment Register (mda_w0_DOM3_dfmt1)", + "description": "TrustZone register - Master 3 Domain Assignment Register (mda_w0_DOM3_dfmt1)", + "default_value_int": "0x20000000" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 0 (mbc0_memn_glbac0)", + "description": "TrustZone register - MBC 0 Global Access Control Register 0 (mbc0_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 1 (mbc0_memn_glbac1)", + "description": "TrustZone register - MBC 0 Global Access Control Register 1 (mbc0_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 2 (mbc0_memn_glbac2)", + "description": "TrustZone register - MBC 0 Global Access Control Register 2 (mbc0_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 3 (mbc0_memn_glbac3)", + "description": "TrustZone register - MBC 0 Global Access Control Register 3 (mbc0_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 4 (mbc0_memn_glbac4)", + "description": "TrustZone register - MBC 0 Global Access Control Register 4 (mbc0_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 5 (mbc0_memn_glbac5)", + "description": "TrustZone register - MBC 0 Global Access Control Register 5 (mbc0_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 6 (mbc0_memn_glbac6)", + "description": "TrustZone register - MBC 0 Global Access Control Register 6 (mbc0_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 7 (mbc0_memn_glbac7)", + "description": "TrustZone register - MBC 0 Global Access Control Register 7 (mbc0_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 0 (mbc0_DOM0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 0 (mbc0_DOM0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 1 (mbc0_DOM0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 1 (mbc0_DOM0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 2 (mbc0_DOM0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 2 (mbc0_DOM0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 3 (mbc0_DOM0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 3 (mbc0_DOM0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 1 Configuration Word Register 0 (mbc0_DOM0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 1 Configuration Word Register 0 (mbc0_DOM0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 2 Configuration Word Register 0 (mbc0_DOM0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 2 Configuration Word Register 0 (mbc0_DOM0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 3 Configuration Word Register 0 (mbc0_DOM0_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 3 Configuration Word Register 0 (mbc0_DOM0_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 3 Configuration Word Register 1 (mbc0_DOM0_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 3 Configuration Word Register 1 (mbc0_DOM0_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 0 (mbc0_DOM1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 0 (mbc0_DOM1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 1 (mbc0_DOM1_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 1 (mbc0_DOM1_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 2 (mbc0_DOM1_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 2 (mbc0_DOM1_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 3 (mbc0_DOM1_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 3 (mbc0_DOM1_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 1 Configuration Word Register 0 (mbc0_DOM1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 1 Configuration Word Register 0 (mbc0_DOM1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 2 Configuration Word Register 0 (mbc0_DOM1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 2 Configuration Word Register 0 (mbc0_DOM1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 3 Configuration Word Register 0 (mbc0_DOM1_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 3 Configuration Word Register 0 (mbc0_DOM1_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 3 Configuration Word Register 1 (mbc0_DOM1_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 3 Configuration Word Register 1 (mbc0_DOM1_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 0 (mbc0_DOM2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 0 (mbc0_DOM2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 1 (mbc0_DOM2_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 1 (mbc0_DOM2_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 2 (mbc0_DOM2_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 2 (mbc0_DOM2_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 3 (mbc0_DOM2_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 3 (mbc0_DOM2_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 1 Configuration Word Register 0 (mbc0_DOM2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 1 Configuration Word Register 0 (mbc0_DOM2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 2 Configuration Word Register 0 (mbc0_DOM2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 2 Configuration Word Register 0 (mbc0_DOM2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 3 Configuration Word Register 0 (mbc0_DOM2_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 3 Configuration Word Register 0 (mbc0_DOM2_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 3 Configuration Word Register 1 (mbc0_DOM2_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 3 Configuration Word Register 1 (mbc0_DOM2_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 0 (mbc1_memn_glbac0)", + "description": "TrustZone register - MBC 1 Global Access Control Register 0 (mbc1_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 1 (mbc1_memn_glbac1)", + "description": "TrustZone register - MBC 1 Global Access Control Register 1 (mbc1_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 2 (mbc1_memn_glbac2)", + "description": "TrustZone register - MBC 1 Global Access Control Register 2 (mbc1_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 3 (mbc1_memn_glbac3)", + "description": "TrustZone register - MBC 1 Global Access Control Register 3 (mbc1_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 4 (mbc1_memn_glbac4)", + "description": "TrustZone register - MBC 1 Global Access Control Register 4 (mbc1_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 5 (mbc1_memn_glbac5)", + "description": "TrustZone register - MBC 1 Global Access Control Register 5 (mbc1_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 6 (mbc1_memn_glbac6)", + "description": "TrustZone register - MBC 1 Global Access Control Register 6 (mbc1_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 7 (mbc1_memn_glbac7)", + "description": "TrustZone register - MBC 1 Global Access Control Register 7 (mbc1_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 0 Configuration Word Register 0 (mbc1_DOM0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 0 Configuration Word Register 0 (mbc1_DOM0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 1 Configuration Word Register 0 (mbc1_DOM0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 1 Configuration Word Register 0 (mbc1_DOM0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 2 Configuration Word Register 0 (mbc1_DOM0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 2 Configuration Word Register 0 (mbc1_DOM0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 3 Configuration Word Register 0 (mbc1_DOM0_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 3 Configuration Word Register 0 (mbc1_DOM0_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 0 Configuration Word Register 0 (mbc1_DOM1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 0 Configuration Word Register 0 (mbc1_DOM1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 1 Configuration Word Register 0 (mbc1_DOM1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 1 Configuration Word Register 0 (mbc1_DOM1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 2 Configuration Word Register 0 (mbc1_DOM1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 2 Configuration Word Register 0 (mbc1_DOM1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 3 Configuration Word Register 0 (mbc1_DOM1_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 3 Configuration Word Register 0 (mbc1_DOM1_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 0 Configuration Word Register 0 (mbc1_DOM2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 0 Configuration Word Register 0 (mbc1_DOM2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 1 Configuration Word Register 0 (mbc1_DOM2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 1 Configuration Word Register 0 (mbc1_DOM2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 2 Configuration Word Register 0 (mbc1_DOM2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 2 Configuration Word Register 0 (mbc1_DOM2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 3 Configuration Word Register 0 (mbc1_DOM2_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 3 Configuration Word Register 0 (mbc1_DOM2_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 0 (mbc2_memn_glbac0)", + "description": "TrustZone register - MBC 2 Global Access Control Register 0 (mbc2_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 1 (mbc2_memn_glbac1)", + "description": "TrustZone register - MBC 2 Global Access Control Register 1 (mbc2_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 2 (mbc2_memn_glbac2)", + "description": "TrustZone register - MBC 2 Global Access Control Register 2 (mbc2_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 3 (mbc2_memn_glbac3)", + "description": "TrustZone register - MBC 2 Global Access Control Register 3 (mbc2_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 4 (mbc2_memn_glbac4)", + "description": "TrustZone register - MBC 2 Global Access Control Register 4 (mbc2_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 5 (mbc2_memn_glbac5)", + "description": "TrustZone register - MBC 2 Global Access Control Register 5 (mbc2_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 6 (mbc2_memn_glbac6)", + "description": "TrustZone register - MBC 2 Global Access Control Register 6 (mbc2_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 7 (mbc2_memn_glbac7)", + "description": "TrustZone register - MBC 2 Global Access Control Register 7 (mbc2_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 0 (mbc2_DOM0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 0 (mbc2_DOM0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 1 (mbc2_DOM0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 1 (mbc2_DOM0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 2 (mbc2_DOM0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 2 (mbc2_DOM0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 3 (mbc2_DOM0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 3 (mbc2_DOM0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 4 (mbc2_DOM0_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 4 (mbc2_DOM0_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 5 (mbc2_DOM0_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 5 (mbc2_DOM0_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 6 (mbc2_DOM0_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 6 (mbc2_DOM0_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 7 (mbc2_DOM0_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 7 (mbc2_DOM0_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 8 (mbc2_DOM0_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 8 (mbc2_DOM0_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 9 (mbc2_DOM0_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 9 (mbc2_DOM0_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 1 Configuration Word Register 0 (mbc2_DOM0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 1 Configuration Word Register 0 (mbc2_DOM0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 2 Configuration Word Register 0 (mbc2_DOM0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 2 Configuration Word Register 0 (mbc2_DOM0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 2 Configuration Word Register 1 (mbc2_DOM0_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 2 Configuration Word Register 1 (mbc2_DOM0_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_DOM1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_DOM1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_DOM1_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_DOM1_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_DOM1_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_DOM1_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_DOM1_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_DOM1_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_DOM1_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_DOM1_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_DOM1_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_DOM1_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_DOM1_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_DOM1_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_DOM1_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_DOM1_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_DOM1_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_DOM1_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_DOM1_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_DOM1_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_DOM1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_DOM1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_DOM1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_DOM1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_DOM1_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_DOM1_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_DOM2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_DOM2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_DOM2_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_DOM2_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_DOM2_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_DOM2_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_DOM2_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_DOM2_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_DOM2_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_DOM2_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_DOM2_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_DOM2_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_DOM2_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_DOM2_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_DOM2_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_DOM2_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_DOM2_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_DOM2_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_DOM2_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_DOM2_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_DOM2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_DOM2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_DOM2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_DOM2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_DOM2_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_DOM2_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 0 (mrc0_memn_glbac0)", + "description": "TrustZone register - MRC 0 Global Access Control Register 0 (mrc0_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 1 (mrc0_memn_glbac1)", + "description": "TrustZone register - MRC 0 Global Access Control Register 1 (mrc0_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 2 (mrc0_memn_glbac2)", + "description": "TrustZone register - MRC 0 Global Access Control Register 2 (mrc0_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 3 (mrc0_memn_glbac3)", + "description": "TrustZone register - MRC 0 Global Access Control Register 3 (mrc0_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 4 (mrc0_memn_glbac4)", + "description": "TrustZone register - MRC 0 Global Access Control Register 4 (mrc0_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 5 (mrc0_memn_glbac5)", + "description": "TrustZone register - MRC 0 Global Access Control Register 5 (mrc0_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 6 (mrc0_memn_glbac6)", + "description": "TrustZone register - MRC 0 Global Access Control Register 6 (mrc0_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 7 (mrc0_memn_glbac7)", + "description": "TrustZone register - MRC 0 Global Access Control Register 7 (mrc0_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM0_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM0_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM1_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM1_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 0 (mrc0_DOM2_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 1 (mrc0_DOM2_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "GPIO A Lock Register (gpioa_lock)", + "description": "TrustZone register - GPIO A Lock Register (gpioa_lock)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "GPIO A Pin Control Non-Secure Register (gpioa_pcns)", + "description": "TrustZone register - GPIO A Pin Control Non-Secure Register (gpioa_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "GPIO A Interrupt Control Non-Secure Register (gpioa_icns)", + "description": "TrustZone register - GPIO A Interrupt Control Non-Secure Register (gpioa_icns)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "GPIO A Pin Control Non-Privilege Register (gpioa_pcnp)", + "description": "TrustZone register - GPIO A Pin Control Non-Privilege Register (gpioa_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "GPIO A Interrupt Control Non-Privilege Register (gpioa_icnp)", + "description": "TrustZone register - GPIO A Interrupt Control Non-Privilege Register (gpioa_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 0 (gpioa_icr0)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 0 (gpioa_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 1 (gpioa_icr1)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 1 (gpioa_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 4 (gpioa_icr4)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 4 (gpioa_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 16 (gpioa_icr16)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 16 (gpioa_icr16)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 17 (gpioa_icr17)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 17 (gpioa_icr17)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 18 (gpioa_icr18)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 18 (gpioa_icr18)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 19 (gpioa_icr19)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 19 (gpioa_icr19)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 20 (gpioa_icr20)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 20 (gpioa_icr20)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 21 (gpioa_icr21)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 21 (gpioa_icr21)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "GPIO B Lock Register (gpiob_lock)", + "description": "TrustZone register - GPIO B Lock Register (gpiob_lock)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "GPIO B Pin Control Non-Secure Register (gpiob_pcns)", + "description": "TrustZone register - GPIO B Pin Control Non-Secure Register (gpiob_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "GPIO B Interrupt Control Non-Secure Register (gpiob_icns)", + "description": "TrustZone register - GPIO B Interrupt Control Non-Secure Register (gpiob_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "GPIO B Pin Control Non-Privilege Register (gpiob_pcnp)", + "description": "TrustZone register - GPIO B Pin Control Non-Privilege Register (gpiob_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "GPIO B Interrupt Control Non-Privilege Register (gpiob_icnp)", + "description": "TrustZone register - GPIO B Interrupt Control Non-Privilege Register (gpiob_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 0 (gpiob_icr0)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 0 (gpiob_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 1 (gpiob_icr1)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 1 (gpiob_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 2 (gpiob_icr2)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 2 (gpiob_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 3 (gpiob_icr3)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 3 (gpiob_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 4 (gpiob_icr4)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 4 (gpiob_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 5 (gpiob_icr5)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 5 (gpiob_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "GPIO C Lock Register (gpioc_lock)", + "description": "TrustZone register - GPIO C Lock Register (gpioc_lock)", + "default_value_int": "0x0" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "GPIO C Pin Control Non-Secure Register (gpioc_pcns)", + "description": "TrustZone register - GPIO C Pin Control Non-Secure Register (gpioc_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Non-Secure Register (gpioc_icns)", + "description": "TrustZone register - GPIO C Interrupt Control Non-Secure Register (gpioc_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "GPIO C Pin Control Non-Privilege Register (gpioc_pcnp)", + "description": "TrustZone register - GPIO C Pin Control Non-Privilege Register (gpioc_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "GPIO C Interrupt Control Non-Privilege Register (gpioc_icnp)", + "description": "TrustZone register - GPIO C Interrupt Control Non-Privilege Register (gpioc_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 0 (gpioc_icr0)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 0 (gpioc_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 1 (gpioc_icr1)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 1 (gpioc_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 2 (gpioc_icr2)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 2 (gpioc_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 3 (gpioc_icr3)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 3 (gpioc_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 4 (gpioc_icr4)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 4 (gpioc_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 5 (gpioc_icr5)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 5 (gpioc_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 6 (gpioc_icr6)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 6 (gpioc_icr6)", + "default_value_int": "0x0" + }, + { + "id": "field41C", + "offset_int": "0x41c", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 7 (gpioc_icr7)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 7 (gpioc_icr7)", + "default_value_int": "0x0" + }, + { + "id": "field420", + "offset_int": "0x420", + "reg_width": 32, + "name": "GPIO D Lock Register (gpiod_lock)", + "description": "TrustZone register - GPIO D Lock Register (gpiod_lock)", + "default_value_int": "0x0" + }, + { + "id": "field424", + "offset_int": "0x424", + "reg_width": 32, + "name": "GPIO D Pin Control Non-Secure Register (gpiod_pcns)", + "description": "TrustZone register - GPIO D Pin Control Non-Secure Register (gpiod_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field428", + "offset_int": "0x428", + "reg_width": 32, + "name": "GPIO D Interrupt Control Non-Secure Register (gpiod_icns)", + "description": "TrustZone register - GPIO D Interrupt Control Non-Secure Register (gpiod_icns)", + "default_value_int": "0x0" + }, + { + "id": "field42C", + "offset_int": "0x42c", + "reg_width": 32, + "name": "GPIO D Pin Control Non-Privilege Register (gpiod_pcnp)", + "description": "TrustZone register - GPIO D Pin Control Non-Privilege Register (gpiod_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field430", + "offset_int": "0x430", + "reg_width": 32, + "name": "GPIO D Interrupt Control Non-Privilege Register (gpiod_icnp)", + "description": "TrustZone register - GPIO D Interrupt Control Non-Privilege Register (gpiod_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field434", + "offset_int": "0x434", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 0 (gpiod_icr0)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 0 (gpiod_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field438", + "offset_int": "0x438", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 1 (gpiod_icr1)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 1 (gpiod_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field43C", + "offset_int": "0x43c", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 2 (gpiod_icr2)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 2 (gpiod_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field440", + "offset_int": "0x440", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 3 (gpiod_icr3)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 3 (gpiod_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field444", + "offset_int": "0x444", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 4 (gpiod_icr4)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 4 (gpiod_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field448", + "offset_int": "0x448", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 5 (gpiod_icr5)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 5 (gpiod_icr5)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41052/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41052/database.yaml new file mode 100644 index 0000000..3c84964 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41052/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41053/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41053/database.yaml new file mode 100644 index 0000000..3c84964 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41053/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41082/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41082/database.yaml new file mode 100644 index 0000000..3c84964 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41082/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41083/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41083/database.yaml new file mode 100644 index 0000000..3c84964 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw45z41083/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z83/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z83/database.yaml new file mode 100644 index 0000000..fcac4a3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z83/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x2_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z96/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z96/database.yaml new file mode 100644 index 0000000..d924f20 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z96/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z97/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z97/database.yaml new file mode 100644 index 0000000..d924f20 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42z97/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb2/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb2/database.yaml new file mode 100644 index 0000000..fe6110d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb2/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb3/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb3/database.yaml new file mode 100644 index 0000000..fe6110d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb3/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb6/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb6/database.yaml new file mode 100644 index 0000000..fe6110d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb6/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/database.yaml new file mode 100644 index 0000000..d789e85 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/database.yaml @@ -0,0 +1,197 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + + a1: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a1.json + cmactable: + reg_spec: ifr_cmactable_a1.json + a2: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a1.json + cmactable: + reg_spec: ifr_cmactable_a1.json + a2.1: + features: + pfr: + romcfg: + reg_spec: ifr_romcfg_a2.1.json + cmactable: + reg_spec: ifr_cmactable_a1.json + +latest: a2.1 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + spsdk_predecessor_name: kw47xx + # Web page of MCU representative + web: https://www.nxp.com + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "can", "spi", "i2c"] + +features: + # ======== Fuses description section ======== + fuses: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x3000_4000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties, property_warnings] + overridden_properties: + 10: "verify-erase" + 34: "fuse-program-voltage" + property_warnings: + 34: # 0x22 in hexadecimal + value: 0 + message: "WARNING: Setting property Fuse Program Voltage (0x22) to 0 on KW47 will cause a device reset!" + + # ======== DAT section ======== + dat: + sub_features: ["famode_cert"] + socc: 9 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + dat_is_using_sha256_always: True + famode_cert: [signed_xip, nxp_signed_xip] # List of Fault analysis Mode certificates (names of MBI classes) + famode_cfg_defaults: # Dictionary of default values of standard MBI members for FAmode image + outputImageExecutionTarget: xip + inputImageFile: generated + outputImageExecutionAddress: 0 + firmwareVersion: 0 + enableTrustZone: false + trustZonePresetFile: null + manifestDigestHashAlgorithm: sha256 + outputImageSubtype: main + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppTrustZone + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + nxp_signed_xip: + image_type: SIGNED_XIP_NXP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_MixinImageSubType + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + nbu_signed_xip: + image_type: NBU_SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageSubType + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + nxp_signed: nxp_signed_xip + nbu_signed: nbu_signed_xip + + # ======== PFR section ======== + pfr: + sub_features: [romcfg, cmactable] + romcfg: + address: 0x200_0000 + reg_spec: ifr_romcfg_a0.json + cmactable: + address: 0x0200_4000 + reg_spec: ifr_cmactable_a0.json + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - loadHashLocking + - fillMemory + - checkFwVersion + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: KW + prov_method: fw_data_split + use_additional_data: true + fw_read_address: 0x3001_0000 + ignored_otp_ranges: [31, 32] + validation_method: max_so_size=1024 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/fuses.json new file mode 100644 index 0000000..eb3a2d6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/fuses.json @@ -0,0 +1,1434 @@ +{ + "cpu": "KW47B42ZB7", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Write/Read/Override Protection" + }, + "registers": [ + { + "id": "fuse5", + "name": "CUST_PROD_OEMFW_AUTH_PUK_LOCK", + "description": "Locks CUST_PROD_OEMFW_AUTH_PUK[255:0]. When blown, the operation with fuses is limited according the burnt value (xx1 - fuse writing disabled;x1x - fuse overriding disabled; 1xx - fuse reading disabled).", + "index_int": "0x0005", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "WRITE_PROTECTION", + "description": "Write protection for CUST_PROD_OEMFW_AUTH_PUK[255:0]. When write protection is blown, it protects the fuses against writing to it.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable write protection lock." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable write protection lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 5 + } + ] + }, + { + "id": "fuse6", + "name": "CUST_PROD_OEMFW_ENC_SK_LOCK", + "description": "Locks CUST_PROD_OEMFW_ENC_SK[255:0]. When blown, the operation with fuses is limited according the burnt value (xx1 - fuse writing disabled;x1x - fuse overriding disabled; 1xx - fuse reading disabled).", + "index_int": "0x0006", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse6-bit-0", + "name": "WRITE_PROTECTION", + "description": "Write protection for CUST_PROD_OEMFW_ENC_SK[255:0]. When write protection is blown, it protects the fuses against writing to it.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable write protection lock." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable write protection lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 5 + } + ] + }, + { + "id": "fuse8", + "name": "DCFG_CC_SOCU_L1_LOCK", + "description": "Locks DCFG_CC_SOCU_L1. When blown, the operation with fuses is limited according the burnt value (xx1 - fuse writing disabled;x1x - fuse overriding disabled; 1xx - fuse reading disabled).", + "index_int": "0x0008", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse8-bit-0", + "name": "WRITE_PROTECTION", + "description": "Write protection for DCFG_CC_SOCU_L1. When write protection is blown, it protects the fuses against writing to it.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable write protection lock." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable write protection lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 5 + } + ] + }, + { + "id": "fuse9", + "name": "DCFG_CC_SOCU_L2_LOCK", + "description": "Locks DCFG_CC_SOCU_L2. When blown, the operation with fuses is limited according the burnt value (xx1 - fuse writing disabled;x1x - fuse overriding disabled; 1xx - fuse reading disabled).", + "index_int": "0x0009", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse9-bit-0", + "name": "WRITE_PROTECTION", + "description": "Write protection for DCFG_CC_SOCU_L2. When write protection is blown, it protects the fuses against writing to it.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable write protection lock." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable write protection lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 5 + } + ] + } + ] + }, + { + "group": { + "name": "Config", + "description": "Miscellaneous security configuration" + }, + "registers": [ + { + "id": "fuse10", + "name": "LIFECYCLE", + "description": "Lifecycle state.", + "index_int": "0x000A", + "default_value_int": "0x0007", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "fuse10-bits-0-7", + "name": "LIFECYCLE", + "description": "Lifecycle state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "OEM_OPEN", + "value": 7, + "description": "OEM Open" + }, + { + "name": "OEM_SEC_CLOSED", + "value": 15, + "description": "OEM Secure World Closed." + }, + { + "name": "OEM_CLOSED", + "value": 31, + "description": "OEM Closed" + }, + { + "name": "OEM_LOCKED", + "value": 159, + "description": "OEM Locked" + }, + { + "name": "OEM_RETURN", + "value": 63, + "description": "OEM Return" + } + ] + } + ] + }, + { + "id": "fuse11", + "name": "DBG_EN_LOCK", + "description": "Debug Enable Lock. To increase the flexibility of the debug controller, an option to enable the debug ports via OEM software can be done by default setting of \u2018DBG_EN_LOCK\u2019 at 0. The SMSCM[DBGEN] and SMSCM[DBGEN_B] registers will not be write-locked, meaning SW can allow specified debug ports to be opened without the challenge-response scheme. It is the responsibility of the OEM\u2019s application to handle these registers carefully. Since this relies solely on OEM\u2019s SW protections it reduces the overall security of the system. If this feature is not required, it is strongly recommended to burn the \u2018DBG_EN_LOCK\u2019 to 1 which disables this feature. For production lifecycles (OEM-Closed and OEM-Locked), this feature is only available in OEM-Closed. In OEM-Locked, the debug access registers are write-locked regardless of the DBG_EN_LOCK fuse value.", + "index_int": "0x000B", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse11-bit-0", + "name": "DBG_EN_LOCK", + "description": "Debug Enable Lock.", + "values": [ + { + "name": "Open", + "value": 0, + "description": "The debug access control registers remain open when jumping to customer code." + }, + { + "name": "Locked", + "value": 1, + "description": "The debug access control registers are write-locked before jumping to customer code." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse12", + "name": "DBG_AUTH_DIS", + "description": "Debug Authentication Disabled.", + "index_int": "0x000C", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse12-bit-0", + "name": "DBG_AUTH_DIS", + "description": "Debug Authentication Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Debug Authentication enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Debug Authentication disabled" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse13", + "name": "TZM_EN", + "description": "Trust Zone Mode Enable.", + "index_int": "0x000D", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse13-bit-0", + "name": "TZM_EN", + "description": "Trust Zone Mode Enable.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "TZ-M is disabled by default." + }, + { + "name": "Enabled", + "value": 1, + "description": "TZ-M is enabled" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse17", + "name": "SERIAL_DIS", + "description": "Serial Download Disabled.", + "index_int": "0x0011", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse17-bit-0", + "name": "SERIAL_DIS", + "description": "Serial Download Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "ISP path is enabled." + }, + { + "name": "Disabled", + "value": 1, + "description": "ISP path is disabled." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse18", + "name": "WAKEUP_DIS", + "description": "Wakeup Disabled.", + "index_int": "0x0012", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse18-bit-0", + "name": "WAKEUP_DIS", + "description": "Wakeup Disabled.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Boot-ROM low power wakeup is enabled." + }, + { + "name": "Disabled", + "value": 1, + "description": "Boot-ROM low power wakeup is disabled." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse19", + "name": "CUST_PROD_OEMFW_AUTH_PUK_REVOKE", + "description": "Key revocation indicators of CUST_PROD_OEMFW_AUTH_PUK.", + "index_int": "0x0013", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse19-bit-0", + "name": "REVOKE_ROTK_1", + "description": "Revokes Root of Trust Key 1.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 1." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 1." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-1", + "name": "REVOKE_ROTK_2", + "description": "Revokes Root of Trust Key 2.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 2." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 2." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-2", + "name": "REVOKE_ROTK_3", + "description": "Revokes Root of Trust Key 3.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 3." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 3." + } + ] + }, + { + "width": 1, + "id": "fuse19-bit-3", + "name": "REVOKE_ROTK_4", + "description": "Revokes Root of Trust Key 4.", + "values": [ + { + "name": "KEEP", + "value": 0, + "description": "Keep the RoTK 4." + }, + { + "name": "REVOKE", + "value": 1, + "description": "Revoke the RoTK 4." + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse21", + "name": "DBG_AUTH_VU", + "description": "These Debug Authentication Vendor Usage fuses are used by customers to restrict debug certificates. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0015", + "reg_width": 16 + }, + { + "id": "fuse22", + "name": "IMG_KEY_REVOKE", + "description": "These fuses are used to revoke image signing keys separately from root keys. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0016", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Keys", + "description": "Authentication and encryption keys" + }, + "registers": [ + { + "id": "fuse31", + "name": "CUST_PROD_OEMFW_AUTH_PUK", + "description": "The RoTKTH for P-256 keys will be 256 bits in length, write as-is. The RoTKTH for P-384 keys will be 384 bits in length, users can truncate the value prior to writing the fuse or write it as is and will be truncated automatically.", + "index_int": "0x001F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0001" + }, + "reg_width": 256 + }, + { + "id": "fuse32", + "name": "CUST_PROD_OEMFW_ENC_SK", + "description": "256-bit encryption key used to protect confidentiality of OEM firmware. Typically required for firmware updates using sb3 (SB3KDK).", + "index_int": "0x0020", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0001" + }, + "reg_width": 256 + } + ] + }, + { + "group": { + "name": "DCFG_CC_SOCU", + "description": "Debug authentication configuration" + }, + "registers": [ + { + "id": "fuse34", + "name": "DCFG_CC_SOCU_L1", + "description": "Debug authentication configuration for level 1 customer.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0022", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0001" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse34-bit-0", + "name": "PIN_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-1", + "name": "PIN_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-2", + "name": "PIN_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-3", + "name": "PIN_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-4", + "name": "PIN_NBU_DBGEN", + "description": "Controls debugging of NBU (radio) core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-5", + "name": "PIN_DSP_DBGEN", + "description": "Controls debugging of DSP core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-6", + "name": "PIN_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-7", + "name": "PIN_FA_CMD_EN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-8", + "name": "PIN_ME_CMD_EN", + "description": "Controls whether DM-AP Mass Erase command (command code: 0x03) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-9", + "name": "DFLT_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-10", + "name": "DFLT_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-11", + "name": "DFLT_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-12", + "name": "DFLT_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-13", + "name": "DFLT_NBU_DBGEN", + "description": "Controls debugging of NBU (radio) core.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-14", + "name": "DFLT_DSP_DBGEN", + "description": "Controls debugging of DSP core.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-15", + "name": "DFLT_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-16", + "name": "DFLT_FA_CMD_EN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-17", + "name": "DFLT_ME_CMD_EN", + "description": "Controls whether DM-AP Mass Erase command (command code: 0x03) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-18", + "name": "UUID_CHECK", + "description": "Controls whether to enforce UUID check during Debug Credential (DC) validation. If this bit is set, then the device will only accept a Debug Credential (DC) certificate containing a UUID attribute that is an exact match to the device's UUID.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "UUID matching not required." + }, + { + "name": "Enabled", + "value": 1, + "description": "UUID matching required" + } + ] + }, + { + "width": 2, + "id": "fuse34-bits-19-20", + "name": "FORCE_P256", + "description": "Valid only for DCFG_SOCU_L1. Must be set to value 10b, when RoTK is based on P-256. All other values (00b, 01b, 11b) indicate P-384. See Protocol Version (DCFG_VER).", + "values": [ + { + "name": "P-384", + "value": 0, + "description": "RoTK is based on P-384." + }, + { + "name": "P-384_0", + "value": 1, + "description": "RoTK is based on P-384." + }, + { + "name": "P-256", + "value": 2, + "description": "RoTK is based on P-256." + }, + { + "name": "P-384_1", + "value": 3, + "description": "RoTK is based on P-384." + } + ] + }, + { + "width": 11 + } + ] + }, + { + "id": "fuse35", + "name": "DCFG_CC_SOCU_L2", + "description": "Debug authentication configuration for level 2 customer.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0023", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0001" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse35-bit-0", + "name": "PIN_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-1", + "name": "PIN_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-2", + "name": "PIN_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-3", + "name": "PIN_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-4", + "name": "PIN_NBU_DBGEN", + "description": "Controls debugging of NBU (radio) core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-5", + "name": "PIN_DSP_DBGEN", + "description": "Controls debugging of DSP core.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-6", + "name": "PIN_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-7", + "name": "PIN_FA_CMD_EN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-8", + "name": "PIN_ME_CMD_EN", + "description": "Controls whether DM-AP Mass Erase command (command code: 0x03) can be issued after authentication.", + "values": [ + { + "name": "DAP", + "value": 0, + "description": "Use debug authentication. DFLT bit must be zero." + }, + { + "name": "DFLT", + "value": 1, + "description": "Behaviour is defined by DFLT bit." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-9", + "name": "DFLT_NIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-10", + "name": "DFLT_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-11", + "name": "DFLT_SPNIDEN", + "description": "Controls non-invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-12", + "name": "DFLT_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0 (AP0).", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-13", + "name": "DFLT_NBU_DBGEN", + "description": "Controls debugging of NBU (radio) core.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-14", + "name": "DFLT_DSP_DBGEN", + "description": "Controls debugging of DSP core.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-15", + "name": "DFLT_ISP_CMD_EN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-16", + "name": "DFLT_FA_CMD_EN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-17", + "name": "DFLT_ME_CMD_EN", + "description": "Controls whether DM-AP Mass Erase command (command code: 0x03) can be issued after authentication.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed;\nPIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up." + }, + { + "name": "Enabled", + "value": 1, + "description": "PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled;\nPIN=0,DFLT=1: Illegal." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-18", + "name": "UUID_CHECK", + "description": "Controls whether to enforce UUID check during Debug Credential (DC) validation. If this bit is set, then the device will only accept a Debug Credential (DC) certificate containing a UUID attribute that is an exact match to the device's UUID.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "UUID matching not required." + }, + { + "name": "Enabled", + "value": 1, + "description": "UUID matching required" + } + ] + }, + { + "width": 13 + } + ] + } + ] + }, + { + "group": { + "name": "Versions", + "description": "Version counters for various software components in SoC" + }, + "registers": [ + { + "id": "fuse37", + "name": "CM33_S_VER_CNT", + "description": "Monotonic counter indicating the minimum secure OEM CM33 firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0025", + "reg_width": 64 + }, + { + "id": "fuse38", + "name": "CM33_NS_VER_CNT", + "description": "Monotonic counter indicating the minimum non-secure OEM CM33 firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0026", + "reg_width": 256 + }, + { + "id": "fuse39", + "name": "RADIO_VER_CNT", + "description": "Monotonic counter indicating the minimal radio firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0027", + "reg_width": 128 + }, + { + "id": "fuse40", + "name": "SNT_VER_CNT", + "description": "Monotonic counter indicating the minimum ELE loadable firmware version. The number of set bits equals the version number. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0028" + }, + { + "id": "fuse41", + "name": "CM33_BOOTLOADER_VER_CNT", + "description": "Monotonic counter indicating the minimal CM33 bootloader version. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0029", + "reg_width": 16 + }, + { + "id": "fuse42", + "name": "CM33_S_VER_CNT_VIRTUAL", + "description": "Virtual counter indicating the secure OEM CM33 firmware version. The integer value of this field indicates the number of set bits in CM33_S_VER_CNT and that number equals the version number. Allowed values increment in form of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, ..., etc.", + "index_int": "0x002A", + "calculated": { + "method": "virtual_counter", + "src_register_id": "fuse37" + }, + "reg_width": 8 + }, + { + "id": "fuse43", + "name": "CM33_NS_VER_CNT_VIRTUAL", + "description": "Virtual counter indicating the non-secure OEM CM33 firmware version. The integer value of this field indicates the number of set bits in CM33_NS_VER_CNT and that number equals the version number. Allowed values increment in form of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, ..., etc.", + "index_int": "0x002B", + "calculated": { + "method": "virtual_counter", + "src_register_id": "fuse38" + }, + "reg_width": 16 + }, + { + "id": "fuse44", + "name": "RADIO_VER_CNT_VIRTUAL", + "description": "Virtual counter indicating the radio firmware version. The integer value of this field indicates the number of set bits in RADIO_VER_CNT and that number equals the version number. Allowed values increment in form of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, ..., etc.", + "index_int": "0x002C", + "calculated": { + "method": "virtual_counter", + "src_register_id": "fuse39" + }, + "reg_width": 8 + }, + { + "id": "fuse45", + "name": "SNT_VER_CNT_VIRTUAL", + "description": "Virtual counter indicating the ELE loadable firmware version. The integer value of this field indicates the number of set bits in SNT_VER_CNT and that number equals the version number. Allowed values increment in form of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, ..., etc.", + "index_int": "0x002D", + "calculated": { + "method": "virtual_counter", + "src_register_id": "fuse40" + }, + "reg_width": 8 + }, + { + "id": "fuse46", + "name": "CM33_BOOTLOADER_VER_CNT_VIRTUAL", + "description": "Virtual counter indicating the minimal version of the CM33 bootloader. Integer value equivalent to number of set fuse bits Allowed values increment in form of 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, ..., etc.", + "index_int": "0x002E", + "calculated": { + "method": "virtual_counter", + "src_register_id": "fuse41" + }, + "reg_width": 8 + } + ] + }, + { + "group": { + "name": "SEC_BOOT_EN", + "description": "Secure boot enable" + }, + "registers": [ + { + "id": "fuse51", + "name": "NBU_SEC_BOOT_EN", + "description": "NBU secure boot enable fuse. NBU image must be authenticated successfully to boot if this fuse is set. See the Security Reference Manual for the value of this fuse reflected in bit 12 of SMSCM_LIFECYCLE register.", + "index_int": "0x0033", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "fuse51-bit-0", + "name": "NBU_SEC_BOOT_EN", + "description": "NBU secure boot enable fuse. NBU image must be authenticated successfully to boot if this fuse is set.\nSee the Security Reference Manual for the value of this fuse reflected in bit 12 of SMSCM_LIFECYCLE register.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "NBU image doesn't need to be authenticated (default)" + }, + { + "name": "Enabled", + "value": 1, + "description": "NBU image must be authenticated to boot" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse53", + "name": "OEM_SEC_BOOT_EN", + "description": "Main core secure boot enable boot enable fuse, boot image must be authenticated successfully to boot if this fuse field is set to 0xA. See the Security Reference Manual for the value of this fuse reflected in bits 24-27 of SMSCM_LIFECYCLE register.", + "index_int": "0x0035", + "reg_width": 8, + "bitfields": [ + { + "width": 4, + "id": "fuse53-bits-0-3", + "name": "OEM_SEC_BOOT_EN", + "description": "Main core secure boot enable boot enable fuse, boot image must be authenticated successfully to boot if this fuse field is set to 0xA. See the Security Reference Manual for the value of this fuse reflected in bits 24-27 of SMSCM_LIFECYCLE register.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Boot image doesn't need to be authenticated to boot (default)" + }, + { + "name": "Enabled", + "value": 10, + "description": "Boot image must be authenticated to boot" + } + ] + }, + { + "width": 4 + } + ] + } + ] + }, + { + "group": { + "name": "SECURE_STORAGE_CNT", + "description": "Secure storage counter" + }, + "registers": [ + { + "id": "fuse56", + "name": "SECURE_STORAGE_VER_CNT", + "description": "Secure Storage Verification Counter. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc.", + "index_int": "0x0038", + "reg_width": 96 + }, + { + "id": "fuse57", + "name": "SECURE_STORAGE_VER_CNT_VIRTUAL", + "description": "Virtual Secure Storage Verification Counter. Allowed values increment in form of 0x1, 0x3, 0x7, 0xF, 0x1F, 0x3F, ..., etc. Fuse is not accessible via ISP mode and can be read and written from application by fuse read and fuse write ELE API.", + "index_int": "0x0039", + "access": "none", + "reg_width": 8 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_cmactable_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_cmactable_a0.json new file mode 100644 index 0000000..ea2c352 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_cmactable_a0.json @@ -0,0 +1,188 @@ +{ + "cpu": "KW45B41Z8", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "Hash update needed", + "description": "Hash update needed", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field000-bits-0-31", + "name": "Hash update needed", + "description": "Hash update needed", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field016", + "name": "CMAC_APP", + "description": "16 byte CMAC for application image. Hash of main flash primary boot image data at 0x0 OR Hash of Image data at ABASE (if FLW is enabled)", + "offset_int": "0x10", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "field032", + "name": "Hash update needed 1", + "description": "Hash update needed 1", + "offset_int": "0x20", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field032-bits-0-31", + "name": "Hash update needed 1", + "description": "Hash update needed 1", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field048", + "name": "CMAC_FALLBACK", + "description": "16 byte CMAC for fallback image. Hash of fallback image data (if “Image 1 Base Address” field in IFR0 page0 is not 0xFFFFFFFF)", + "offset_int": "0x30", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "field064", + "name": "Hash update needed 2", + "description": "Hash update needed", + "offset_int": "0x40", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128, + "bitfields": [ + { + "width": 32, + "id": "field064-bits-0-31", + "name": "Hash update needed", + "description": "Hash update needed", + "values": [ + { + "name": "NO HASH UPDATE NEEDED", + "value": 0, + "description": "No hash update needed" + }, + { + "name": "HASH UPDATE NEEDED", + "value": 4294967295, + "description": "Hash update needed" + } + ] + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "field0080", + "name": "CMAC_NBU", + "description": "Hash of radio (NBU) flash image data", + "offset_int": "0x50", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 128 + }, + { + "id": "Reserved0096", + "name": "Reserved0096", + "description": "This field is reserved for internal use", + "offset_int": "0x60", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "none", + "is_reserved": true, + "reg_width": 128, + "bitfields": [ + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + }, + { + "width": 32 + } + ] + }, + { + "id": "Reserved00112", + "name": "Reserved00112", + "description": "This field is reserved for internal use", + "offset_int": "0x70", + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "none", + "is_reserved": true, + "reg_width": 128 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a0.json new file mode 100644 index 0000000..901ad0c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a0.json @@ -0,0 +1,1462 @@ +{ + "cpu": "KW47B42ZB7", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_32_MHZ", + "value": 0, + "description": "Normal Boot (32MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 1, + "id": "field050-bit3", + "name": "BOOT_LOW_POWER", + "description": "Boot low power", + "values": [ + { + "name": "POWER_CFG0", + "value": 0, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.35 V" + }, + { + "name": "POWER_CFG1", + "value": 1, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.8 V" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot failure alert pin", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot failure alert pin is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot failure alert pin is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN_SELECTION", + "description": "Secure Boot Failure Alert Pin Selection", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00070-0007F", + "description": "Block 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000C0-000CF", + "description": "Block 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000D0-000DF", + "description": "Block 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000E0-000EF", + "description": "Block 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000F0-000FF", + "description": "Block 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CAN0 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CAN0enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0xFF", + "individual_write_lock": "none", + "reg_width": 8 + }, + { + "id": "Reserved0010A", + "name": "Reserved 0x0010A", + "description": "This field is reserved for internal use", + "offset_int": "0x010A", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "Field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "Field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "ELE_LOADABLE_FW_ENTRY_ADDRESS", + "description": "ELE_Loadable_FW_Entry_Address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled" + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a1.json new file mode 100644 index 0000000..ce2ba8b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a1.json @@ -0,0 +1,1727 @@ +{ + "cpu": "KW47B42ZB7", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_48_MHZ", + "value": 0, + "description": "Normal Boot (48MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 1, + "id": "field050-bit3", + "name": "BOOT_LOW_POWER", + "description": "Boot low power", + "values": [ + { + "name": "LOWER", + "value": 0, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.35 V" + }, + { + "name": "NORMAL", + "value": 1, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.8 V" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_OPTION", + "description": "Secure Boot option", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot option is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot option is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot Failure Alert Pin", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-0007F", + "description": "Reserved 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000CF", + "description": "Reserved 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000D0-000DF", + "description": "Reserved 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000E0-000EF", + "description": "Reserved 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000F0-000FF", + "description": "Reserved 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CAN0 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CAN0 enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout in milliseconds for active peripheral detection", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0xFF", + "individual_write_lock": "none", + "reg_width": 8 + }, + { + "id": "Reserved0010A", + "name": "Reserved 0x0010A", + "description": "This field is reserved for internal use", + "offset_int": "0x010A", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "TxID field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "RxID field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "ELE_LOADABLE_FW_ENTRY_ADDRESS", + "description": "ELE loadable FW resides address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature (for faster subsequent boot)", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00140-0014F", + "description": "Block 00140-0014F" + }, + "registers": [ + { + "id": "field140", + "name": "GO_ISP_MODE_OPTIONS", + "description": "If enter ISP mode, the log will be recorded on the corresponding pin when this bit and GoIspModeFailAlertPin are enable.", + "offset_int": "0x0140", + "default_value_int": "0xFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field140-bit1", + "name": "SECURE_BOOT_OPTION", + "description": "Secure Boot option", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot option is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot option is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field141", + "name": "GO_ISP_MODE_FAIL_ALERT_PIN", + "description": "Go ISP mode fail alert pin", + "offset_int": "0x0141", + "default_value_int": "0xFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field141-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field141-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00142", + "name": "Reserved 0x00142", + "description": "This field is reserved for internal use", + "offset_int": "0x00142", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 112 + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a2.1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a2.1.json new file mode 100644 index 0000000..d310c18 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/ifr_romcfg_a2.1.json @@ -0,0 +1,1771 @@ +{ + "cpu": "KW47B42ZB7", + "groups": [ + { + "group": { + "name": "Block 00000-0000F", + "description": "Block 00000-0000F" + }, + "registers": [ + { + "id": "field000", + "name": "FLW_Configuration", + "description": "FLW Configuration", + "offset_int": "0", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field000-bit0", + "name": "RESTORE_FLW_FLAG", + "description": "FLW Configuration", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal, use specified mapping" + }, + { + "name": "UNINITIALIZED", + "value": 1, + "description": "Dual Image Boot is uninitialized" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00001", + "name": "Reserved 0x00001", + "description": "This field is reserved for internal use", + "offset_int": "0x0001", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00004", + "name": "Reserved 0x00004", + "description": "This field is reserved for internal use", + "offset_int": "0x0004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FLW_REGION_ABASE", + "description": "FLW region, the starting address of the alternative boot image", + "offset_int": "0x0008", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field00C", + "name": "FLW_REGION_BCNT", + "description": "FLW region, the size of the alternative boot image in 32 KB blocks", + "offset_int": "0x000C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00010-0001F", + "description": "Block 00010-0001F" + }, + "registers": [ + { + "id": "field010", + "name": "CONFIGURE_NPX_FOR_NORMAL_BOOT", + "description": "NPX configuration", + "offset_int": "0x0010", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "USE_PRINCE", + "description": "Configure NPX to use PRINCE", + "values": [ + { + "name": "CONFIGURE_NPX", + "value": 0, + "description": "Configure NPX" + }, + { + "name": "NOT_CONFIGURE_NPX", + "value": 1, + "description": "Not configure NPX" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "GLOBAL_LOCK", + "description": "Global lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SYSTEM_LOCK", + "description": "System lock", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "System lock enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "System lock disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "GLOBAL_DECRYPTION", + "description": "Global decryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global decryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global decryption disable" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "GLOBAL_ENCRYPTION", + "description": "Global encryption", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Global encryption enable" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Global encryption disable" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "STICKY", + "description": "NPX configuration", + "offset_int": "0x0011", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field011-bit0", + "name": "CONFIGURE_NPX_REQUIRED", + "description": "Configure NPX required", + "values": [ + { + "name": "REQUIRED", + "value": 0, + "description": "NPX config. required; ROM follows normal boot path" + }, + { + "name": "NOT_REQUIRED", + "value": 1, + "description": "Not required, ROM follows Low-power wakeup path" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00012", + "name": "Reserved 0x00012", + "description": "This field is reserved for internal use", + "offset_int": "0x0012", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "NPX_REGIONS_VALID", + "description": "NPX regions valid", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field01C", + "name": "NPX_REGIONS_COUNT", + "description": "NPX regions count", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00020-0002F", + "description": "Block 00020-0002F" + }, + "registers": [ + { + "id": "field020", + "name": "NPX_REGION_0_VALID", + "description": "NPX region 0 valid", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field024", + "name": "NPX_REGION_0_START_ADDRESS", + "description": "NPX region 0 start address", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field028", + "name": "NPX_REGION_0_END_ADDRESS", + "description": "NPX region 0 end address", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field02C", + "name": "NPX_REGION_1_VALID", + "description": "NPX region 1 valid", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00030-0003F", + "description": "Block 00030-0003F" + }, + "registers": [ + { + "id": "field030", + "name": "NPX_REGION_1_START_ADDRESS", + "description": "NPX region 1 start address", + "offset_int": "0x0030", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field034", + "name": "NPX_REGION_1_END_ADDRESS", + "description": "NPX region 1 end address", + "offset_int": "0x0034", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field038", + "name": "NPX_REGION_2_VALID", + "description": "NPX region 2 valid", + "offset_int": "0x0038", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field03C", + "name": "NPX_REGION_2_START_ADDRESS", + "description": "NPX region 2 start address", + "offset_int": "0x003C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00040-0004F", + "description": "Block 00040-0004F" + }, + "registers": [ + { + "id": "field040", + "name": "NPX_REGION_2_END_ADDRESS", + "description": "NPX region 2 end address", + "offset_int": "0x0040", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field044", + "name": "NPX_REGION_3_VALID", + "description": "NPX region 3 valid", + "offset_int": "0x0044", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field048", + "name": "NPX_REGION_3_START_ADDRESS", + "description": "NPX region 3 start address", + "offset_int": "0x0048", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "field04C", + "name": "NPX_REGION_3_END_ADDRESS", + "description": "NPX region 3 end address", + "offset_int": "0x004C", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + } + ] + }, + { + "group": { + "name": "Block 00050-0005F", + "description": "Block 00050-0005F" + }, + "registers": [ + { + "id": "field050", + "name": "BOOT_CONFIGURATION", + "description": "Boot configuration", + "offset_int": "0x0050", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field050-bit0", + "name": "ENABLE_ISP_OR_NOT", + "description": "Enable ISP", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "Boot config pin enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "Boot config pin disabled" + } + ] + }, + { + "width": 2, + "id": "field050-bits1-2", + "name": "BOOT_SPEED", + "description": "Boot speed", + "values": [ + { + "name": "NORMAL_BOOT_48_MHZ", + "value": 0, + "description": "Normal Boot (48MHz)" + }, + { + "name": "FAST_BOOT_96_MHZ", + "value": 2, + "description": "Fast Boot (96 MHz)" + }, + { + "name": "NORM_BOOT_DFLT1", + "value": 1, + "description": "Normal Boot (default)" + }, + { + "name": "NORM_BOOT_DFLT2", + "value": 3, + "description": "Normal Boot (default)" + } + ] + }, + { + "width": 1, + "id": "field050-bit3", + "name": "BOOT_LOW_POWER", + "description": "Boot low power", + "values": [ + { + "name": "LOWER", + "value": 0, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.35 V" + }, + { + "name": "NORMAL", + "value": 1, + "description": "Normal Boot: Core LDO = 1.0 V, DCDC = 1.25 V; Fast Boot: Core LDO = 1.1 V DCDC = 1.8 V" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00051", + "name": "Reserved 0x00051", + "description": "This field is reserved for internal use", + "offset_int": "0x0051", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00060-0006F", + "description": "Block 00060-0006F" + }, + "registers": [ + { + "id": "field060", + "name": "SECURE_BOOT_OPTIONS", + "description": "Secure Boot options", + "offset_int": "0x0060", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field060-bit1", + "name": "SECURE_BOOT_OPTION", + "description": "Secure Boot option", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot option is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot option is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field061", + "name": "SECURE_BOOT_FAILURE_ALERT_PIN", + "description": "Secure Boot Failure Alert Pin", + "offset_int": "0x0061", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field061-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field061-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00062", + "name": "Reserved 0x00062", + "description": "This field is reserved for internal use", + "offset_int": "0x0062", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-0007F", + "description": "Reserved 00070-0007F" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00080-0008F", + "description": "Block 00080-0008F" + }, + "registers": [ + { + "id": "field080", + "name": "BOOT_IMAGE_BASE_ADDRESS3", + "description": "Boot Image Base Address 3", + "offset_int": "0x0080", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00090-0009F", + "description": "Block 00090-0009F" + }, + "registers": [ + { + "id": "field090", + "name": "BOOT_IMAGE_BASE_ADDRESS2", + "description": "Boot Image Base Address 2", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000A0-000AF", + "description": "Block 000A0-000AF" + }, + "registers": [ + { + "id": "field0A0", + "name": "BOOT_IMAGE_BASE_ADDRESS1", + "description": "Boot Image Base Address 1", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 000B0-000BF", + "description": "Block 000B0-000BF" + }, + "registers": [ + { + "id": "field0B0", + "name": "BOOT_IMAGE_BASE_ADDRESS0", + "description": "Boot Image Base Address 0", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000CF", + "description": "Reserved 000C0-000CF" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000D0-000DF", + "description": "Reserved 000D0-000DF" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000E0-000EF", + "description": "Reserved 000E0-000EF" + }, + "registers": [ + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000F0-000FF", + "description": "Reserved 000F0-000FF" + }, + "registers": [ + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00100-0010F", + "description": "Block 00100-0010F" + }, + "registers": [ + { + "id": "field100", + "name": "PERIPHERALS_ENABLE", + "description": "Peripherals Enable", + "offset_int": "0x0100", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field100-bit0", + "name": "LPUART1_PERIPHERAL_FOR_ISP", + "description": "LPUART1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPUART1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPUART1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit1", + "name": "LPI2C1_PERIPHERAL_FOR_ISP", + "description": "LPI2C1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPI2C1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPI2C1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit2", + "name": "LPSPI1_PERIPHERAL_FOR_ISP", + "description": "LPSPI1 peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "LPSPI1 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "LPSPI1 enabled" + } + ] + }, + { + "width": 1, + "id": "field100-bit3", + "name": "CAN_PERIPHERAL_FOR_ISP", + "description": "CAN peripheral for ISP", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CAN0 disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CAN0 enabled" + } + ] + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00101", + "name": "Reserved 0x00101", + "description": "This field is reserved for internal use", + "offset_int": "0x0101", + "is_reserved": true, + "default_value_int": "0x00FFFFFF", + "individual_write_lock": "none", + "reg_width": 24 + }, + { + "id": "field104", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Peripheral Detection Timeout in milliseconds for active peripheral detection", + "offset_int": "0x0104", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "Reserved00106", + "name": "Reserved 0x00106", + "description": "This field is reserved for internal use", + "offset_int": "0x0106", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field108", + "name": "I2C_SLAVE_ADDRESS", + "description": "I2C Slave Address", + "offset_int": "0x0108", + "default_value_int": "0x00FF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8 + }, + { + "id": "Reserved00109", + "name": "Reserved 0x00109", + "description": "This field is reserved for internal use", + "offset_int": "0x0109", + "is_reserved": true, + "default_value_int": "0xFF", + "individual_write_lock": "none", + "reg_width": 8 + }, + { + "id": "Reserved0010A", + "name": "Reserved 0x0010A", + "description": "This field is reserved for internal use", + "offset_int": "0x010A", + "is_reserved": true, + "default_value_int": "0xFFFF", + "individual_write_lock": "none", + "reg_width": 16 + }, + { + "id": "field10C", + "name": "CANTxID", + "description": "TxID field.", + "offset_int": "0x010C", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + }, + { + "id": "field10E", + "name": "CANRxID", + "description": "RxID field.", + "offset_int": "0x010E", + "default_value_int": "0xFFFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Block 00110-0011F", + "description": "Block 00110-0011F" + }, + "registers": [ + { + "id": "field110", + "name": "ELE_LOADABLE_FW_ENTRY_ADDRESS", + "description": "ELE loadable FW resides address", + "offset_int": "0x0110", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00120-0012F", + "description": "Block 00120-0012F" + }, + "registers": [ + { + "id": "field120", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION", + "description": "Secure Hash based image verification feature (for faster subsequent boot)", + "offset_int": "0x0120", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit_16bytes", + "bitfields": [ + { + "width": 32, + "id": "field120-bits0-31", + "name": "SECURE_HASH_BASED_IMAGE_VERIFICATION_CONFIG", + "description": "Secure Hash based image verification feature", + "values": [ + { + "name": "DISABLED", + "value": 4294967295, + "description": "Disabled (ECDSA based verification will be used)." + }, + { + "name": "ENABLED", + "value": 1213415752, + "description": "Enabled ('HASH')." + } + ] + } + ] + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00130-0013F", + "description": "Block 00130-0013F" + }, + "registers": [ + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Block 00140-0014F", + "description": "Block 00140-0014F" + }, + "registers": [ + { + "id": "field140", + "name": "GO_ISP_MODE_OPTIONS", + "description": "If enter ISP mode, the log will be recorded on the corresponding pin when this bit and GoIspModeFailAlertPin are enable.", + "offset_int": "0x0140", + "default_value_int": "0xFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field140-bit1", + "name": "SECURE_BOOT_OPTION", + "description": "Secure Boot option", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Secure Boot option is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Secure Boot option is disabled" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field141", + "name": "GO_ISP_MODE_FAIL_ALERT_PIN", + "description": "Go ISP mode fail alert pin", + "offset_int": "0x0141", + "default_value_int": "0xFF", + "individual_write_lock": "implicit_16bytes", + "reg_width": 8, + "bitfields": [ + { + "width": 5, + "id": "field141-bits0-4", + "name": "PIN_SELECTION", + "description": "Pin selection", + "values": [ + { + "name": "PIN_0", + "value": 0, + "description": "Pin 0" + }, + { + "name": "PIN_1", + "value": 1, + "description": "Pin 1" + }, + { + "name": "PIN_2", + "value": 2, + "description": "Pin 2" + }, + { + "name": "PIN_3", + "value": 3, + "description": "Pin 3" + }, + { + "name": "PIN_4", + "value": 4, + "description": "Pin 4" + }, + { + "name": "PIN_5", + "value": 5, + "description": "Pin 5" + }, + { + "name": "PIN_6", + "value": 6, + "description": "Pin 6" + }, + { + "name": "PIN_7", + "value": 7, + "description": "Pin 7" + }, + { + "name": "PIN_8", + "value": 8, + "description": "Pin 8" + }, + { + "name": "PIN_9", + "value": 9, + "description": "Pin 9" + }, + { + "name": "PIN_10", + "value": 10, + "description": "Pin 10" + }, + { + "name": "PIN_11", + "value": 11, + "description": "Pin 11" + }, + { + "name": "PIN_12", + "value": 12, + "description": "Pin 12" + }, + { + "name": "PIN_13", + "value": 13, + "description": "Pin 13" + }, + { + "name": "PIN_14", + "value": 14, + "description": "Pin 14" + }, + { + "name": "PIN_15", + "value": 15, + "description": "Pin 15" + }, + { + "name": "PIN_16", + "value": 16, + "description": "Pin 16" + }, + { + "name": "PIN_17", + "value": 17, + "description": "Pin 17" + }, + { + "name": "PIN_18", + "value": 18, + "description": "Pin 18" + }, + { + "name": "PIN_19", + "value": 19, + "description": "Pin 19" + }, + { + "name": "PIN_20", + "value": 20, + "description": "Pin 20" + }, + { + "name": "PIN_21", + "value": 21, + "description": "Pin 21" + }, + { + "name": "PIN_22", + "value": 22, + "description": "Pin 22" + }, + { + "name": "PIN_23", + "value": 23, + "description": "Pin 23" + }, + { + "name": "PIN_24", + "value": 24, + "description": "Pin 24" + }, + { + "name": "PIN_25", + "value": 25, + "description": "Pin 25" + }, + { + "name": "PIN_26", + "value": 26, + "description": "Pin 26" + }, + { + "name": "PIN_27", + "value": 27, + "description": "Pin 27" + }, + { + "name": "PIN_28", + "value": 28, + "description": "Pin 28" + }, + { + "name": "PIN_29", + "value": 29, + "description": "Pin 29" + }, + { + "name": "PIN_30", + "value": 30, + "description": "Pin 30" + }, + { + "name": "PIN_31", + "value": 31, + "description": "Pin 31" + } + ] + }, + { + "width": 3, + "id": "field141-bits5-7", + "name": "PORT_SELECTION", + "description": "Port Selection", + "values": [ + { + "name": "PORTA", + "value": 0, + "description": "Port A" + }, + { + "name": "PORTB", + "value": 1, + "description": "Port B" + }, + { + "name": "PORTC", + "value": 2, + "description": "Port C" + }, + { + "name": "PORTD", + "value": 3, + "description": "Port D" + }, + { + "name": "PORTE", + "value": 4, + "description": "Port E" + } + ] + } + ] + }, + { + "id": "Reserved00142", + "name": "Reserved 0x00142", + "description": "This field is reserved for internal use", + "offset_int": "0x00142", + "is_reserved": true, + "default_value_int": "0xFFFFFFFFFFFFFFFFFFFFFFFFFFFF", + "individual_write_lock": "none", + "reg_width": 112 + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/tz.json new file mode 100644 index 0000000..9736f65 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47b42zb7/tz.json @@ -0,0 +1,2725 @@ +{ + "cpu": "kw47b42zb7", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "TZM info which data are initialized (tzm_control)", + "description": "TrustZone register - TZM info which data are initialized (tzm_control)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register(cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register(cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register(cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register(cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "TRDC Control Register (cr)", + "description": "TrustZone register - TRDC Control Register (cr)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "TRDC IDAU Control Register (idau_cr)", + "description": "TrustZone register - TRDC IDAU Control Register (idau_cr)", + "default_value_int": "0x8" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Master 0 Domain Assignment Register (mda_w0_0_dfmt0)", + "description": "TrustZone register - Master 0 Domain Assignment Register (mda_w0_0_dfmt0)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Master 1 Domain Assignment Register (mda_w0_1_dfmt1)", + "description": "TrustZone register - Master 1 Domain Assignment Register (mda_w0_1_dfmt1)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Master 2 Domain Assignment Register (mda_w0_2_dfmt1)", + "description": "TrustZone register - Master 2 Domain Assignment Register (mda_w0_2_dfmt1)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "Master 3 Domain Assignment Register (mda_w0_3_dfmt1)", + "description": "TrustZone register - Master 3 Domain Assignment Register (mda_w0_3_dfmt1)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "Master 4 Domain Assignment Register (mda_w0_4_dfmt1)", + "description": "TrustZone register - Master 4 Domain Assignment Register (mda_w0_4_dfmt1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 0 (mbc0_memn_glbac0)", + "description": "TrustZone register - MBC 0 Global Access Control Register 0 (mbc0_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 1 (mbc0_memn_glbac1)", + "description": "TrustZone register - MBC 0 Global Access Control Register 1 (mbc0_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 2 (mbc0_memn_glbac2)", + "description": "TrustZone register - MBC 0 Global Access Control Register 2 (mbc0_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 3 (mbc0_memn_glbac3)", + "description": "TrustZone register - MBC 0 Global Access Control Register 3 (mbc0_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 4 (mbc0_memn_glbac4)", + "description": "TrustZone register - MBC 0 Global Access Control Register 4 (mbc0_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 5 (mbc0_memn_glbac5)", + "description": "TrustZone register - MBC 0 Global Access Control Register 5 (mbc0_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 6 (mbc0_memn_glbac6)", + "description": "TrustZone register - MBC 0 Global Access Control Register 6 (mbc0_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "MBC 0 Global Access Control Register 7 (mbc0_memn_glbac7)", + "description": "TrustZone register - MBC 0 Global Access Control Register 7 (mbc0_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 0 (mbc0_0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 0 (mbc0_0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 1 (mbc0_0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 1 (mbc0_0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 2 (mbc0_0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 2 (mbc0_0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 3 (mbc0_0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 3 (mbc0_0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 4 (mbc0_0_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 4 (mbc0_0_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 5 (mbc0_0_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 5 (mbc0_0_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 6 (mbc0_0_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 6 (mbc0_0_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 0 Configuration Word Register 7 (mbc0_0_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 0 Configuration Word Register 7 (mbc0_0_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 1 Configuration Word Register 0 (mbc0_0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 1 Configuration Word Register 0 (mbc0_0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 2 Configuration Word Register 0 (mbc0_0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 2 Configuration Word Register 0 (mbc0_0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 3 Configuration Word Register 0 (mbc0_0_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 3 Configuration Word Register 0 (mbc0_0_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "MBC 0 Domain 0 Slave 3 Configuration Word Register 1 (mbc0_0_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 0 Slave 3 Configuration Word Register 1 (mbc0_0_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 0 (mbc0_1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 0 (mbc0_1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 1 (mbc0_1_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 1 (mbc0_1_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 2 (mbc0_1_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 2 (mbc0_1_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 3 (mbc0_1_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 3 (mbc0_1_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 4 (mbc0_1_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 4 (mbc0_1_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 5 (mbc0_1_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 5 (mbc0_1_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 6 (mbc0_1_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 6 (mbc0_1_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 0 Configuration Word Register 7 (mbc0_1_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 0 Configuration Word Register 7 (mbc0_1_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 1 Configuration Word Register 0 (mbc0_1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 1 Configuration Word Register 0 (mbc0_1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 2 Configuration Word Register 0 (mbc0_1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 2 Configuration Word Register 0 (mbc0_1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 3 Configuration Word Register 0 (mbc0_1_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 3 Configuration Word Register 0 (mbc0_1_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "MBC 0 Domain 1 Slave 3 Configuration Word Register 1 (mbc0_1_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 1 Slave 3 Configuration Word Register 1 (mbc0_1_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 0 (mbc0_2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 0 (mbc0_2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 1 (mbc0_2_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 1 (mbc0_2_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 2 (mbc0_2_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 2 (mbc0_2_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 3 (mbc0_2_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 3 (mbc0_2_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 4 (mbc0_2_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 4 (mbc0_2_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 5 (mbc0_2_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 5 (mbc0_2_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 6 (mbc0_2_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 6 (mbc0_2_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 0 Configuration Word Register 7 (mbc0_2_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 0 Configuration Word Register 7 (mbc0_2_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 1 Configuration Word Register 0 (mbc0_2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 1 Configuration Word Register 0 (mbc0_2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 2 Configuration Word Register 0 (mbc0_2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 2 Configuration Word Register 0 (mbc0_2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 3 Configuration Word Register 0 (mbc0_2_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 3 Configuration Word Register 0 (mbc0_2_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "MBC 0 Domain 2 Slave 3 Configuration Word Register 1 (mbc0_2_mem3_blk_cfg_w1)", + "description": "TrustZone register - MBC 0 Domain 2 Slave 3 Configuration Word Register 1 (mbc0_2_mem3_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 0 (mbc1_memn_glbac0)", + "description": "TrustZone register - MBC 1 Global Access Control Register 0 (mbc1_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 1 (mbc1_memn_glbac1)", + "description": "TrustZone register - MBC 1 Global Access Control Register 1 (mbc1_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 2 (mbc1_memn_glbac2)", + "description": "TrustZone register - MBC 1 Global Access Control Register 2 (mbc1_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 3 (mbc1_memn_glbac3)", + "description": "TrustZone register - MBC 1 Global Access Control Register 3 (mbc1_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 4 (mbc1_memn_glbac4)", + "description": "TrustZone register - MBC 1 Global Access Control Register 4 (mbc1_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 5 (mbc1_memn_glbac5)", + "description": "TrustZone register - MBC 1 Global Access Control Register 5 (mbc1_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 6 (mbc1_memn_glbac6)", + "description": "TrustZone register - MBC 1 Global Access Control Register 6 (mbc1_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "MBC 1 Global Access Control Register 7 (mbc1_memn_glbac7)", + "description": "TrustZone register - MBC 1 Global Access Control Register 7 (mbc1_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 0 Configuration Word Register 0 (mbc1_0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 0 Configuration Word Register 0 (mbc1_0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 1 Configuration Word Register 0 (mbc1_0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 1 Configuration Word Register 0 (mbc1_0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 1 Configuration Word Register 1 (mbc1_0_mem1_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 1 Configuration Word Register 1 (mbc1_0_mem1_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 2 Configuration Word Register 0 (mbc1_0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 2 Configuration Word Register 0 (mbc1_0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 2 Configuration Word Register 1 (mbc1_0_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 2 Configuration Word Register 1 (mbc1_0_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "MBC 1 Domain 0 Slave 3 Configuration Word Register 0 (mbc1_0_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 0 Slave 3 Configuration Word Register 0 (mbc1_0_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 0 Configuration Word Register 0 (mbc1_1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 0 Configuration Word Register 0 (mbc1_1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 1 Configuration Word Register 0 (mbc1_1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 1 Configuration Word Register 0 (mbc1_1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 1 Configuration Word Register 1 (mbc1_1_mem1_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 1 Configuration Word Register 1 (mbc1_1_mem1_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 2 Configuration Word Register 0 (mbc1_1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 2 Configuration Word Register 0 (mbc1_1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 2 Configuration Word Register 1 (mbc1_1_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 2 Configuration Word Register 1 (mbc1_1_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "MBC 1 Domain 1 Slave 3 Configuration Word Register 0 (mbc1_1_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 1 Slave 3 Configuration Word Register 0 (mbc1_1_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 0 Configuration Word Register 0 (mbc1_2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 0 Configuration Word Register 0 (mbc1_2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 1 Configuration Word Register 0 (mbc1_2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 1 Configuration Word Register 0 (mbc1_2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 1 Configuration Word Register 1 (mbc1_2_mem1_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 1 Configuration Word Register 1 (mbc1_2_mem1_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 2 Configuration Word Register 0 (mbc1_2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 2 Configuration Word Register 0 (mbc1_2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 2 Configuration Word Register 1 (mbc1_2_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 2 Configuration Word Register 1 (mbc1_2_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "MBC 1 Domain 2 Slave 3 Configuration Word Register 0 (mbc1_2_mem3_blk_cfg_w0)", + "description": "TrustZone register - MBC 1 Domain 2 Slave 3 Configuration Word Register 0 (mbc1_2_mem3_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 0 (mbc2_memn_glbac0)", + "description": "TrustZone register - MBC 2 Global Access Control Register 0 (mbc2_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 1 (mbc2_memn_glbac1)", + "description": "TrustZone register - MBC 2 Global Access Control Register 1 (mbc2_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 2 (mbc2_memn_glbac2)", + "description": "TrustZone register - MBC 2 Global Access Control Register 2 (mbc2_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 3 (mbc2_memn_glbac3)", + "description": "TrustZone register - MBC 2 Global Access Control Register 3 (mbc2_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 4 (mbc2_memn_glbac4)", + "description": "TrustZone register - MBC 2 Global Access Control Register 4 (mbc2_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 5 (mbc2_memn_glbac5)", + "description": "TrustZone register - MBC 2 Global Access Control Register 5 (mbc2_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 6 (mbc2_memn_glbac6)", + "description": "TrustZone register - MBC 2 Global Access Control Register 6 (mbc2_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "MBC 2 Global Access Control Register 7 (mbc2_memn_glbac7)", + "description": "TrustZone register - MBC 2 Global Access Control Register 7 (mbc2_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 0 (mbc2_0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 0 (mbc2_0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 1 (mbc2_0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 1 (mbc2_0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 2 (mbc2_0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 2 (mbc2_0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 3 (mbc2_0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 3 (mbc2_0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 4 (mbc2_0_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 4 (mbc2_0_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 5 (mbc2_0_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 5 (mbc2_0_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 6 (mbc2_0_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 6 (mbc2_0_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 7 (mbc2_0_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 7 (mbc2_0_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 8 (mbc2_0_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 8 (mbc2_0_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 9 (mbc2_0_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 9 (mbc2_0_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 0 Configuration Word Register 10 (mbc2_0_mem0_blk_cfg_w10)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 0 Configuration Word Register 10 (mbc2_0_mem0_blk_cfg_w10)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 1 Configuration Word Register 0 (mbc2_0_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 1 Configuration Word Register 0 (mbc2_0_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 2 Configuration Word Register 0 (mbc2_0_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 2 Configuration Word Register 0 (mbc2_0_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "MBC 2 Domain 0 Slave 2 Configuration Word Register 1 (mbc2_0_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 0 Slave 2 Configuration Word Register 1 (mbc2_0_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_1_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_1_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_1_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_1_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_1_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_1_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_1_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_1_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_1_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_1_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_1_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_1_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_1_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_1_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_1_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_1_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_1_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_1_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_1_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_1_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 10 (mbc2_1_mem0_blk_cfg_w10)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 10 (mbc2_1_mem0_blk_cfg_w10)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_1_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_1_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_1_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_1_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_1_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_1_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_2_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 0 (mbc2_2_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_2_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 1 (mbc2_2_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_2_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 2 (mbc2_2_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_2_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 3 (mbc2_2_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_2_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 4 (mbc2_2_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_2_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 5 (mbc2_2_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_2_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 6 (mbc2_2_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_2_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 7 (mbc2_2_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_2_mem0_blk_cfg_w8)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 8 (mbc2_2_mem0_blk_cfg_w8)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_2_mem0_blk_cfg_w9)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 9 (mbc2_2_mem0_blk_cfg_w9)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 0 Configuration Word Register 10 (mbc2_2_mem0_blk_cfg_w10)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 0 Configuration Word Register 10 (mbc2_2_mem0_blk_cfg_w10)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_2_mem1_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 1 Configuration Word Register 0 (mbc2_2_mem1_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_2_mem2_blk_cfg_w0)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 0 (mbc2_2_mem2_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_2_mem2_blk_cfg_w1)", + "description": "TrustZone register - MBC 2 Domain 1 Slave 2 Configuration Word Register 1 (mbc2_2_mem2_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 0 (mrc0_memn_glbac0)", + "description": "TrustZone register - MRC 0 Global Access Control Register 0 (mrc0_memn_glbac0)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 1 (mrc0_memn_glbac1)", + "description": "TrustZone register - MRC 0 Global Access Control Register 1 (mrc0_memn_glbac1)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 2 (mrc0_memn_glbac2)", + "description": "TrustZone register - MRC 0 Global Access Control Register 2 (mrc0_memn_glbac2)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 3 (mrc0_memn_glbac3)", + "description": "TrustZone register - MRC 0 Global Access Control Register 3 (mrc0_memn_glbac3)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 4 (mrc0_memn_glbac4)", + "description": "TrustZone register - MRC 0 Global Access Control Register 4 (mrc0_memn_glbac4)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 5 (mrc0_memn_glbac5)", + "description": "TrustZone register - MRC 0 Global Access Control Register 5 (mrc0_memn_glbac5)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 6 (mrc0_memn_glbac6)", + "description": "TrustZone register - MRC 0 Global Access Control Register 6 (mrc0_memn_glbac6)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "MRC 0 Global Access Control Register 7 (mrc0_memn_glbac7)", + "description": "TrustZone register - MRC 0 Global Access Control Register 7 (mrc0_memn_glbac7)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 0 (mrc0_0_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 0 (mrc0_0_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 1 (mrc0_0_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 0 Memory Region Descriptor Register 1 (mrc0_0_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 0 (mrc0_0_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 0 (mrc0_0_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 1 (mrc0_0_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 1 Memory Region Descriptor Register 1 (mrc0_0_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 0 (mrc0_0_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 0 (mrc0_0_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 1 (mrc0_0_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 2 Memory Region Descriptor Register 1 (mrc0_0_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 0 (mrc0_0_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 0 (mrc0_0_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 1 (mrc0_0_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 3 Memory Region Descriptor Register 1 (mrc0_0_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 0 (mrc0_0_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 0 (mrc0_0_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 1 (mrc0_0_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 4 Memory Region Descriptor Register 1 (mrc0_0_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 0 (mrc0_0_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 0 (mrc0_0_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 1 (mrc0_0_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 5 Memory Region Descriptor Register 1 (mrc0_0_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 0 (mrc0_0_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 0 (mrc0_0_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 1 (mrc0_0_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 6 Memory Region Descriptor Register 1 (mrc0_0_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 0 (mrc0_0_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 0 (mrc0_0_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 1 (mrc0_0_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 0 Region 7 Memory Region Descriptor Register 1 (mrc0_0_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 0 (mrc0_1_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 0 (mrc0_1_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 1 (mrc0_1_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 0 Memory Region Descriptor Register 1 (mrc0_1_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 0 (mrc0_1_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 0 (mrc0_1_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 1 (mrc0_1_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 1 Memory Region Descriptor Register 1 (mrc0_1_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 0 (mrc0_1_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 0 (mrc0_1_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 1 (mrc0_1_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 2 Memory Region Descriptor Register 1 (mrc0_1_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 0 (mrc0_1_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 0 (mrc0_1_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 1 (mrc0_1_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 3 Memory Region Descriptor Register 1 (mrc0_1_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 0 (mrc0_1_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 0 (mrc0_1_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 1 (mrc0_1_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 4 Memory Region Descriptor Register 1 (mrc0_1_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 0 (mrc0_1_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 0 (mrc0_1_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 1 (mrc0_1_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 5 Memory Region Descriptor Register 1 (mrc0_1_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 0 (mrc0_1_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 0 (mrc0_1_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 1 (mrc0_1_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 6 Memory Region Descriptor Register 1 (mrc0_1_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 0 (mrc0_1_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 0 (mrc0_1_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 1 (mrc0_1_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 1 Region 7 Memory Region Descriptor Register 1 (mrc0_1_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 0 (mrc0_2_rgd0_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 0 (mrc0_2_rgd0_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 1 (mrc0_2_rgd0_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 0 Memory Region Descriptor Register 1 (mrc0_2_rgd0_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 0 (mrc0_2_rgd1_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 0 (mrc0_2_rgd1_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 1 (mrc0_2_rgd1_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 1 Memory Region Descriptor Register 1 (mrc0_2_rgd1_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 0 (mrc0_2_rgd2_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 0 (mrc0_2_rgd2_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 1 (mrc0_2_rgd2_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 2 Memory Region Descriptor Register 1 (mrc0_2_rgd2_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 0 (mrc0_2_rgd3_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 0 (mrc0_2_rgd3_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 1 (mrc0_2_rgd3_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 3 Memory Region Descriptor Register 1 (mrc0_2_rgd3_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 0 (mrc0_2_rgd4_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 0 (mrc0_2_rgd4_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 1 (mrc0_2_rgd4_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 4 Memory Region Descriptor Register 1 (mrc0_2_rgd4_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 0 (mrc0_2_rgd5_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 0 (mrc0_2_rgd5_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 1 (mrc0_2_rgd5_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 5 Memory Region Descriptor Register 1 (mrc0_2_rgd5_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 0 (mrc0_2_rgd6_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 0 (mrc0_2_rgd6_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 1 (mrc0_2_rgd6_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 6 Memory Region Descriptor Register 1 (mrc0_2_rgd6_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 0 (mrc0_2_rgd7_w0)", + "description": "TrustZone register - MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 0 (mrc0_2_rgd7_w0)", + "default_value_int": "0x0" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 1 (mrc0_2_rgd7_w1)", + "description": "TrustZone register - MRC 0 Domain 2 Region 7 Memory Region Descriptor Register 1 (mrc0_2_rgd7_w1)", + "default_value_int": "0x0" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "GPIO A Lock Register (gpioa_lock)", + "description": "TrustZone register - GPIO A Lock Register (gpioa_lock)", + "default_value_int": "0x0" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "GPIO A Pin Control Non-Secure Register (gpioa_pcns)", + "description": "TrustZone register - GPIO A Pin Control Non-Secure Register (gpioa_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "GPIO A Interrupt Control Non-Secure Register (gpioa_icns)", + "description": "TrustZone register - GPIO A Interrupt Control Non-Secure Register (gpioa_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "GPIO A Pin Control Non-Privilege Register (gpioa_pcnp)", + "description": "TrustZone register - GPIO A Pin Control Non-Privilege Register (gpioa_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "GPIO A Interrupt Control Non-Privilege Register (gpioa_icnp)", + "description": "TrustZone register - GPIO A Interrupt Control Non-Privilege Register (gpioa_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 0 (gpioa_icr0)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 0 (gpioa_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 1 (gpioa_icr1)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 1 (gpioa_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 2 (gpioa_icr2)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 2 (gpioa_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 3 (gpioa_icr3)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 3 (gpioa_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 4 (gpioa_icr4)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 4 (gpioa_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 5 (gpioa_icr5)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 5 (gpioa_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 6 (gpioa_icr6)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 6 (gpioa_icr6)", + "default_value_int": "0x0" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 7 (gpioa_icr7)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 7 (gpioa_icr7)", + "default_value_int": "0x0" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 8 (gpioa_icr8)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 8 (gpioa_icr8)", + "default_value_int": "0x0" + }, + { + "id": "field41C", + "offset_int": "0x41c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 9 (gpioa_icr9)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 9 (gpioa_icr9)", + "default_value_int": "0x0" + }, + { + "id": "field420", + "offset_int": "0x420", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 10 (gpioa_icr10)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 10 (gpioa_icr10)", + "default_value_int": "0x0" + }, + { + "id": "field424", + "offset_int": "0x424", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 11 (gpioa_icr11)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 11 (gpioa_icr11)", + "default_value_int": "0x0" + }, + { + "id": "field428", + "offset_int": "0x428", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 16 (gpioa_icr16)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 16 (gpioa_icr16)", + "default_value_int": "0x0" + }, + { + "id": "field42C", + "offset_int": "0x42c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 17 (gpioa_icr17)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 17 (gpioa_icr17)", + "default_value_int": "0x0" + }, + { + "id": "field430", + "offset_int": "0x430", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 18 (gpioa_icr18)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 18 (gpioa_icr18)", + "default_value_int": "0x0" + }, + { + "id": "field434", + "offset_int": "0x434", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 19 (gpioa_icr19)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 19 (gpioa_icr19)", + "default_value_int": "0x0" + }, + { + "id": "field438", + "offset_int": "0x438", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 20 (gpioa_icr20)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 20 (gpioa_icr20)", + "default_value_int": "0x0" + }, + { + "id": "field43C", + "offset_int": "0x43c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 21 (gpioa_icr21)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 21 (gpioa_icr21)", + "default_value_int": "0x0" + }, + { + "id": "field440", + "offset_int": "0x440", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 22 (gpioa_icr22)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 22 (gpioa_icr22)", + "default_value_int": "0x0" + }, + { + "id": "field444", + "offset_int": "0x444", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 23 (gpioa_icr23)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 23 (gpioa_icr23)", + "default_value_int": "0x0" + }, + { + "id": "field448", + "offset_int": "0x448", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 24 (gpioa_icr24)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 24 (gpioa_icr24)", + "default_value_int": "0x0" + }, + { + "id": "field44C", + "offset_int": "0x44c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 25 (gpioa_icr25)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 25 (gpioa_icr25)", + "default_value_int": "0x0" + }, + { + "id": "field450", + "offset_int": "0x450", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 26 (gpioa_icr26)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 26 (gpioa_icr26)", + "default_value_int": "0x0" + }, + { + "id": "field454", + "offset_int": "0x454", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 27 (gpioa_icr27)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 27 (gpioa_icr27)", + "default_value_int": "0x0" + }, + { + "id": "field458", + "offset_int": "0x458", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 30 (gpioa_icr30)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 30 (gpioa_icr30)", + "default_value_int": "0x0" + }, + { + "id": "field45C", + "offset_int": "0x45c", + "reg_width": 32, + "name": "GPIO A Interrupt Control Pin 31 (gpioa_icr31)", + "description": "TrustZone register - GPIO A Interrupt Control Pin 31 (gpioa_icr31)", + "default_value_int": "0x0" + }, + { + "id": "field460", + "offset_int": "0x460", + "reg_width": 32, + "name": "GPIO B Lock Register (gpiob_lock)", + "description": "TrustZone register - GPIO B Lock Register (gpiob_lock)", + "default_value_int": "0x0" + }, + { + "id": "field464", + "offset_int": "0x464", + "reg_width": 32, + "name": "GPIO B Pin Control Non-Secure Register (gpiob_pcns)", + "description": "TrustZone register - GPIO B Pin Control Non-Secure Register (gpiob_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field468", + "offset_int": "0x468", + "reg_width": 32, + "name": "GPIO B Interrupt Control Non-Secure Register (gpiob_icns)", + "description": "TrustZone register - GPIO B Interrupt Control Non-Secure Register (gpiob_icns)", + "default_value_int": "0x0" + }, + { + "id": "field46C", + "offset_int": "0x46c", + "reg_width": 32, + "name": "GPIO B Pin Control Non-Privilege Register (gpiob_pcnp)", + "description": "TrustZone register - GPIO B Pin Control Non-Privilege Register (gpiob_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field470", + "offset_int": "0x470", + "reg_width": 32, + "name": "GPIO B Interrupt Control Non-Privilege Register (gpiob_icnp)", + "description": "TrustZone register - GPIO B Interrupt Control Non-Privilege Register (gpiob_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field474", + "offset_int": "0x474", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 0 (gpiob_icr0)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 0 (gpiob_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field478", + "offset_int": "0x478", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 1 (gpiob_icr1)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 1 (gpiob_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field47C", + "offset_int": "0x47c", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 2 (gpiob_icr2)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 2 (gpiob_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field480", + "offset_int": "0x480", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 3 (gpiob_icr3)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 3 (gpiob_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field484", + "offset_int": "0x484", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 4 (gpiob_icr4)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 4 (gpiob_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field488", + "offset_int": "0x488", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 5 (gpiob_icr5)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 5 (gpiob_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field48C", + "offset_int": "0x48c", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 6 (gpiob_icr6)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 6 (gpiob_icr6)", + "default_value_int": "0x0" + }, + { + "id": "field490", + "offset_int": "0x490", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 7 (gpiob_icr7)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 7 (gpiob_icr7)", + "default_value_int": "0x0" + }, + { + "id": "field494", + "offset_int": "0x494", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 8 (gpiob_icr8)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 8 (gpiob_icr8)", + "default_value_int": "0x0" + }, + { + "id": "field498", + "offset_int": "0x498", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 9 (gpiob_icr9)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 9 (gpiob_icr9)", + "default_value_int": "0x0" + }, + { + "id": "field49C", + "offset_int": "0x49c", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 10 (gpiob_icr10)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 10 (gpiob_icr10)", + "default_value_int": "0x0" + }, + { + "id": "field4A0", + "offset_int": "0x4a0", + "reg_width": 32, + "name": "GPIO B Interrupt Control Pin 11 (gpiob_icr11)", + "description": "TrustZone register - GPIO B Interrupt Control Pin 11 (gpiob_icr11)", + "default_value_int": "0x0" + }, + { + "id": "field4A4", + "offset_int": "0x4a4", + "reg_width": 32, + "name": "GPIO C Lock Register (gpioc_lock)", + "description": "TrustZone register - GPIO C Lock Register (gpioc_lock)", + "default_value_int": "0x0" + }, + { + "id": "field4A8", + "offset_int": "0x4a8", + "reg_width": 32, + "name": "GPIO C Pin Control Non-Secure Register (gpioc_pcns)", + "description": "TrustZone register - GPIO C Pin Control Non-Secure Register (gpioc_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field4AC", + "offset_int": "0x4ac", + "reg_width": 32, + "name": "GPIO C Interrupt Control Non-Secure Register (gpioc_icns)", + "description": "TrustZone register - GPIO C Interrupt Control Non-Secure Register (gpioc_icns)", + "default_value_int": "0x0" + }, + { + "id": "field4B0", + "offset_int": "0x4b0", + "reg_width": 32, + "name": "GPIO C Pin Control Non-Privilege Register (gpioc_pcnp)", + "description": "TrustZone register - GPIO C Pin Control Non-Privilege Register (gpioc_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field4B4", + "offset_int": "0x4b4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Non-Privilege Register (gpioc_icnp)", + "description": "TrustZone register - GPIO C Interrupt Control Non-Privilege Register (gpioc_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field4B8", + "offset_int": "0x4b8", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 0 (gpioc_icr0)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 0 (gpioc_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field4BC", + "offset_int": "0x4bc", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 1 (gpioc_icr1)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 1 (gpioc_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field4C0", + "offset_int": "0x4c0", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 2 (gpioc_icr2)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 2 (gpioc_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field4C4", + "offset_int": "0x4c4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 3 (gpioc_icr3)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 3 (gpioc_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field4C8", + "offset_int": "0x4c8", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 4 (gpioc_icr4)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 4 (gpioc_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field4CC", + "offset_int": "0x4cc", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 5 (gpioc_icr5)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 5 (gpioc_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field4D0", + "offset_int": "0x4d0", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 6 (gpioc_icr6)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 6 (gpioc_icr6)", + "default_value_int": "0x0" + }, + { + "id": "field4D4", + "offset_int": "0x4d4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 7 (gpioc_icr7)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 7 (gpioc_icr7)", + "default_value_int": "0x0" + }, + { + "id": "field4D8", + "offset_int": "0x4d8", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 8 (gpioc_icr8)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 8 (gpioc_icr8)", + "default_value_int": "0x0" + }, + { + "id": "field4DC", + "offset_int": "0x4dc", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 9 (gpioc_icr9)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 9 (gpioc_icr9)", + "default_value_int": "0x0" + }, + { + "id": "field4E0", + "offset_int": "0x4e0", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 10 (gpioc_icr10)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 10 (gpioc_icr10)", + "default_value_int": "0x0" + }, + { + "id": "field4E4", + "offset_int": "0x4e4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 11 (gpioc_icr11)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 11 (gpioc_icr11)", + "default_value_int": "0x0" + }, + { + "id": "field4E8", + "offset_int": "0x4e8", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 12 (gpioc_icr12)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 12 (gpioc_icr12)", + "default_value_int": "0x0" + }, + { + "id": "field4EC", + "offset_int": "0x4ec", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 13 (gpioc_icr13)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 13 (gpioc_icr13)", + "default_value_int": "0x0" + }, + { + "id": "field4F0", + "offset_int": "0x4f0", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 14 (gpioc_icr14)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 14 (gpioc_icr14)", + "default_value_int": "0x0" + }, + { + "id": "field4F4", + "offset_int": "0x4f4", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 15 (gpioc_icr15)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 15 (gpioc_icr15)", + "default_value_int": "0x0" + }, + { + "id": "field4F8", + "offset_int": "0x4f8", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 16 (gpioc_icr16)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 16 (gpioc_icr16)", + "default_value_int": "0x0" + }, + { + "id": "field4FC", + "offset_int": "0x4fc", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 17 (gpioc_icr17)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 17 (gpioc_icr17)", + "default_value_int": "0x0" + }, + { + "id": "field500", + "offset_int": "0x500", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 18 (gpioc_icr18)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 18 (gpioc_icr18)", + "default_value_int": "0x0" + }, + { + "id": "field504", + "offset_int": "0x504", + "reg_width": 32, + "name": "GPIO C Interrupt Control Pin 19 (gpioc_icr19)", + "description": "TrustZone register - GPIO C Interrupt Control Pin 19 (gpioc_icr19)", + "default_value_int": "0x0" + }, + { + "id": "field508", + "offset_int": "0x508", + "reg_width": 32, + "name": "GPIO D Lock Register (gpiod_lock)", + "description": "TrustZone register - GPIO D Lock Register (gpiod_lock)", + "default_value_int": "0x0" + }, + { + "id": "field50C", + "offset_int": "0x50c", + "reg_width": 32, + "name": "GPIO D Pin Control Non-Secure Register (gpiod_pcns)", + "description": "TrustZone register - GPIO D Pin Control Non-Secure Register (gpiod_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field510", + "offset_int": "0x510", + "reg_width": 32, + "name": "GPIO D Interrupt Control Non-Secure Register (gpiod_icns)", + "description": "TrustZone register - GPIO D Interrupt Control Non-Secure Register (gpiod_icns)", + "default_value_int": "0x0" + }, + { + "id": "field514", + "offset_int": "0x514", + "reg_width": 32, + "name": "GPIO D Pin Control Non-Privilege Register (gpiod_pcnp)", + "description": "TrustZone register - GPIO D Pin Control Non-Privilege Register (gpiod_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field518", + "offset_int": "0x518", + "reg_width": 32, + "name": "GPIO D Interrupt Control Non-Privilege Register (gpiod_icnp)", + "description": "TrustZone register - GPIO D Interrupt Control Non-Privilege Register (gpiod_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field51C", + "offset_int": "0x51c", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 0 (gpiod_icr0)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 0 (gpiod_icr0)", + "default_value_int": "0x0" + }, + { + "id": "field520", + "offset_int": "0x520", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 1 (gpiod_icr1)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 1 (gpiod_icr1)", + "default_value_int": "0x0" + }, + { + "id": "field524", + "offset_int": "0x524", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 2 (gpiod_icr2)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 2 (gpiod_icr2)", + "default_value_int": "0x0" + }, + { + "id": "field528", + "offset_int": "0x528", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 3 (gpiod_icr3)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 3 (gpiod_icr3)", + "default_value_int": "0x0" + }, + { + "id": "field52C", + "offset_int": "0x52c", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 4 (gpiod_icr4)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 4 (gpiod_icr4)", + "default_value_int": "0x0" + }, + { + "id": "field530", + "offset_int": "0x530", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 5 (gpiod_icr5)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 5 (gpiod_icr5)", + "default_value_int": "0x0" + }, + { + "id": "field534", + "offset_int": "0x534", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 6 (gpiod_icr6)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 6 (gpiod_icr6)", + "default_value_int": "0x0" + }, + { + "id": "field538", + "offset_int": "0x538", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 7 (gpiod_icr7)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 7 (gpiod_icr7)", + "default_value_int": "0x0" + }, + { + "id": "field53C", + "offset_int": "0x53c", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 8 (gpiod_icr8)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 8 (gpiod_icr8)", + "default_value_int": "0x0" + }, + { + "id": "field540", + "offset_int": "0x540", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 9 (gpiod_icr9)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 9 (gpiod_icr9)", + "default_value_int": "0x0" + }, + { + "id": "field544", + "offset_int": "0x544", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 10 (gpiod_icr10)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 10 (gpiod_icr10)", + "default_value_int": "0x0" + }, + { + "id": "field548", + "offset_int": "0x548", + "reg_width": 32, + "name": "GPIO D Interrupt Control Pin 11 (gpiod_icr11)", + "description": "TrustZone register - GPIO D Interrupt Control Pin 11 (gpiod_icr11)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42082/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42082/database.yaml new file mode 100644 index 0000000..d924f20 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42082/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42092/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42092/database.yaml new file mode 100644 index 0000000..d924f20 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z42092/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b2/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b2/database.yaml new file mode 100644 index 0000000..fe6110d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b2/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b3/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b3/database.yaml new file mode 100644 index 0000000..fe6110d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/kw47z420b3/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5502/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5502/database.yaml new file mode 100644 index 0000000..7a2ae93 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5502/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5506 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x4000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5504/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5504/database.yaml new file mode 100644 index 0000000..d386dee --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5504/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5506 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20000" + external: false + sram: + start_int: "0x20000000" + size_int: "0xC000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/database.yaml new file mode 100644 index 0000000..186af2d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/database.yaml @@ -0,0 +1,103 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc550x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc550x-s0x-baseline-arm-cortex-m33-based-microcontroller-family:LPC550x + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x3D000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x10000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + load_to_ram: + crc: crc_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x3_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + cmpa: # CMPA description + address: 0x3_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cfpa.json new file mode 100644 index 0000000..15cad8f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cfpa.json @@ -0,0 +1,1129 @@ +{ + "cpu": "lpc5506", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00008", + "name": "Reserved 0x00008", + "description": "This field is reserved for internal use", + "offset_int": "0x0008", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-000FC", + "description": "Reserved 00040-000FC" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cmpa.json new file mode 100644 index 0000000..8751fcc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5506/pfr_cmpa.json @@ -0,0 +1,1517 @@ +{ + "cpu": "lpc5506", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 15 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved00008", + "name": "Reserved 0x00008", + "description": "This field is reserved for internal use", + "offset_int": "0x0008", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0000C", + "name": "Reserved 0x0000C", + "description": "This field is reserved for internal use", + "offset_int": "0x000C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-000FC", + "description": "Reserved 00040-000FC" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5512/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5512/database.yaml new file mode 100644 index 0000000..0887893 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5512/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5516 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x10000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x4000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5514/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5514/database.yaml new file mode 100644 index 0000000..b33a1e0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5514/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5516 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20000" + external: false + sram: + start_int: "0x20000000" + size_int: "0xC000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/database.yaml new file mode 100644 index 0000000..77f8b52 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/database.yaml @@ -0,0 +1,18 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5506 + +# General MCU information +info: + spsdk_predecessor_name: lpc551x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc551x-s1x-baseline-arm-cortex-m33-based-microcontroller-family:LPC551X-S1X + isp: + rom: + protocol: mboot + interfaces: ["usb","uart", "spi", "i2c"] + usb: + - vid: 0x1FC9 + pid: 0x0022 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/pfr_cmpa.json new file mode 100644 index 0000000..4fac9be --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5516/pfr_cmpa.json @@ -0,0 +1,1544 @@ +{ + "cpu": "LPC5516", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "USB_HID_ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 2, + "id": "field000-bits9-10", + "name": "USB_SPEED", + "description": "Defines which USB module is used for ISP:", + "values": [ + { + "name": "USB_SPEED_0", + "value": 0, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + }, + { + "name": "USB_FS", + "value": 1, + "description": "USB FS module used for ISP" + }, + { + "name": "USB_HS", + "value": 2, + "description": "USB HS module used for ISP" + }, + { + "name": "USB_SPEED_1", + "value": 3, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + } + ] + }, + { + "width": 13 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-000FC", + "description": "Reserved 00040-000FC" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + 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"offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/database.yaml new file mode 100644 index 0000000..432c7ab --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/database.yaml @@ -0,0 +1,110 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + 1a: {} + 1b: {} +latest: 1b + +# General MCU information +info: + purpose: LPC5500 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc552x-s2x-mainstream-arm-cortex-m33-based-microcontroller-family:LPC552x-S2x + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x80000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x30000" + external: false + sram4: + start_int: "0x20040000" + size_int: "0x4000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false + isp: + rom: + interfaces: ["usb","uart", "spi", "i2c"] + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + load_to_ram: + crc: crc_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x9_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + cmpa: # CMPA description + address: 0x9_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cfpa.json new file mode 100644 index 0000000..2241ce0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cfpa.json @@ -0,0 +1,1129 @@ +{ + "cpu": "lpc5526", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00008", + "name": "Reserved 0x00008", + "description": "This field is reserved for internal use", + "offset_int": "0x0008", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for 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"offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cmpa.json new file mode 100644 index 0000000..8861340 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5526/pfr_cmpa.json @@ -0,0 +1,1471 @@ +{ + "cpu": "lpc5526", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "USB_HID_ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_96MHZ", + "value": 1, + "description": "96MHz FRO" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 2, + "id": "field000-bits9-10", + "name": "USB_SPEED", + "description": "Defines which USB module is used for ISP:", + "values": [ + { + "name": "USB_SPEED_0", + "value": 0, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + }, + { + "name": "USB_FS", + "value": 1, + "description": "USB FS module used for ISP" + }, + { + "name": "USB_HS", + "value": 2, + "description": "USB HS module used for ISP" + }, + { + "name": "USB_SPEED_1", + "value": 3, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + } + ] + }, + { + "width": 13 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-000FC", + "description": "Reserved 00040-000FC" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 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"description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5528/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5528/database.yaml new file mode 100644 index 0000000..7083c43 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5528/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5526 + +# General MCU information +info: + spsdk_predecessor_name: lpc552x + # Web page of MCU representative + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x40000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x18000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/database.yaml new file mode 100644 index 0000000..065c4ca --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/database.yaml @@ -0,0 +1,144 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + 0a: + features: + pfr: + cfpa: + reg_spec: pfr_cfpa_0a.json + cmpa: + reg_spec: pfr_cmpa_0a.json + 1a: + features: + pfr: + cfpa: + reg_spec: pfr_cfpa_1a.json + cmpa: + reg_spec: pfr_cmpa_1a.json +latest: 1a + +# General MCU information +info: + purpose: LPC5500 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-arm-cortex-m33/lpc553x-s3x-advanced-analog-armcortex-m33-based-mcu-family:LPC553x + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20000" + external: false + flexspi_ns: + start_int: "0x8000000" + size_int: "0x8000000" + external: true + sram: + start_int: "0x20000000" + size_int: "0x18000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["usb", "uart", "spi", "i2c"] + usb: + - vid: 0x1FC9 + pid: 0x0025 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: {} + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + + images: + xip: + plain: plain_xip + crc: crc_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x3_DC00 + seal_start: field1EC # CFPA_CRC32 + seal_count: 1 + cmpa: # CMPA description + address: 0x3_E200 + cert_block_version: 21 + seal_start: field1FC # CMPA_CRC32 + seal_count: 1 + rules: + - ../../common/pfrc_rules.yaml + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + flexspi_nor: + segments: + fcb: 0x0400 + image_version_ap: 0x0600 + mbi: 0x1000 + remap_align: 0x40000 # 256 KB + image_pattern: ones + recovery_spi_sb31: + segments: + sb31: 0x00 + recovery_spi_mbi: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fcb_flexspi_nor.json new file mode 100644 index 0000000..5b6470e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fcb_flexspi_nor.json @@ -0,0 +1,25587 @@ +{ + "cpu": "LPC5534", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x56020000" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details ", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same ", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3 ", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false ", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution ", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size ", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Reserved2_0", + "deprecated_names": ["reserve2_0"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Reserved2_1", + "deprecated_names": ["reserve2_1"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Reserved2_2", + "deprecated_names": ["reserve2_2"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Reserved2_3", + "deprecated_names": ["reserve2_3"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Reserved2_4", + "deprecated_names": ["reserve2_4"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Reserved2_5", + "deprecated_names": ["reserve2_5"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Reserved2_6", + "deprecated_names": ["reserve2_6"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Reserved2_7", + "deprecated_names": ["reserve2_7"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Reserved2_8", + "deprecated_names": ["reserve2_8"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "Reserved2_9", + "deprecated_names": ["reserve2_9"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fuses.json new file mode 100644 index 0000000..caf49db --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/fuses.json @@ -0,0 +1,172 @@ +{ + "cpu": "lpc5534", + "groups": [ + { + "group": { + "name": "LC_STATE", + "description": "Device life cycle state, only the lowest 8 bits are valid." + }, + "registers": [ + { + "id": "fuse0", + "name": "LC_STATE", + "description": "Device life cycle state. \nThis field is used to determine Code Read Protection (CRP) level.", + "index_int": "0", + "default_value_int": "0x0003", + "bitfields": [ + { + "width": 8, + "id": "fuse0-bits-0-7", + "name": "LC_STATE", + "description": "Device life cycle state LC_STATE[7:0].", + "values": [ + { + "name": "CRP_LEVEL0", + "value": 3, + "description": "CRP_LEVEL0 (LC_STATE = 0x03)" + }, + { + "name": "CRP_LEVEL1", + "value": 7, + "description": "CRP_LEVEL1 (LC_STATE = 0x07)" + }, + { + "name": "CRP_LEVEL2_3", + "value": 15, + "description": "CRP_LEVEL2 (LC_STATE = 0x0F), CRP_LEVEL3 (LC_STATE = 0x0F) and CMPA.ISP_mode = Disable." + }, + { + "name": "FIELD_RETURN", + "value": 31, + "description": "Field Return OEM (LC_STATE = 0x1F)" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure analysis NXP (LC_STATE = 0x7F)" + }, + { + "name": "CRP_LEVEL4", + "value": 207, + "description": "CRP_LEVEL4 (LC_STATE = 0xCF) and CMPA.ISP_mode = Disable." + } + ] + }, + { + "width": 24 + } + ] + } + ] + }, + { + "group": { + "name": "CMPA_CRC", + "description": "CMPA CRC check value." + }, + "registers": [ + { + "id": "fuse1", + "name": "CMPA_CRC", + "description": "CRC32 of CMPA fields. \n- Used by non-secure part during boot.", + "index_int": "0x0001" + } + ] + }, + { + "group": { + "name": "MFG_DATA", + "description": "Customer Manufacturing-time programmed words." + }, + "registers": [ + { + "id": "fuse2", + "name": "MFG_DATA0", + "description": "CMPA MFG data value word 0.", + "index_int": "0x0002" + }, + { + "id": "fuse3", + "name": "MFG_DATA1", + "description": "CMPA MFG data value word 1.", + "index_int": "0x0003" + }, + { + "id": "fuse4", + "name": "MFG_DATA2", + "description": "CMPA MFG data value word 2.", + "index_int": "0x0004" + }, + { + "id": "fuse5", + "name": "MFG_DATA3", + "description": "CMPA MFG data value word 3.", + "index_int": "0x0005" + } + ] + }, + { + "group": { + "name": "Reserved 0x6", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved6", + "name": "Reserved 0x6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0006", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "CUSTOMER_WORDS", + "description": "Customer words area." + }, + "registers": [ + { + "id": "fuse7", + "name": "CUSTOMER_WORD0", + "description": "Customer use word 0.", + "index_int": "0x0007" + }, + { + "id": "fuse8", + "name": "CUSTOMER_WORD1", + "description": "Customer use word 1, only the lowest 8 bits are valid.", + "index_int": "0x0008", + "bitfields": [ + { + "width": 8, + "id": "fuse8-bits-0-7", + "name": "CUSTOMER_WORD1", + "description": "Customer use word 1." + }, + { + "width": 24 + } + ] + }, + { + "id": "fuse9", + "name": "CUSTOMER_WORD2", + "description": "Customer use word 2, only the lowest 8 bits are valid.", + "index_int": "0x0009", + "bitfields": [ + { + "width": 8, + "id": "fuse9-bits-0-7", + "name": "CUSTOMER_WORD2", + "description": "Customer use word 2." + }, + { + "width": 24 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_0a.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_0a.json new file mode 100644 index 0000000..d0f1707 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_0a.json @@ -0,0 +1,1367 @@ +{ + "cpu": "LPC5534", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "CFPA Page Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "FW_Version", + "description": "Firmware Version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "MCTR_NXP_CTR0", + "description": "Monotonic counter 0", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "MFLAG_CUST_0", + "description": "Customer defined Monotonic flags", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field014", + "name": "MCTR_NXP_CTR1", + "description": "Monotonic counter 1", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "MCTR_NXP_CTR2", + "description": "Monotonic counter 2", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field01C", + "name": "MCTR_NXP_CTR3", + "description": "Monotonic counter 3", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field020", + "name": "MCTR_NXP_CTR4", + "description": "Monotonic counter 4", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field024", + "name": "MCTR_NXP_CTR5", + "description": "Monotonic counter 5", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "MCTR_NXP_CTR6", + "description": "Monotonic counter 6", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "MCTR_NXP_CTR7", + "description": "Monotonic counter 7", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field038", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4.", + "offset_int": "0x0040", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5.", + "offset_int": "0x0044", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6.", + "offset_int": "0x0048", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7.", + "offset_int": "0x004C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "MFLAG_CUST_1", + "description": "Customer defined Monotonic flags", + "offset_int": "0x0050", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0058", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field058-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field058-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 16, + "id": "field058-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value of Bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field05C", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x005C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field05C-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field05C-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 7 + }, + { + "width": 16, + "id": "field05C-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field060", + "name": "ENABLE_FA_MODE", + "description": "Enable FA Mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0060", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page Programming On Going. Set this field to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00068-001E8", + "description": "Reserved 00068-001E8" + }, + "registers": [ + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for 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true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for 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true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CFPA CRC32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_1a.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_1a.json new file mode 100644 index 0000000..0f910d8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cfpa_1a.json @@ -0,0 +1,1039 @@ +{ + "cpu": "lpc5534", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "Header", + "description": "Header", + "offset_int": "0", + "default_value_int": "0" + }, + { + "id": "field004", + "name": "CFPA_PAGE_Version", + "description": "CFPA Page Version. Write '0xFFFF_FFFF' to auto increment current CFPA page version value (by ROM).", + "offset_int": "0x0004", + "default_value_int": "0" + }, + { + "id": "field008", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware Version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0" + }, + { + "id": "field00C", + "name": "MCTR_NXP_CTR0", + "description": "Monotonic counter 0", + "offset_int": "0x000C", + "default_value_int": "0" + }, + { + "id": "field010", + "name": "MFLAG_CUST_0", + "description": "Customer defined Monotonic flags", + "offset_int": "0x0010", + "default_value_int": "0" + }, + { + "id": "field014", + "name": "MCTR_NXP_CTR1", + "description": "Monotonic counter 1", + "offset_int": "0x0014", + "default_value_int": "0" + }, + { + "id": "field018", + "name": "MCTR_NXP_CTR2", + "description": "Monotonic counter 2", + "offset_int": "0x0018", + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "MCTR_NXP_CTR3", + "description": "Monotonic counter 3", + "offset_int": "0x001C", + "default_value_int": "0" + }, + { + "id": "field020", + "name": "MCTR_NXP_CTR4", + "description": "Monotonic counter 4", + "offset_int": "0x0020", + "default_value_int": "0" + }, + { + "id": "field024", + "name": "MCTR_NXP_CTR5", + "description": "Monotonic counter 5", + "offset_int": "0x0024", + "default_value_int": "0" + }, + { + "id": "field028", + "name": "MCTR_NXP_CTR6", + "description": "Monotonic counter 6", + "offset_int": "0x0028", + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "MCTR_NXP_CTR7", + "description": "Monotonic counter 7", + "offset_int": "0x002C", + "default_value_int": "0" + }, + { + "id": "field030", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0.", + "offset_int": "0x0030", + "default_value_int": "0" + }, + { + "id": "field034", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1.", + "offset_int": "0x0034", + "default_value_int": "0" + }, + { + "id": "field038", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2.", + "offset_int": "0x0038", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3.", + "offset_int": "0x003C", + "default_value_int": "0" + }, + { + "id": "field040", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4.", + "offset_int": "0x0040", + "default_value_int": "0" + }, + { + "id": "field044", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5.", + "offset_int": "0x0044", + "default_value_int": "0" + }, + { + "id": "field048", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6.", + "offset_int": "0x0048", + "default_value_int": "0" + }, + { + "id": "field04C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7.", + "offset_int": "0x004C", + "default_value_int": "0" + }, + { + "id": "field050", + "name": "MFLAG_CUST_1", + "description": "Customer defined Monotonic flags", + "offset_int": "0x0050", + "default_value_int": "0" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field060", + "name": "ENABLE_FA_MODE", + "description": "Enable FA Mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0060", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page Programming On Going. Set this field to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00068-001E8", + "description": "Reserved 00068-001E8" + }, + "registers": [ + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00120", + "name": "Reserved 0x00120", + "description": "This field is reserved for internal use", + "offset_int": "0x0120", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CFPA CRC32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 001F0-001FC", + "description": "Reserved 001F0-001FC" + }, + "registers": [ + { + "id": "Reserved001F0", + "name": "Reserved 0x001F0", + "description": "This field is reserved for internal use", + "offset_int": "0x01F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001F4", + "name": "Reserved 0x001F4", + "description": "This field is reserved for internal use", + "offset_int": "0x01F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001F8", + "name": "Reserved 0x001F8", + "description": "This field is reserved for internal use", + "offset_int": "0x01F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001FC", + "name": "Reserved 0x001FC", + "description": "This field is reserved for internal use", + "offset_int": "0x01FC", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_0a.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_0a.json new file mode 100644 index 0000000..9da4717 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_0a.json @@ -0,0 +1,2122 @@ +{ + "cpu": "LPC5534", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field000-bits0-2", + "name": "DEFAULT_BOOT_SOURCE", + "description": "Default Boot Source", + "values": [ + { + "name": "ISP_PIN", + "value": 0, + "description": "ISP pin source" + }, + { + "name": "FLEXSPI_FLASH", + "value": 1, + "description": "FlexSPI flash" + }, + { + "name": "SERIAL_ISP_BOOT", + "value": 2, + "description": "Serial ISP boot" + }, + { + "name": "INTERNAL_FLASH", + "value": 3, + "description": "Internal Flash" + }, + { + "name": "AUTO_BOOT", + "value": 4, + "description": "Auto boot similar to ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_MSC", + "value": 1, + "description": "USB HID MSC" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "CAN_ISP", + "value": 5, + "description": "CAN ISP" + }, + { + "name": "DISBL_ISP_FALLTHRU", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Boot Speed Core Clock", + "values": [ + { + "name": "SYS_SPD_CODE", + "value": 0, + "description": "Defined by NMPA[SYSTEM_SPEED_CODE]" + }, + { + "name": "HHZ96_FRO", + "value": 1, + "description": "96MHz FRO" + }, + { + "name": "MHZ48_FRO", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 12 + }, + { + "width": 1, + "id": "field000-bit21", + "name": "ASRT_FATAL", + "description": "ASRT_FATAL" + }, + { + "width": 1, + "id": "field000-bit22", + "name": "ASRT_RBF", + "description": "ASRT_RBF" + }, + { + "width": 1, + "id": "field000-bit23", + "name": "ASRT_ISPF", + "description": "ASRT_ISPF" + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "Boot Failure Pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_CAN_CFG", + "description": "SPI CAN Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field004-bits0-1", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI Recovery Boot Enable" + }, + { + "width": 3, + "id": "field004-bits2-4", + "name": "SPI_REC_IF", + "description": "SPI Recovery Interface", + "values": [ + { + "name": "HSPI", + "value": 0, + "description": "HSPI P1_3-MISO, P0_26-MOSI, P1_1-SSEL1, P1_2-SCK" + }, + { + "name": "FC0", + "value": 1, + "description": "FC0 P0_30-MISO, P0_24-MOSI, P0_31-SSEL0, P0_28-SCK" + }, + { + "name": "FC3", + "value": 2, + "description": "FC3 P0_2-MISO, P0_3-MOSI, P0_4-SSEL0, P0_6-SCK" + }, + { + "name": "FC1", + "value": 3, + "description": "FC1 P2_4-MISO, P2_3-MOSI, P2_5-SSEL0, P1_9-SCK" + } + ] + }, + { + "width": 11 + }, + { + "width": 4, + "id": "field004-bits16-19", + "name": "CAN_BAUD_RATE", + "description": "CAN Baud Rate", + "values": [ + { + "name": "AUTO_BAUD_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 1M). Default." + }, + { + "name": "KBPS_10", + "value": 1, + "description": "10 kbp" + }, + { + "name": "KBPS_20", + "value": 2, + "description": "20 kbp" + }, + { + "name": "KBPS_50", + "value": 3, + "description": "50 kbps" + }, + { + "name": "KBPS_125", + "value": 4, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 5, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 6, + "description": "500 kbps" + }, + { + "name": "KBPS_800", + "value": 7, + "description": "800 kbps" + }, + { + "name": "KBPS_1000", + "value": 8, + "description": "1,000 kbps" + } + ] + }, + { + "width": 12 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMEOUT", + "description": "Boot Timeout", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown Timeout" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_SECS", + "description": "WDOG Timeout" + } + ] + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field010-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "UUID Check" + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field014-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 7 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz Capabank Trimming", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used." + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid." + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "XTAL LOAD CAP IEC PF X100" + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN PARA CAP PF X100" + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT PARA CAP PF X100" + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz Capabank Trimming", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used." + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid." + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "XTAL LOAD CAP IEC PF X100" + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN PARA CAP PF X100" + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT PARA CAP PF X100" + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "Flash Remap Size", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "Flash Remap Offset", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-0007C", + "description": "Reserved 00040-0007C" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field080-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "FLEXSPI_AUTO_PROBE_EN", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field080-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "FLEXSPI_PROBE_TYPE", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIX_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field080-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "FLEXSPI_FLASH_TYPE", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI_ADDR_3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER_1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER_3V3" + }, + { + "name": "FlexSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FlexSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field080-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "FLEXSPI_DUMMY_CYCLES" + }, + { + "width": 3, + "id": "field080-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "FLEXSPI_FREQUENCY", + "values": [ + { + "name": "MHZ_50", + "value": 0, + "description": "50 Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60 Mhz" + }, + { + "name": "MHZ_80", + "value": 2, + "description": "80 Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100 Mhz" + }, + { + "name": "MHZ_120", + "value": 4, + "description": "120 Mhz" + }, + { + "name": "MHZ_133", + "value": 5, + "description": "133 Mhz" + }, + { + "name": "MHZ_166", + "value": 6, + "description": "166 Mhz" + }, + { + "name": "MHZ_200", + "value": 7, + "description": "200 Mhz" + } + ] + }, + { + "width": 1, + "id": "field080-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "FLEXSPI_RESET_ENABLE", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "No Reset(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "ENABLE_RESET", + "value": 1, + "description": "Enable Reset(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "field080-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "FLEXSPI_RESET_ENABLE" + }, + { + "width": 5, + "id": "field080-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "FLEXSPI_RESET_GPIO_PIN" + }, + { + "width": 2, + "id": "field080-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "FLEXSPI_HOLD TIME", + "values": [ + { + "name": "WAIT_500_MICROSECS", + "value": 0, + "description": "Wait for 500 micro seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 1, + "description": "Wait for 1 mili seconds" + }, + { + "name": "WAIT_3_MILISECS", + "value": 2, + "description": "Wait for 3 mili seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 3, + "description": "Wait for 10 mili seconds" + } + ] + }, + { + "width": 4, + "id": "field080-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "FLEXSPI_PWR_HOLD_TIME", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100_MICROSECS", + "value": 1, + "description": "Waits additional 100 micro-seconds." + }, + { + "name": "WAIT_500_MICROSECS", + "value": 2, + "description": "Waits additional 500 micro-seconds." + }, + { + "name": "WAIT_1_MILISECS", + "value": 3, + "description": "Waits additional 1 mili-seconds." + }, + { + "name": "WAIT_10_MILISECS", + "value": 4, + "description": "Waits additional 10 mili-seconds." + }, + { + "name": "WAIT_20_MILISECS", + "value": 5, + "description": "Waits additional 20 mili-seconds." + }, + { + "name": "WAIT_40_MILISECS", + "value": 6, + "description": "Waits additional 40 mili-seconds." + }, + { + "name": "WAIT_60_MILISECS", + "value": 7, + "description": "Waits additional 60 mili-seconds." + }, + { + "name": "WAIT_80_MILISECS", + "value": 8, + "description": "Waits additional 80 mili-seconds." + }, + { + "name": "WAIT_100_MILISECS", + "value": 9, + "description": "Waits additional 100 mili-seconds." + }, + { + "name": "WAIT_120_MILISECS", + "value": 10, + "description": "Waits additional 120 mili-seconds." + }, + { + "name": "WAIT_140_MILISECS", + "value": 11, + "description": "Waits additional 140 mili-seconds." + }, + { + "name": "WAIT_160_MILISECS", + "value": 12, + "description": "Waits additional 160 mili-seconds." + }, + { + "name": "WAIT_180_MILISECS", + "value": 13, + "description": "Waits additional 180 mili-seconds." + }, + { + "name": "WAIT_200_MILISECS", + "value": 14, + "description": "Waits additional 200 mili-seconds." + }, + { + "name": "WAIT_220_MILISECS", + "value": 15, + "description": "Waits additional 220 mili-seconds." + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field084", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 7, + "id": "field084-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "FLEXSPI_DELAY_CELL_NUM" + }, + { + "width": 10, + "id": "field084-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field084-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "FLEXSPI_REMAP_IMAGE_SIZE", + "values": [ + { + "name": "SIZE", + "value": 0, + "description": "SIZE" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "SIZE_1MB Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "SIZE_2MB Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "SIZE_3MB Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "SIZE_4MB Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "SIZE_5MB Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "SIZE_6MB Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "SIZE_7MB Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "SIZE_8MB Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "SIZE_9MB Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "SIZE_10MB Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "SIZE_11MB Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "SIZE_12MB Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "SIZE_256KB Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "SIZE_512KB Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "SIZE_768KB Size of remapped area is 768KByte." + } + ] + }, + { + "width": 11 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00088-000AC", + "description": "Reserved 00088-000AC" + }, + "registers": [ + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port pins high", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port pins low", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port pins high", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port pins low", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000FC", + "description": "Reserved 000C0-000FC" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E0", + "name": "CUSTOMER_DEFINED56", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "CUSTOMER_DEFINED57", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "CUSTOMER_DEFINED58", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "CUSTOMER_DEFINED59", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01EC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 001F0-001F8", + "description": "Reserved 001F0-001F8" + }, + "registers": [ + { + "id": "Reserved001F0", + "name": "Reserved 0x001F0", + "description": "This field is reserved for internal use", + "offset_int": "0x01F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001F4", + "name": "Reserved 0x001F4", + "description": "This field is reserved for internal use", + "offset_int": "0x01F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001F8", + "name": "Reserved 0x001F8", + "description": "This field is reserved for internal use", + "offset_int": "0x01F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1FC", + "name": "CMPA_CRC32", + "description": "CMPA_CRC32[31:0]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_1a.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_1a.json new file mode 100644 index 0000000..9f287fc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5534/pfr_cmpa_1a.json @@ -0,0 +1,2181 @@ +{ + "cpu": "lpc5534", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field000-bits0-2", + "name": "Default_Boot_Source", + "description": "Default Boot Source", + "values": [ + { + "name": "ISP_PIN", + "value": 0, + "description": "ISP pin source" + }, + { + "name": "FLEXSPI_FLASH", + "value": 1, + "description": "FlexSPI flash" + }, + { + "name": "SERIAL_ISP_BOOT", + "value": 2, + "description": "Serial ISP boot" + }, + { + "name": "INTERNAL_FLASH", + "value": 3, + "description": "Internal flash" + }, + { + "name": "AUTO_BOOT", + "value": 4, + "description": "Auto boot similar to ISP auto boot option" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "Default_ISP_mode", + "description": "Default ISP mode", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_MSC", + "value": 1, + "description": "USB HID MSC" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C slave ISP" + }, + { + "name": "CAN_ISP", + "value": 5, + "description": "CAN ISP" + }, + { + "name": "DISBL_ISP_FALLTHRU", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "Boot_Speed", + "description": "Boot Speed Core Clock", + "values": [ + { + "name": "SYS_SPD_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "MHZ48_FRO", + "value": 1, + "description": "48MHz FRO" + }, + { + "name": "MHZ96_FRO", + "value": 2, + "description": "96MHz FRO" + }, + { + "name": "MHZ150_FRO", + "value": 3, + "description": "150MHz PLL" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field000-bit21", + "name": "ASRT_FATAL", + "description": "Assert on fatal errors. When set ROM drives BOOT_FAIL_PIN high when fatal error condition occurs on three attempts to boot image before locking the part" + }, + { + "width": 1, + "id": "field000-bit22", + "name": "ASRT_RBF", + "description": "Assert on recovery boot. When this bit is set ROM drives the BOOT_FAIL_PIN high whenever no valid image is found in primary boot media and execution enters recovery boot mode from secondary boot media" + }, + { + "width": 1, + "id": "field000-bit23", + "name": "ASRT_ISPF", + "description": "Assert on ISP fall through. When this bit is set ROM drives BOOT_FAIL_PIN high whenever there is no valid image in boot media and execution falls through to ISP mode" + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "Boot_failure_pin", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_CAN_CFG", + "description": "SPI CAN Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field004-bits0-1", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "REC_BOOT_EN SPI flash recovery boot is enabled, if non-zero value is written to this field" + }, + { + "width": 3, + "id": "field004-bits2-4", + "name": "SPI_REC_IF", + "description": "Recovery SPI interface", + "values": [ + { + "name": "HSPI", + "value": 0, + "description": "HSPI P1_3-MISO, P0_26-MOSI, P1_1-SSEL1, P1_2-SCK" + }, + { + "name": "FC0", + "value": 1, + "description": "FC0 P0_30-MISO, P0_24-MOSI, P0_31-SSEL0, P0_28-SCK" + }, + { + "name": "FC3", + "value": 2, + "description": "FC3 P0_2-MISO, P0_3-MOSI, P0_4-SSEL0, P0_6-SCK" + }, + { + "name": "FC1", + "value": 3, + "description": "FC1 P2_4-MISO, P2_3-MOSI, P2_5-SSEL0, P1_9-SCK" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "field004-bits16-19", + "name": "CAN_BAUD_RATE", + "description": "CAN baud rate. Baud rate configured during CAN ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 1M)" + }, + { + "name": "KBPS_10", + "value": 1, + "description": "10 kbps" + }, + { + "name": "KBPS_20", + "value": 2, + "description": "20 kbps" + }, + { + "name": "KBPS_50", + "value": 3, + "description": "50 kbps" + }, + { + "name": "KBPS_125", + "value": 4, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 5, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 6, + "description": "500 kbps" + }, + { + "name": "KBPS_800", + "value": 7, + "description": "800 kbps" + }, + { + "name": "KBPS_1000", + "value": 8, + "description": "1,000 kbps" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMEOUT", + "description": "Boot Timeout", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Power-down timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_SECS", + "description": "WDOG timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code" + } + ] + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0001C", + "name": "Reserved 0x0001C", + "description": "This field is reserved for internal use", + "offset_int": "0x001C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00020", + "name": "Reserved 0x00020", + "description": "This field is reserved for internal use", + "offset_int": "0x0020", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz Capabank Trimming", + "offset_int": "0x0030", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz Capabank Trimming", + "offset_int": "0x0034", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "Flash Remap Size", + "offset_int": "0x0038", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "Flash Remap Offset", + "offset_int": "0x003C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00040-0007C", + "description": "Reserved 00040-0007C" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "FLEXSPI_BOOT_CFG", + "description": "FlexSPI boot cfg" + }, + "registers": [ + { + "id": "field080", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "offset_int": "0x0080", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field080-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field080-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIX_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field080-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI ADDR 3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER 1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER 3V3" + }, + { + "name": "FLEXSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FLEXSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field080-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command" + }, + { + "width": 3, + "id": "field080-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Q/O-SPI flash interface frequency", + "values": [ + { + "name": "MHZ_50", + "value": 0, + "description": "50Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60Mhz" + }, + { + "name": "MHZ_80", + "value": 2, + "description": "80Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100Mhz" + }, + { + "name": "MHZ_120", + "value": 4, + "description": "120Mhz" + }, + { + "name": "MHZ_133", + "value": 5, + "description": "133Mhz" + }, + { + "name": "MHZ_166", + "value": 6, + "description": "166Mhz" + }, + { + "name": "MHZ_200", + "value": 7, + "description": "200Mhz" + } + ] + }, + { + "width": 1, + "id": "field080-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use QSPI_RESET_PIN to reset the flash device", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "ENABLE_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "field080-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "GPIO port number to use for O/QSPI reset function" + }, + { + "width": 5, + "id": "field080-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "GPIO pin number to use for O/QSPI reset function" + }, + { + "width": 2, + "id": "field080-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "Wait time before access to Serial Flash", + "values": [ + { + "name": "WAIT_500_MICROSECS", + "value": 0, + "description": "Wait for 500 micro seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 1, + "description": "Wait for 1 mili seconds" + }, + { + "name": "WAIT_3_MILISECS", + "value": 2, + "description": "Wait for 3 mili seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 3, + "description": "Wait for 10 mili seconds" + } + ] + }, + { + "width": 4, + "id": "field080-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100_MICROSECS", + "value": 1, + "description": "Waits additional 100 micro-seconds" + }, + { + "name": "WAIT_500_MICROSECS", + "value": 2, + "description": "Waits additional 500 micro-seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 3, + "description": "Waits additional 1 mili-seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 4, + "description": "Waits additional 10 mili-seconds" + }, + { + "name": "WAIT_20_MILISECS", + "value": 5, + "description": "Waits additional 20 mili-seconds" + }, + { + "name": "WAIT_40_MILISECS", + "value": 6, + "description": "Waits additional 40 mili-seconds" + }, + { + "name": "WAIT_60_MILISECS", + "value": 7, + "description": "Waits additional 60 mili-seconds" + }, + { + "name": "WAIT_80_MILISECS", + "value": 8, + "description": "Waits additional 80 mili-seconds" + }, + { + "name": "WAIT_100_MILISECS", + "value": 9, + "description": "Waits additional 100 mili-seconds" + }, + { + "name": "WAIT_120_MILISECS", + "value": 10, + "description": "Waits additional 120 mili-seconds" + }, + { + "name": "WAIT_140_MILISECS", + "value": 11, + "description": "Waits additional 140 mili-seconds" + }, + { + "name": "WAIT_160_MILISECS", + "value": 12, + "description": "Waits additional 160 mili-seconds" + }, + { + "name": "WAIT_180_MILISECS", + "value": 13, + "description": "Waits additional 180 mili-seconds" + }, + { + "name": "WAIT_200_MILISECS", + "value": 14, + "description": "Waits additional 200 mili-seconds" + }, + { + "name": "WAIT_220_MILISECS", + "value": 15, + "description": "Waits additional220 mili-seconds" + } + ] + }, + { + "width": 1, + "id": "field080-bit29", + "name": "PIN_SLEW_RATE", + "description": "Enable faster slew rate. When this bit is set ROM will configure FlexSPI pin with faster slew rate instead of standard slew rate", + "values": [ + { + "name": "STANDARD", + "value": 0, + "description": "Standard slew rate" + }, + { + "name": "FASTER", + "value": 1, + "description": "Faster slew rate" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field084", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "offset_int": "0x0084", + "default_value_int": "0", + "bitfields": [ + { + "width": 7, + "id": "field084-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS)" + }, + { + "width": 10, + "id": "field084-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "Any offset in memory mapped Q/Octal-SPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FlLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. If this field is left blank boot ROM assumes that application intends to not use redundant image boot feature. The physical flash offset is computed as below: physical offset = FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field084-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped QSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. SIZE_OFFSET \"Size of the remapped area (aka second half) is same as first half. It is determined by FLEXSPI_IMAGE_OFFSET Field. Remap size = FLEXSPI_IMAGE_OFFSET", + "values": [ + { + "name": "SIZE", + "value": 0, + "description": "SIZE" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "SIZE_1MB Size of remapped area is 1MByte" + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "SIZE_2MB Size of remapped area is 2MByte" + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "SIZE_3MB Size of remapped area is 3MByte" + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "SIZE_4MB Size of remapped area is 4MByte" + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "SIZE_5MB Size of remapped area is 5MByte" + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "SIZE_6MB Size of remapped area is 6MByte" + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "SIZE_7MB Size of remapped area is 7MByte" + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "SIZE_8MB Size of remapped area is 8MByte" + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "SIZE_9MB Size of remapped area is 9MByte" + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "SIZE_10MB Size of remapped area is 10MByte" + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "SIZE_11MB Size of remapped area is 11MByte" + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "SIZE_12MB Size of remapped area is 12MByte" + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "SIZE_256KB Size of remapped area is 256KByte" + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "SIZE_512KB Size of remapped area is 512KByte" + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "SIZE_768KB Size of remapped area is 768KByte" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00088-0008C", + "description": "Reserved 00088-000AC" + }, + "registers": [ + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port pins high", + "offset_int": "0x00B0", + "default_value_int": "0" + }, + { + "id": "field0B4", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port pins low", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port pins high", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "field0BC", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port pins low", + "offset_int": "0x00BC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000FC", + "description": "Reserved 000C0-000FC" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "Customer_Defined0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0" + }, + { + "id": "field104", + "name": "Customer_Defined1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0" + }, + { + "id": "field108", + "name": "Customer_Defined2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0" + }, + { + "id": "field10C", + "name": "Customer_Defined3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0" + }, + { + "id": "field110", + "name": "Customer_Defined4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0" + }, + { + "id": "field114", + "name": "Customer_Defined5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0" + }, + { + "id": "field118", + "name": "Customer_Defined6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0" + }, + { + "id": "field11C", + "name": "Customer_Defined7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0" + }, + { + "id": "field120", + "name": "Customer_Defined8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0" + }, + { + "id": "field124", + "name": "Customer_Defined9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0" + }, + { + "id": "field128", + "name": "Customer_Defined10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0" + }, + { + "id": "field12C", + "name": "Customer_Defined11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0" + }, + { + "id": "field130", + "name": "Customer_Defined12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0" + }, + { + "id": "field134", + "name": "Customer_Defined13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0" + }, + { + "id": "field138", + "name": "Customer_Defined14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0" + }, + { + "id": "field13C", + "name": "Customer_Defined15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0" + }, + { + "id": "field140", + "name": "Customer_Defined16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0" + }, + { + "id": "field144", + "name": "Customer_Defined17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0" + }, + { + "id": "field148", + "name": "Customer_Defined18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0" + }, + { + "id": "field14C", + "name": "Customer_Defined19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0" + }, + { + "id": "field150", + "name": "Customer_Defined20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0" + }, + { + "id": "field154", + "name": "Customer_Defined21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0" + }, + { + "id": "field158", + "name": "Customer_Defined22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0" + }, + { + "id": "field15C", + "name": "Customer_Defined23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0" + }, + { + "id": "field160", + "name": "Customer_Defined24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0" + }, + { + "id": "field164", + "name": "Customer_Defined25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0" + }, + { + "id": "field168", + "name": "Customer_Defined26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0" + }, + { + "id": "field16C", + "name": "Customer_Defined27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0" + }, + { + "id": "field170", + "name": "Customer_Defined28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0" + }, + { + "id": "field174", + "name": "Customer_Defined29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0" + }, + { + "id": "field178", + "name": "Customer_Defined30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0" + }, + { + "id": "field17C", + "name": "Customer_Defined31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0" + }, + { + "id": "field180", + "name": "Customer_Defined32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0" + }, + { + "id": "field184", + "name": "Customer_Defined33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0" + }, + { + "id": "field188", + "name": "Customer_Defined34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0" + }, + { + "id": "field18C", + "name": "Customer_Defined35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0" + }, + { + "id": "field190", + "name": "Customer_Defined36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0" + }, + { + "id": "field194", + "name": "Customer_Defined37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0" + }, + { + "id": "field198", + "name": "Customer_Defined38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0" + }, + { + "id": "field19C", + "name": "Customer_Defined39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0" + }, + { + "id": "field1A0", + "name": "Customer_Defined40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0" + }, + { + "id": "field1A4", + "name": "Customer_Defined41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0" + }, + { + "id": "field1A8", + "name": "Customer_Defined42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0" + }, + { + "id": "field1AC", + "name": "Customer_Defined43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0" + }, + { + "id": "field1B0", + "name": "Customer_Defined44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0" + }, + { + "id": "field1B4", + "name": "Customer_Defined45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0" + }, + { + "id": "field1B8", + "name": "Customer_Defined46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0" + }, + { + "id": "field1BC", + "name": "Customer_Defined47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0" + }, + { + "id": "field1C0", + "name": "Customer_Defined48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0" + }, + { + "id": "field1C4", + "name": "Customer_Defined49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0" + }, + { + "id": "field1C8", + "name": "Customer_Defined50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0" + }, + { + "id": "field1CC", + "name": "Customer_Defined51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0" + }, + { + "id": "field1D0", + "name": "Customer_Defined52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0" + }, + { + "id": "field1D4", + "name": "Customer_Defined53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0" + }, + { + "id": "field1D8", + "name": "Customer_Defined54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0" + }, + { + "id": "field1DC", + "name": "Customer_Defined55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0" + }, + { + "id": "field1E0", + "name": "Customer_Defined56", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E0", + "default_value_int": "0" + }, + { + "id": "field1E4", + "name": "Customer_Defined57", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E4", + "default_value_int": "0" + }, + { + "id": "field1E8", + "name": "Customer_Defined58", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E8", + "default_value_int": "0" + }, + { + "id": "field1EC", + "name": "Customer_Defined59", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01EC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 001F0-001F8", + "description": "Reserved 001F0-001F8" + }, + "registers": [ + { + "id": "Reserved001F0", + "name": "Reserved 0x001F0", + "description": "This field is reserved for internal use", + "offset_int": "0x01F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001F4", + "name": "Reserved 0x001F4", + "description": "This field is reserved for internal use", + "offset_int": "0x01F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001F8", + "name": "Reserved 0x001F8", + "description": "This field is reserved for internal use", + "offset_int": "0x01F8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1FC", + "name": "CMPA_CRC32", + "description": "CMPA_CRC32[31:0]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5536/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5536/database.yaml new file mode 100644 index 0000000..053d0b3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc5536/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc5534 + +# General MCU information +info: + spsdk_predecessor_name: lpc553x + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x3DC00" + external: false + flexspi_ns: + start_int: "0x8000000" + size_int: "0x8000000" + external: true + sram: + start_int: "0x20000000" + size_int: "0x1C000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s04/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s04/database.yaml new file mode 100644 index 0000000..6993821 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s04/database.yaml @@ -0,0 +1,30 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc55s06 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x20000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x20000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0xC000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/database.yaml new file mode 100644 index 0000000..1c22f99 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/database.yaml @@ -0,0 +1,195 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a1: {} +latest: a1 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc55s0x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc550x-s0x-baseline-arm-cortex-m33-based-microcontroller-family:LPC550x + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x3D000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x3D000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x10000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x3_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x3_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - name: ROTKH + uid: cmpa_rotkh + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field050 + - field054 + - field058 + - field05C + - field060 + - field064 + - field068 + - field06C + + computed_fields: + field010: # DCFG_CC_SOCU_PIN + field010-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field014: # DCFG_CC_SOCU_DFLT + field014-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + rules: + - ../../common/pfrc_rules.yaml + - pfrc_rules.yaml + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cfpa.json new file mode 100644 index 0000000..e70eab3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cfpa.json @@ -0,0 +1,1666 @@ +{ + "cpu": "lpc55s06", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 0", + "description": "PRINCE region 0" + }, + "registers": [ + { + "id": "field030", + "name": "PRINCE_REGION0_IV_CODE0", + "description": "Field.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "PRINCE_REGION0_IV_CODE1", + "description": "Field.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field034-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field034-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field034-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field038", + "name": "PRINCE_REGION0_IV_BODY0", + "description": "Field.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "PRINCE_REGION0_IV_BODY1", + "description": "Field.", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "PRINCE_REGION0_IV_BODY2", + "description": "Field.", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "PRINCE_REGION0_IV_BODY3", + "description": "Field.", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "PRINCE_REGION0_IV_BODY4", + "description": "Field.", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "PRINCE_REGION0_IV_BODY5", + "description": "Field.", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "PRINCE_REGION0_IV_BODY6", + "description": "Field.", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "PRINCE_REGION0_IV_BODY7", + "description": "Field.", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "PRINCE_REGION0_IV_BODY8", + "description": "Field.", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "PRINCE_REGION0_IV_BODY9", + "description": "Field.", + "offset_int": "0x005C", + "access": "RO", + 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(Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cmpa.json new file mode 100644 index 0000000..dc0c4e6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfr_cmpa.json @@ -0,0 +1,2141 @@ +{ + "cpu": "lpc55s06", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 15 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved00008", + "name": "Reserved 0x00008", + "description": "This field is reserved for internal use", + "offset_int": "0x0008", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure boot configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "RSA4K", + "description": "Select minimal key length. To enforce usage of RSA4096, setting 0b11 value is recommended to allow RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "RSA2048 or higher can be used for image signing. Only RSA2048 can be used as debug keys." + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block PUF enrollment", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits16-17", + "name": "SKIP_BOOT_SEED", + "description": "Skip boot seed computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable BOOT_SEED" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable BOOT_SEED" + } + ] + }, + { + "width": 2, + "id": "field01C-bits18-19", + "name": "BOOT_SEED_INC_NXP_CFG", + "description": "Include NXP area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits20-21", + "name": "BOOT_SEED_CUST_CFG", + "description": "Include CMPA area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits22-23", + "name": "BOOT_SEED_INC_EPOCH", + "description": "Include security epoch area in BOOT_SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_BASE_ADDR", + "description": "Prince Base Address", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4, + "id": "field020-bits0-3", + "name": "ADDR0_PRG", + "description": "Programmable portion of the base address of region 0" + }, + { + "width": 4, + "id": "field020-bits4-7", + "name": "ADDR1_PRG", + "description": "Programmable portion of the base address of region 1" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "ADDR2_PRG", + "description": "Programmable portion of the base address of region 2" + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG0", + "description": "Lock PRINCE region0 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG1", + "description": "Lock PRINCE region1 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "For PRINCE region1 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "For PRINCE region2 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, sub-region enable", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, sub-region enable", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, sub-region enable", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-0004C", + "description": "Reserved 00040-0004C" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-000FC", + "description": "Reserved 00070-000FC" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfrc_rules.yaml new file mode 100644 index 0000000..60198c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/pfrc_rules.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "lpc55xx_4.1" + desc: + By default (blank device), the RoTKx_EN values are set to 0b00 which means + invalid. When secure boot is enabled (SEC_BOOT_EN != 0) there must be at + least one RoTKx_EN which is set to 0b01 (enabled) to allow device to boot + successfully. + msg: Secure boot is enabled. Make sure at least one Root of Trust Key Enable bit is set. + cond: CMPA.SECURE_BOOT_CFG.SEC_BOOT_EN != 0 and not (CFPA.ROTKH_REVOKE.RoTK3_EN == 1 or CFPA.ROTKH_REVOKE.RoTK2_EN == 1 or CFPA.ROTKH_REVOKE.RoTK1_EN == 1 or CFPA.ROTKH_REVOKE.RoTK0_EN == 1) + + - req_id: "lpc55xx_5.1" + desc: Inverse value (upper 16 bits) of VENDOR_USAGE must be always + valid. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.VENDOR_USAGE != 0 and (~(CFPA.VENDOR_USAGE>>int(16)) & 0xFFFF) != (CFPA.VENDOR_USAGE & 0xFFFF) diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/tz.json new file mode 100644 index 0000000..177e645 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s06/tz.json @@ -0,0 +1,837 @@ +{ + "cpu": "lpc55s06", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "RAM3 Memory Rule Register 0 (ram3_mem_rule)", + "description": "TrustZone register - RAM3 Memory Rule Register 0 (ram3_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule)", + "description": "TrustZone register - AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s14/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s14/database.yaml new file mode 100644 index 0000000..7b64dfe --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s14/database.yaml @@ -0,0 +1,31 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc55s16 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x20000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x20000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0xC000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/database.yaml new file mode 100644 index 0000000..86a4543 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/database.yaml @@ -0,0 +1,195 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a1: {} +latest: a1 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc55s1x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc551x-s1x-baseline-arm-cortex-m33-based-microcontroller-family:LPC551X-S1X + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x3D000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x3D000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x10000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + usb-ram: + start_int: "0x20010000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0022 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x3_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x3_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field050 + - field054 + - field058 + - field05C + - field060 + - field064 + - field068 + - field06C + computed_fields: + field010: # DCFG_CC_SOCU_PIN + field010-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field014: # DCFG_CC_SOCU_DFLT + field014-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + rules: + - ../../common/pfrc_rules.yaml + - pfrc_rules.yaml + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cfpa.json new file mode 100644 index 0000000..529270c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cfpa.json @@ -0,0 +1,1666 @@ +{ + "cpu": "lpc55s16", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 0", + "description": "PRINCE region 0" + }, + "registers": [ + { + "id": "field030", + "name": "PRINCE_REGION0_IV_CODE0", + "description": "Field.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "PRINCE_REGION0_IV_CODE1", + "description": "Field.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field034-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field034-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field034-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field038", + "name": "PRINCE_REGION0_IV_BODY0", + "description": "Field.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "PRINCE_REGION0_IV_BODY1", + "description": "Field.", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "PRINCE_REGION0_IV_BODY2", + "description": "Field.", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "PRINCE_REGION0_IV_BODY3", + "description": "Field.", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "PRINCE_REGION0_IV_BODY4", + "description": "Field.", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "PRINCE_REGION0_IV_BODY5", + "description": "Field.", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "PRINCE_REGION0_IV_BODY6", + "description": "Field.", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "PRINCE_REGION0_IV_BODY7", + "description": "Field.", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "PRINCE_REGION0_IV_BODY8", + "description": "Field.", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "PRINCE_REGION0_IV_BODY9", + "description": "Field.", + "offset_int": "0x005C", + "access": "RO", + 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(Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cmpa.json new file mode 100644 index 0000000..2dcccc6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfr_cmpa.json @@ -0,0 +1,2187 @@ +{ + "cpu": "lpc55s16", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "USB_HID_ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 2, + "id": "field000-bits9-10", + "name": "USB_SPEED", + "description": "Defines which USB module is used for ISP:", + "values": [ + { + "name": "USB_SPEED_0", + "value": 0, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + }, + { + "name": "USB_FS", + "value": 1, + "description": "USB FS module used for ISP" + }, + { + "name": "USB_HS", + "value": 2, + "description": "USB HS module used for ISP" + }, + { + "name": "USB_SPEED_1", + "value": 3, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + } + ] + }, + { + "width": 13 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure boot configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "RSA4K", + "description": "Select minimal key length. To enforce usage of RSA4096, setting 0b11 value is recommended to allow RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "RSA2048 or higher can be used for image signing. Only RSA2048 can be used as debug keys." + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block PUF enrollment", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits16-17", + "name": "SKIP_BOOT_SEED", + "description": "Skip boot seed computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable BOOT_SEED" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable BOOT_SEED" + } + ] + }, + { + "width": 2, + "id": "field01C-bits18-19", + "name": "BOOT_SEED_INC_NXP_CFG", + "description": "Include NXP area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits20-21", + "name": "BOOT_SEED_CUST_CFG", + "description": "Include CMPA area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits22-23", + "name": "BOOT_SEED_INC_EPOCH", + "description": "Include security epoch area in BOOT_SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_BASE_ADDR", + "description": "Prince Base Address", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4, + "id": "field020-bits0-3", + "name": "ADDR0_PRG", + "description": "Programmable portion of the base address of region 0" + }, + { + "width": 4, + "id": "field020-bits4-7", + "name": "ADDR1_PRG", + "description": "Programmable portion of the base address of region 1" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "ADDR2_PRG", + "description": "Programmable portion of the base address of region 2" + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG0", + "description": "Lock PRINCE region0 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG1", + "description": "Lock PRINCE region1 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "For PRINCE region1 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "For PRINCE region2 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, sub-region enable", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, sub-region enable", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, sub-region enable", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00040-0004C", + "description": "Reserved 00040-0004C" + }, + "registers": [ + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-000FC", + "description": "Reserved 00070-000FC" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfrc_rules.yaml new file mode 100644 index 0000000..60198c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/pfrc_rules.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "lpc55xx_4.1" + desc: + By default (blank device), the RoTKx_EN values are set to 0b00 which means + invalid. When secure boot is enabled (SEC_BOOT_EN != 0) there must be at + least one RoTKx_EN which is set to 0b01 (enabled) to allow device to boot + successfully. + msg: Secure boot is enabled. Make sure at least one Root of Trust Key Enable bit is set. + cond: CMPA.SECURE_BOOT_CFG.SEC_BOOT_EN != 0 and not (CFPA.ROTKH_REVOKE.RoTK3_EN == 1 or CFPA.ROTKH_REVOKE.RoTK2_EN == 1 or CFPA.ROTKH_REVOKE.RoTK1_EN == 1 or CFPA.ROTKH_REVOKE.RoTK0_EN == 1) + + - req_id: "lpc55xx_5.1" + desc: Inverse value (upper 16 bits) of VENDOR_USAGE must be always + valid. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.VENDOR_USAGE != 0 and (~(CFPA.VENDOR_USAGE>>int(16)) & 0xFFFF) != (CFPA.VENDOR_USAGE & 0xFFFF) diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/tz.json new file mode 100644 index 0000000..9b77837 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s16/tz.json @@ -0,0 +1,837 @@ +{ + "cpu": "lpc55s16", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "USB_HS Slave Rule Register (usb_hs_slave_rule)", + "description": "TrustZone register - USB_HS Slave Rule Register (usb_hs_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "USB_HS Memory Rule Register 0 (usb_hs_mem_rule)", + "description": "TrustZone register - USB_HS Memory Rule Register 0 (usb_hs_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule)", + "description": "TrustZone register - AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/database.yaml new file mode 100644 index 0000000..d9274a2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/database.yaml @@ -0,0 +1,189 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: {} +latest: a1 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc55s2x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc552x-s2x-mainstream-arm-cortex-m33-based-microcontroller-family:LPC552x-S2x + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x40000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x40000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x18000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x9_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x9_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field050 + - field054 + - field058 + - field05C + - field060 + - field064 + - field068 + - field06C + computed_fields: + field010: # DCFG_CC_SOCU_PIN + field010-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field014: # DCFG_CC_SOCU_DFLT + field014-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + rules: + - ../../common/pfrc_rules.yaml + - pfrc_rules.yaml + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cfpa.json new file mode 100644 index 0000000..2391530 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cfpa.json @@ -0,0 +1,1600 @@ +{ + "cpu": "lpc55s26", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 0", + "description": "PRINCE region 0" + }, + "registers": [ + { + "id": "field030", + "name": "PRINCE_REGION0_IV_CODE0", + "description": "Field.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "PRINCE_REGION0_IV_CODE1", + "description": "Field.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field034-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field034-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field034-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field038", + "name": "PRINCE_REGION0_IV_BODY0", + "description": "Field.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "PRINCE_REGION0_IV_BODY1", + "description": "Field.", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "PRINCE_REGION0_IV_BODY2", + "description": "Field.", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "PRINCE_REGION0_IV_BODY3", + "description": "Field.", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "PRINCE_REGION0_IV_BODY4", + "description": "Field.", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "PRINCE_REGION0_IV_BODY5", + "description": "Field.", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "PRINCE_REGION0_IV_BODY6", + "description": "Field.", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "PRINCE_REGION0_IV_BODY7", + "description": "Field.", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "PRINCE_REGION0_IV_BODY8", + "description": "Field.", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "PRINCE_REGION0_IV_BODY9", + "description": "Field.", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "PRINCE_REGION0_IV_BODY10", + "description": "Field.", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "PRINCE_REGION0_IV_BODY11", + "description": "Field.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 1", + "description": "PRINCE region 1" + }, + "registers": [ + { + "id": "field068", + "name": "PRINCE_REGION1_IV_CODE0", + "description": "Field.", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "PRINCE_REGION1_IV_CODE1", + "description": "Field.", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field06C-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field06C-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field06C-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field070", + "name": "PRINCE_REGION1_IV_BODY0", + "description": "Field.", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "PRINCE_REGION1_IV_BODY1", + "description": "Field.", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "PRINCE_REGION1_IV_BODY2", + "description": "Field.", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "PRINCE_REGION1_IV_BODY3", + "description": "Field.", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "PRINCE_REGION1_IV_BODY4", + "description": "Field.", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "PRINCE_REGION1_IV_BODY5", + "description": "Field.", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "PRINCE_REGION1_IV_BODY6", + "description": "Field.", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "PRINCE_REGION1_IV_BODY7", + "description": "Field.", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "PRINCE_REGION1_IV_BODY8", + "description": "Field.", + "offset_int": "0x0090", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "PRINCE_REGION1_IV_BODY9", + "description": "Field.", + "offset_int": "0x0094", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "PRINCE_REGION1_IV_BODY10", + "description": "Field.", + "offset_int": "0x0098", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "PRINCE_REGION1_IV_BODY11", + "description": "Field.", + "offset_int": "0x009C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 2", + "description": "PRINCE region 2" + }, + "registers": [ + { + "id": "field0A0", + "name": "PRINCE_REGION2_IV_CODE0", + "description": "Field.", + "offset_int": "0x00A0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "PRINCE_REGION2_IV_CODE1", + "description": "Field.", + "offset_int": "0x00A4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0A4-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field0A4-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field0A4-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field0A8", + "name": "PRINCE_REGION2_IV_BODY0", + "description": "Field.", + "offset_int": "0x00A8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "PRINCE_REGION2_IV_BODY1", + "description": "Field.", + "offset_int": "0x00AC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "PRINCE_REGION2_IV_BODY2", + "description": "Field.", + "offset_int": "0x00B0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "PRINCE_REGION2_IV_BODY3", + "description": "Field.", + "offset_int": "0x00B4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "PRINCE_REGION2_IV_BODY4", + "description": "Field.", + "offset_int": "0x00B8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "PRINCE_REGION2_IV_BODY5", + "description": "Field.", + "offset_int": "0x00BC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C0", + "name": "PRINCE_REGION2_IV_BODY6", + "description": "Field.", + "offset_int": "0x00C0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C4", + "name": "PRINCE_REGION2_IV_BODY7", + "description": "Field.", + "offset_int": "0x00C4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C8", + "name": "PRINCE_REGION2_IV_BODY8", + "description": "Field.", + "offset_int": "0x00C8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0CC", + "name": "PRINCE_REGION2_IV_BODY9", + "description": "Field.", + "offset_int": "0x00CC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D0", + "name": "PRINCE_REGION2_IV_BODY10", + "description": "Field.", + "offset_int": "0x00D0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D4", + "name": "PRINCE_REGION2_IV_BODY11", + "description": "Field.", + "offset_int": "0x00D4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000D8-000FC", + "description": "Reserved 000D8-000FC" + }, + "registers": [ + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cmpa.json new file mode 100644 index 0000000..1048ed7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfr_cmpa.json @@ -0,0 +1,1994 @@ +{ + "cpu": "lpc55s26", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "USB_HID_ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_96MHZ", + "value": 1, + "description": "96MHz FRO" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 2, + "id": "field000-bits9-10", + "name": "USB_SPEED", + "description": "Defines which USB module is used for ISP:", + "values": [ + { + "name": "USB_SPEED_0", + "value": 0, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + }, + { + "name": "USB_FS", + "value": 1, + "description": "USB FS module used for ISP" + }, + { + "name": "USB_HS", + "value": 2, + "description": "USB HS module used for ISP" + }, + { + "name": "USB_SPEED_1", + "value": 3, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + } + ] + }, + { + "width": 13 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure boot configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "RSA4K", + "description": "Select minimal key length. To enforce usage of RSA4096, setting 0b11 value is recommended to allow RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "RSA2048 or higher can be used for image signing. Only RSA2048 can be used as debug keys." + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block PUF enrollment", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE" + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_BASE_ADDR", + "description": "Prince Base Address", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4, + "id": "field020-bits0-3", + "name": "ADDR0_PRG", + "description": "Programmable portion of the base address of region 0" + }, + { + "width": 4, + "id": "field020-bits4-7", + "name": "ADDR1_PRG", + "description": "Programmable portion of the base address of region 1" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "ADDR2_PRG", + "description": "Programmable portion of the base address of region 2" + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG0", + "description": "Lock PRINCE region0 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG1", + "description": "Lock PRINCE region1 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "For PRINCE region1 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "For PRINCE region2 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, sub-region enable", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, sub-region enable", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, sub-region enable", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00038-0004C", + "description": "Reserved 00038-0004C" + }, + "registers": [ + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-000FC", + "description": "Reserved 00070-000FC" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfrc_rules.yaml new file mode 100644 index 0000000..60198c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s26/pfrc_rules.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "lpc55xx_4.1" + desc: + By default (blank device), the RoTKx_EN values are set to 0b00 which means + invalid. When secure boot is enabled (SEC_BOOT_EN != 0) there must be at + least one RoTKx_EN which is set to 0b01 (enabled) to allow device to boot + successfully. + msg: Secure boot is enabled. Make sure at least one Root of Trust Key Enable bit is set. + cond: CMPA.SECURE_BOOT_CFG.SEC_BOOT_EN != 0 and not (CFPA.ROTKH_REVOKE.RoTK3_EN == 1 or CFPA.ROTKH_REVOKE.RoTK2_EN == 1 or CFPA.ROTKH_REVOKE.RoTK1_EN == 1 or CFPA.ROTKH_REVOKE.RoTK0_EN == 1) + + - req_id: "lpc55xx_5.1" + desc: Inverse value (upper 16 bits) of VENDOR_USAGE must be always + valid. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.VENDOR_USAGE != 0 and (~(CFPA.VENDOR_USAGE>>int(16)) & 0xFFFF) != (CFPA.VENDOR_USAGE & 0xFFFF) diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s28/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s28/database.yaml new file mode 100644 index 0000000..c3fdc05 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s28/database.yaml @@ -0,0 +1,34 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc55s26 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x80000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x80000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x30000" + external: false + sram4: + start_int: "0x20040000" + size_int: "0x4000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/database.yaml new file mode 100644 index 0000000..341d817 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/database.yaml @@ -0,0 +1,345 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: + features: + pfr: + cfpa: + reg_spec: pfr_cfpa_a0.json + cmpa: + reg_spec: pfr_cmpa_a0.json + tz: + reg_spec: tz_a0.json + a1: + features: + pfr: + cfpa: + reg_spec: pfr_cfpa_a1.json + cmpa: + reg_spec: pfr_cmpa_a1.json + deprecated_reg_names: + field04C: + alt_names: [RoTK_USAGE] + bitfields: + field04C-bits0-2: [RoTK0_Usage] + field04C-bits3-5: [RoTK1_Usage] + field04C-bits6-8: [RoTK2_Usage] + field04C-bits9-11: [RoTK3_Usage] + + tz: + reg_spec: tz_a1.json + dice: + reg_spec: dice_had_a1.json +latest: a1 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc55s3x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-arm-cortex-m33/lpc553x-s3x-advanced-analog-armcortex-m33-based-mcu-family:LPC553x + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x3DC00" + external: false + flexspi_ns: + start_int: "0x8000000" + size_int: "0x8000000" + external: true + flexspi_s: + start_int: "0x18000000" + size_int: "0x8000000" + external: true + mirror_of: flexspi_ns + internal-flash_s: + start_int: "0x10000000" + size_int: "0x3DC00" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x1C000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x4000" + external: false + __comment: + Does not work as target `onchip RAM` memory, blhost reports 10200 + (0x27d8) Memory Range Invalid. + isp: + rom: + protocol: mboot + interfaces: ["uart", "usb", "can", "spi", "i2c"] + usb: + - vid: 0x1FC9 + pid: 0x0025 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== DAT section ======== + dat: + socc: 4 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinImageVersion + - Mbi_MixinIvt + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifest + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x3_DC00 + size: 512 + seal_start: field1EC # CFPA_CRC32 + seal_count: 1 + computed_fields: + field054: # VENDOR_USAGE + field054-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field058: # DCFG_CC_SOCU_NS_PIN + field058-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field05C: # DCFG_CC_SOCU_NS_DFLT + field05C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + cmpa: # CMPA description + address: 0x3_E200 + size: 512 + seal_start: field1F0 # CMPA_CMAC0 + seal_count: 4 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 384 + config_as_hexstring: true + reversed: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key + table hash. For ECC P-256 keys RKTH is a 32-byte SHA-256 digest of four + SHA-256 digests computed over four OEM public keys (OEM has four + private-public key pairs in case one of its private keys becomes + compromised) or in case that ECC P-384 keys are used, RKTH is 48-byte + SHA-384 digest. + sub_regs: + - field050 + - field054 + - field058 + - field05C + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + computed_fields: + field010: # DCFG_CC_SOCU_PIN + field010-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field014: # DCFG_CC_SOCU_DFLT + field014-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + reg_spec_modification: + field090: + bitfields: + field090-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field094: + bitfields: + field094-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field098: + bitfields: + field098-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field09C: + bitfields: + field09C-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0A4: + bitfields: + field0A4-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0A8: + bitfields: + field0A8-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0AC: + bitfields: + field0AC-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + rules: + - ../../common/pfrc_rules.yaml + - pfrc_rules.yaml + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + flexspi_nor: + segments: + fcb: 0x0400 + image_version_ap: 0x0600 + mbi: 0x1000 + remap_align: 0x40000 # 256 KB + image_pattern: ones + recovery_spi_sb31: + segments: + sb31: 0x00 + recovery_spi_mbi: + segments: + mbi: 0x00 + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB31] + key_blob_offset: 0x4 + key_blob_command_position: -1 + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + + # ======== TrustZone section ======== + tz: {} + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + spi_nor: + instances: [0, 1, 3, 8] + + # ======== DICE configuration ======== + dice: + buffer_address: 0x3001_5000 + buffer_size: 0x1000 + csr_address: 0x2000_0000 + csr_length: 208 + rkth_length: 32 + rkth_truncated_length: 32 + response_length: 324 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/dice_had_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/dice_had_a1.json new file mode 100644 index 0000000..33e52d2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/dice_had_a1.json @@ -0,0 +1,522 @@ +{ + "cpu": "LPC55S36", + "groups": [ + { + "group": { + "name": "DICE HAD registers", + "description": "Registers used by DICE attestation." + }, + "registers": [ + { + "id": "field9D0", + "offset_int": "0x000", + "reg_width": 32, + "name": "ELS_AS_CFG0", + "description": "ELS AS configuration", + "default_value_int": "0xff00355", + "bitfields": [ + { + "id": "field9D0-bits0-7", + "width": 8, + "name": "CFG_LC_STATE", + "access": "RO", + "description": "LC state configuration bit." + }, + { + "id": "field9D0-bit8", + "width": 1, + "name": "CFG_BOD_VBAT_RESET_ENABLED", + "access": "RO", + "description": "When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN reset is enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit9", + "width": 1, + "name": "CFG_BOD_CORE_RESET_ENABLED", + "access": "RO", + "description": "When BOD CORE analog detector is turned on and BOD CORE reset is enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit10", + "width": 1, + "name": "CFG_BOD_VBAT_IRQ_ENABLED", + "access": "RO", + "description": "When BOD VDDMAIN analog detector is turned on and BOD VDDMAIN IRQ is enabled, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "id": "field9D0-bit12", + "width": 1, + "name": "CFG_WDT_ENABLED", + "access": "RO", + "description": "When WatchDog Timer is activated, this bit indicates state 1." + }, + { + "id": "field9D0-bit13", + "width": 1, + "name": "CFG_CWDT_ENABLED", + "access": "RO", + "description": "When Code WatchDog Timer is activated, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "id": "field9D0-bit15", + "width": 1, + "name": "CFG_ELS_GDET_ENABLED", + "access": "RO", + "description": "When ELS GDET is enabled, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "id": "field9D0-bit17", + "width": 1, + "name": "CFG_TAMPER_DET_ENABLED", + "access": "RO", + "description": "When tamper detector is enabled in RTC, this bit indicates state 1." + }, + { + "id": "field9D0-bit18", + "width": 1, + "name": "CFG_FLASH_IS_REMAPPED", + "access": "RO", + "description": "When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000, this bit indicates state 1." + }, + { + "id": "field9D0-bit19", + "width": 1, + "name": "CFG_FLASH_IS_REMAPPED_DP", + "access": "RO", + "description": "When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000, this bit indicates state 1." + }, + { + "id": "field9D0-bits20-23", + "width": 4, + "name": "CFG_FLASH_BANK0_ENABLE", + "access": "RO", + "description": "The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as below." + }, + { + "id": "field9D0-bits24-27", + "width": 4, + "name": "CFG_FLASH_BANK1_ENABLE", + "access": "RO", + "description": "The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as below:" + }, + { + "id": "field9D0-bit28", + "width": 1, + "name": "CFG_QK_DISABLE_ENROLL", + "access": "RO", + "description": "When CONFIG[DIS_PUF_ENROLL] bit is set 1, this bit indicates state 1." + }, + { + "id": "field9D0-bit29", + "width": 1, + "name": "CFG_QK_DISABLE_WRAP", + "access": "RO", + "description": "When CONFIG[DIS_PUF_WRAP_KEY] bit is set 1, this bit indicates state 1." + }, + { + "width": 2 + } + ] + }, + { + "id": "field9D4", + "offset_int": "0x004", + "reg_width": 32, + "name": "ELS_AS_CFG1", + "description": "ELS AS configuration1", + "default_value_int": "0x22", + "bitfields": [ + { + "width": 1 + }, + { + "id": "field9D4-bit1", + "width": 1, + "name": "CFG_SEC_DIS_STRICT_MODE", + "access": "RO", + "description": "When \"CFG_SEC_ENA_SEC_CHK\" indicates state 0 or when \"DISABLE_STRICT_MODE\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are equal to 01, this bit indicates state 1." + }, + { + "id": "field9D4-bit2", + "width": 1, + "name": "CFG_SEC_DIS_VIOL_ABORT", + "access": "RO", + "description": "When \"DISABLE_VIOLATION_ABORT\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit3", + "width": 1, + "name": "CFG_SEC_ENA_NS_PRIV_CHK", + "access": "RO", + "description": "When \"ENABLE_NS_PRIV_CHECK\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit4", + "width": 1, + "name": "CFG_SEC_ENA_S_PRIV_CHK", + "access": "RO", + "description": "When \"ENABLE_S_PRIV_CHECK\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit5", + "width": 1, + "name": "CFG_SEC_ENA_SEC_CHK", + "access": "RO", + "description": "When \"ENABLE_SECURE_CHECKING\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit6", + "width": 1, + "name": "CFG_SEC_IDAU_ALLNS", + "access": "RO", + "description": "When \"IDAU_ALL_NS\" bits in \"MISC_CTRL_REG\" and \"MISC_CTRL_DP_REG\" on AHB secure controller, both bits are equal to 01, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "id": "field9D4-bit8", + "width": 1, + "name": "CFG_SEC_LOCK_NS_MPU", + "access": "RO", + "description": "When \"LOCK_NS_MPU\" bits in \"CPU0_LOCK_REG\" on AHB secure controller are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit9", + "width": 1, + "name": "CFG_SEC_LOCK_NS_VTOR", + "access": "RO", + "description": "When \"LOCK_NS_VTOR\" bits in \"CPU0_LOCK_REG\" on AHB secure controller are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit10", + "width": 1, + "name": "CFG_SEC_LOCK_S_MPU", + "access": "RO", + "description": "When \"LOCK_S_MPU\" bits in \"CPU0_LOCK_REG\" on AHB secure controller are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit11", + "width": 1, + "name": "CFG_SEC_LOCK_S_VTAIRCR", + "access": "RO", + "description": "When \"LOCK_S_VTAIRCR\" bits in \"CPU0_LOCK_REG\" on AHB secure controller are not equal to 10, this bit indicates state 1." + }, + { + "id": "field9D4-bit12", + "width": 1, + "name": "CFG_SEC_LOCK_SAU", + "access": "RO", + "description": "When \"LOCK_SAU\" bits in \"CPU0_LOCK_REG\" on AHB secure controller are not equal to 10, this bit indicates state 1." + }, + { + "width": 19 + } + ] + }, + { + "id": "field9D8", + "offset_int": "0x008", + "reg_width": 32, + "name": "ELS_AS_CFG2", + "description": "ELS configuration command enable bit.", + "default_value_int": "0xffffffff" + }, + { + "id": "field9E0", + "offset_int": "0x010", + "reg_width": 32, + "name": "ELS_AS_ST0", + "description": "ELS AS state register", + "default_value_int": "0xdc00", + "bitfields": [ + { + "id": "field9E0-bits0-3", + "width": 4, + "name": "ST_TEMPORAL_STATE", + "access": "RO", + "description": "\"TEMPORAL_STATE[3:0]\" on \"ELS_TEMPORAL_STATE\" register reflects this register." + }, + { + "id": "field9E0-bit4", + "width": 1, + "name": "ST_CPU0_DBGEN", + "access": "RO", + "description": "When CPU0 (CM33) \"dbgen\" input is state 1, this bit indicates state 1." + }, + { + "id": "field9E0-bit5", + "width": 1, + "name": "ST_CPU0_NIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"niden\" input is state 1, this bit indicates state 1." + }, + { + "id": "field9E0-bit6", + "width": 1, + "name": "ST_CPU0_SPIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"spiden\" input is state 1, this bit indicates state 1." + }, + { + "id": "field9E0-bit7", + "width": 1, + "name": "ST_CPU0_SPNIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"spniden\" input is state 1, this bit indicates state 1." + }, + { + "width": 2 + }, + { + "id": "field9E0-bit10", + "width": 1, + "name": "ST_DAP_ENABLE_CPU0", + "access": "RO", + "description": "When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "id": "field9E0-bit13", + "width": 1, + "name": "ST_ELS_DEBUG_EN", + "access": "RO", + "description": "When ELS uCode code fetch out of AHB for debug is enabled, this bit indicates state 1." + }, + { + "id": "field9E0-bit14", + "width": 1, + "name": "ST_ALLOW_TEST_ACCESS", + "access": "RO", + "description": "When JTAG TAP access is allowed, this bit indicates state 1." + }, + { + "id": "field9E0-bit15", + "width": 1, + "name": "ST_XO32K_FAILED", + "access": "RO", + "description": "When XO32K oscillation fail flag is state 1 in PMC register block, this bit indicates state 1." + }, + { + "width": 16 + } + ] + }, + { + "id": "field9E4", + "offset_int": "0x014", + "reg_width": 32, + "name": "ELS_AS_ST1", + "description": "ELS AS state1", + "default_value_int": "0x18f", + "bitfields": [ + { + "id": "field9E4-bits0-3", + "width": 4, + "name": "ST_QK_PUF_SCORE", + "access": "RO", + "description": "These register bits indicate the state of \"qk_puf_score[3:0]\" outputs from QK PUF block." + }, + { + "id": "field9E4-bit4", + "width": 1, + "name": "ST_QK_ZEROIZED", + "access": "RO", + "description": "This register bit indicates the state of \"qk_zeroized\" output from QK PUF block." + }, + { + "id": "field9E4-bit5", + "width": 1, + "name": "ST_MAIN_CLK_IS_EXT", + "access": "RO", + "description": "When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1." + }, + { + "id": "field9E4-bits6-9", + "width": 4, + "name": "ST_DCDC_VOUT", + "access": "RO", + "description": "VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register." + }, + { + "id": "field9E4-bits10-11", + "width": 2, + "name": "ST_BOOT_MODE", + "access": "RO", + "description": "BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register." + }, + { + "id": "field9E4-bits12-15", + "width": 4, + "name": "ST_BOOT_RETRY_CNT", + "access": "RO", + "description": "\"BOOT_RETRY_CNT[3:0]\" on \"ELS_BOOT_RETRY_CNT\" register reflects this register." + }, + { + "width": 16 + } + ] + }, + { + "id": "field9E8", + "offset_int": "0x018", + "reg_width": 32, + "name": "ELS_AS_ST2", + "description": "\"BOOT_STATE[31:0]\" on \"ELS_BOOT_STATE\" register reflects this register.", + "default_value_int": "0x0" + }, + { + "id": "field9F0", + "offset_int": "0x020", + "reg_width": 32, + "name": "ELS_AS_FLAG0", + "description": "ELS AS flag0", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field9F0-bit0", + "width": 1, + "name": "FLAG_AP_ENABLE_CPU0", + "access": "RO", + "description": "This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "id": "field9F0-bit4", + "width": 1, + "name": "FLAG_BOD_VBAT_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when BOD VDDMAIN reset is enabled and BOD VDDMAIN analog detector is tripped. This register is cleared 0 by AO domain POR." + }, + { + "id": "field9F0-bit5", + "width": 1, + "name": "FLAG_BOD_CORE_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE analog detector is tripped. This register is cleared 0 by AO domain POR." + }, + { + "id": "field9F0-bit6", + "width": 1, + "name": "FLAG_BOD_VBAT_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when BOD VDDMAIN IRQ is enabled and BOD VDDMAIN analog detector is tripped. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit7", + "width": 1, + "name": "FLAG_BOD_CORE_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE analog detector is tripped. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit8", + "width": 1, + "name": "FLAG_WDT_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when WatchDog Timer reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR." + }, + { + "id": "field9F0-bit9", + "width": 1, + "name": "FLAG_CWDT_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when Code WatchDog Timer reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR." + }, + { + "id": "field9F0-bit10", + "width": 1, + "name": "FLAG_WDT_IRQ_OCCURRED", + "access": "RO", + "description": "This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit11", + "width": 1, + "name": "FLAG_CWDT_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit12", + "width": 1, + "name": "FLAG_QK_ERROR", + "access": "RO", + "description": "This flag bit is set 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit13", + "width": 1, + "name": "FLAG_ELS_GLITCH_DETECTED", + "access": "RO", + "description": "This flag bit is set 1 when GDET error is flagged from ELS. This register is cleared 0 by PMC reset event." + }, + { + "width": 1 + }, + { + "id": "field9F0-bit15", + "width": 1, + "name": "FLAG_TAMPER_EVENT_DETECTED", + "access": "RO", + "description": "This flag bit is set 1 when tamper event is flagged from RTC. This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is cleared by software." + }, + { + "id": "field9F0-bit16", + "width": 1, + "name": "FLAG_FLASH_ECC_INVALID", + "access": "RO", + "description": "This flag bit is set 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit17", + "width": 1, + "name": "FLAG_SEC_VIOL_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when security violation is indicated from FLASH sub-system or AHB bus matrix." + }, + { + "id": "field9F0-bit18", + "width": 1, + "name": "FLAG_CPU0_NS_C_ACC_OCCURRED", + "access": "RO", + "description": "This flag bit is set 1 when CPU0 (CM33) makes non-secure code transactions. This register is cleared 0 by PMC reset event." + }, + { + "id": "field9F0-bit19", + "width": 1, + "name": "FLAG_CPU0_NS_D_ACC_OCCURRED", + "access": "RO", + "description": "This flag register is set 1 when CPU0 (CM33) makes non-secure data transactions. This register is cleared 0 by PMC reset event." + }, + { + "width": 12 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fcb_flexspi_nor.json new file mode 100644 index 0000000..6dd178d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fcb_flexspi_nor.json @@ -0,0 +1,25617 @@ +{ + "cpu": "LPC55S36", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps" + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells" + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps" + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells" + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "dll0CrVal", + "description": " [0x1b0-0x1b3] Customizable DLL0CR setting", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "dll1CrVal", + "description": " [0x1b4-0x1b7] Customizable DLL1CR setting", + "default_value_int": "0x0" + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b8-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b8-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2)", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context", + "default_value_int": "0x0" + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Reserved2_0", + "deprecated_names": ["reserve2_0"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Reserved2_1", + "deprecated_names": ["reserve2_1"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Reserved2_2", + "deprecated_names": ["reserve2_2"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Reserved2_3", + "deprecated_names": ["reserve2_3"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Reserved2_4", + "deprecated_names": ["reserve2_4"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Reserved2_5", + "deprecated_names": ["reserve2_5"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Reserved2_6", + "deprecated_names": ["reserve2_6"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Reserved2_7", + "deprecated_names": ["reserve2_7"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Reserved2_8", + "deprecated_names": ["reserve2_8"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "Reserved2_9", + "deprecated_names": ["reserve2_9"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fuses.json new file mode 100644 index 0000000..3415167 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/fuses.json @@ -0,0 +1,236 @@ +{ + "cpu": "LPC55S36", + "groups": [ + { + "group": { + "name": "LC_STATE", + "description": "Device life cycle state, only the lowest 8 bits are valid." + }, + "registers": [ + { + "id": "fuse0", + "name": "LC_STATE", + "description": "Device life cycle state. \nLife-cycle state provided to SYSCON block to distribute it to CSS and PUF ports to implement implicit security on the device.", + "index_int": "0", + "default_value_int": "0x0003", + "bitfields": [ + { + "width": 8, + "id": "fuse0-bits-0-7", + "name": "LC_STATE", + "description": "OTP life cycle state LC_STATE[7:0].", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank = State of the device before doing any wafer or package testing." + }, + { + "name": "FAB", + "value": 1, + "description": "Fab = Initial state in NXP factory." + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop = Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop2 = Optional customer development state. Used for development of NS world code." + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field = In-field application state for end-customer use." + }, + { + "name": "FIELD_RETURN", + "value": 31, + "description": "Field Return OEM = Field return state." + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure analysis (FA) = NXP field return state (CQC)." + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field Locked = Alternative in-field application state that prevents use of field return/failure analysis states. The rest of the behavior of the device is same as the In-field state." + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked = Bricked state to prevent device use." + } + ] + }, + { + "width": 24 + } + ] + } + ] + }, + { + "group": { + "name": "CMPA_CRC", + "description": "CMPA CRC check value." + }, + "registers": [ + { + "id": "fuse1", + "name": "CMPA_CRC", + "description": "CRC32 of CMPA fields. \n- For secure parts used during deep power-down wake before using the fields in CMPA area.", + "index_int": "0x0001" + } + ] + }, + { + "group": { + "name": "CMPA_CMAC", + "description": "CMAC of CMPA pages.\nUsed by secure parts during cold & warm boots.\nWake up from deep-power down mode CMPA_CRC is used." + }, + "registers": [ + { + "id": "fuse2", + "name": "CMPA_CMAC0", + "description": "CMPA CMA check value word 0.", + "index_int": "0x0002" + }, + { + "id": "fuse3", + "name": "CMPA_CMAC1", + "description": "CMPA CMA check value word 1.", + "index_int": "0x0003" + }, + { + "id": "fuse4", + "name": "CMPA_CMAC2", + "description": "CMPA CMA check value word 2.", + "index_int": "0x0004" + }, + { + "id": "fuse5", + "name": "CMPA_CMAC3", + "description": "CMPA CMA check value word 3.", + "index_int": "0x0005" + } + ] + }, + { + "group": { + "name": "SECBOOT_CFG", + "description": "Secure boot configure, only the lowest 8 bits are valid." + }, + "registers": [ + { + "id": "fuse6", + "name": "SECBOOT_CFG", + "description": "Secure boot configuration.", + "index_int": "0x0006", + "bitfields": [ + { + "width": 1, + "id": "fuse6-bit-0", + "name": "RoTK0_dis", + "description": "Revoke RoTK0 key." + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "RoTK1_dis", + "description": "Revoke RoTK1 key." + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "RoTK2_dis", + "description": "Revoke RoTK2 key." + }, + { + "width": 1, + "id": "fuse6-bit-3", + "name": "RoTK3_dis", + "description": "Revoke RoTK3 key." + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "EN_CNSA", + "description": "Enforce CNSA suite for secure boot, FW update and debug authentication." + }, + { + "width": 1, + "id": "fuse6-bit-6", + "name": "EN_ECDSA", + "description": "Enforce ECDSA signature verify on every boot." + }, + { + "width": 1, + "id": "fuse6-bit-7", + "name": "EN_CMAC", + "description": "Enforce CMPA CMAC checking on low-power wake." + }, + { + "width": 24 + } + ] + } + ] + }, + { + "group": { + "name": "CUSTOMER_WORDS", + "description": "Customer words area." + }, + "registers": [ + { + "id": "fuse7", + "name": "CUSTOMER_WORD0", + "description": "Customer use word 0.", + "index_int": "0x0007" + }, + { + "id": "fuse8", + "name": "CUSTOMER_WORD1", + "description": "Customer use word 1, only the lowest 8 bits are valid.", + "index_int": "0x0008", + "bitfields": [ + { + "width": 8, + "id": "fuse8-bits-0-7", + "name": "CUSTOMER_WORD1", + "description": "Customer use word 1." + }, + { + "width": 24 + } + ] + }, + { + "id": "fuse9", + "name": "CUSTOMER_WORD2", + "description": "Customer use word 2, only the lowest 8 bits are valid.", + "index_int": "0x0009", + "bitfields": [ + { + "width": 8, + "id": "fuse9-bits-0-7", + "name": "CUSTOMER_WORD2", + "description": "Customer use word 2." + }, + { + "width": 24 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a0.json new file mode 100644 index 0000000..0bfc4b2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a0.json @@ -0,0 +1,1710 @@ +{ + "cpu": "LPC55S36", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "CFPA Page Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "Secure_FW_Version", + "description": "Secure Firmware Version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware Version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image Key Revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field014", + "name": "MCTR_INT_IV_CTR0", + "description": "Erase count for internal Prince region 0 (Monotonic counter)", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "MCTR_INT_IV_CTR1", + "description": "Erase count for internal Prince region 1 (Monotonic counter)", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field01C", + "name": "MCTR_INT_IV_CTR2", + "description": "Erase count for internal Prince region 2 (Monotonic counter)", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field020", + "name": "IPED_IV_CTR0", + "description": "Erase count for external Prince region 0 (Monotonic counter)", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field024", + "name": "IPED_IV_CTR1", + "description": "Erase count for external Prince region 1 (Monotonic counter)", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "IPED_IV_CTR2", + "description": "Erase count for external Prince region 2 (Monotonic counter)", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "IPED_IV_CTR3", + "description": "Erase count for external Prince region 3 (Monotonic counter)", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field038", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2.", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3.", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4.", + "offset_int": "0x0040", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5.", + "offset_int": "0x0044", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6.", + "offset_int": "0x0048", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7.", + "offset_int": "0x004C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0050", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "RoTK0_EN", + "description": "Root of Trust Key 0 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits2-3", + "name": "RoTK1_EN", + "description": "Root of Trust Key 1 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits4-5", + "name": "RoTK2_EN", + "description": "Root of Trust Key 2 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits6-7", + "name": "RoTK3_EN", + "description": "Root of Trust Key 3 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 8 + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "DICE_SKIP_CSR", + "description": "DICE Skip CSR", + "values": [ + { + "name": "GENERATE_CSR", + "value": 0, + "description": "Generate CSR" + }, + { + "name": "SKIP_CSR", + "value": 1, + "description": "Skip CSR" + } + ] + }, + { + "width": 14 + } + ] + }, + { + "id": "field054", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0054", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field054-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field054-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field058", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0058", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field058-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field058-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "field058-bit15", + "name": "UUID_CHECK", + "description": "UUID Check", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field058-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value of Bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field05C", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x005C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field05C-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field05C-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 7 + }, + { + "width": 16, + "id": "field05C-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field060", + "name": "ENABLE_FA_MODE", + "description": "Enable FA Mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0060", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page Programming On Going. Set this field to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "CMAC_UPD", + "description": "CMAC Update", + "offset_int": "0x0068", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field068-bits0-1", + "name": "IMG_UPD", + "description": "Image Updated", + "values": [ + { + "name": "NOTHING_CHANGED", + "value": 0, + "description": "Nothing changed" + }, + { + "name": "IMAGE0_CMAC_UPDATE", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "IMAGE1_CMAC_UPDATE", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "BOTH_IMG_CMAC_UPDATE", + "value": 3, + "description": "Update CMAC for both images" + } + ] + }, + { + "width": 3, + "id": "field068-bits2-4", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in OEM_OPEN (0x3) LC state.", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "UPDATE_IN_CMPA", + "value": 2, + "description": "Update CMAC field in CMPA page." + }, + { + "name": "TO_OEM_SECURE", + "value": 3, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_SECURE (0x7)." + }, + { + "name": "TO_OEM_CLOSED", + "value": 5, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_CLOSED (0xF)." + }, + { + "name": "TO_OEM_LOCKED", + "value": 6, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_LOCKED (0xCF)." + } + ] + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "IMG0_CMAC0", + "description": "Image 0 CMAC 0", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "IMG0_CMAC1", + "description": "Image 0 CMAC 1", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "IMG0_CMAC2", + "description": "Image 0 CMAC 2", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "IMG0_CMAC3", + "description": "Image 0 CMAC 3", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "IMG1_CMAC0", + "description": "Image 1 CMAC 0", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "IMG1_CMAC1", + "description": "Image 1 CMAC 1", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "IMG1_CMAC2", + "description": "Image 1 CMAC 2", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "IMG1_CMAC3", + "description": "Image 1 CMAC 3", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00090-001E8", + "description": "Reserved 00090-001E8" + }, + "registers": [ + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00120", + "name": "Reserved 0x00120", + "description": "This field is reserved for internal use", + "offset_int": "0x0120", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CFPA CRC32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "CFPA0 CMAC 0", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CFPA0 CMAC 1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CFPA0 CMAC 2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CFPA0 CMAC 3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a1.json new file mode 100644 index 0000000..583cf84 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cfpa_a1.json @@ -0,0 +1,1723 @@ +{ + "cpu": "lpc55s36", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "Header", + "description": "Header", + "offset_int": "0", + "default_value_int": "0" + }, + { + "id": "field004", + "name": "CFPA_PAGE_Version", + "description": "CFPA Page Version. Write '0xFFFF_FFFF' to auto increment current CFPA page version value (by ROM).", + "offset_int": "0x0004", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure Firmware Version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware Version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image Key Revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0" + }, + { + "id": "field014", + "name": "MCTR_INT_IV_CTR0", + "description": "Erase count for internal Prince region 0 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x0014", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field018", + "name": "MCTR_INT_IV_CTR1", + "description": "Erase count for internal Prince region 1 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x0018", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field01C", + "name": "MCTR_INT_IV_CTR2", + "description": "Erase count for internal Prince region 2 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x001C", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field020", + "name": "IPED_IV_CTR0", + "description": "Erase count for external Prince region 0 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x0020", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field024", + "name": "IPED_IV_CTR1", + "description": "Erase count for external Prince region 1 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x0024", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field028", + "name": "IPED_IV_CTR2", + "description": "Erase count for external Prince region 2 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x0028", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field02C", + "name": "IPED_IV_CTR3", + "description": "Erase count for external Prince region 3 (Monotonic counter). Write '0' to reset the counter; write '0xFFFF_FFFF' to avoid any change.", + "offset_int": "0x002C", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field030", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0.", + "offset_int": "0x0030", + "default_value_int": "0" + }, + { + "id": "field034", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1.", + "offset_int": "0x0034", + "default_value_int": "0" + }, + { + "id": "field038", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2.", + "offset_int": "0x0038", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3.", + "offset_int": "0x003C", + "default_value_int": "0" + }, + { + "id": "field040", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4.", + "offset_int": "0x0040", + "default_value_int": "0" + }, + { + "id": "field044", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5.", + "offset_int": "0x0044", + "default_value_int": "0" + }, + { + "id": "field048", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6.", + "offset_int": "0x0048", + "default_value_int": "0" + }, + { + "id": "field04C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7.", + "offset_int": "0x004C", + "default_value_int": "0" + }, + { + "id": "field050", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0050", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "RoTK0_EN", + "description": "Root of Trust Key 0 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits2-3", + "name": "RoTK1_EN", + "description": "Root of Trust Key 1 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits4-5", + "name": "RoTK2_EN", + "description": "Root of Trust Key 2 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field050-bits6-7", + "name": "RoTK3_EN", + "description": "Root of Trust Key 3 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "DICE_SKIP_CSR", + "description": "Skip DICE CSR generation", + "values": [ + { + "name": "GENERATE_CSR", + "value": 0, + "description": "Generate CSR" + }, + { + "name": "SKIP_CSR", + "value": 1, + "description": "Skip CSR" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field054", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0054", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field054-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage - Implemented as a monotonic counter field. Whenever a new version of CFPA page is written this field can have the same value or a higher value. It is recommended to use this field to revoke DC certificates issued till that point" + }, + { + "width": 16, + "id": "field054-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field058", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0058", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field058-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field058-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field058-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field058-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field058-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of Bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field05C", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x005C", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field05C-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field05C-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field05C-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field05C-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field060", + "name": "ENABLE_FA_MODE", + "description": "Enable FA Mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0060", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page Programming On Going. Set this field to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "CMAC_UPD", + "description": "CMAC Update", + "offset_int": "0x0068", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field068-bits0-1", + "name": "IMG_UPD", + "description": "Image updated", + "values": [ + { + "name": "NOTHING_CHANGED", + "value": 0, + "description": "Nothing changed" + }, + { + "name": "IMAGE0_CMAC_UPDATE", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "IMAGE1_CMAC_UPDATE", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "BOTH_IMG_CMAC_UPDATE", + "value": 3, + "description": "Update CMAC for both images" + } + ] + }, + { + "width": 3, + "id": "field068-bits2-4", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in OEM_OPEN (0x3) LC state", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "UPDATE_IN_CMPA", + "value": 2, + "description": "Update CMAC field in CMPA page" + }, + { + "name": "TO_OEM_SECURE", + "value": 3, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_SECURE (0x7)" + }, + { + "name": "TO_OEM_CLOSED", + "value": 5, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_CLOSED (0xF)" + }, + { + "name": "TO_OEM_LOCKED", + "value": 6, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_LOCKED (0xCF)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field070", + "name": "IMG0_CMAC0", + "description": "Image 0 CMAC 0", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "IMG0_CMAC1", + "description": "Image 0 CMAC 1", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "IMG0_CMAC2", + "description": "Image 0 CMAC 2", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "IMG0_CMAC3", + "description": "Image 0 CMAC 3", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field080", + "name": "IMG1_CMAC0", + "description": "Image 1 CMAC 0", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "IMG1_CMAC1", + "description": "Image 1 CMAC 1", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "IMG1_CMAC2", + "description": "Image 1 CMAC 2", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "IMG1_CMAC3", + "description": "Image 1 CMAC 3", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00090-001E8", + "description": "Reserved 00090-001E8" + }, + "registers": [ + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00120", + "name": "Reserved 0x00120", + "description": "This field is reserved for internal use", + "offset_int": "0x0120", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CFPA CRC32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "cfpa0 cmac", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CFPA0 CMAC1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CFPA0 CMAC2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CFPA0 CMAC3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a0.json new file mode 100644 index 0000000..4d84349 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a0.json @@ -0,0 +1,3191 @@ +{ + "cpu": "LPC55S36", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field000-bits0-2", + "name": "DEFAULT_BOOT_SOURCE", + "description": "Default Boot Source", + "values": [ + { + "name": "ISP_PIN", + "value": 0, + "description": "ISP pin source" + }, + { + "name": "FLEXSPI_FLASH", + "value": 1, + "description": "FlexSPI flash" + }, + { + "name": "SERIAL_ISP_BOOT", + "value": 2, + "description": "Serial ISP boot" + }, + { + "name": "INTERNAL_FLASH", + "value": 3, + "description": "Internal Flash" + }, + { + "name": "AUTO_BOOT", + "value": 4, + "description": "Auto boot similar to ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_MSC", + "value": 1, + "description": "USB HID MSC" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "CAN_ISP", + "value": 5, + "description": "CAN ISP" + }, + { + "name": "DISBL_ISP_FALLTHRU", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Boot Speed Core Clock", + "values": [ + { + "name": "SYS_SPD_CODE", + "value": 0, + "description": "Defined by NMPA[SYSTEM_SPEED_CODE]" + }, + { + "name": "HHZ96_FRO", + "value": 1, + "description": "96MHz FRO" + }, + { + "name": "MHZ48_FRO", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 10 + }, + { + "width": 2, + "id": "field000-bits19-20", + "name": "ITRC_ZEROIZE", + "description": "ITRC_ZEROIZE", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "PKC_RAM", + "value": 1, + "description": "Zeroize PKC RAM" + }, + { + "name": "A0_RAM", + "value": 2, + "description": "Zeroize low power RAM (AO_RAM)" + }, + { + "name": "BOTH_A0_AND_PKC_RAM", + "value": 3, + "description": "Zeroize both AO_RAM and PKC_RAM" + } + ] + }, + { + "width": 1, + "id": "field000-bit21", + "name": "ASRT_FATAL", + "description": "ASRT_FATAL" + }, + { + "width": 1, + "id": "field000-bit22", + "name": "ASRT_RBF", + "description": "ASRT_RBF" + }, + { + "width": 1, + "id": "field000-bit23", + "name": "ASRT_ISPF", + "description": "ASRT_ISPF" + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "Boot Failure Pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_CAN_CFG", + "description": "SPI CAN Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field004-bits0-1", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI Recovery Boot Enable" + }, + { + "width": 3, + "id": "field004-bits2-4", + "name": "SPI_REC_IF", + "description": "SPI Recovery Interface", + "values": [ + { + "name": "HSPI", + "value": 0, + "description": "HSPI P1_3-MISO, P0_26-MOSI, P1_1-SSEL1, P1_2-SCK" + }, + { + "name": "FC0", + "value": 1, + "description": "FC0 P0_30-MISO, P0_24-MOSI, P0_31-SSEL0, P0_28-SCK" + }, + { + "name": "FC3", + "value": 2, + "description": "FC3 P0_2-MISO, P0_3-MOSI, P0_4-SSEL0, P0_6-SCK" + }, + { + "name": "FC1", + "value": 3, + "description": "FC1 P2_4-MISO, P2_3-MOSI, P2_5-SSEL0, P1_9-SCK" + } + ] + }, + { + "width": 11 + }, + { + "width": 4, + "id": "field004-bits16-19", + "name": "CAN_BAUD_RATE", + "description": "CAN Baud Rate", + "values": [ + { + "name": "AUTO_BAUD_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 1M). Default." + }, + { + "name": "KBPS_10", + "value": 1, + "description": "10 kbp" + }, + { + "name": "KBPS_20", + "value": 2, + "description": "20 kbp" + }, + { + "name": "KBPS_50", + "value": 3, + "description": "50 kbps" + }, + { + "name": "KBPS_125", + "value": 4, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 5, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 6, + "description": "500 kbps" + }, + { + "name": "KBPS_800", + "value": 7, + "description": "800 kbps" + }, + { + "name": "KBPS_1000", + "value": 8, + "description": "1,000 kbps" + } + ] + }, + { + "width": 12 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMEOUT", + "description": "Boot Timeout", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown Timeout" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_SECS", + "description": "WDOG Timeout" + } + ] + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "UUID Check" + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 7 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Vendor Usage [31:16]" + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "ENF_CNSA", + "description": "Enforce CNSA", + "values": [ + { + "name": "ECC_P256", + "value": 0, + "description": "ECC P-256 keys" + }, + { + "name": "ECC_P384_0", + "value": 1, + "description": "ECC P-384 keys, SHA384 and AES256" + }, + { + "name": "ECC_P384_1", + "value": 2, + "description": "ECC P-384 keys, SHA384 and AES256" + }, + { + "name": "ECC_P384_2", + "value": 3, + "description": "ECC P-384 keys, SHA384 and AES256" + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "DICE Include NXP Configuration", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "Included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "Included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "Included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "DICE Customer Configuration", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "Included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "Included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "Included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation.", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_DICE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_DICE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "ENF_TZM_PRESET", + "description": "Enforce TrustZone-M Preset", + "values": [ + { + "name": "IGNORE", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_0", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_1", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_2", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block Set Key", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable key code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable key code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable key code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable key code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block Enroll", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable enrollment mode" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable further enrollment" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable further enrollment" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable further enrollment" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field01C-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "FIPS_SHA_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field01C-bits18-19", + "name": "FIPS_AES_STEN", + "description": "FIPS_AES_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field01C-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "FIPS_ECDSA_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field01C-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "FIPS_DRBG_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field01C-bits24-25", + "name": "FIPS_CMAC_STEN", + "description": "FIPS_CMAC_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field01C-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "FIPS_KDF_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure Boot Enable", + "values": [ + { + "name": "PLAIN_IMAGE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "CMAC_CHECK_IMAGE", + "value": 1, + "description": "Do CMAC checking of image." + }, + { + "name": "ECDSA_CHECK_IMAGE_0", + "value": 2, + "description": "Do complete ECDSA checking of signed images. (internal flash, ECDSA signed)" + }, + { + "name": "ECDSA_CHECK_IMAGE_1", + "value": 3, + "description": "Do complete ECDSA checking of signed images. (internal flash, ECDSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_CONFIG", + "description": "Prince Configuration", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 2, + "id": "field020-bits16-17", + "name": "LOCK_REG0", + "description": "Lock Region 0", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked." + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked." + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked." + } + ] + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG1", + "description": "Lock Region 1", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked." + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked." + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked." + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG2", + "description": "Lock Region 2", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked." + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked." + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "Region 0 Erase Check Enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "Region 1 Erase Check Enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "Region 2 Erase Check Enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, Sub-region Enable", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, Sub-region Enable", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, Sub-region Enable", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz Capabank Trimming", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used." + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid." + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "XTAL LOAD CAP IEC PF X100" + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN PARA CAP PF X100" + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT PARA CAP PF X100" + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz Capabank Trimming", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used." + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid." + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "XTAL LOAD CAP IEC PF X100" + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN PARA CAP PF X100" + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT PARA CAP PF X100" + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "Flash Remap Size", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "Flash Remap Offset", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "PRINCE_XOM_0", + "description": "Prince eXecute-Only-Memory (XOM) 0", + "offset_int": "0x0040", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "PRINCE_XOM_1", + "description": "Prince eXecute-Only-Memory (XOM) 1", + "offset_int": "0x0044", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "PRINCE_XOM_2", + "description": "Prince eXecute-Only-Memory (XOM) 2", + "offset_int": "0x0048", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "RoTK_USAGE", + "description": "Root of Trust Key Usage", + "offset_int": "0x004C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "RoTK0_Usage", + "description": "RoTK0_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field04C-bits3-5", + "name": "RoTK1_Usage", + "description": "RoTK1_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field04C-bits6-8", + "name": "RoTK2_Usage", + "description": "RoTK2_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field04C-bits9-11", + "name": "RoTK3_Usage", + "description": "RoTK3_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 20 + } + ] + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "Root of Trust Key Hash 0", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "Root of Trust Key Hash 1", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "Root of Trust Key Hash 2", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "Root of Trust Key Hash 3", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "Root of Trust Key Hash 4", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "Root of Trust Key Hash 5", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "Root of Trust Key Hash 6", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "Root of Trust Key Hash 7", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "ROTKH8", + "description": "Root of Trust Key Hash 8", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "ROTKH9", + "description": "Root of Trust Key Hash 9", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "ROTKH10", + "description": "Root of Trust Key Hash 10", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "ROTKH11", + "description": "Root of Trust Key Hash 11", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field080-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "FLEXSPI_AUTO_PROBE_EN", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field080-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "FLEXSPI_PROBE_TYPE", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIX_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field080-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "FLEXSPI_FLASH_TYPE", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI_ADDR_3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER_1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER_3V3" + }, + { + "name": "FlexSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FlexSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field080-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "FLEXSPI_DUMMY_CYCLES" + }, + { + "width": 3, + "id": "field080-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "FLEXSPI_FREQUENCY", + "values": [ + { + "name": "MHZ_50", + "value": 0, + "description": "50 Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60 Mhz" + }, + { + "name": "MHZ_80", + "value": 2, + "description": "80 Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100 Mhz" + }, + { + "name": "MHZ_120", + "value": 4, + "description": "120 Mhz" + }, + { + "name": "MHZ_133", + "value": 5, + "description": "133 Mhz" + }, + { + "name": "MHZ_166", + "value": 6, + "description": "166 Mhz" + }, + { + "name": "MHZ_200", + "value": 7, + "description": "200 Mhz" + } + ] + }, + { + "width": 1, + "id": "field080-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "FLEXSPI_RESET_ENABLE", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "No Reset(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "ENABLE_RESET", + "value": 1, + "description": "Enable Reset(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "field080-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "FLEXSPI_RESET_ENABLE" + }, + { + "width": 5, + "id": "field080-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "FLEXSPI_RESET_GPIO_PIN" + }, + { + "width": 2, + "id": "field080-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "FLEXSPI_HOLD TIME", + "values": [ + { + "name": "WAIT_500_MICROSECS", + "value": 0, + "description": "Wait for 500 micro seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 1, + "description": "Wait for 1 mili seconds" + }, + { + "name": "WAIT_3_MILISECS", + "value": 2, + "description": "Wait for 3 mili seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 3, + "description": "Wait for 10 mili seconds" + } + ] + }, + { + "width": 4, + "id": "field080-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "FLEXSPI_PWR_HOLD_TIME", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100_MICROSECS", + "value": 1, + "description": "Waits additional 100 micro-seconds." + }, + { + "name": "WAIT_500_MICROSECS", + "value": 2, + "description": "Waits additional 500 micro-seconds." + }, + { + "name": "WAIT_1_MILISECS", + "value": 3, + "description": "Waits additional 1 mili-seconds." + }, + { + "name": "WAIT_10_MILISECS", + "value": 4, + "description": "Waits additional 10 mili-seconds." + }, + { + "name": "WAIT_20_MILISECS", + "value": 5, + "description": "Waits additional 20 mili-seconds." + }, + { + "name": "WAIT_40_MILISECS", + "value": 6, + "description": "Waits additional 40 mili-seconds." + }, + { + "name": "WAIT_60_MILISECS", + "value": 7, + "description": "Waits additional 60 mili-seconds." + }, + { + "name": "WAIT_80_MILISECS", + "value": 8, + "description": "Waits additional 80 mili-seconds." + }, + { + "name": "WAIT_100_MILISECS", + "value": 9, + "description": "Waits additional 100 mili-seconds." + }, + { + "name": "WAIT_120_MILISECS", + "value": 10, + "description": "Waits additional 120 mili-seconds." + }, + { + "name": "WAIT_140_MILISECS", + "value": 11, + "description": "Waits additional 140 mili-seconds." + }, + { + "name": "WAIT_160_MILISECS", + "value": 12, + "description": "Waits additional 160 mili-seconds." + }, + { + "name": "WAIT_180_MILISECS", + "value": 13, + "description": "Waits additional 180 mili-seconds." + }, + { + "name": "WAIT_200_MILISECS", + "value": 14, + "description": "Waits additional 200 mili-seconds." + }, + { + "name": "WAIT_220_MILISECS", + "value": 15, + "description": "Waits additional 220 mili-seconds." + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field084", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 7, + "id": "field084-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "FLEXSPI_DELAY_CELL_NUM" + }, + { + "width": 10, + "id": "field084-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field084-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "FLEXSPI_REMAP_IMAGE_SIZE", + "values": [ + { + "name": "SIZE", + "value": 0, + "description": "SIZE" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "SIZE_1MB Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "SIZE_2MB Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "SIZE_3MB Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "SIZE_4MB Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "SIZE_5MB Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "SIZE_6MB Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "SIZE_7MB Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "SIZE_8MB Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "SIZE_9MB Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "SIZE_10MB Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "SIZE_11MB Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "SIZE_12MB Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "SIZE_256KB Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "SIZE_512KB Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "SIZE_768KB Size of remapped area is 768KByte." + } + ] + }, + { + "width": 11 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00088-0008C", + "description": "Reserved 00088-0008C" + }, + "registers": [ + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED fields" + }, + "registers": [ + { + "id": "field090", + "name": "IPED0_START", + "description": "IPED region 0 Start", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field090-bits0-1", + "name": "ENABLE_REG0", + "description": "ENABLE_REG0", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled and locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled and locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field090-bits8-31", + "name": "IPED_REG0_START_ADDR", + "description": "IPED_REG0_START_ADDR" + } + ] + }, + { + "id": "field094", + "name": "IPED0_END", + "description": "IPED region 0 End", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field094-bits8-31", + "name": "IPED_REG0_END_ADDR", + "description": "IPED_REG0_END_ADDR" + } + ] + }, + { + "id": "field098", + "name": "IPED1_START", + "description": "IPED region 1 Start", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field098-bits0-1", + "name": "ENABLE_REG1", + "description": "ENABLE_REG1", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled and locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled and locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field098-bits8-31", + "name": "IPED_REG1_START_ADDR", + "description": "IPED_REG1_START_ADDR" + } + ] + }, + { + "id": "field09C", + "name": "IPED1_END", + "description": "IPED region 1 End", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field09C-bits8-31", + "name": "IPED_REG1_END_ADDR", + "description": "IPED_REG1_END_ADDR" + } + ] + }, + { + "id": "field0A0", + "name": "IPED2_START", + "description": "IPED region 2 Start", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0A0-bits0-1", + "name": "ENABLE_REG2", + "description": "ENABLE_REG2", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled and locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled and locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0A0-bits8-31", + "name": "IPED_REG2_START_ADDR", + "description": "IPED_REG2_START_ADDR" + } + ] + }, + { + "id": "field0A4", + "name": "IPED2_END", + "description": "IPED region 2 End", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field0A4-bits8-31", + "name": "IPED_REG2_END_ADDR", + "description": "IPED_REG2_END_ADDR" + } + ] + }, + { + "id": "field0A8", + "name": "IPED3_START", + "description": "IPED region 3 Start", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0A8-bits0-1", + "name": "ENABLE_REG3", + "description": "ENABLE_REG3", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled and locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled and locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0A8-bits8-31", + "name": "IPED_REG3_START_ADDR", + "description": "IPED_REG3_START_ADDR" + } + ] + }, + { + "id": "field0AC", + "name": "IPED3_END", + "description": "IPED region 3 End", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field0AC-bits8-31", + "name": "IPED_REG3_END_ADDR", + "description": "IPED_REG3_END_ADDR" + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port pins high", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port pins low", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port pins high", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port pins low", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000FC", + "description": "Reserved 000C0-000FC" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", 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"default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E0", + "name": "CUSTOMER_DEFINED56", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "CUSTOMER_DEFINED57", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "CUSTOMER_DEFINED58", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "CUSTOMER_DEFINED59", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01EC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CMAC", + "description": "CMAC fields" + }, + "registers": [ + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "CMPA CMAC 0", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMPA CMAC 1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMPA CMAC 2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMPA CMAC 3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a1.json new file mode 100644 index 0000000..a4f211f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfr_cmpa_a1.json @@ -0,0 +1,3535 @@ +{ + "cpu": "lpc55s36", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field000-bits0-2", + "name": "Default_Boot_Source", + "description": "Default Boot Source", + "values": [ + { + "name": "ISP_PIN", + "value": 0, + "description": "ISP pin source" + }, + { + "name": "FLEXSPI_FLASH", + "value": 1, + "description": "FlexSPI flash" + }, + { + "name": "SERIAL_ISP_BOOT", + "value": 2, + "description": "Serial ISP boot" + }, + { + "name": "INTERNAL_FLASH", + "value": 3, + "description": "Internal flash" + }, + { + "name": "AUTO_BOOT", + "value": 4, + "description": "Auto boot similar to ISP auto boot option" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "Default_ISP_mode", + "description": "Default ISP mode", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_MSC", + "value": 1, + "description": "USB HID MSC" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C slave ISP" + }, + { + "name": "CAN_ISP", + "value": 5, + "description": "CAN ISP" + }, + { + "name": "DISBL_ISP_FALLTHRU", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "Boot_Speed", + "description": "Boot Speed Core Clock", + "values": [ + { + "name": "SYS_SPD_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "MHZ48_FRO", + "value": 1, + "description": "48MHz FRO" + }, + { + "name": "MHZ96_FRO", + "value": 2, + "description": "96MHz FRO" + }, + { + "name": "MHZ150_FRO", + "value": 3, + "description": "150MHz PLL" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits19-20", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event. Zeroize long-term storage RAM (AO_RAM) on subsequent boot when Intrusion & Tamper control signals an intrusion event", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "PKC_RAM", + "value": 1, + "description": "Zeroize PKC RAM" + }, + { + "name": "A0_RAM", + "value": 2, + "description": "Zeroize low power RAM (AO_RAM)" + }, + { + "name": "BOTH_A0_AND_PKC_RAM", + "value": 3, + "description": "Zeroize both AO_RAM and PKC_RAM" + } + ] + }, + { + "width": 1, + "id": "field000-bit21", + "name": "ASRT_FATAL", + "description": "Assert on fatal errors. When set ROM drives BOOT_FAIL_PIN high when fatal error condition occurs on three attempts to boot image before locking the part" + }, + { + "width": 1, + "id": "field000-bit22", + "name": "ASRT_RBF", + "description": "Assert on recovery boot. When this bit is set ROM drives the BOOT_FAIL_PIN high whenever no valid image is found in primary boot media and execution enters recovery boot mode from secondary boot media" + }, + { + "width": 1, + "id": "field000-bit23", + "name": "ASRT_ISPF", + "description": "Assert on ISP fall through. When this bit is set ROM drives BOOT_FAIL_PIN high whenever there is no valid image in boot media and execution falls through to ISP mode" + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "Boot_failure_pin", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_CAN_CFG", + "description": "SPI CAN Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field004-bits0-1", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "REC_BOOT_EN SPI flash recovery boot is enabled, if non-zero value is written to this field" + }, + { + "width": 3, + "id": "field004-bits2-4", + "name": "SPI_REC_IF", + "description": "Recovery SPI interface", + "values": [ + { + "name": "HSPI", + "value": 0, + "description": "HSPI P1_3-MISO, P0_26-MOSI, P1_1-SSEL1, P1_2-SCK" + }, + { + "name": "FC0", + "value": 1, + "description": "FC0 P0_30-MISO, P0_24-MOSI, P0_31-SSEL0, P0_28-SCK" + }, + { + "name": "FC3", + "value": 2, + "description": "FC3 P0_2-MISO, P0_3-MOSI, P0_4-SSEL0, P0_6-SCK" + }, + { + "name": "FC1", + "value": 3, + "description": "FC1 P2_4-MISO, P2_3-MOSI, P2_5-SSEL0, P1_9-SCK" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "field004-bits16-19", + "name": "CAN_BAUD_RATE", + "description": "CAN baud rate. Baud rate configured during CAN ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 1M)" + }, + { + "name": "KBPS_10", + "value": 1, + "description": "10 kbps" + }, + { + "name": "KBPS_20", + "value": 2, + "description": "20 kbps" + }, + { + "name": "KBPS_50", + "value": 3, + "description": "50 kbps" + }, + { + "name": "KBPS_125", + "value": 4, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 5, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 6, + "description": "500 kbps" + }, + { + "name": "KBPS_800", + "value": 7, + "description": "800 kbps" + }, + { + "name": "KBPS_1000", + "value": 8, + "description": "1,000 kbps" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMEOUT", + "description": "Boot Timeout", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Power-down timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_SECS", + "description": "WDOG timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code" + } + ] + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. Combinations of PIN and DFLT bits and resulting restriction level: - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. - PIN=1,DFLT=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Recommended to use this field to identify department or model number. So that Debug Credential (DC) Certificates can be issued on class basis instead of issuing UUID specific certificates" + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite algorithm", + "values": [ + { + "name": "ECC_P256", + "value": 0, + "description": "ECC P-256 keys" + }, + { + "name": "ECC_P384_0", + "value": 1, + "description": "ECC P-384 keys, SHA384 & AES256" + }, + { + "name": "ECC_P384_1", + "value": 2, + "description": "ECC P-384 keys, SHA384 & AES256" + }, + { + "name": "ECC_P384_2", + "value": 3, + "description": "ECC P-384 keys, SHA384 & AES256" + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_DICE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_DICE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "ENF_TZM_PRESET", + "description": "TrustZone-M mode", + "values": [ + { + "name": "IGNORE", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_0", + "value": 1, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_1", + "value": 2, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_2", + "value": 3, + "description": "Enforce preset TZM data in image manifest" + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation. (PF commands qk_wrap and qy_wrap_generated_random are disabled)", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Enable Key code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable key code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable key code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable key code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block PUF enrollment", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Enable enrollment mode" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable further enrollment" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable further enrollment" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable further enrollment" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field01C-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field01C-bits18-19", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field01C-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field01C-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field01C-bits24-25", + "name": "FIPS_CMAC_STEN", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field01C-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "PLAIN_IMAGE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "CMAC_CHECK_IMAGE", + "value": 1, + "description": "Do CMAC checking of image" + }, + { + "name": "ECDSA_CHECK_IMAGE_0", + "value": 2, + "description": "Do complete ECDSA checking of signed images. (internal flash, ECDSA signed)" + }, + { + "name": "ECDSA_CHECK_IMAGE_1", + "value": 3, + "description": "Do complete ECDSA checking of signed images. (internal flash, ECDSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_CONFIG", + "description": "Prince Configuration", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field020-bits16-17", + "name": "LOCK_REG0", + "description": "Lock PRINCE region0 settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG1", + "description": "Lock PRINCE region1 settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG2", + "description": "Lock PRINCE region2 settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, Sub-region Enable", + "offset_int": "0x0024", + "default_value_int": "0" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, Sub-region Enable", + "offset_int": "0x0028", + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, Sub-region Enable", + "offset_int": "0x002C", + "default_value_int": "0" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz Capabank Trimming", + "offset_int": "0x0030", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz Capabank Trimming", + "offset_int": "0x0034", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "Trim Valid", + "values": [ + { + "name": "NOT_VALID", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600" + }, + { + "width": 1 + } + ] + }, + { + "id": "field038", + "name": "FLASH_REMAP_SIZE", + "description": "Flash Remap Size", + "offset_int": "0x0038", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "FLASH_REMAP_OFFSET", + "description": "Flash Remap Offset", + "offset_int": "0x003C", + "default_value_int": "0" + }, + { + "id": "field040", + "name": "PRINCE_XOM_0", + "description": "Prince eXecute-Only-Memory (XOM) 0", + "offset_int": "0x0040", + "default_value_int": "0" + }, + { + "id": "field044", + "name": "PRINCE_XOM_1", + "description": "Prince eXecute-Only-Memory (XOM) 1", + "offset_int": "0x0044", + "default_value_int": "0" + }, + { + "id": "field048", + "name": "PRINCE_XOM_2", + "description": "Prince eXecute-Only-Memory (XOM) 2", + "offset_int": "0x0048", + "default_value_int": "0" + }, + { + "id": "field04C", + "name": "RoTK_USAGE", + "description": "Root of Trust Key Usage", + "offset_int": "0x004C", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "RoTK0_Usage", + "description": "RoT key 0 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field04C-bits3-5", + "name": "RoTK1_Usage", + "description": "RoT key 1 usage properties. Check RoTK0_usage field description", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA" + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field04C-bits6-8", + "name": "RoTK2_Usage", + "description": "RoT key 2 usage properties. Check RoTK0_Usage field description", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA" + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field04C-bits9-11", + "name": "RoTK3_Usage", + "description": "RoT key 3 usage properties. Check RoTK0_usage field description", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_AND_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA" + }, + { + "name": "IMGKEY_FWUPD_KEY", + "value": 4, + "description": "Usable as image key and FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "Root of Trust Key Hash 0", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "Root of Trust Key Hash 1", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "Root of Trust Key Hash 2", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "Root of Trust Key Hash 3", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "Root of Trust Key Hash 4", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "Root of Trust Key Hash 5", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "Root of Trust Key Hash 6", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "Root of Trust Key Hash 7", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "ROTKH8", + "description": "Root of Trust Key Hash 8", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "ROTKH9", + "description": "Root of Trust Key Hash 9", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "ROTKH10", + "description": "Root of Trust Key Hash 10", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "ROTKH11", + "description": "Root of Trust Key Hash 11", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "FLEXSPI_BOOT_CFG", + "description": "FlexSPI boot cfg" + }, + "registers": [ + { + "id": "field080", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "offset_int": "0x0080", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field080-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field080-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIX_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field080-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI ADDR 3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER 1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER 3V3" + }, + { + "name": "FLEXSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FLEXSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field080-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command" + }, + { + "width": 3, + "id": "field080-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Q/O-SPI flash interface frequency", + "values": [ + { + "name": "MHZ_50", + "value": 0, + "description": "50Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60Mhz" + }, + { + "name": "MHZ_80", + "value": 2, + "description": "80Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100Mhz" + }, + { + "name": "MHZ_120", + "value": 4, + "description": "120Mhz" + }, + { + "name": "MHZ_133", + "value": 5, + "description": "133Mhz" + }, + { + "name": "MHZ_166", + "value": 6, + "description": "166Mhz" + }, + { + "name": "MHZ_200", + "value": 7, + "description": "200Mhz" + } + ] + }, + { + "width": 1, + "id": "field080-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use QSPI_RESET_PIN to reset the flash device", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "ENABLE_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "field080-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "GPIO port number to use for O/QSPI reset function" + }, + { + "width": 5, + "id": "field080-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "GPIO pin number to use for O/QSPI reset function" + }, + { + "width": 2, + "id": "field080-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "Wait time before access to Serial Flash", + "values": [ + { + "name": "WAIT_500_MICROSECS", + "value": 0, + "description": "Wait for 500 micro seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 1, + "description": "Wait for 1 mili seconds" + }, + { + "name": "WAIT_3_MILISECS", + "value": 2, + "description": "Wait for 3 mili seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 3, + "description": "Wait for 10 mili seconds" + } + ] + }, + { + "width": 4, + "id": "field080-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100_MICROSECS", + "value": 1, + "description": "Waits additional 100 micro-seconds" + }, + { + "name": "WAIT_500_MICROSECS", + "value": 2, + "description": "Waits additional 500 micro-seconds" + }, + { + "name": "WAIT_1_MILISECS", + "value": 3, + "description": "Waits additional 1 mili-seconds" + }, + { + "name": "WAIT_10_MILISECS", + "value": 4, + "description": "Waits additional 10 mili-seconds" + }, + { + "name": "WAIT_20_MILISECS", + "value": 5, + "description": "Waits additional 20 mili-seconds" + }, + { + "name": "WAIT_40_MILISECS", + "value": 6, + "description": "Waits additional 40 mili-seconds" + }, + { + "name": "WAIT_60_MILISECS", + "value": 7, + "description": "Waits additional 60 mili-seconds" + }, + { + "name": "WAIT_80_MILISECS", + "value": 8, + "description": "Waits additional 80 mili-seconds" + }, + { + "name": "WAIT_100_MILISECS", + "value": 9, + "description": "Waits additional 100 mili-seconds" + }, + { + "name": "WAIT_120_MILISECS", + "value": 10, + "description": "Waits additional 120 mili-seconds" + }, + { + "name": "WAIT_140_MILISECS", + "value": 11, + "description": "Waits additional 140 mili-seconds" + }, + { + "name": "WAIT_160_MILISECS", + "value": 12, + "description": "Waits additional 160 mili-seconds" + }, + { + "name": "WAIT_180_MILISECS", + "value": 13, + "description": "Waits additional 180 mili-seconds" + }, + { + "name": "WAIT_200_MILISECS", + "value": 14, + "description": "Waits additional 200 mili-seconds" + }, + { + "name": "WAIT_220_MILISECS", + "value": 15, + "description": "Waits additional220 mili-seconds" + } + ] + }, + { + "width": 1, + "id": "field080-bit29", + "name": "PIN_SLEW_RATE", + "description": "Enable faster slew rate. When this bit is set ROM will configure FlexSPI pin with faster slew rate instead of standard slew rate", + "values": [ + { + "name": "STANDARD", + "value": 0, + "description": "Standard slew rate" + }, + { + "name": "FASTER", + "value": 1, + "description": "Faster slew rate" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field084", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "offset_int": "0x0084", + "default_value_int": "0", + "bitfields": [ + { + "width": 7, + "id": "field084-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS)" + }, + { + "width": 10, + "id": "field084-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "Any offset in memory mapped Q/Octal-SPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FlLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. If this field is left blank boot ROM assumes that application intends to not use redundant image boot feature. The physical flash offset is computed as below: physical offset = FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field084-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped QSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. SIZE_OFFSET \"Size of the remapped area (aka second half) is same as first half. It is determined by FLEXSPI_IMAGE_OFFSET Field. Remap size = FLEXSPI_IMAGE_OFFSET", + "values": [ + { + "name": "SIZE", + "value": 0, + "description": "SIZE" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "SIZE_1MB Size of remapped area is 1MByte" + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "SIZE_2MB Size of remapped area is 2MByte" + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "SIZE_3MB Size of remapped area is 3MByte" + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "SIZE_4MB Size of remapped area is 4MByte" + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "SIZE_5MB Size of remapped area is 5MByte" + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "SIZE_6MB Size of remapped area is 6MByte" + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "SIZE_7MB Size of remapped area is 7MByte" + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "SIZE_8MB Size of remapped area is 8MByte" + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "SIZE_9MB Size of remapped area is 9MByte" + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "SIZE_10MB Size of remapped area is 10MByte" + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "SIZE_11MB Size of remapped area is 11MByte" + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "SIZE_12MB Size of remapped area is 12MByte" + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "SIZE_256KB Size of remapped area is 256KByte" + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "SIZE_512KB Size of remapped area is 512KByte" + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "SIZE_768KB Size of remapped area is 768KByte" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00088-0008C", + "description": "Reserved 00088-0008C" + }, + "registers": [ + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED fields" + }, + "registers": [ + { + "id": "field090", + "name": "IPED0_START", + "description": "IPED region 0 Start", + "offset_int": "0x0090", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field090-bits0-1", + "name": "ENABLE_REG0", + "description": "Enable IPED region 0 settings during boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled & locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled & locked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field090-bits8-31", + "name": "IPED_REG0_START_ADDR", + "description": "Upper 24-bits of IPED region 0 decryption start address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field094", + "name": "IPED0_END", + "description": "IPED region 0 End", + "offset_int": "0x0094", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field094-bits8-31", + "name": "IPED_REG0_END_ADDR", + "description": "Upper 24-bits of IPED region 0 decryption end address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field098", + "name": "IPED1_START", + "description": "IPED region 1 Start", + "offset_int": "0x0098", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field098-bits0-1", + "name": "ENABLE_REG1", + "description": "Enable IPED region 1 settings during boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled & locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled & locked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field098-bits8-31", + "name": "IPED_REG1_START_ADDR", + "description": "Upper 24-bits of IPED region 1 decryption start address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field09C", + "name": "IPED1_END", + "description": "IPED region 1 End", + "offset_int": "0x009C", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field09C-bits8-31", + "name": "IPED_REG1_END_ADDR", + "description": "Upper 24-bits of IPED region 1 decryption end address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field0A0", + "name": "IPED2_START", + "description": "IPED region 2 Start", + "offset_int": "0x00A0", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0A0-bits0-1", + "name": "ENABLE_REG2", + "description": "Enable IPED region 2 settings during boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled & locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled & locked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field0A0-bits8-31", + "name": "IPED_REG2_START_ADDR", + "description": "Upper 24-bits of IPED region 2 decryption start address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field0A4", + "name": "IPED2_END", + "description": "IPED region 2 End", + "offset_int": "0x00A4", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field0A4-bits8-31", + "name": "IPED_REG2_END_ADDR", + "description": "Upper 24-bits of IPED region 2 decryption end address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field0A8", + "name": "IPED3_START", + "description": "IPED region 3 Start", + "offset_int": "0x00A8", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0A8-bits0-1", + "name": "ENABLE_REG3", + "description": "Enable IPED region 3 settings during boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLED_AND_LOCKED_0", + "value": 2, + "description": "Region is enabled & locked" + }, + { + "name": "ENABLED_AND_LOCKED_1", + "value": 3, + "description": "Region is enabled & locked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field0A8-bits8-31", + "name": "IPED_REG3_START_ADDR", + "description": "Upper 24-bits of IPED region 3 decryption start address for FlexSPI boot. Lower address bits are always 0" + } + ] + }, + { + "id": "field0AC", + "name": "IPED3_END", + "description": "IPED region 3 End", + "offset_int": "0x00AC", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 24, + "id": "field0AC-bits8-31", + "name": "IPED_REG3_END_ADDR", + "description": "Upper 24-bits of IPED region 3 decryption end address for FlexSPI boot. Lower address bits are always 0" + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port pins high", + "offset_int": "0x00B0", + "default_value_int": "0" + }, + { + "id": "field0B4", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port pins low", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port pins high", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "field0BC", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port pins low", + "offset_int": "0x00BC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000C0-000FC", + "description": "Reserved 000C0-000FC" + }, + "registers": [ + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "Customer_Defined0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0" + }, + { + "id": "field104", + "name": "Customer_Defined1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0" + }, + { + "id": "field108", + "name": "Customer_Defined2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0" + }, + { + "id": "field10C", + "name": "Customer_Defined3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0" + }, + { + "id": "field110", + "name": "Customer_Defined4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0" + }, + { + "id": "field114", + "name": "Customer_Defined5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0" + }, + { + "id": "field118", + "name": "Customer_Defined6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0" + }, + { + "id": "field11C", + "name": "Customer_Defined7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0" + }, + { + "id": "field120", + "name": "Customer_Defined8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0" + }, + { + "id": "field124", + "name": "Customer_Defined9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0" + }, + { + "id": "field128", + "name": "Customer_Defined10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0" + }, + { + "id": "field12C", + "name": "Customer_Defined11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0" + }, + { + "id": "field130", + "name": "Customer_Defined12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0" + }, + { + "id": "field134", + "name": "Customer_Defined13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0" + }, + { + "id": "field138", + "name": "Customer_Defined14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0" + }, + { + "id": "field13C", + "name": "Customer_Defined15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0" + }, + { + "id": "field140", + "name": "Customer_Defined16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0" + }, + { + "id": "field144", + "name": "Customer_Defined17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0" + }, + { + "id": "field148", + "name": "Customer_Defined18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0" + }, + { + "id": "field14C", + "name": "Customer_Defined19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0" + }, + { + "id": "field150", + "name": "Customer_Defined20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0" + }, + { + "id": "field154", + "name": "Customer_Defined21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0" + }, + { + "id": "field158", + "name": "Customer_Defined22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0" + }, + { + "id": "field15C", + "name": "Customer_Defined23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0" + }, + { + "id": "field160", + "name": "Customer_Defined24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0" + }, + { + "id": "field164", + "name": "Customer_Defined25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0" + }, + { + "id": "field168", + "name": "Customer_Defined26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0" + }, + { + "id": "field16C", + "name": "Customer_Defined27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0" + }, + { + "id": "field170", + "name": "Customer_Defined28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0" + }, + { + "id": "field174", + "name": "Customer_Defined29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0" + }, + { + "id": "field178", + "name": "Customer_Defined30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0" + }, + { + "id": "field17C", + "name": "Customer_Defined31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0" + }, + { + "id": "field180", + "name": "Customer_Defined32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0" + }, + { + "id": "field184", + "name": "Customer_Defined33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0" + }, + { + "id": "field188", + "name": "Customer_Defined34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0" + }, + { + "id": "field18C", + "name": "Customer_Defined35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0" + }, + { + "id": "field190", + "name": "Customer_Defined36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0" + }, + { + "id": "field194", + "name": "Customer_Defined37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0" + }, + { + "id": "field198", + "name": "Customer_Defined38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0" + }, + { + "id": "field19C", + "name": "Customer_Defined39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0" + }, + { + "id": "field1A0", + "name": "Customer_Defined40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0" + }, + { + "id": "field1A4", + "name": "Customer_Defined41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0" + }, + { + "id": "field1A8", + "name": "Customer_Defined42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0" + }, + { + "id": "field1AC", + "name": "Customer_Defined43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0" + }, + { + "id": "field1B0", + "name": "Customer_Defined44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0" + }, + { + "id": "field1B4", + "name": "Customer_Defined45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0" + }, + { + "id": "field1B8", + "name": "Customer_Defined46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0" + }, + { + "id": "field1BC", + "name": "Customer_Defined47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0" + }, + { + "id": "field1C0", + "name": "Customer_Defined48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0" + }, + { + "id": "field1C4", + "name": "Customer_Defined49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0" + }, + { + "id": "field1C8", + "name": "Customer_Defined50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0" + }, + { + "id": "field1CC", + "name": "Customer_Defined51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0" + }, + { + "id": "field1D0", + "name": "Customer_Defined52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0" + }, + { + "id": "field1D4", + "name": "Customer_Defined53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0" + }, + { + "id": "field1D8", + "name": "Customer_Defined54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0" + }, + { + "id": "field1DC", + "name": "Customer_Defined55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0" + }, + { + "id": "field1E0", + "name": "Customer_Defined56", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E0", + "default_value_int": "0" + }, + { + "id": "field1E4", + "name": "Customer_Defined57", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E4", + "default_value_int": "0" + }, + { + "id": "field1E8", + "name": "Customer_Defined58", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01E8", + "default_value_int": "0" + }, + { + "id": "field1EC", + "name": "Customer_Defined59", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01EC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CMAC", + "description": "CMAC fields" + }, + "registers": [ + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "cmpa cmac", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMPA CMAC1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMPA CMAC2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMPA CMAC3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfrc_rules.yaml new file mode 100644 index 0000000..c2ab6eb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/pfrc_rules.yaml @@ -0,0 +1,18 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "lpc55s3x_4.1" + desc: By default (blank device), the RoTKx_EN values are set to 0b00. + When secure boot is enabled (SEC_BOOT_EN != 0) there must be at + least one RoTKx_EN which is set to 0b01 or 0b00 (enabled) to allow device to boot + successfully. + msg: Secure boot is enabled. Make sure at least one Root of Trust Key Enable bit is set. + cond: CMPA.SECURE_BOOT_CFG.SEC_BOOT_EN != 0 and CFPA.ROTKH_REVOKE.RoTK3_EN >=2 and CFPA.ROTKH_REVOKE.RoTK2_EN >=2 and CFPA.ROTKH_REVOKE.RoTK1_EN >=2 and CFPA.ROTKH_REVOKE.RoTK0_EN >=2 + + - req_id: "lpc55s3x_5.1" + desc: Inverse value (upper 16 bits) of VENDOR_USAGE must be always + valid. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.VENDOR_USAGE != 0 and (~(CFPA.VENDOR_USAGE>>int(16)) & 0xFFFF) != (CFPA.VENDOR_USAGE & 0xFFFF) diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a0.json new file mode 100644 index 0000000..a1fd496 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a0.json @@ -0,0 +1,1013 @@ +{ + "cpu": "lpc55s36", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Control Register (mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Control Register (sau_ctrl)", + "description": "TrustZone register - SAU Control Register (sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAMX Memory Rule Register (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "QSPI Slave Rule Register (qspi_slave_rule)", + "description": "TrustZone register - QSPI Slave Rule Register (qspi_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "QSPI Memory Rule [0][0] Register (qspi_mem_rule00)", + "description": "TrustZone register - QSPI Memory Rule [0][0] Register (qspi_mem_rule00)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "QSPI Memory Rule [0][1] Register (qspi_mem_rule01)", + "description": "TrustZone register - QSPI Memory Rule [0][1] Register (qspi_mem_rule01)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "QSPI Memory Rule [0][2] Register (qspi_mem_rule02)", + "description": "TrustZone register - QSPI Memory Rule [0][2] Register (qspi_mem_rule02)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "QSPI Memory Rule [0][3] Register (qspi_mem_rule03)", + "description": "TrustZone register - QSPI Memory Rule [0][3] Register (qspi_mem_rule03)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "QSPI Memory Rule [1][0] Register (qspi_mem_rule10)", + "description": "TrustZone register - QSPI Memory Rule [1][0] Register (qspi_mem_rule10)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "QSPI Memory Rule [2][0] Register (qspi_mem_rule20)", + "description": "TrustZone register - QSPI Memory Rule [2][0] Register (qspi_mem_rule20)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "QSPI Memory Rule [3][0] Register (qspi_mem_rule30)", + "description": "TrustZone register - QSPI Memory Rule [3][0] Register (qspi_mem_rule30)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "QSPI Memory Rule [4][0] Register (qspi_mem_rule40)", + "description": "TrustZone register - QSPI Memory Rule [4][0] Register (qspi_mem_rule40)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAM0 Memory Rule Register (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register (ram0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAM1 Memory Rule Register (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM2 Memory Rule Register (ram2_mem_rule)", + "description": "TrustZone register - RAM2 Memory Rule Register (ram2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM3 Memory Rule Register (ram3_mem_rule)", + "description": "TrustZone register - RAM3 Memory Rule Register (ram3_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM4 Memory Rule Register (ram4_mem_rule)", + "description": "TrustZone register - RAM4 Memory Rule Register (ram4_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 0 (apb_bridge0_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 0 (apb_bridge0_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 1 (apb_bridge0_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 1 (apb_bridge0_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 2 (apb_bridge0_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 2 (apb_bridge0_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 3 (apb_bridge0_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 3 (apb_bridge0_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 0 (apb_bridge1_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 0 (apb_bridge1_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 1 (apb_bridge1_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 1 (apb_bridge1_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 2 (apb_bridge1_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 2 (apb_bridge1_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 3 (apb_bridge1_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 3 (apb_bridge1_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 0 (apb_bridge2_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 0 (apb_bridge2_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 1 (apb_bridge2_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 1 (apb_bridge2_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 2 (apb_bridge2_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 2 (apb_bridge2_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 3 (apb_bridge2_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 3 (apb_bridge2_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "AHB0 Peripherals 0 Slave Rule Register 0 (ahb0_0_slave_rule)", + "description": "TrustZone register - AHB0 Peripherals 0 Slave Rule Register 0 (ahb0_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "AHB0 Peripherals 1 Slave Rule Register 0 (ahb0_1_slave_rule)", + "description": "TrustZone register - AHB0 Peripherals 1 Slave Rule Register 0 (ahb0_1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "AHB1 Peripherals 0 Slave Rule Register 0 (ahb1_0_slave_rule)", + "description": "TrustZone register - AHB1 Peripherals 0 Slave Rule Register 0 (ahb1_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "AHB2 Peripherals 0 Slave Rule Register 0 (ahb2_0_slave_rule)", + "description": "TrustZone register - AHB2 Peripherals 0 Slave Rule Register 0 (ahb2_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "AHB2 Peripherals 0 Memory Rule Register 0 (ahb2_0_mem_rule)", + "description": "TrustZone register - AHB2 Peripherals 0 Memory Rule Register 0 (ahb2_0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "AHB3 Peripherals 0 Slave Rule Register 0 (ahb3_0_slave_rule)", + "description": "TrustZone register - AHB3 Peripherals 0 Slave Rule Register 0 (ahb3_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "AHB4 Peripherals 0 Slave Rule Register 0 (ahb4_0_slave_rule)", + "description": "TrustZone register - AHB4 Peripherals 0 Slave Rule Register 0 (ahb4_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0x7f" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaa" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x8aaa" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x8aaa" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a1.json new file mode 100644 index 0000000..ff4d71b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s36/tz_a1.json @@ -0,0 +1,1125 @@ +{ + "cpu": "lpc55s36", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "description": "TrustZone register - Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Control Register (mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Control Register (sau_ctrl)", + "description": "TrustZone register - SAU Control Register (sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAMX Memory Rule Register (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "QSPI Slave Rule Register (qspi_slave_rule)", + "description": "TrustZone register - QSPI Slave Rule Register (qspi_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "QSPI Memory Rule [0][0] Register (qspi_mem_rule00)", + "description": "TrustZone register - QSPI Memory Rule [0][0] Register (qspi_mem_rule00)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "QSPI Memory Rule [0][1] Register (qspi_mem_rule01)", + "description": "TrustZone register - QSPI Memory Rule [0][1] Register (qspi_mem_rule01)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "QSPI Memory Rule [0][2] Register (qspi_mem_rule02)", + "description": "TrustZone register - QSPI Memory Rule [0][2] Register (qspi_mem_rule02)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "QSPI Memory Rule [0][3] Register (qspi_mem_rule03)", + "description": "TrustZone register - QSPI Memory Rule [0][3] Register (qspi_mem_rule03)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "QSPI Memory Rule [1][0] Register (qspi_mem_rule10)", + "description": "TrustZone register - QSPI Memory Rule [1][0] Register (qspi_mem_rule10)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "QSPI Memory Rule [2][0] Register (qspi_mem_rule20)", + "description": "TrustZone register - QSPI Memory Rule [2][0] Register (qspi_mem_rule20)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "QSPI Memory Rule [3][0] Register (qspi_mem_rule30)", + "description": "TrustZone register - QSPI Memory Rule [3][0] Register (qspi_mem_rule30)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "QSPI Memory Rule [4][0] Register (qspi_mem_rule40)", + "description": "TrustZone register - QSPI Memory Rule [4][0] Register (qspi_mem_rule40)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAM0 Memory Rule Register (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register (ram0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM1 Memory Rule Register (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM2 Memory Rule Register (ram2_mem_rule)", + "description": "TrustZone register - RAM2 Memory Rule Register (ram2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM3 Memory Rule Register (ram3_mem_rule)", + "description": "TrustZone register - RAM3 Memory Rule Register (ram3_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAM4 Memory Rule Register (ram4_mem_rule)", + "description": "TrustZone register - RAM4 Memory Rule Register (ram4_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 0 (apb_bridge0_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 0 (apb_bridge0_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 1 (apb_bridge0_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 1 (apb_bridge0_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 2 (apb_bridge0_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 2 (apb_bridge0_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "APB Bridge 0 Memory Control Register 3 (apb_bridge0_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 0 Memory Control Register 3 (apb_bridge0_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 0 (apb_bridge1_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 0 (apb_bridge1_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 1 (apb_bridge1_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 1 (apb_bridge1_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 2 (apb_bridge1_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 2 (apb_bridge1_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "APB Bridge 1 Memory Control Register 3 (apb_bridge1_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 1 Memory Control Register 3 (apb_bridge1_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 0 (apb_bridge2_mem_ctrl0)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 0 (apb_bridge2_mem_ctrl0)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 1 (apb_bridge2_mem_ctrl1)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 1 (apb_bridge2_mem_ctrl1)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 2 (apb_bridge2_mem_ctrl2)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 2 (apb_bridge2_mem_ctrl2)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "APB Bridge 2 Memory Control Register 3 (apb_bridge2_mem_ctrl3)", + "description": "TrustZone register - APB Bridge 2 Memory Control Register 3 (apb_bridge2_mem_ctrl3)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "AHB0 Peripherals 0 Slave Rule Register 0 (ahb0_0_slave_rule)", + "description": "TrustZone register - AHB0 Peripherals 0 Slave Rule Register 0 (ahb0_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "AHB0 Peripherals 1 Slave Rule Register 0 (ahb0_1_slave_rule)", + "description": "TrustZone register - AHB0 Peripherals 1 Slave Rule Register 0 (ahb0_1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "AHB1 Peripherals 0 Slave Rule Register 0 (ahb1_0_slave_rule)", + "description": "TrustZone register - AHB1 Peripherals 0 Slave Rule Register 0 (ahb1_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "AHB2 Peripherals 0 Slave Rule Register 0 (ahb2_0_slave_rule)", + "description": "TrustZone register - AHB2 Peripherals 0 Slave Rule Register 0 (ahb2_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "AHB2 Peripherals 0 Memory Rule Register 0 (ahb2_0_mem_rule)", + "description": "TrustZone register - AHB2 Peripherals 0 Memory Rule Register 0 (ahb2_0_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "AHB3 Peripherals 0 Slave Rule Register 0 (ahb3_0_slave_rule)", + "description": "TrustZone register - AHB3 Peripherals 0 Slave Rule Register 0 (ahb3_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "AHB4 Peripherals 0 Slave Rule Register 0 (ahb4_0_slave_rule)", + "description": "TrustZone register - AHB4 Peripherals 0 Slave Rule Register 0 (ahb4_0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0x7f" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaa" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x8aaa" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x8aaa" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "ITRC IRQ Trigger Source Selector Register 0 (itrc_irq_out0_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger Source Selector Register 0 (itrc_irq_out0_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "ITRC IRQ Trigger Source Selector Register 1 (itrc_irq_out0_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger Source Selector Register 1 (itrc_irq_out0_sel1)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger Source Selector Register 0 (itrc_css_reset_out1_sel0)", + "description": "TrustZone register - ITRC CSS_RESET Trigger Source Selector Register 0 (itrc_css_reset_out1_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger Source Selector Register 1 (itrc_css_reset_out1_sel1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger Source Selector Register 1 (itrc_css_reset_out1_sel1)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger Source Selector Register 0 (itrc_puf_zeroize_out2_sel0)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger Source Selector Register 0 (itrc_puf_zeroize_out2_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger Source Selector Register 1 (itrc_puf_zeroize_out2_sel1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger Source Selector Register 1 (itrc_puf_zeroize_out2_sel1)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger Source Selector Register 0 (itrc_ram_zeroize_out3_sel0)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger Source Selector Register 0 (itrc_ram_zeroize_out3_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger Source Selector Register 1 (itrc_ram_zeroize_out3_sel1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger Source Selector Register 1 (itrc_ram_zeroize_out3_sel1)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger Source Selector Register 0 (itrc_chip_reset_out4_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger Source Selector Register 0 (itrc_chip_reset_out4_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger Source Selector Register 1 (itrc_chip_reset_out4_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger Source Selector Register 1 (itrc_chip_reset_out4_sel1)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger Source Selector Register 0 (itrc_itr_out_out5_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger Source Selector Register 0 (itrc_itr_out_out5_sel0)", + "default_value_int": "0xa02aaaaa" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger Source Selector Register 1 (itrc_itr_out_out5_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger Source Selector Register 1 (itrc_itr_out_out5_sel1)", + "default_value_int": "0xa02aaaaa" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s66/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s66/database.yaml new file mode 100644 index 0000000..7db7733 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s66/database.yaml @@ -0,0 +1,30 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: lpc55s69 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x40000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x40000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x18000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/database.yaml new file mode 100644 index 0000000..ee56bb0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/database.yaml @@ -0,0 +1,196 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: + features: + tz: + reg_spec: tz_a0.json + a1: {} +latest: a1 + +# General MCU information +info: + purpose: LPC5500 Series + spsdk_predecessor_name: lpc55s6x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x40000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x40000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x18000" + external: false + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + usb-ram: + start_int: "0x40100000" + size_int: "0x4000" + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x9_DE00 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x9_E400 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field050 + - field054 + - field058 + - field05C + - field060 + - field064 + - field068 + - field06C + computed_fields: + field010: # DCFG_CC_SOCU_PIN + field010-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field014: # DCFG_CC_SOCU_DFLT + field014-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + rules: + - ../../common/pfrc_rules.yaml + - pfrc_rules.yaml + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== TrustZone section ======== + tz: + reg_spec: tz_a1.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [3] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cfpa.json new file mode 100644 index 0000000..e67fa10 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cfpa.json @@ -0,0 +1,1738 @@ +{ + "cpu": "lpc55s69", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Header", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "Version", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit5", + "name": "CPU1_DBGEN", + "description": "CPU1 (Micro cortex M33) invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit9", + "name": "CPU1_NIDEN", + "description": "CPU1 (Micro cortex M33) non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 5 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit5", + "name": "CPU1_DBGEN", + "description": "CPU1 (Micro cortex M33) invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit9", + "name": "CPU1_NIDEN", + "description": "CPU1 (Micro cortex M33) non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 0", + "description": "PRINCE region 0" + }, + "registers": [ + { + "id": "field030", + "name": "PRINCE_REGION0_IV_CODE0", + "description": "Field.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "PRINCE_REGION0_IV_CODE1", + "description": "Field.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field034-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field034-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field034-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field038", + "name": "PRINCE_REGION0_IV_BODY0", + "description": "Field.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "PRINCE_REGION0_IV_BODY1", + "description": "Field.", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "PRINCE_REGION0_IV_BODY2", + "description": "Field.", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "PRINCE_REGION0_IV_BODY3", + "description": "Field.", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "PRINCE_REGION0_IV_BODY4", + "description": "Field.", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "PRINCE_REGION0_IV_BODY5", + "description": "Field.", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "PRINCE_REGION0_IV_BODY6", + "description": "Field.", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "PRINCE_REGION0_IV_BODY7", + "description": "Field.", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "PRINCE_REGION0_IV_BODY8", + "description": "Field.", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "PRINCE_REGION0_IV_BODY9", + "description": "Field.", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "PRINCE_REGION0_IV_BODY10", + "description": "Field.", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "PRINCE_REGION0_IV_BODY11", + "description": "Field.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "PRINCE region 1", + "description": "PRINCE region 1" + }, + "registers": [ + { + "id": "field068", + "name": "PRINCE_REGION1_IV_CODE0", + "description": "Field.", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "PRINCE_REGION1_IV_CODE1", + "description": "Field.", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field06C-bits0-1", + "name": "TYPE", + "description": "Type." + }, + { + "width": 6 + }, + { + "width": 4, + "id": "field06C-bits8-11", + "name": "INDEX", + "description": "Index." + }, + { + "width": 12 + }, + { + "width": 6, + "id": "field06C-bits24-29", + "name": "SIZE", + "description": "Size." + }, + { + "width": 2 + } + ] + }, + { + "id": "field070", + "name": "PRINCE_REGION1_IV_BODY0", + "description": "Field.", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "PRINCE_REGION1_IV_BODY1", + "description": "Field.", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "PRINCE_REGION1_IV_BODY2", + "description": "Field.", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": 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"CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cmpa.json new file mode 100644 index 0000000..1bfaabf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfr_cmpa.json @@ -0,0 +1,2132 @@ +{ + "cpu": "lpc55s69", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "USB_HID_ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_96MHZ", + "value": 1, + "description": "96MHz FRO" + }, + { + "name": "FRO_48MHZ", + "value": 2, + "description": "48MHz FRO" + } + ] + }, + { + "width": 2, + "id": "field000-bits9-10", + "name": "USB_SPEED", + "description": "Defines which USB module is used for ISP:", + "values": [ + { + "name": "USB_SPEED_0", + "value": 0, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + }, + { + "name": "USB_FS", + "value": 1, + "description": "USB FS module used for ISP" + }, + { + "name": "USB_HS", + "value": 2, + "description": "USB HS module used for ISP" + }, + { + "name": "USB_SPEED_1", + "value": 3, + "description": "Defined by NMPA.USBCFG.USB_SPEED" + } + ] + }, + { + "width": 13 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and pin number to use for indicating failure reason. The toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "USB_ID", + "description": "USB Identifiers", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field00C", + "name": "SDIO_CFG", + "description": "SDIO Configuration", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit5", + "name": "CPU1_DBGEN", + "description": "CPU1 (Micro cortex M33) invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field010-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit9", + "name": "CPU1_NIDEN", + "description": "CPU1 (Micro cortex M33) non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 5 + }, + { + "width": 1, + "id": "field010-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field014", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field014-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit5", + "name": "CPU1_DBGEN", + "description": "CPU1 (Micro cortex M33) invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field014-bit7", + "name": "FA_ME_CMD_EN", + "description": "Fault Analysis/Mass Erase Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field014-bit9", + "name": "CPU1_NIDEN", + "description": "CPU1 (Micro cortex M33) non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field018", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field018-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field01C", + "name": "SECURE_BOOT_CFG", + "description": "Secure boot configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field01C-bits0-1", + "name": "RSA4K", + "description": "Select minimal key length. To enforce usage of RSA4096, setting 0b11 value is recommended to allow RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "RSA2048 or higher can be used for image signing. Only RSA2048 can be used as debug keys." + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + } + ] + }, + { + "width": 2, + "id": "field01C-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field01C-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field01C-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field01C-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits12-13", + "name": "BLOCK_ENROLL", + "description": "Block PUF enrollment", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF enroll operation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2, + "id": "field01C-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE" + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "field020", + "name": "PRINCE_BASE_ADDR", + "description": "Prince Base Address", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4, + "id": "field020-bits0-3", + "name": "ADDR0_PRG", + "description": "Programmable portion of the base address of region 0" + }, + { + "width": 4, + "id": "field020-bits4-7", + "name": "ADDR1_PRG", + "description": "Programmable portion of the base address of region 1" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "ADDR2_PRG", + "description": "Programmable portion of the base address of region 2" + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field020-bits18-19", + "name": "LOCK_REG0", + "description": "Lock PRINCE region0 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field020-bits20-21", + "name": "LOCK_REG1", + "description": "Lock PRINCE region1 settings", + "values": [ + { + "name": "UNLOCK", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCK_0", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCK_1", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCK_2", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field020-bits24-25", + "name": "REG0_ERASE_CHECK_EN", + "description": "For PRINCE region0 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits26-27", + "name": "REG1_ERASE_CHECK_EN", + "description": "For PRINCE region1 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "REG2_ERASE_CHECK_EN", + "description": "For PRINCE region2 enable checking whether all encrypted pages are erased together", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Region is disabled" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Region is enabled" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Region is enabled" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Region is enabled" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "PRINCE_SR_0", + "description": "Region 0, sub-region enable", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field028", + "name": "PRINCE_SR_1", + "description": "Region 1, sub-region enable", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "PRINCE_SR_2", + "description": "Region 2, sub-region enable", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "XTAL_32KHZ_CAPABANK_TRIM", + "description": "Xtal 32kHz capabank trimming.", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field030-bit0", + "name": "TRIM_VALID", + "description": "XTAL 32kHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field030-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field030-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + }, + { + "id": "field034", + "name": "XTAL_16MHZ_CAPABANK_TRIM", + "description": "Xtal 16MHz capabank trimming.", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field034-bit0", + "name": "TRIM_VALID", + "description": "XTAL 16MHz capa bank trimmings", + "values": [ + { + "name": "NOT_TRIM", + "value": 0, + "description": "Capa Bank trimmings not valid. Default trimmings value are used" + }, + { + "name": "VALID", + "value": 1, + "description": "Capa Bank trimmings valid" + } + ] + }, + { + "width": 10, + "id": "field034-bits1-10", + "name": "XTAL_LOAD_CAP_IEC_PF_X100", + "description": "Load capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits11-20", + "name": "PCB_XIN_PARA_CAP_PF_X100", + "description": "PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 10, + "id": "field034-bits21-30", + "name": "PCB_XOUT_PARA_CAP_PF_X100", + "description": "PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600." + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00038-0004C", + "description": "Reserved 00038-0004C" + }, + "registers": [ + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field050", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00070-000FC", + "description": "Reserved 00070-000FC" + }, + "registers": [ + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00090", + "name": "Reserved 0x00090", + "description": "This field is reserved for internal use", + "offset_int": "0x0090", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A0", + "name": "Reserved 0x000A0", + "description": "This field is reserved for internal use", + "offset_int": "0x00A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field100", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfrc_rules.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfrc_rules.yaml new file mode 100644 index 0000000..60198c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/pfrc_rules.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +rules: + - req_id: "lpc55xx_4.1" + desc: + By default (blank device), the RoTKx_EN values are set to 0b00 which means + invalid. When secure boot is enabled (SEC_BOOT_EN != 0) there must be at + least one RoTKx_EN which is set to 0b01 (enabled) to allow device to boot + successfully. + msg: Secure boot is enabled. Make sure at least one Root of Trust Key Enable bit is set. + cond: CMPA.SECURE_BOOT_CFG.SEC_BOOT_EN != 0 and not (CFPA.ROTKH_REVOKE.RoTK3_EN == 1 or CFPA.ROTKH_REVOKE.RoTK2_EN == 1 or CFPA.ROTKH_REVOKE.RoTK1_EN == 1 or CFPA.ROTKH_REVOKE.RoTK0_EN == 1) + + - req_id: "lpc55xx_5.1" + desc: Inverse value (upper 16 bits) of VENDOR_USAGE must be always + valid. + msg: Inverse values are generated automatically based on configuration. + cond: CFPA.VENDOR_USAGE != 0 and (~(CFPA.VENDOR_USAGE>>int(16)) & 0xFFFF) != (CFPA.VENDOR_USAGE & 0xFFFF) diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a0.json new file mode 100644 index 0000000..28cd87f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a0.json @@ -0,0 +1,933 @@ +{ + "cpu": "lpc55s69", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MCM33 Secure vector table address (mcm33_vtor_addr)", + "description": "TrustZone register - MCM33 Secure vector table address (mcm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Control Register.(cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register.(cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Control Register.(cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register.(cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Control Register.(cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register.(cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule0)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 1 (ram0_mem_rule1)", + "description": "TrustZone register - RAM0 Memory Rule Register 1 (ram0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule0)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 1 (ram1_mem_rule1)", + "description": "TrustZone register - RAM1 Memory Rule Register 1 (ram1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "description": "TrustZone register - RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "RAM3 Memory Rule Register 0 (ram3_mem_rule0)", + "description": "TrustZone register - RAM3 Memory Rule Register 0 (ram3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAM3 Memory Rule Register 1 (ram3_mem_rule1)", + "description": "TrustZone register - RAM3 Memory Rule Register 1 (ram3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAM4 Memory Rule Register 0 (ram4_mem_rule0)", + "description": "TrustZone register - RAM4 Memory Rule Register 0 (ram4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "HS USB Slave Rule Register 0 (usb_hs_slave_rule0)", + "description": "TrustZone register - HS USB Slave Rule Register 0 (usb_hs_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "HS USB Memory Rule Register 0 (usb_hs__mem_rule0)", + "description": "TrustZone register - HS USB Memory Rule Register 0 (usb_hs__mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaaa" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "MCM33 Lock Control Register (mcm33_lock_reg)", + "description": "TrustZone register - MCM33 Lock Control Register (mcm33_lock_reg)", + "default_value_int": "0x8000000a" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a1.json new file mode 100644 index 0000000..69aec39 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc55s69/tz_a1.json @@ -0,0 +1,941 @@ +{ + "cpu": "lpc55s69", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MCM33 Secure vector table address (mcm33_vtor_addr)", + "description": "TrustZone register - MCM33 Secure vector table address (mcm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Control Register.(cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register.(cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Control Register.(cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register.(cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Control Register.(cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register.(cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule0)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 1 (ram0_mem_rule1)", + "description": "TrustZone register - RAM0 Memory Rule Register 1 (ram0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule0)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 1 (ram1_mem_rule1)", + "description": "TrustZone register - RAM1 Memory Rule Register 1 (ram1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "description": "TrustZone register - RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "RAM3 Memory Rule Register 0 (ram3_mem_rule0)", + "description": "TrustZone register - RAM3 Memory Rule Register 0 (ram3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAM3 Memory Rule Register 1 (ram3_mem_rule1)", + "description": "TrustZone register - RAM3 Memory Rule Register 1 (ram3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAM4 Memory Rule Register 0 (ram4_mem_rule0)", + "description": "TrustZone register - RAM4 Memory Rule Register 0 (ram4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 0 (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register 1 (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 1 (ahb_periph2_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Memory Rule Register 0 (ahb_periph2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "HS USB Slave Rule Register 0 (usb_hs_slave_rule0)", + "description": "TrustZone register - HS USB Slave Rule Register 0 (usb_hs_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "HS USB Memory Rule Register 0 (usb_hs__mem_rule0)", + "description": "TrustZone register - HS USB Memory Rule Register 0 (usb_hs__mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaaa" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "MCM33 Lock Control Register (mcm33_lock_reg)", + "description": "TrustZone register - MCM33 Lock Control Register (mcm33_lock_reg)", + "default_value_int": "0x8000000a" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc804/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc804/database.yaml new file mode 100644 index 0000000..0b95899 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc804/database.yaml @@ -0,0 +1,35 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC800 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-arm-cortex-m0-plus-/lpc800-32-bit-arm-cortex-m0-plus-based-low-cost-mcu:LPC80X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8000 + external: false + ram0: + start_int: 0x1000_0000 + size_int: 0x1000 + external: false + isp: + rom: + protocol: lpc + interfaces: ["uart"] + +features: + lpcprog: + part_ids: + "8040": LPC804M101JBD64 + "8041": LPC804M101JDH20 + "8042": LPC804M101JDH24 + "8043": LPC804M111JDH24 + "8044": LPC804M101JHI33 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc810/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc810/database.yaml new file mode 100644 index 0000000..dcab271 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc810/database.yaml @@ -0,0 +1,33 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC800 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-arm-cortex-m0-plus-/lpc810-and-lpc830-32-bit-arm-cortex-m0-plus-based-low-cost-mcu:LPC81X_LPC83X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size: 0x1000 + external: false + ram0: + start_int: 0x1000_0000 + size: 0x400 + external: false + isp: + rom: + protocol: lpc + interfaces: ["uart"] + +features: + lpcprog: + part_ids: + "8100": LPC810M021FN8 + buffer_address: 0x1000_0300 + buffer_size: 0x100 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc812/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc812/database.yaml new file mode 100644 index 0000000..0b84767 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc812/database.yaml @@ -0,0 +1,32 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC800 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-arm-cortex-m0-plus-/lpc810-and-lpc830-32-bit-arm-cortex-m0-plus-based-low-cost-mcu:LPC81X_LPC83X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size: 0x4000 + external: false + ram0: + start_int: 0x1000_0000 + size: 0x1000 + external: false + isp: + rom: + protocol: lpc + interfaces: ["uart"] + +features: + lpcprog: + part_ids: + "8122": LPC812M101JDH20 + buffer_size: 0x200 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc845/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc845/database.yaml new file mode 100644 index 0000000..cd6e6f9 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc845/database.yaml @@ -0,0 +1,34 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC800 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-arm-cortex-m0-plus-/lpc840-32-bit-arm-cortex-m0-plus-based-low-cost-mcu:LPC84X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10000 + external: false + ram0: + start_int: 0x1000_0000 + size_int: 0x4000 + external: false + isp: + rom: + protocol: lpc + interfaces: ["uart"] + +features: + lpcprog: + part_ids: + "8451": LPC845M301JBD64 + "8452": LPC845M301JBD48 + "8453": LPC845M301JHI48 + "8454": LPC845M301JHI33 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc865/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc865/database.yaml new file mode 100644 index 0000000..8eb5723 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/lpc865/database.yaml @@ -0,0 +1,33 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: LPC800 Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-arm-cortex-m0-plus-/lpc860-32-bit-arm-cortex-m0-plus-based-low-cost-mcu-with-i3c-interface:LPC86X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10000 + external: false + ram0: + start_int: 0x1000_0000 + size_int: 0x2000 + external: false + isp: + rom: + protocol: lpc + interfaces: ["uart"] + +features: + lpcprog: + part_ids: + "8651": LPC865M201JBD64 + "8652": LPC865M201JHI48 + "8654": LPC865M201JHI33 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81646/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81646/database.yaml new file mode 100644 index 0000000..70f4157 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81646/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81648 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81648/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81648/database.yaml new file mode 100644 index 0000000..d896526 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81648/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81668 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10000 + external: false + ram: + start_int: 0x60000 + size_int: 0x3000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81666/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81666/database.yaml new file mode 100644 index 0000000..1de117d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81666/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81668 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81668/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81668/database.yaml new file mode 100644 index 0000000..1cabeaa --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81668/database.yaml @@ -0,0 +1,8 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81768 + +info: + spsdk_predecessor_name: mc56f816xx diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81746/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81746/database.yaml new file mode 100644 index 0000000..e2aef4d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81746/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81748 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81748/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81748/database.yaml new file mode 100644 index 0000000..8ef00d0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81748/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81768 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10000 + external: false + ram: + start_int: 0x60000 + size_int: 0x3000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81766/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81766/database.yaml new file mode 100644 index 0000000..063317c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81766/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81768 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/bca.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/bca.json new file mode 100644 index 0000000..384ec85 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/bca.json @@ -0,0 +1,260 @@ +{ + "cpu": "mcf56f81xxx", + "groups": [ + { + "group": { + "name": "General regs", + "description": "BCA registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "TAG", + "description": "Tag: Magic number to verify bootloader configuration is valid. Must be set to 'KCFG'", + "offset_int": "0", + "default_value_int": "0x6766636B", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field004", + "name": "CRC_START_ADDRESS", + "description": "Start address for application image CRC check", + "offset_int": "0x004", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field008", + "name": "CRC_BYTE_COUNT", + "description": "Byte count for application image CRC check", + "offset_int": "0x008", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field00C", + "name": "CRC_EXPECTED_VALUE", + "description": "Expected CRC value for application CRC check", + "offset_int": "0x00C", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field010", + "name": "ENABLED_PERIPHERALS", + "description": "Bitfield of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1", + "offset_int": "0x010", + "default_value_int": "3", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "UART_SCI", + "description": "Enable UART/SCI peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable UART/SCI peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable UART/SCI peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "LPI2C", + "description": "Enable LPI2C peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable LPI2C peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable LPI2C peripheral" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field011", + "name": "I2C_SLAVE_ADDRESS", + "description": "If not 0xFF, used as the 7-bit I2C slave address", + "offset_int": "0x011", + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field012", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Timeout in milliseconds for active peripheral detection", + "offset_int": "0x012", + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved014", + "name": "Reserved 0x014", + "description": "This field is reserved for internal use", + "offset_int": "0x014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved018", + "name": "Reserved 0x018", + "description": "This field is reserved for internal use", + "offset_int": "0x018", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved01C", + "name": "Reserved 0x01C", + "description": "This field is reserved for internal use", + "offset_int": "0x01C", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved01D", + "name": "Reserved 0x01D", + "description": "This field is reserved for internal use", + "offset_int": "0x01D", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field01E", + "name": "BOOT_FLAGS", + "description": "One's complement of direct boot flag. 0xFE represents direct boot", + "offset_int": "0x01E", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field01E-bit0", + "name": "DIRECT_BOOT", + "description": "Enable direct boot", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable direct boot" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Disable direct boot - standard boot with ISP" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved01F", + "name": "Reserved 0x01F", + "description": "This field is reserved for internal use", + "offset_int": "0x01F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field020", + "name": "IMAGE_SIZE", + "description": "The information about total size of the image", + "offset_int": "0x020", + "default_value_int": "0", + "reg_width": 32 + }, + { + "id": "field024", + "name": "FIRMWARE_VERSION", + "description": "Firmware version, stored in little endian format. Used for anti-rollback protection. New firmware must have the same or higher FW version", + "offset_int": "0x024", + "default_value_int": "0", + "reg_width": 32 + }, + { + "id": "Reserved028", + "name": "Reserved 0x028", + "description": "This field is reserved for internal use", + "offset_int": "0x028", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved02C", + "name": "Reserved 0x02C", + "description": "This field is reserved for internal use", + "offset_int": "0x02C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved030", + "name": "Reserved 0x030", + "description": "This field is reserved for internal use", + "offset_int": "0x030", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved034", + "name": "Reserved 0x034", + "description": "This field is reserved for internal use", + "offset_int": "0x034", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved038", + "name": "Reserved 0x038", + "description": "This field is reserved for internal use", + "offset_int": "0x038", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved03C", + "name": "Reserved 0x03C", + "description": "This field is reserved for internal use", + "offset_int": "0x03C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/database.yaml new file mode 100644 index 0000000..faf8c92 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/database.yaml @@ -0,0 +1,87 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + b1: {} +latest: b1 + +# General MCU information +info: + purpose: 32-bit DSC Series + spsdk_predecessor_name: mc56f817xx + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/digital-signal-controllers/32-bit-56800ex-ef-core/up-to-100mhz-digital-signal-controllers-with-dsass-and-operational-amplifier:MC56F81xxx + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x20000 + external: false + ram: + start_int: 0x60000 + size_int: 0x5000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "i2c", "spi"] + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x04003000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinBca + - Mbi_MixinFcf + - Mbi_ExportMixinAppBcaFcf + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinFcf + - Mbi_MixinBca + - Mbi_ExportMixinAppBcaFcf + - Mbi_ExportMixinCrcSignBca + images: + xip: + plain: plain_xip + crc: crc_xip + # Fixed image type redefines the image type fetched from IVT + fixed_image_type: 5 + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== BCA section ======== + bca: + reg_spec: bca.json + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + reg_spec_modification: + field000: + reverse: True + config_as_hexstring: True + + # ======== PFR section ======== + pfr: + sub_features: [ifr] + ifr: + address: 0x0 + reg_spec: ifr_ns.json diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/fcf.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/fcf.json new file mode 100644 index 0000000..7b41812 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/fcf.json @@ -0,0 +1,147 @@ +{ + "cpu": "mcf56f81xxx", + "groups": [ + { + "group": { + "name": "General regs", + "description": "FCF registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "BACKDOOR_KEY", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFF", + "reg_width": 64, + "description": "Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access." + }, + { + "id": "field008", + "name": "FPROT", + "description": "Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).", + "offset_int": "0x008", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "FPROT3", + "description": "Program Flash Protection Registers (FPROT3)" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "FPROT2", + "description": "Program Flash Protection Registers (FPROT2)" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "FPROT1", + "description": "Program Flash Protection Registers (FPROT1)" + }, + { + "width": 8, + "id": "field008-bits24-31", + "name": "FPROT0", + "description": "Program Flash Protection Registers (FPROT0)" + } + ] + }, + { + "id": "field00C", + "name": "LIFECYCLE", + "description": "DSA Secure Lifecycle state", + "offset_int": "0x00C", + "default_value_int": "0xFE", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field00C-bits0-7", + "name": "LIFECYCLE_STATE", + "description": "DSA Secure Lifecycle state", + "values": [ + { + "name": "OEM_OPEN_ROP0", + "value": 254, + "description": "Most permissive state - full ISP command set available in all conditions" + }, + { + "name": "OEM_CLOSED_ROP1", + "value": 144, + "description": "Moderate security - partial ISP commands on normal boot, full commands via ROM_API" + }, + { + "name": "OEM_CLOSED_ROP2", + "value": 149, + "description": "Higher security - no ISP commands on normal boot, partial commands via ROM_API or invalid image" + }, + { + "name": "OEM_CLOSED_ROP3", + "value": 155, + "description": "Very high security - no ISP commands except ReceiveSBFile via ROM_API for secure devices only" + }, + { + "name": "OEM_CLOSED_NO_RETURN", + "value": 107, + "description": "Maximum security - no ISP commands available in any condition, device cannot be reprogrammed" + } + ] + } + ] + }, + { + "id": "field00D", + "name": "OPTION_BYTE", + "description": "Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).", + "offset_int": "0x00D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00D-bit-0", + "name": "POWER_MODE", + "description": "Controls which power mode register takes effect", + "values": [ + { + "name": "SIM_PWRMODE", + "value": 1, + "description": "Writing SIM_PWRMODE register takes effect, writing SIM_PWR register doesn't take effect" + }, + { + "name": "SIM_PWR", + "value": 0, + "description": "Writing SIM_PWRMODE register doesn't take effect, writing SIM_PWR register takes effect" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00E", + "name": "Reserved 0x00E", + "description": "This field is reserved for internal use", + "offset_int": "0x00E", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved00F", + "name": "Reserved 0x00F", + "description": "This field is reserved for internal use", + "offset_int": "0x00F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/ifr_ns.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/ifr_ns.json new file mode 100644 index 0000000..b3197c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81768/ifr_ns.json @@ -0,0 +1,121 @@ +{ + "cpu": "MWCT20D2", + "groups": [ + { + "group": { + "name": "Customer IFR data", + "description": "Customer IFR data" + }, + "registers": [ + { + "id": "field000", + "name": "CUSTOMER_DEFINED0", + "description": "Customer defined", + "offset_int": "0x00C0", + "index_int": "0", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field001", + "name": "CUSTOMER_DEFINED1", + "description": "Customer defined", + "offset_int": "0x00C4", + "index_int": "0x0001", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field002", + "name": "CUSTOMER_DEFINED2", + "description": "Customer defined", + "offset_int": "0x00C8", + "index_int": "0x0002", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field003", + "name": "CUSTOMER_DEFINED3", + "description": "Customer defined", + "offset_int": "0x00CC", + "index_int": "0x0003", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field004", + "name": "CUSTOMER_DEFINED4", + "description": "Customer defined", + "offset_int": "0x00D0", + "index_int": "0x0004", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field005", + "name": "CUSTOMER_DEFINED5", + "description": "Customer defined", + "offset_int": "0x00D4", + "index_int": "0x0005", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field006", + "name": "CUSTOMER_DEFINED6", + "description": "Customer defined", + "offset_int": "0x00D8", + "index_int": "0x0006", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field007", + "name": "CUSTOMER_DEFINED7", + "description": "Customer defined", + "offset_int": "0x00DC", + "index_int": "0x0007", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field008", + "name": "CUSTOMER_DEFINED8", + "description": "Customer defined", + "offset_int": "0x00E0", + "index_int": "0x0008", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field009", + "name": "CUSTOMER_DEFINED9", + "description": "Customer defined", + "offset_int": "0x00E4", + "index_int": "0x0009", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field010", + "name": "CUSTOMER_DEFINED10", + "description": "Customer defined", + "offset_int": "0x00E8", + "index_int": "0x000A", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field011", + "name": "CUSTOMER_DEFINED11", + "description": "Customer defined", + "offset_int": "0x00EC", + "index_int": "0x000B", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81866/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81866/database.yaml new file mode 100644 index 0000000..00d6f2a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81866/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81868 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/bca.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/bca.json new file mode 100644 index 0000000..384ec85 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/bca.json @@ -0,0 +1,260 @@ +{ + "cpu": "mcf56f81xxx", + "groups": [ + { + "group": { + "name": "General regs", + "description": "BCA registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "TAG", + "description": "Tag: Magic number to verify bootloader configuration is valid. Must be set to 'KCFG'", + "offset_int": "0", + "default_value_int": "0x6766636B", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field004", + "name": "CRC_START_ADDRESS", + "description": "Start address for application image CRC check", + "offset_int": "0x004", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field008", + "name": "CRC_BYTE_COUNT", + "description": "Byte count for application image CRC check", + "offset_int": "0x008", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field00C", + "name": "CRC_EXPECTED_VALUE", + "description": "Expected CRC value for application CRC check", + "offset_int": "0x00C", + "default_value_int": "0", + "access": "RO", + "reg_width": 32 + }, + { + "id": "field010", + "name": "ENABLED_PERIPHERALS", + "description": "Bitfield of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1", + "offset_int": "0x010", + "default_value_int": "3", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "UART_SCI", + "description": "Enable UART/SCI peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable UART/SCI peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable UART/SCI peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "LPI2C", + "description": "Enable LPI2C peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable LPI2C peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable LPI2C peripheral" + } + ] + }, + { + "width": 6 + } + ] + }, + { + "id": "field011", + "name": "I2C_SLAVE_ADDRESS", + "description": "If not 0xFF, used as the 7-bit I2C slave address", + "offset_int": "0x011", + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field012", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Timeout in milliseconds for active peripheral detection", + "offset_int": "0x012", + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved014", + "name": "Reserved 0x014", + "description": "This field is reserved for internal use", + "offset_int": "0x014", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved018", + "name": "Reserved 0x018", + "description": "This field is reserved for internal use", + "offset_int": "0x018", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved01C", + "name": "Reserved 0x01C", + "description": "This field is reserved for internal use", + "offset_int": "0x01C", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved01D", + "name": "Reserved 0x01D", + "description": "This field is reserved for internal use", + "offset_int": "0x01D", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field01E", + "name": "BOOT_FLAGS", + "description": "One's complement of direct boot flag. 0xFE represents direct boot", + "offset_int": "0x01E", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field01E-bit0", + "name": "DIRECT_BOOT", + "description": "Enable direct boot", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable direct boot" + }, + { + "name": "DISABLE", + "value": 1, + "description": "Disable direct boot - standard boot with ISP" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved01F", + "name": "Reserved 0x01F", + "description": "This field is reserved for internal use", + "offset_int": "0x01F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "field020", + "name": "IMAGE_SIZE", + "description": "The information about total size of the image", + "offset_int": "0x020", + "default_value_int": "0", + "reg_width": 32 + }, + { + "id": "field024", + "name": "FIRMWARE_VERSION", + "description": "Firmware version, stored in little endian format. Used for anti-rollback protection. New firmware must have the same or higher FW version", + "offset_int": "0x024", + "default_value_int": "0", + "reg_width": 32 + }, + { + "id": "Reserved028", + "name": "Reserved 0x028", + "description": "This field is reserved for internal use", + "offset_int": "0x028", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved02C", + "name": "Reserved 0x02C", + "description": "This field is reserved for internal use", + "offset_int": "0x02C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved030", + "name": "Reserved 0x030", + "description": "This field is reserved for internal use", + "offset_int": "0x030", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved034", + "name": "Reserved 0x034", + "description": "This field is reserved for internal use", + "offset_int": "0x034", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved038", + "name": "Reserved 0x038", + "description": "This field is reserved for internal use", + "offset_int": "0x038", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved03C", + "name": "Reserved 0x03C", + "description": "This field is reserved for internal use", + "offset_int": "0x03C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/database.yaml new file mode 100644 index 0000000..0b37165 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/database.yaml @@ -0,0 +1,95 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + b1: {} +latest: b1 + +# General MCU information +info: + purpose: 32-bit DSC Series + spsdk_predecessor_name: mc56f818xx + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/additional-mpu-mcus-architectures/digital-signal-controllers/32-bit-56800ex-ef-core/up-to-100mhz-digital-signal-controllers-with-dsass-and-operational-amplifier:MC56F81xxx + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x20000 + external: false + sram: + start_int: 0x60000 + size_int: 0x5000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "i2c", "spi"] + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x04003000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_certx] + rot_type: "cert_block_x" + + # ======== MBI section ======== + mbi: + mbi_classes: + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinBca + - Mbi_MixinFcf + - Mbi_MixinCertBlockVx + - Mbi_ExportMixinAppBcaFcf + - Mbi_ExportMixinEccSignVx + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinBca + - Mbi_MixinFcf + - Mbi_ExportMixinAppBcaFcf + images: + xip: + signed: signed_xip + plain: plain_xip + # Fixed image type redefines the image type fetched from IVT + fixed_image_type: 4 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSBx] + key_blob_offset: -1 + key_blob_command_position: -1 + + # ======== Secure binary vX section ======== + sbx: {} + + # ======== BCA section ======== + bca: + reg_spec: bca.json + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + reg_spec_modification: + field000: + reverse: True + config_as_hexstring: True + + # ======== PFR section ======== + pfr: + sub_features: [ifr] + ifr: + address: 0x0 + reg_spec: ifr_s.json diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/fcf.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/fcf.json new file mode 100644 index 0000000..7b41812 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/fcf.json @@ -0,0 +1,147 @@ +{ + "cpu": "mcf56f81xxx", + "groups": [ + { + "group": { + "name": "General regs", + "description": "FCF registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "BACKDOOR_KEY", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFF", + "reg_width": 64, + "description": "Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access." + }, + { + "id": "field008", + "name": "FPROT", + "description": "Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).", + "offset_int": "0x008", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "FPROT3", + "description": "Program Flash Protection Registers (FPROT3)" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "FPROT2", + "description": "Program Flash Protection Registers (FPROT2)" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "FPROT1", + "description": "Program Flash Protection Registers (FPROT1)" + }, + { + "width": 8, + "id": "field008-bits24-31", + "name": "FPROT0", + "description": "Program Flash Protection Registers (FPROT0)" + } + ] + }, + { + "id": "field00C", + "name": "LIFECYCLE", + "description": "DSA Secure Lifecycle state", + "offset_int": "0x00C", + "default_value_int": "0xFE", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field00C-bits0-7", + "name": "LIFECYCLE_STATE", + "description": "DSA Secure Lifecycle state", + "values": [ + { + "name": "OEM_OPEN_ROP0", + "value": 254, + "description": "Most permissive state - full ISP command set available in all conditions" + }, + { + "name": "OEM_CLOSED_ROP1", + "value": 144, + "description": "Moderate security - partial ISP commands on normal boot, full commands via ROM_API" + }, + { + "name": "OEM_CLOSED_ROP2", + "value": 149, + "description": "Higher security - no ISP commands on normal boot, partial commands via ROM_API or invalid image" + }, + { + "name": "OEM_CLOSED_ROP3", + "value": 155, + "description": "Very high security - no ISP commands except ReceiveSBFile via ROM_API for secure devices only" + }, + { + "name": "OEM_CLOSED_NO_RETURN", + "value": 107, + "description": "Maximum security - no ISP commands available in any condition, device cannot be reprogrammed" + } + ] + } + ] + }, + { + "id": "field00D", + "name": "OPTION_BYTE", + "description": "Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).", + "offset_int": "0x00D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00D-bit-0", + "name": "POWER_MODE", + "description": "Controls which power mode register takes effect", + "values": [ + { + "name": "SIM_PWRMODE", + "value": 1, + "description": "Writing SIM_PWRMODE register takes effect, writing SIM_PWR register doesn't take effect" + }, + { + "name": "SIM_PWR", + "value": 0, + "description": "Writing SIM_PWRMODE register doesn't take effect, writing SIM_PWR register takes effect" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "Reserved00E", + "name": "Reserved 0x00E", + "description": "This field is reserved for internal use", + "offset_int": "0x00E", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved00F", + "name": "Reserved 0x00F", + "description": "This field is reserved for internal use", + "offset_int": "0x00F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/ifr_s.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/ifr_s.json new file mode 100644 index 0000000..f221865 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mc56f81868/ifr_s.json @@ -0,0 +1,165 @@ +{ + "cpu": "MWCT20D2", + "groups": [ + { + "group": { + "name": "Customer IFR data", + "description": "Customer IFR data" + }, + "registers": [ + { + "id": "field000", + "name": "CUSTOMER_DEFINED0", + "description": "Customer defined", + "offset_int": "0x00C0", + "index_int": "0", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field001", + "name": "CUSTOMER_DEFINED1", + "description": "Customer defined", + "offset_int": "0x00C4", + "index_int": "0x0001", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field002", + "name": "CUSTOMER_DEFINED2", + "description": "Customer defined", + "offset_int": "0x00C8", + "index_int": "0x0002", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field003", + "name": "CUSTOMER_DEFINED3", + "description": "Customer defined", + "offset_int": "0x00CC", + "index_int": "0x0003", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field004", + "name": "CUSTOMER_DEFINED4", + "description": "Customer defined", + "offset_int": "0x00D0", + "index_int": "0x0004", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field005", + "name": "CUSTOMER_DEFINED5", + "description": "Customer defined", + "offset_int": "0x00D4", + "index_int": "0x0005", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field006", + "name": "CUSTOMER_DEFINED6", + "description": "Customer defined", + "offset_int": "0x00D8", + "index_int": "0x0006", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field007", + "name": "CUSTOMER_DEFINED7", + "description": "Customer defined", + "offset_int": "0x00DC", + "index_int": "0x0007", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field008", + "name": "CUSTOMER_DEFINED8", + "description": "Customer defined", + "offset_int": "0x00E0", + "index_int": "0x0008", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field009", + "name": "CUSTOMER_DEFINED9", + "description": "Customer defined", + "offset_int": "0x00E4", + "index_int": "0x0009", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field010", + "name": "CUSTOMER_DEFINED10", + "description": "Customer defined", + "offset_int": "0x00E8", + "index_int": "0x000A", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field011", + "name": "CUSTOMER_DEFINED11", + "description": "Customer defined", + "offset_int": "0x00EC", + "index_int": "0x000B", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + } + ] + }, + { + "group": { + "name": "ISK_CERT_HASH", + "description": "ISK_CERT_HASH" + }, + "registers": [ + { + "id": "field012", + "name": "ISK_CERT_HASH[31:0]", + "description": "ISK_CERT_HASH[31:0]", + "offset_int": "0x00F0", + "index_int": "0x000C", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field013", + "name": "ISK_CERT_HASH[63:32]", + "description": "ISK_CERT_HASH[63:32]", + "offset_int": "0x00F4", + "index_int": "0x000D", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field014", + "name": "ISK_CERT_HASH[95:64]", + "description": "ISK_CERT_HASH[95:64]", + "offset_int": "0x00F8", + "index_int": "0x000E", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field015", + "name": "ISK_CERT_HASH[127:96]", + "description": "ISK_CERT_HASH[127:96]", + "offset_int": "0x00FC", + "index_int": "0x000F", + "individual_write_lock": "implicit", + "default_value_int": "0xFFFFFFFF" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa132/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa132/database.yaml new file mode 100644 index 0000000..6caa26e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa132/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa142 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x4000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa133/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa133/database.yaml new file mode 100644 index 0000000..b949857 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa133/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa142 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x20000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x6000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/database.yaml new file mode 100644 index 0000000..e1ecc1d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/database.yaml @@ -0,0 +1,95 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + spsdk_predecessor_name: mcxa1xx + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x1_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x4000 + external: false + + isp: + rom: + protocol: mboot + interfaces: ["usb", "uart", "spi", "i2c"] + usb: + - vid: 0x1FC9 + pid: 0x0155 + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + size: 0x1000 + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 10: "life-cycle" + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0x100_0000 + size: 256 + reg_spec: pfr_cmpa.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/pfr_cmpa.json new file mode 100644 index 0000000..bbb8fdf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa142/pfr_cmpa.json @@ -0,0 +1,1756 @@ +{ + "cpu": "MCXA142", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0_HID" + } + ] + }, + { + "width": 5 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core Clock", + "values": [ + { + "name": "FRO_48_MHZ", + "value": 0, + "description": "48Mhz FRO @1v0" + }, + { + "name": "FRO_96_MHZ", + "value": 1, + "description": "96MHz FRO @1v1" + } + ] + }, + { + "width": 2, + "id": "field000-bits14-15", + "name": "AGDET_RE_EN", + "description": "AGDET reset must be enabled during boot (must be 00b).", + "values": [ + { + "name": "ENABLED_0b00", + "value": 0, + "description": "Enable AGDET reset" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Don't enable AGDET reset" + }, + { + "name": "DISABLED_0b10", + "value": 2, + "description": "Don't enable AGDET reset" + }, + { + "name": "DISABLED_0b11", + "value": 3, + "description": "Don't enable AGDET reset" + } + ] + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. \nThis field should be written to remap field in flash." + }, + { + "width": 5 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. \nROM toggles the GPIO pin identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. \nNote, use QUICK_SET_/CLR_GPIOx field to set the default level of pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 8 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: \nTimeout value in seconds. \nWhen a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power." + }, + { + "width": 16 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. \nIdentifies the pin to be used as UART_RX pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_INSTANCE", + "description": "Identifies the LPUART instance used for UART ISP mode." + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. \nIdentifies the pin to be used as UART_TX pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. \nIdentifies the pin to be used as I2C_SCL pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_INSTANCE", + "description": "Identifies the LPI2C instance used for I2C ISP mode." + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. \nIdentifies the pin to be used as I2C_SDA pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI SCK ISP pin. \nIdentifies the pin to be used as SPI_SCK pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_INSTANCE", + "description": "Identifies the LPSPI instance used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI MOSI ISP pin. \nIdentifies the pin to be used as SPI_MOSI pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI MISO ISP pin. \nIdentifies the pin to be used as SPI_MISO pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI SSEL ISP pin. \nIdentifies the pin to be used as SPI_SSEL pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. \nFlexComm SPI interfaces supports up to four chip selects." + }, + { + "width": 2 + } + ] + }, + { + "id": "field024", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field024-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USB0_VBUS_DETECT ISP pin. \nIdentifies the pin to be used as USB0_VBUS detect pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 20 + } + ] + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address. \nA 7-bit Address used for selecting our device on shared I2C bus system. \nBy default ROM uses 0x10 as slave address." + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field02C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode.", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins." + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect." + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + } + ] + }, + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Flash access control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector 0-7", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector 8-15", + "offset_int": "0x0044", + "default_value_int": "0x44444444", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00048-0005C", + "description": "Reserved 00048-0005C" + }, + "registers": [ + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field060", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0060", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0064", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0068", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x006C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0070", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0074", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0078", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x007C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00080-0008C", + "description": "Reserved 00080-0008C" + }, + "registers": [ + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field090", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. \nDevice does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. \nThis read out protection is a mechanism that allows user to enable different levels of protection in the system. \nROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. \nAny other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 32, + "id": "field090-bits0-31", + "name": "ROP_STATE", + "description": "ROP_STATE[31:0]", + "values": [ + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state." + }, + { + "name": "ROP_LEVEL1", + "value": 3, + "description": "ROP_STATE = 0x0000_0003. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL2", + "value": 1, + "description": "ROP_STATE = 0x0000_0001. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL3", + "value": 0, + "description": "ROP_STATE = 0x0000_0000. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available." + } + ] + } + ] + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. \nROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. \nAny other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 32, + "id": "field0A0-bits0-31", + "name": "ROP_STATE_DP", + "description": "ROP_STATE_DP[31:0]", + "values": [ + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state." + }, + { + "name": "ROP_LEVEL1", + "value": 3, + "description": "ROP_STATE = 0x0000_0003. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL2", + "value": 1, + "description": "ROP_STATE = 0x0000_0001. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL3", + "value": 0, + "description": "ROP_STATE = 0x0000_0000. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available." + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa143/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa143/database.yaml new file mode 100644 index 0000000..3a87a01 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa143/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa142 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x2_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x8000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa144/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa144/database.yaml new file mode 100644 index 0000000..bc8f204 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa144/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa156 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x4_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_0000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa145/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa145/database.yaml new file mode 100644 index 0000000..334adcb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa145/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa156 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_8000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa146/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa146/database.yaml new file mode 100644 index 0000000..3338f53 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa146/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa156 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x2_0000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa152/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa152/database.yaml new file mode 100644 index 0000000..030df42 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa152/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa142 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x1_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x4000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa153/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa153/database.yaml new file mode 100644 index 0000000..3a87a01 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa153/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa142 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x2_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x8000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa154/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa154/database.yaml new file mode 100644 index 0000000..bc8f204 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa154/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa156 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x4_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_0000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa155/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa155/database.yaml new file mode 100644 index 0000000..334adcb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa155/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa156 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_8000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/database.yaml new file mode 100644 index 0000000..4ffb1b1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/database.yaml @@ -0,0 +1,93 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/MCX-A13X-A14X-A15X + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x2_0000 + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x015e + +features: + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + size: 0x1000 + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0x100_0000 + size: 256 + reg_spec: pfr_cmpa.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/pfr_cmpa.json new file mode 100644 index 0000000..17dfe3d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa156/pfr_cmpa.json @@ -0,0 +1,4200 @@ +{ + "cpu": "MCXA156", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0_HID" + } + ] + }, + { + "width": 5 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core Clock", + "values": [ + { + "name": "FRO_48_MHZ", + "value": 0, + "description": "48Mhz FRO @1v0" + }, + { + "name": "FRO_96_MHZ", + "value": 1, + "description": "96MHz FRO @1v1" + } + ] + }, + { + "width": 2, + "id": "field000-bits14-15", + "name": "AGDET_RE_EN", + "description": "AGDET reset must be enabled during boot (must be 00b).", + "values": [ + { + "name": "ENABLED_0b00", + "value": 0, + "description": "Enable AGDET reset" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Don't enable AGDET reset" + }, + { + "name": "DISABLED_0b10", + "value": 2, + "description": "Don't enable AGDET reset" + }, + { + "name": "DISABLED_0b11", + "value": 3, + "description": "Don't enable AGDET reset" + } + ] + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ], + "default_value_int": "0x59630000" + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. \nThis field should be written to remap field in flash." + }, + { + "width": 5 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2 + }, + { + "width": 16 + } + ], + "default_value_int": "0" + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. \nROM toggles the GPIO pin identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. \nNote, use QUICK_SET_/CLR_GPIOx field to set the default level of pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 8 + } + ], + "default_value_int": "0" + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: \nTimeout value in seconds. \nWhen a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power." + }, + { + "width": 16 + } + ], + "default_value_int": "0" + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. \nIdentifies the pin to be used as UART_RX pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_INSTANCE", + "description": "Identifies the LPUART instance used for UART ISP mode." + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. \nIdentifies the pin to be used as UART_TX pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ], + "default_value_int": "0" + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. \nIdentifies the pin to be used as I2C_SCL pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_INSTANCE", + "description": "Identifies the LPI2C instance used for I2C ISP mode." + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. \nIdentifies the pin to be used as I2C_SDA pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ], + "default_value_int": "0" + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI SCK ISP pin. \nIdentifies the pin to be used as SPI_SCK pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_INSTANCE", + "description": "Identifies the LPSPI instance used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI MOSI ISP pin. \nIdentifies the pin to be used as SPI_MOSI pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ], + "default_value_int": "0" + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI MISO ISP pin. \nIdentifies the pin to be used as SPI_MISO pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI SSEL ISP pin. \nIdentifies the pin to be used as SPI_SSEL pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. \nFlexComm SPI interfaces supports up to four chip selects." + }, + { + "width": 2 + } + ], + "default_value_int": "0" + }, + { + "id": "field024", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0024", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field024-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ], + "default_value_int": "0" + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0028", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USB0_VBUS_DETECT ISP pin. \nIdentifies the pin to be used as USB0_VBUS detect pin. \n[4:0] GPIO Pin number \n[7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 20 + } + ], + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address. \nA 7-bit Address used for selecting our device on shared I2C bus system. \nBy default ROM uses 0x10 as slave address." + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field02C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode.", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins." + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect." + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins." + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins." + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins." + } + ] + } + ], + "default_value_int": "0" + }, + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash access control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector 0-7, ACL_SEC_x 3 bits represents GAC Index configuration", + "offset_int": "0x0040", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field044", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector 8-15", + "offset_int": "0x0044", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field048", + "name": "FLASH_ACL_16_23", + "description": "Access control for flash sector 16-23", + "offset_int": "0x0048", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x04_4000 - 0x04_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x04_C000 - 0x04_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x05_4000 - 0x05_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x05_8000 - 0x05_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x05_C000 - 0x05_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field04C", + "name": "FLASH_ACL_24_31", + "description": "Access control for flash sector 24-31", + "offset_int": "0x004C", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x06_4000 - 0x06_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x06_C000 - 0x06_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x07_4000 - 0x07_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x07_C000 - 0x07_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field050", + "name": "FLASH_ACL_32_39", + "description": "Access control for flash sector 32-39", + "offset_int": "0x0050", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field050-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x08_4000 - 0x08_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector (offset range 0x08_C000 - 0x08_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x09_4000 - 0x09_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x09_8000 - 0x09_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x09_C000 - 0x09_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field054", + "name": "FLASH_ACL_40_47", + "description": "Access control for flash sector 40-47", + "offset_int": "0x0054", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x0A_4000 - 0x0A_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector (offset range 0x0A_C000 - 0x0A_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x0B_4000 - 0x0B_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x0B_C000 - 0x0B_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field058", + "name": "FLASH_ACL_48_55", + "description": "Access control for flash sector 48-55", + "offset_int": "0x0058", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field058-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x0C_4000 - 0x0C_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector (offset range 0x0C_C000 - 0x0C_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x0D_4000 - 0x0D_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x0D_8000 - 0x0D_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x0D_C000 - 0x0D_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + }, + { + "id": "field05C", + "name": "FLASH_ACL_56_63", + "description": "Access control for flash sector 55-63", + "offset_int": "0x005C", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field05C-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x0E_4000 - 0x0E_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector (offset range 0x0E_C000 - 0x0E_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_3FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x0F_4000 - 0x0F_7FFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_BFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x0F_C000 - 0x0F_FFFF).", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ], + "default_value_int": "0x44444444" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field060", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0060", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0064", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0068", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x006C", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0070", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0074", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0078", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x007C", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field080", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port [31:0] pins high after reset. \nEach bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0080", + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port [31:0] pins low after reset. \nEach bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. \nThis feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0084", + "individual_write_lock": "none", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00088-0008C", + "description": "Reserved 00088-0008C" + }, + "registers": [ + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field090", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. \nDevice does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. \nThis read out protection is a mechanism that allows user to enable different levels of protection in the system. \nROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. \nAny other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x0090", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 32, + "id": "field090-bits0-31", + "name": "ROP_STATE", + "description": "ROP_STATE[31:0]", + "values": [ + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state." + }, + { + "name": "ROP_LEVEL1", + "value": 4005168323, + "description": "ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL2", + "value": 1228508555, + "description": "ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL3", + "value": 2964043523, + "description": "ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available." + } + ] + } + ], + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved00098", + "name": "Reserved 0x00098", + "description": "This field is reserved for internal use", + "offset_int": "0x0098", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "individual_write_lock": "none", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. \nROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. \nAny other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00A0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 32, + "id": "field0A0-bits0-31", + "name": "ROP_STATE_DP", + "description": "ROP_STATE_DP[31:0]", + "values": [ + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state." + }, + { + "name": "ROP_LEVEL1", + "value": 4005168323, + "description": "ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL2", + "value": 1228508555, + "description": "ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available." + }, + { + "name": "ROP_LEVEL3", + "value": 2964043523, + "description": "ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available." + } + ] + } + ], + "default_value_int": "0xFFFFFFFF" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa173/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa173/database.yaml new file mode 100644 index 0000000..93804a0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa173/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa343 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x2_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x8000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa174/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa174/database.yaml new file mode 100644 index 0000000..73396a7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa174/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa343 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x4_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_0000 + external: false +features: + pfr: + cmpa: # CMPA description + address: 0x3_E000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa175/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa175/database.yaml new file mode 100644 index 0000000..e4525f2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa175/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa345 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa176/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa176/database.yaml new file mode 100644 index 0000000..2906dcf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa176/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa346 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa185/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa185/database.yaml new file mode 100644 index 0000000..46926a3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa185/database.yaml @@ -0,0 +1,28 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa345 + + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x7_e000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa186/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa186/database.yaml new file mode 100644 index 0000000..df50e54 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa186/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa346 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0xF_e000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/database.yaml new file mode 100644 index 0000000..9f90d11 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/database.yaml @@ -0,0 +1,115 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_2000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0x7_e000 + size: 256 + reg_spec: pfr_cmpa.json + grouped_registers: + - name: ERASE_TOKEN + uid: cmpa_erase_token + width: 128 + config_as_hexstring: true + reversed: false + description: + ERASE_TOKEN[127:0] + sub_regs: + - field0D0 + - field0D4 + - field0D8 + - field0DC + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSBc] + supported_commands: + - erase + - load + - loadKeyBlob + - execute + + sbc: + supported_commands: + - erase + - load + - execute + - loadKeyBlob + \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/pfr_cmpa.json new file mode 100644 index 0000000..bef9cc8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa255/pfr_cmpa.json @@ -0,0 +1,7775 @@ +{ + "cpu": "mcxa255", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core clock", + "values": [ + { + "name": "FRO_45_MHZ", + "value": 0, + "description": "45Mhz FRO @1v0" + }, + { + "name": "FRO_90_MHZ", + "value": 1, + "description": "90MHz FRO @1v2" + }, + { + "name": "FRO_180_MHZ", + "value": 2, + "description": "180MHz FRO @1v2" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field004-bits0-7", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. This field should be written to remap field in flash. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = FLASH_REMAP_SIZE" + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin identified by this field whenever primary boot fails and execution falls through to ISP mode. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate. Baud rate configured during UART ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection" + } + ] + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field024", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field024-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USB0_VBUS_DETECT ISP pin. Identifies the pin to be used as USB0_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field02C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins" + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect" + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0003C", + "description": "Reserved 00030-0003C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_15_8", + "description": "Access control for flash sector", + "offset_int": "0x0044", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field048", + "name": "FLASH_ACL_23_16", + "description": "Access control for flash sector", + "offset_int": "0x0048", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x02_2000 - 0x02_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x02_6000 - 0x02_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x02_A000 - 0x02_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x02_E000 - 0x02_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field04C", + "name": "FLASH_ACL_31_24", + "description": "Access control for flash sector", + "offset_int": "0x004C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x03_2000 - 0x03_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x03_6000 - 0x03_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x03_A000 - 0x03_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x03_E000 - 0x03_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field050", + "name": "FLASH_ACL_39_32", + "description": "Access control for flash sector", + "offset_int": "0x0050", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field050-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x04_2000 - 0x04_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x04_4000 - 0x04_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector (offset range 0x04_6000 - 0x04_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x04_A000 - 0x04_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x04_C000 - 0x04_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x04_E000 - 0x04_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field054", + "name": "FLASH_ACL_47_40", + "description": "Access control for flash sector", + "offset_int": "0x0054", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x05_2000 - 0x05_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x05_4000 - 0x05_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector (offset range 0x05_6000 - 0x05_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x05_8000 - 0x05_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x05_A000 - 0x05_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x05_C000 - 0x05_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x05_E000 - 0x05_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field058", + "name": "FLASH_ACL_55_48", + "description": "Access control for flash sector", + "offset_int": "0x0058", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field058-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x06_2000 - 0x06_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x06_4000 - 0x06_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector (offset range 0x06_6000 - 0x06_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x06_A000 - 0x06_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x06_C000 - 0x06_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x06_E000 - 0x06_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field05C", + "name": "FLASH_ACL_63_56", + "description": "Access control for flash sector", + "offset_int": "0x005C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field05C-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x07_2000 - 0x07_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x07_4000 - 0x07_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector (offset range 0x07_6000 - 0x07_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x07_A000 - 0x07_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x07_C000 - 0x07_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x07_E000 - 0x07_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field060", + "name": "FLASH_ACL_71_64", + "description": "Access control for flash sector", + "offset_int": "0x0060", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field060-bits0-2", + "name": "ACL_SEC_64", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits4-6", + "name": "ACL_SEC_65", + "description": "Access control for flash sector (offset range 0x08_2000 - 0x08_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits8-10", + "name": "ACL_SEC_66", + "description": "Access control for flash sector (offset range 0x08_4000 - 0x08_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits12-14", + "name": "ACL_SEC_67", + "description": "Access control for flash sector (offset range 0x08_6000 - 0x08_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits16-18", + "name": "ACL_SEC_68", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits20-22", + "name": "ACL_SEC_69", + "description": "Access control for flash sector (offset range 0x08_A000 - 0x08_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits24-26", + "name": "ACL_SEC_70", + "description": "Access control for flash sector (offset range 0x08_C000 - 0x08_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits28-30", + "name": "ACL_SEC_71", + "description": "Access control for flash sector (offset range 0x08_E000 - 0x08_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field064", + "name": "FLASH_ACL_79_72", + "description": "Access control for flash sector", + "offset_int": "0x0064", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field064-bits0-2", + "name": "ACL_SEC_72", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits4-6", + "name": "ACL_SEC_73", + "description": "Access control for flash sector (offset range 0x09_2000 - 0x09_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits8-10", + "name": "ACL_SEC_74", + "description": "Access control for flash sector (offset range 0x09_4000 - 0x09_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits12-14", + "name": "ACL_SEC_75", + "description": "Access control for flash sector (offset range 0x09_6000 - 0x09_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits16-18", + "name": "ACL_SEC_76", + "description": "Access control for flash sector (offset range 0x09_8000 - 0x09_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits20-22", + "name": "ACL_SEC_77", + "description": "Access control for flash sector (offset range 0x09_A000 - 0x09_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits24-26", + "name": "ACL_SEC_78", + "description": "Access control for flash sector (offset range 0x09_C000 - 0x09_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits28-30", + "name": "ACL_SEC_79", + "description": "Access control for flash sector (offset range 0x09_E000 - 0x09_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field068", + "name": "FLASH_ACL_87_80", + "description": "Access control for flash sector", + "offset_int": "0x0068", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field068-bits0-2", + "name": "ACL_SEC_80", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits4-6", + "name": "ACL_SEC_81", + "description": "Access control for flash sector (offset range 0x0A_2000 - 0x0A_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits8-10", + "name": "ACL_SEC_82", + "description": "Access control for flash sector (offset range 0x0A_4000 - 0x0A_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits12-14", + "name": "ACL_SEC_83", + "description": "Access control for flash sector (offset range 0x0A_6000 - 0x0A_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits16-18", + "name": "ACL_SEC_84", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits20-22", + "name": "ACL_SEC_85", + "description": "Access control for flash sector (offset range 0x0A_A000 - 0x0A_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits24-26", + "name": "ACL_SEC_86", + "description": "Access control for flash sector (offset range 0x0A_C000 - 0x0A_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits28-30", + "name": "ACL_SEC_87", + "description": "Access control for flash sector (offset range 0x0A_E000 - 0x0A_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field06C", + "name": "FLASH_ACL_95_88", + "description": "Access control for flash sector", + "offset_int": "0x006C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field06C-bits0-2", + "name": "ACL_SEC_88", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits4-6", + "name": "ACL_SEC_89", + "description": "Access control for flash sector (offset range 0x0B_2000 - 0x0B_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits8-10", + "name": "ACL_SEC_90", + "description": "Access control for flash sector (offset range 0x0B_4000 - 0x0B_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits12-14", + "name": "ACL_SEC_91", + "description": "Access control for flash sector (offset range 0x0B_6000 - 0x0B_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits16-18", + "name": "ACL_SEC_92", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits20-22", + "name": "ACL_SEC_93", + "description": "Access control for flash sector (offset range 0x0B_A000 - 0x0B_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits24-26", + "name": "ACL_SEC_94", + "description": "Access control for flash sector (offset range 0x0B_C000 - 0x0B_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits28-30", + "name": "ACL_SEC_95", + "description": "Access control for flash sector (offset range 0x0B_E000 - 0x0B_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field070", + "name": "FLASH_ACL_103_96", + "description": "Access control for flash sector", + "offset_int": "0x0070", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field070-bits0-2", + "name": "ACL_SEC_96", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits4-6", + "name": "ACL_SEC_97", + "description": "Access control for flash sector (offset range 0x0C_2000 - 0x0C_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits8-10", + "name": "ACL_SEC_98", + "description": "Access control for flash sector (offset range 0x0C_4000 - 0x0C_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits12-14", + "name": "ACL_SEC_99", + "description": "Access control for flash sector (offset range 0x0C_6000 - 0x0C_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits16-18", + "name": "ACL_SEC_100", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits20-22", + "name": "ACL_SEC_101", + "description": "Access control for flash sector (offset range 0x0C_A000 - 0x0C_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits24-26", + "name": "ACL_SEC_102", + "description": "Access control for flash sector (offset range 0x0C_C000 - 0x0C_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits28-30", + "name": "ACL_SEC_103", + "description": "Access control for flash sector (offset range 0x0C_E000 - 0x0C_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field074", + "name": "FLASH_ACL_111_104", + "description": "Access control for flash sector", + "offset_int": "0x0074", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field074-bits0-2", + "name": "ACL_SEC_104", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits4-6", + "name": "ACL_SEC_105", + "description": "Access control for flash sector (offset range 0x0D_2000 - 0x0D_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits8-10", + "name": "ACL_SEC_106", + "description": "Access control for flash sector (offset range 0x0D_4000 - 0x0D_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits12-14", + "name": "ACL_SEC_107", + "description": "Access control for flash sector (offset range 0x0D_6000 - 0x0D_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits16-18", + "name": "ACL_SEC_108", + "description": "Access control for flash sector (offset range 0x0D_8000 - 0x0D_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits20-22", + "name": "ACL_SEC_109", + "description": "Access control for flash sector (offset range 0x0D_A000 - 0x0D_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits24-26", + "name": "ACL_SEC_110", + "description": "Access control for flash sector (offset range 0x0D_C000 - 0x0D_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits28-30", + "name": "ACL_SEC_111", + "description": "Access control for flash sector (offset range 0x0D_E000 - 0x0D_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field078", + "name": "FLASH_ACL_119_112", + "description": "Access control for flash sector", + "offset_int": "0x0078", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field078-bits0-2", + "name": "ACL_SEC_112", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits4-6", + "name": "ACL_SEC_113", + "description": "Access control for flash sector (offset range 0x0E_2000 - 0x0E_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits8-10", + "name": "ACL_SEC_114", + "description": "Access control for flash sector (offset range 0x0E_4000 - 0x0E_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits12-14", + "name": "ACL_SEC_115", + "description": "Access control for flash sector (offset range 0x0E_6000 - 0x0E_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits16-18", + "name": "ACL_SEC_116", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits20-22", + "name": "ACL_SEC_117", + "description": "Access control for flash sector (offset range 0x0E_A000 - 0x0E_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits24-26", + "name": "ACL_SEC_118", + "description": "Access control for flash sector (offset range 0x0E_C000 - 0x0E_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits28-30", + "name": "ACL_SEC_119", + "description": "Access control for flash sector (offset range 0x0E_E000 - 0x0E_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field07C", + "name": "FLASH_ACL_127_120", + "description": "Access control for flash sector", + "offset_int": "0x007C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field07C-bits0-2", + "name": "ACL_SEC_120", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits4-6", + "name": "ACL_SEC_121", + "description": "Access control for flash sector (offset range 0x0F_2000 - 0x0F_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits8-10", + "name": "ACL_SEC_122", + "description": "Access control for flash sector (offset range 0x0F_4000 - 0x0F_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits12-14", + "name": "ACL_SEC_123", + "description": "Access control for flash sector (offset range 0x0F_6000 - 0x0F_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits16-18", + "name": "ACL_SEC_124", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits20-22", + "name": "ACL_SEC_125", + "description": "Access control for flash sector (offset range 0x0F_A000 - 0x0F_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits24-26", + "name": "ACL_SEC_126", + "description": "Access control for flash sector (offset range 0x0F_C000 - 0x0F_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits28-30", + "name": "ACL_SEC_127", + "description": "Access control for flash sector (offset range 0x0F_E000 - 0x0F_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field080", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A4", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000A8-000AC", + "description": "Reserved 000A8-000AC" + }, + "registers": [ + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. Device does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. This read out protection is a mechanism that allows user to enable different levels of protection in the system. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0B4", + "name": "SBL_PROT", + "description": "Secondary Boot Loader Protection.", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "SBL_START_ADDR", + "description": "Secondary Boot Loader Start Address.", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0C0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00C0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0C4", + "name": "SBL_PROT_DP", + "description": "Secondary Boot Loader Protection (Duplicate).", + "offset_int": "0x00C4", + "default_value_int": "0" + }, + { + "id": "field0C8", + "name": "SBL_START_ADDR_DP", + "description": "Secondary Boot Loader Start Address (Duplicate).", + "offset_int": "0x00C8", + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Secure Installer", + "description": "Secure installer" + }, + "registers": [ + { + "id": "field0D0", + "name": "ERASE_TOKEN0", + "description": "ERASE_TOKEN[31:0]", + "offset_int": "0x00D0", + "default_value_int": "0" + }, + { + "id": "field0D4", + "name": "ERASE_TOKEN1", + "description": "ERASE_TOKEN[63:32]", + "offset_int": "0x00D4", + "default_value_int": "0" + }, + { + "id": "field0D8", + "name": "ERASE_TOKEN2", + "description": "ERASE_TOKEN[95:64]", + "offset_int": "0x00D8", + "default_value_int": "0" + }, + { + "id": "field0DC", + "name": "ERASE_TOKEN3", + "description": "ERASE_TOKEN[127:96]", + "offset_int": "0x00DC", + "default_value_int": "0" + }, + { + "id": "field0E0", + "name": "DELETE_INSTALLER", + "description": "DELETE_INSTALLER", + "offset_int": "0x00E0", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000E4-000F0", + "description": "Reserved 000E4-000F0" + }, + "registers": [ + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa256/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa256/database.yaml new file mode 100644 index 0000000..d6982b0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa256/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa255 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0xF_e000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa265/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa265/database.yaml new file mode 100644 index 0000000..7dac664 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa265/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa255 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x7_e000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa266/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa266/database.yaml new file mode 100644 index 0000000..acf1087 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa266/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa256 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0xF_e000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/database.yaml new file mode 100644 index 0000000..d402607 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/database.yaml @@ -0,0 +1,88 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x2_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x8000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0x1_E000 + size: 512 + reg_spec: pfr_cmpa.json + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/pfr_cmpa.json new file mode 100644 index 0000000..fff9fdc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa343/pfr_cmpa.json @@ -0,0 +1,2700 @@ +{ + "cpu": "MCXA343", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 2, + "description": "SPI ISP" + }, + { + "name": "I2C_ISP", + "value": 3, + "description": "I2C ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core clock", + "values": [ + { + "name": "FRO_45_MHZ", + "value": 0, + "description": "45Mhz FRO @1v0" + }, + { + "name": "FRO_90_MHZ", + "value": 1, + "description": "90MHz FRO @1v2" + }, + { + "name": "FRO_180_MHZ", + "value": 2, + "description": "180MHz FRO @1v2" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963. After this header is set, all non-zero values will take effect; leaving all settings at 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CMPA header value" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field004-bits0-7", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. This field should be written to remap field in flash. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = FLASH_REMAP_SIZE" + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin identified by this field whenever primary boot fails and execution falls through to ISP mode. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode UART_BAUD_RATE" + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate. Baud rate configured during UART ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection" + } + ] + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field024", + "name": "ISP_USB_ID", + "description": "isp usb id", + "offset_int": "0x0024", + "default_value_int": "0" + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "isp usb cfg", + "offset_int": "0x0028", + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0003C", + "description": "Reserved 00030-0003C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector", + "offset_int": "0x0044", + "deprecated_names": [ + "FLASH_ACL_8_15" + ], + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field048", + "name": "FLASH_ACL_16_23", + "description": "Access control for flash sector", + "offset_int": "0x0048", + "deprecated_names": [ + "FLASH_ACL_16_23" + ], + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x02_2000 - 0x02_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x02_6000 - 0x02_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x02_A000 - 0x02_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x02_E000 - 0x02_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field04C", + "name": "FLASH_ACL_24_31", + "description": "Access control for flash sector", + "offset_int": "0x004C", + "deprecated_names": [ + "FLASH_ACL_24_31" + ], + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x03_2000 - 0x03_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x03_6000 - 0x03_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x03_A000 - 0x03_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x03_E000 - 0x03_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00050-0007C", + "description": "Reserved 00050-0007C" + }, + "registers": [ + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field080", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. Device does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. This read out protection is a mechanism that allows user to enable different levels of protection in the system. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0C0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00C0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000D0-000DC", + "description": "Reserved 000D0-000DC" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa344/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa344/database.yaml new file mode 100644 index 0000000..37b009c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa344/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa343 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x4_0000 + external: false + sram: + start_int: 0x200_00000 + size_int: 0x1_0000 + external: false +features: + pfr: + cmpa: + address: 0x3_E000 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa345/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa345/database.yaml new file mode 100644 index 0000000..9b6ace6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa345/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa346 +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x1_e000 + external: false + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x7_e000 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/database.yaml new file mode 100644 index 0000000..8dbdbf3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/database.yaml @@ -0,0 +1,98 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x3_c000 + external: false + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_2000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0xf_e000 + size: 256 + reg_spec: pfr_cmpa.json + grouped_registers: + - name: ERASE_TOKEN + uid: cmpa_erase_token + width: 128 + config_as_hexstring: true + reversed: false + description: + ERASE_TOKEN[127:0] + sub_regs: + - field0D0 + - field0D4 + - field0D8 + - field0DC + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/pfr_cmpa.json new file mode 100644 index 0000000..5548d1e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa346/pfr_cmpa.json @@ -0,0 +1,7736 @@ +{ + "cpu": "mcxa346", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core clock", + "values": [ + { + "name": "FRO_45_MHZ", + "value": 0, + "description": "45Mhz FRO @1v0" + }, + { + "name": "FRO_90_MHZ", + "value": 1, + "description": "90MHz FRO @1v2" + }, + { + "name": "FRO_180_MHZ", + "value": 2, + "description": "180MHz FRO @1v2" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field004-bits0-7", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. This field should be written to remap field in flash. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = FLASH_REMAP_SIZE" + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin identified by this field whenever primary boot fails and execution falls through to ISP mode. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate. Baud rate configured during UART ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection" + } + ] + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USB0_VBUS_DETECT ISP pin. Identifies the pin to be used as USB0_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0003C", + "description": "Reserved 00030-0003C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_15_8", + "description": "Access control for flash sector", + "offset_int": "0x0044", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field048", + "name": "FLASH_ACL_23_16", + "description": "Access control for flash sector", + "offset_int": "0x0048", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x02_2000 - 0x02_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x02_6000 - 0x02_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x02_A000 - 0x02_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x02_E000 - 0x02_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field04C", + "name": "FLASH_ACL_31_24", + "description": "Access control for flash sector", + "offset_int": "0x004C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x03_2000 - 0x03_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x03_6000 - 0x03_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x03_A000 - 0x03_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x03_E000 - 0x03_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field050", + "name": "FLASH_ACL_39_32", + "description": "Access control for flash sector", + "offset_int": "0x0050", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field050-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x04_2000 - 0x04_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x04_4000 - 0x04_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector (offset range 0x04_6000 - 0x04_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x04_A000 - 0x04_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x04_C000 - 0x04_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x04_E000 - 0x04_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field054", + "name": "FLASH_ACL_47_40", + "description": "Access control for flash sector", + "offset_int": "0x0054", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x05_2000 - 0x05_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x05_4000 - 0x05_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector (offset range 0x05_6000 - 0x05_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x05_8000 - 0x05_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x05_A000 - 0x05_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x05_C000 - 0x05_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x05_E000 - 0x05_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field058", + "name": "FLASH_ACL_55_48", + "description": "Access control for flash sector", + "offset_int": "0x0058", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field058-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x06_2000 - 0x06_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x06_4000 - 0x06_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector (offset range 0x06_6000 - 0x06_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x06_A000 - 0x06_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x06_C000 - 0x06_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x06_E000 - 0x06_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field05C", + "name": "FLASH_ACL_63_56", + "description": "Access control for flash sector", + "offset_int": "0x005C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field05C-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x07_2000 - 0x07_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x07_4000 - 0x07_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector (offset range 0x07_6000 - 0x07_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x07_A000 - 0x07_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x07_C000 - 0x07_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x07_E000 - 0x07_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field060", + "name": "FLASH_ACL_71_64", + "description": "Access control for flash sector", + "offset_int": "0x0060", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field060-bits0-2", + "name": "ACL_SEC_64", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits4-6", + "name": "ACL_SEC_65", + "description": "Access control for flash sector (offset range 0x08_2000 - 0x08_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits8-10", + "name": "ACL_SEC_66", + "description": "Access control for flash sector (offset range 0x08_4000 - 0x08_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits12-14", + "name": "ACL_SEC_67", + "description": "Access control for flash sector (offset range 0x08_6000 - 0x08_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits16-18", + "name": "ACL_SEC_68", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits20-22", + "name": "ACL_SEC_69", + "description": "Access control for flash sector (offset range 0x08_A000 - 0x08_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits24-26", + "name": "ACL_SEC_70", + "description": "Access control for flash sector (offset range 0x08_C000 - 0x08_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits28-30", + "name": "ACL_SEC_71", + "description": "Access control for flash sector (offset range 0x08_E000 - 0x08_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field064", + "name": "FLASH_ACL_79_72", + "description": "Access control for flash sector", + "offset_int": "0x0064", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field064-bits0-2", + "name": "ACL_SEC_72", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits4-6", + "name": "ACL_SEC_73", + "description": "Access control for flash sector (offset range 0x09_2000 - 0x09_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits8-10", + "name": "ACL_SEC_74", + "description": "Access control for flash sector (offset range 0x09_4000 - 0x09_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits12-14", + "name": "ACL_SEC_75", + "description": "Access control for flash sector (offset range 0x09_6000 - 0x09_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits16-18", + "name": "ACL_SEC_76", + "description": "Access control for flash sector (offset range 0x09_8000 - 0x09_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits20-22", + "name": "ACL_SEC_77", + "description": "Access control for flash sector (offset range 0x09_A000 - 0x09_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits24-26", + "name": "ACL_SEC_78", + "description": "Access control for flash sector (offset range 0x09_C000 - 0x09_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits28-30", + "name": "ACL_SEC_79", + "description": "Access control for flash sector (offset range 0x09_E000 - 0x09_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field068", + "name": "FLASH_ACL_87_80", + "description": "Access control for flash sector", + "offset_int": "0x0068", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field068-bits0-2", + "name": "ACL_SEC_80", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits4-6", + "name": "ACL_SEC_81", + "description": "Access control for flash sector (offset range 0x0A_2000 - 0x0A_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits8-10", + "name": "ACL_SEC_82", + "description": "Access control for flash sector (offset range 0x0A_4000 - 0x0A_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits12-14", + "name": "ACL_SEC_83", + "description": "Access control for flash sector (offset range 0x0A_6000 - 0x0A_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits16-18", + "name": "ACL_SEC_84", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits20-22", + "name": "ACL_SEC_85", + "description": "Access control for flash sector (offset range 0x0A_A000 - 0x0A_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits24-26", + "name": "ACL_SEC_86", + "description": "Access control for flash sector (offset range 0x0A_C000 - 0x0A_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits28-30", + "name": "ACL_SEC_87", + "description": "Access control for flash sector (offset range 0x0A_E000 - 0x0A_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field06C", + "name": "FLASH_ACL_95_88", + "description": "Access control for flash sector", + "offset_int": "0x006C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field06C-bits0-2", + "name": "ACL_SEC_88", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits4-6", + "name": "ACL_SEC_89", + "description": "Access control for flash sector (offset range 0x0B_2000 - 0x0B_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits8-10", + "name": "ACL_SEC_90", + "description": "Access control for flash sector (offset range 0x0B_4000 - 0x0B_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits12-14", + "name": "ACL_SEC_91", + "description": "Access control for flash sector (offset range 0x0B_6000 - 0x0B_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits16-18", + "name": "ACL_SEC_92", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits20-22", + "name": "ACL_SEC_93", + "description": "Access control for flash sector (offset range 0x0B_A000 - 0x0B_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits24-26", + "name": "ACL_SEC_94", + "description": "Access control for flash sector (offset range 0x0B_C000 - 0x0B_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits28-30", + "name": "ACL_SEC_95", + "description": "Access control for flash sector (offset range 0x0B_E000 - 0x0B_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field070", + "name": "FLASH_ACL_103_96", + "description": "Access control for flash sector", + "offset_int": "0x0070", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field070-bits0-2", + "name": "ACL_SEC_96", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits4-6", + "name": "ACL_SEC_97", + "description": "Access control for flash sector (offset range 0x0C_2000 - 0x0C_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits8-10", + "name": "ACL_SEC_98", + "description": "Access control for flash sector (offset range 0x0C_4000 - 0x0C_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits12-14", + "name": "ACL_SEC_99", + "description": "Access control for flash sector (offset range 0x0C_6000 - 0x0C_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits16-18", + "name": "ACL_SEC_100", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits20-22", + "name": "ACL_SEC_101", + "description": "Access control for flash sector (offset range 0x0C_A000 - 0x0C_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits24-26", + "name": "ACL_SEC_102", + "description": "Access control for flash sector (offset range 0x0C_C000 - 0x0C_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits28-30", + "name": "ACL_SEC_103", + "description": "Access control for flash sector (offset range 0x0C_E000 - 0x0C_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field074", + "name": "FLASH_ACL_111_104", + "description": "Access control for flash sector", + "offset_int": "0x0074", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field074-bits0-2", + "name": "ACL_SEC_104", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits4-6", + "name": "ACL_SEC_105", + "description": "Access control for flash sector (offset range 0x0D_2000 - 0x0D_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits8-10", + "name": "ACL_SEC_106", + "description": "Access control for flash sector (offset range 0x0D_4000 - 0x0D_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits12-14", + "name": "ACL_SEC_107", + "description": "Access control for flash sector (offset range 0x0D_6000 - 0x0D_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits16-18", + "name": "ACL_SEC_108", + "description": "Access control for flash sector (offset range 0x0D_8000 - 0x0D_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits20-22", + "name": "ACL_SEC_109", + "description": "Access control for flash sector (offset range 0x0D_A000 - 0x0D_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits24-26", + "name": "ACL_SEC_110", + "description": "Access control for flash sector (offset range 0x0D_C000 - 0x0D_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits28-30", + "name": "ACL_SEC_111", + "description": "Access control for flash sector (offset range 0x0D_E000 - 0x0D_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field078", + "name": "FLASH_ACL_119_112", + "description": "Access control for flash sector", + "offset_int": "0x0078", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field078-bits0-2", + "name": "ACL_SEC_112", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits4-6", + "name": "ACL_SEC_113", + "description": "Access control for flash sector (offset range 0x0E_2000 - 0x0E_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits8-10", + "name": "ACL_SEC_114", + "description": "Access control for flash sector (offset range 0x0E_4000 - 0x0E_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits12-14", + "name": "ACL_SEC_115", + "description": "Access control for flash sector (offset range 0x0E_6000 - 0x0E_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits16-18", + "name": "ACL_SEC_116", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits20-22", + "name": "ACL_SEC_117", + "description": "Access control for flash sector (offset range 0x0E_A000 - 0x0E_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits24-26", + "name": "ACL_SEC_118", + "description": "Access control for flash sector (offset range 0x0E_C000 - 0x0E_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits28-30", + "name": "ACL_SEC_119", + "description": "Access control for flash sector (offset range 0x0E_E000 - 0x0E_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field07C", + "name": "FLASH_ACL_127_120", + "description": "Access control for flash sector", + "offset_int": "0x007C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field07C-bits0-2", + "name": "ACL_SEC_120", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits4-6", + "name": "ACL_SEC_121", + "description": "Access control for flash sector (offset range 0x0F_2000 - 0x0F_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits8-10", + "name": "ACL_SEC_122", + "description": "Access control for flash sector (offset range 0x0F_4000 - 0x0F_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits12-14", + "name": "ACL_SEC_123", + "description": "Access control for flash sector (offset range 0x0F_6000 - 0x0F_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits16-18", + "name": "ACL_SEC_124", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits20-22", + "name": "ACL_SEC_125", + "description": "Access control for flash sector (offset range 0x0F_A000 - 0x0F_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits24-26", + "name": "ACL_SEC_126", + "description": "Access control for flash sector (offset range 0x0F_C000 - 0x0F_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits28-30", + "name": "ACL_SEC_127", + "description": "Access control for flash sector (offset range 0x0F_E000 - 0x0F_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field080", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A4", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000A8-000AC", + "description": "Reserved 000A8-000AC" + }, + "registers": [ + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. Device does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. This read out protection is a mechanism that allows user to enable different levels of protection in the system. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0B4", + "name": "SBL_PROT", + "description": "sbl prot", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "SBL_START_ADDR.", + "description": "sbl start addr.", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0C0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00C0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0C4", + "name": "SBL_PROT_DP", + "description": "sbl prot dp", + "offset_int": "0x00C4", + "default_value_int": "0" + }, + { + "id": "field0C8", + "name": "SBL_START_ADDR_DP", + "description": "sbl start addr dp", + "offset_int": "0x00C8", + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000C4-000F0", + "description": "Reserved 000C4-000F0" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa355/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa355/database.yaml new file mode 100644 index 0000000..b85607f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa355/database.yaml @@ -0,0 +1,30 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa356 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x1_e000 + external: false + sramx: + start_int: 0x4000000 + size_int: 0x2000 + external: false +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x7_e000 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa356/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa356/database.yaml new file mode 100644 index 0000000..92682f0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa356/database.yaml @@ -0,0 +1,31 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa346 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x3_c000 + external: false + sramx: + start_int: 0x4000000 + size_int: 0x2000 + external: false + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0xF_e000 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa365/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa365/database.yaml new file mode 100644 index 0000000..a8bca74 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa365/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxa366 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x20000000 + size_int: 0x1_e000 + external: false +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x7_e000 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/database.yaml new file mode 100644 index 0000000..edf4fee --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/database.yaml @@ -0,0 +1,118 @@ +# Copyright 2024-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers:MCX-A-SERIES + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x10_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x3_c000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_2000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0xf_e000 + size: 256 + reg_spec: pfr_cmpa.json + grouped_registers: + - name: ERASE_TOKEN + uid: cmpa_erase_token + width: 128 + config_as_hexstring: true + reversed: false + description: ERASE_TOKEN[127:0] + sub_regs: + - field0D0 + - field0D4 + - field0D8 + - field0DC + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSBc] + supported_commands: + - erase + - load + - loadKeyBlob + - execute + + sbc: + supported_commands: + - erase + - load + - execute + - loadKeyBlob diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/pfr_cmpa.json new file mode 100644 index 0000000..73be00b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxa366/pfr_cmpa.json @@ -0,0 +1,7775 @@ +{ + "cpu": "MCXA366", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core clock", + "values": [ + { + "name": "FRO_45_MHZ", + "value": 0, + "description": "45Mhz FRO @1v0" + }, + { + "name": "FRO_90_MHZ", + "value": 1, + "description": "90MHz FRO @1v2" + }, + { + "name": "FRO_180_MHZ", + "value": 2, + "description": "180MHz FRO @1v2" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field004-bits0-7", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. This field should be written to remap field in flash. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = FLASH_REMAP_SIZE" + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin identified by this field whenever primary boot fails and execution falls through to ISP mode. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 16 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate. Baud rate configured during UART ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection" + } + ] + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field024", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field024-bits0-15", + "name": "USB_VENDOR_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "USB_PRODUCT_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field028", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "USBX_VBUS_PIN", + "description": "Override default USB0_VBUS_DETECT ISP pin. Identifies the pin to be used as USB0_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "USBX_VBUS_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field02C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins" + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect" + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0003C", + "description": "Reserved 00030-0003C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_15_8", + "description": "Access control for flash sector", + "offset_int": "0x0044", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field048", + "name": "FLASH_ACL_23_16", + "description": "Access control for flash sector", + "offset_int": "0x0048", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x02_2000 - 0x02_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x02_6000 - 0x02_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x02_A000 - 0x02_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x02_E000 - 0x02_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field04C", + "name": "FLASH_ACL_31_24", + "description": "Access control for flash sector", + "offset_int": "0x004C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x03_2000 - 0x03_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x03_6000 - 0x03_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x03_A000 - 0x03_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x03_E000 - 0x03_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field050", + "name": "FLASH_ACL_39_32", + "description": "Access control for flash sector", + "offset_int": "0x0050", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field050-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x04_2000 - 0x04_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x04_4000 - 0x04_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector (offset range 0x04_6000 - 0x04_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x04_A000 - 0x04_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x04_C000 - 0x04_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x04_E000 - 0x04_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field054", + "name": "FLASH_ACL_47_40", + "description": "Access control for flash sector", + "offset_int": "0x0054", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x05_2000 - 0x05_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x05_4000 - 0x05_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector (offset range 0x05_6000 - 0x05_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x05_8000 - 0x05_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x05_A000 - 0x05_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x05_C000 - 0x05_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x05_E000 - 0x05_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field058", + "name": "FLASH_ACL_55_48", + "description": "Access control for flash sector", + "offset_int": "0x0058", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field058-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x06_2000 - 0x06_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x06_4000 - 0x06_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector (offset range 0x06_6000 - 0x06_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x06_A000 - 0x06_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x06_C000 - 0x06_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x06_E000 - 0x06_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field05C", + "name": "FLASH_ACL_63_56", + "description": "Access control for flash sector", + "offset_int": "0x005C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field05C-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x07_2000 - 0x07_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x07_4000 - 0x07_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector (offset range 0x07_6000 - 0x07_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x07_A000 - 0x07_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x07_C000 - 0x07_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x07_E000 - 0x07_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field060", + "name": "FLASH_ACL_71_64", + "description": "Access control for flash sector", + "offset_int": "0x0060", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field060-bits0-2", + "name": "ACL_SEC_64", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits4-6", + "name": "ACL_SEC_65", + "description": "Access control for flash sector (offset range 0x08_2000 - 0x08_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits8-10", + "name": "ACL_SEC_66", + "description": "Access control for flash sector (offset range 0x08_4000 - 0x08_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits12-14", + "name": "ACL_SEC_67", + "description": "Access control for flash sector (offset range 0x08_6000 - 0x08_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits16-18", + "name": "ACL_SEC_68", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits20-22", + "name": "ACL_SEC_69", + "description": "Access control for flash sector (offset range 0x08_A000 - 0x08_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits24-26", + "name": "ACL_SEC_70", + "description": "Access control for flash sector (offset range 0x08_C000 - 0x08_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field060-bits28-30", + "name": "ACL_SEC_71", + "description": "Access control for flash sector (offset range 0x08_E000 - 0x08_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field064", + "name": "FLASH_ACL_79_72", + "description": "Access control for flash sector", + "offset_int": "0x0064", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field064-bits0-2", + "name": "ACL_SEC_72", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits4-6", + "name": "ACL_SEC_73", + "description": "Access control for flash sector (offset range 0x09_2000 - 0x09_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits8-10", + "name": "ACL_SEC_74", + "description": "Access control for flash sector (offset range 0x09_4000 - 0x09_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits12-14", + "name": "ACL_SEC_75", + "description": "Access control for flash sector (offset range 0x09_6000 - 0x09_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits16-18", + "name": "ACL_SEC_76", + "description": "Access control for flash sector (offset range 0x09_8000 - 0x09_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits20-22", + "name": "ACL_SEC_77", + "description": "Access control for flash sector (offset range 0x09_A000 - 0x09_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits24-26", + "name": "ACL_SEC_78", + "description": "Access control for flash sector (offset range 0x09_C000 - 0x09_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field064-bits28-30", + "name": "ACL_SEC_79", + "description": "Access control for flash sector (offset range 0x09_E000 - 0x09_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field068", + "name": "FLASH_ACL_87_80", + "description": "Access control for flash sector", + "offset_int": "0x0068", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field068-bits0-2", + "name": "ACL_SEC_80", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits4-6", + "name": "ACL_SEC_81", + "description": "Access control for flash sector (offset range 0x0A_2000 - 0x0A_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits8-10", + "name": "ACL_SEC_82", + "description": "Access control for flash sector (offset range 0x0A_4000 - 0x0A_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits12-14", + "name": "ACL_SEC_83", + "description": "Access control for flash sector (offset range 0x0A_6000 - 0x0A_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits16-18", + "name": "ACL_SEC_84", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits20-22", + "name": "ACL_SEC_85", + "description": "Access control for flash sector (offset range 0x0A_A000 - 0x0A_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits24-26", + "name": "ACL_SEC_86", + "description": "Access control for flash sector (offset range 0x0A_C000 - 0x0A_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field068-bits28-30", + "name": "ACL_SEC_87", + "description": "Access control for flash sector (offset range 0x0A_E000 - 0x0A_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field06C", + "name": "FLASH_ACL_95_88", + "description": "Access control for flash sector", + "offset_int": "0x006C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field06C-bits0-2", + "name": "ACL_SEC_88", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits4-6", + "name": "ACL_SEC_89", + "description": "Access control for flash sector (offset range 0x0B_2000 - 0x0B_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits8-10", + "name": "ACL_SEC_90", + "description": "Access control for flash sector (offset range 0x0B_4000 - 0x0B_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits12-14", + "name": "ACL_SEC_91", + "description": "Access control for flash sector (offset range 0x0B_6000 - 0x0B_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits16-18", + "name": "ACL_SEC_92", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits20-22", + "name": "ACL_SEC_93", + "description": "Access control for flash sector (offset range 0x0B_A000 - 0x0B_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits24-26", + "name": "ACL_SEC_94", + "description": "Access control for flash sector (offset range 0x0B_C000 - 0x0B_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field06C-bits28-30", + "name": "ACL_SEC_95", + "description": "Access control for flash sector (offset range 0x0B_E000 - 0x0B_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field070", + "name": "FLASH_ACL_103_96", + "description": "Access control for flash sector", + "offset_int": "0x0070", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field070-bits0-2", + "name": "ACL_SEC_96", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits4-6", + "name": "ACL_SEC_97", + "description": "Access control for flash sector (offset range 0x0C_2000 - 0x0C_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits8-10", + "name": "ACL_SEC_98", + "description": "Access control for flash sector (offset range 0x0C_4000 - 0x0C_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits12-14", + "name": "ACL_SEC_99", + "description": "Access control for flash sector (offset range 0x0C_6000 - 0x0C_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits16-18", + "name": "ACL_SEC_100", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits20-22", + "name": "ACL_SEC_101", + "description": "Access control for flash sector (offset range 0x0C_A000 - 0x0C_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits24-26", + "name": "ACL_SEC_102", + "description": "Access control for flash sector (offset range 0x0C_C000 - 0x0C_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field070-bits28-30", + "name": "ACL_SEC_103", + "description": "Access control for flash sector (offset range 0x0C_E000 - 0x0C_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field074", + "name": "FLASH_ACL_111_104", + "description": "Access control for flash sector", + "offset_int": "0x0074", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field074-bits0-2", + "name": "ACL_SEC_104", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits4-6", + "name": "ACL_SEC_105", + "description": "Access control for flash sector (offset range 0x0D_2000 - 0x0D_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits8-10", + "name": "ACL_SEC_106", + "description": "Access control for flash sector (offset range 0x0D_4000 - 0x0D_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits12-14", + "name": "ACL_SEC_107", + "description": "Access control for flash sector (offset range 0x0D_6000 - 0x0D_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits16-18", + "name": "ACL_SEC_108", + "description": "Access control for flash sector (offset range 0x0D_8000 - 0x0D_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits20-22", + "name": "ACL_SEC_109", + "description": "Access control for flash sector (offset range 0x0D_A000 - 0x0D_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits24-26", + "name": "ACL_SEC_110", + "description": "Access control for flash sector (offset range 0x0D_C000 - 0x0D_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field074-bits28-30", + "name": "ACL_SEC_111", + "description": "Access control for flash sector (offset range 0x0D_E000 - 0x0D_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field078", + "name": "FLASH_ACL_119_112", + "description": "Access control for flash sector", + "offset_int": "0x0078", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field078-bits0-2", + "name": "ACL_SEC_112", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits4-6", + "name": "ACL_SEC_113", + "description": "Access control for flash sector (offset range 0x0E_2000 - 0x0E_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits8-10", + "name": "ACL_SEC_114", + "description": "Access control for flash sector (offset range 0x0E_4000 - 0x0E_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits12-14", + "name": "ACL_SEC_115", + "description": "Access control for flash sector (offset range 0x0E_6000 - 0x0E_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits16-18", + "name": "ACL_SEC_116", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits20-22", + "name": "ACL_SEC_117", + "description": "Access control for flash sector (offset range 0x0E_A000 - 0x0E_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits24-26", + "name": "ACL_SEC_118", + "description": "Access control for flash sector (offset range 0x0E_C000 - 0x0E_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field078-bits28-30", + "name": "ACL_SEC_119", + "description": "Access control for flash sector (offset range 0x0E_E000 - 0x0E_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field07C", + "name": "FLASH_ACL_127_120", + "description": "Access control for flash sector", + "offset_int": "0x007C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field07C-bits0-2", + "name": "ACL_SEC_120", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits4-6", + "name": "ACL_SEC_121", + "description": "Access control for flash sector (offset range 0x0F_2000 - 0x0F_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits8-10", + "name": "ACL_SEC_122", + "description": "Access control for flash sector (offset range 0x0F_4000 - 0x0F_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits12-14", + "name": "ACL_SEC_123", + "description": "Access control for flash sector (offset range 0x0F_6000 - 0x0F_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits16-18", + "name": "ACL_SEC_124", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits20-22", + "name": "ACL_SEC_125", + "description": "Access control for flash sector (offset range 0x0F_A000 - 0x0F_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits24-26", + "name": "ACL_SEC_126", + "description": "Access control for flash sector (offset range 0x0F_C000 - 0x0F_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field07C-bits28-30", + "name": "ACL_SEC_127", + "description": "Access control for flash sector (offset range 0x0F_E000 - 0x0F_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L)" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL)" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L)" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_)" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_)" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL)" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L)" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field080", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 3. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 4. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x00A4", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000A8-000AC", + "description": "Reserved 000A8-000AC" + }, + "registers": [ + { + "id": "Reserved000A8", + "name": "Reserved 0x000A8", + "description": "This field is reserved for internal use", + "offset_int": "0x00A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. Device does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. This read out protection is a mechanism that allows user to enable different levels of protection in the system. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00B0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0B4", + "name": "SBL_PROT", + "description": "Secondary Boot Loader Protection.", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "SBL_START_ADDR", + "description": "Secondary Boot Loader Start Address.", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0C0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x00C0", + "default_value_int": "0xFFFFFFFF" + }, + { + "id": "field0C4", + "name": "SBL_PROT_DP", + "description": "Secondary Boot Loader Protection (Duplicate).", + "offset_int": "0x00C4", + "default_value_int": "0" + }, + { + "id": "field0C8", + "name": "SBL_START_ADDR_DP", + "description": "Secondary Boot Loader Start Address (Duplicate).", + "offset_int": "0x00C8", + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Secure Installer", + "description": "Secure installer" + }, + "registers": [ + { + "id": "field0D0", + "name": "ERASE_TOKEN0", + "description": "ERASE_TOKEN[31:0]", + "offset_int": "0x00D0", + "default_value_int": "0" + }, + { + "id": "field0D4", + "name": "ERASE_TOKEN1", + "description": "ERASE_TOKEN[63:32]", + "offset_int": "0x00D4", + "default_value_int": "0" + }, + { + "id": "field0D8", + "name": "ERASE_TOKEN2", + "description": "ERASE_TOKEN[95:64]", + "offset_int": "0x00D8", + "default_value_int": "0" + }, + { + "id": "field0DC", + "name": "ERASE_TOKEN3", + "description": "ERASE_TOKEN[127:96]", + "offset_int": "0x00DC", + "default_value_int": "0" + }, + { + "id": "field0E0", + "name": "DELETE_INSTALLER", + "description": "DELETE_INSTALLER", + "offset_int": "0x00E0", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000E4-000F0", + "description": "Reserved 000E4-000F0" + }, + "registers": [ + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/bca.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/bca.json new file mode 100644 index 0000000..46c0799 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/bca.json @@ -0,0 +1,309 @@ +{ + "cpu": "mcxc041", + "groups": [ + { + "group": { + "name": "General regs", + "description": "BCA registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "TAG", + "description": "Tag: Magic number to verify bootloader configuration is valid. Must be set to 'kcfg' (0x6766636B).", + "offset_int": "0", + "default_value_int": "0x6766636B", + "reg_width": 32, + "access": "RO" + }, + { + "id": "Reserved004", + "name": "Reserved 0x004", + "description": "This field is reserved for internal use", + "offset_int": "0x004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved008", + "name": "Reserved 0x008", + "description": "This field is reserved for internal use", + "offset_int": "0x008", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved00C", + "name": "Reserved 0x00C", + "description": "This field is reserved for internal use", + "offset_int": "0x00C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "field010", + "name": "ENABLED_PERIPHERALS", + "description": "Configuration bitfields of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1.", + "offset_int": "0x0010", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "LPUART", + "description": "Enable LPUART peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable LPUART peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable LPUART peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "I2C", + "description": "Enable I2C peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable I2C peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable I2C peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPI", + "description": "Enable SPI peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable SPI peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable SPI peripheral" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "I2C_SLAVE_ADDRESS", + "description": "Configuration of I2C slave address", + "offset_int": "0x011", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field011-bits0-7", + "name": "i2cSlaveAddress", + "description": "If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address." + } + ] + }, + { + "id": "field012", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.", + "offset_int": "0x012", + "default_value_int": "0xFFFF", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "field012-bits0-15", + "name": "peripheralDetectionTimeout", + "description": "Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds." + } + ] + }, + { + "id": "Reserved014", + "name": "Reserved 0x014", + "description": "This field is reserved for internal use", + "offset_int": "0x014", + "is_reserved": true, + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved016", + "name": "Reserved 0x016", + "description": "This field is reserved for internal use", + "offset_int": "0x016", + "is_reserved": true, + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved018", + "name": "Reserved 0x018", + "description": "This field is reserved for internal use", + "offset_int": "0x018", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "field01C", + "name": "CLOCK_FLAGS", + "description": "Configuration clockFlags field. The flags in the clockFlags configuration field are enabled if the corresponding bit is cleared (0).", + "offset_int": "0x01C", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field01C-bit0", + "name": "HighSpeed", + "description": "Enable high speed mode (i.e., 48 MHz).", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable high speed." + }, + { + "name": "DISABLE", + "value": 1, + "description": "Disable high speed." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "field01D", + "name": "CLOCK_DIVIDER", + "description": "Clock divider configuration", + "offset_int": "0x01D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field01D-bits0-7", + "name": "clockDivider", + "description": "Inverted value of the divider to use for core and bus clocks when in high speed mode." + } + ] + }, + { + "id": "Reserved01E", + "name": "Reserved 0x01E", + "description": "This field is reserved for internal use", + "offset_int": "0x01E", + "is_reserved": true, + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved020", + "name": "Reserved 0x020", + "description": "This field is reserved for internal use", + "offset_int": "0x020", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved024", + "name": "Reserved 0x024", + "description": "This field is reserved for internal use", + "offset_int": "0x024", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved028", + "name": "Reserved 0x028", + "description": "This field is reserved for internal use", + "offset_int": "0x028", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved02C", + "name": "Reserved 0x02C", + "description": "This field is reserved for internal use", + "offset_int": "0x02C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved030", + "name": "Reserved 0x030", + "description": "This field is reserved for internal use", + "offset_int": "0x030", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved034", + "name": "Reserved 0x034", + "description": "This field is reserved for internal use", + "offset_int": "0x034", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved038", + "name": "Reserved 0x038", + "description": "This field is reserved for internal use", + "offset_int": "0x038", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved03C", + "name": "Reserved 0x03C", + "description": "This field is reserved for internal use", + "offset_int": "0x03C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/database.yaml new file mode 100644 index 0000000..32decb8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/database.yaml @@ -0,0 +1,71 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-c-series-microcontrollers/mcx-c04x-mcus-with-arm-cortex-m0-plus-entry-level-mcus-with-classical-peripherals:MCX-C04x + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x7FFF + external: false + sram-l: + start_int: 0x1FFF_FE00 + size_int: 0x1FF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x5FF + external: false + isp: + rom: + interfaces: ["uart", "spi", "i2c"] + protocol: mboot + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + size: 0x500 + + # ======== Blhost section ======== + blhost: {} + + # ======== BCA section ======== + bca: + reg_spec: bca.json + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + reg_spec_modification: + field000: + reverse: True + config_as_hexstring: True + + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinBca + - Mbi_MixinFcf + - Mbi_ExportMixinApp + images: + xip: + plain: plain_xip diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/fcf.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/fcf.json new file mode 100644 index 0000000..ac022c1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc041/fcf.json @@ -0,0 +1,336 @@ +{ + "cpu": "mcxc041", + "groups": [ + { + "group": { + "name": "General regs", + "description": "FCF registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "BACKDOOR_KEY", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFF", + "reg_width": 64, + "description": "Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access." + }, + { + "id": "field008", + "name": "FPROT", + "description": "Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).", + "offset_int": "0x008", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "FPROT3", + "description": "Program Flash Protection Registers (FPROT3)" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "FPROT2", + "description": "Program Flash Protection Registers (FPROT2)" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "FPROT1", + "description": "Program Flash Protection Registers (FPROT1)" + }, + { + "width": 8, + "id": "field008-bits24-31", + "name": "FPROT0", + "description": "Program Flash Protection Registers (FPROT0)" + } + ] + }, + { + "id": "field00C", + "name": "FSEC", + "description": "Flash security byte. Refer to the description of the Flash Security Register (FSEC).", + "offset_int": "0x00C", + "reg_width": 8, + "bitfields": [ + { + "width": 2, + "id": "field00C-bits0-1", + "name": "SEC", + "description": "Flash Security.", + "values": [ + { + "name": "SECURE_0", + "value": 0, + "description": "MCU security status is secure." + }, + { + "name": "SECURE", + "value": 1, + "description": "MCU security status is secure." + }, + { + "name": "UNSECURE", + "value": 2, + "description": "MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)" + }, + { + "name": "SECURE_3", + "value": 3, + "description": "MCU security status is secure." + } + ] + }, + { + "width": 2, + "id": "field00C-bits2-3", + "name": "FSLACC", + "description": "Factory Security Level Access Code.", + "values": [ + { + "name": "GRANTED_0", + "value": 0, + "description": "NXP factory access granted" + }, + { + "name": "DENIED_1", + "value": 1, + "description": "NXP factory access denied" + }, + { + "name": "DENIED_2", + "value": 2, + "description": "NXP factory access denied" + }, + { + "name": "GRANTED_3", + "value": 3, + "description": "NXP factory access granted" + } + ] + }, + { + "width": 2, + "id": "field00C-bits4-5", + "name": "MEEN", + "description": "Mass Erase Enable. Enables and disables mass erase capability of the flash memory module.", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Mass erase is enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Mass erase is enabled" + }, + { + "name": "DISABLED", + "value": 2, + "description": "Mass erase is disabled" + }, + { + "name": "ENABLED_3", + "value": 3, + "description": "Mass erase is enabled" + } + ] + }, + { + "width": 2, + "id": "field00C-bits6-7", + "name": "KEYEN", + "description": "Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.", + "values": [ + { + "name": "DISABLED_0", + "value": 0, + "description": "Backdoor key access disabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)" + }, + { + "name": "ENABLED", + "value": 2, + "description": "Backdoor key access enabled" + }, + { + "name": "DISABLED_3", + "value": 3, + "description": "Backdoor key access disabled" + } + ] + } + ], + "default_value_int": "0xfe" + }, + { + "id": "field00D", + "name": "FOPT", + "description": "Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).", + "offset_int": "0x00D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00D-bit0", + "name": "LPBOOT[0]", + "description": "Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register, and the state of the RUNM register in SMC_PMCTRL. \nLarger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected.", + "values": [ + { + "name": "DIV_BY_8_OR_2", + "value": 0, + "description": "VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).\nRUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2)." + }, + { + "name": "DIV_BY_4_OR_1", + "value": 1, + "description": "VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).\nRUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1)." + } + ] + }, + { + "width": 1, + "id": "field00D-bit1", + "name": "BOOTPIN_OPT", + "description": "External pin selects boot options.", + "values": [ + { + "name": "FORCE_FROM_ROM", + "value": 0, + "description": "Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESET_PIN_CFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits." + }, + { + "name": "BOOTSRC_SEL", + "value": 1, + "description": "Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits." + } + ] + }, + { + "width": 1, + "id": "field00D-bit2", + "name": "NMI_DIS", + "description": "Enables/disables control for the NMI function.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up." + }, + { + "name": "ENABLE", + "value": 1, + "description": "NMI_b pin/interrupts reset default to enabled." + } + ] + }, + { + "width": 1, + "id": "field00D-bit3", + "name": "RESET_PIN_CFG", + "description": "Enables/disables control for the RESET pin.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "RESET pin is disabled following a POR and cannot be enabled as reset function." + }, + { + "name": "ENABLE", + "value": 1, + "description": "RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled." + } + ] + }, + { + "width": 1, + "id": "field00D-bit4", + "name": "LPBOOT[1]", + "description": "Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register, and the state of the RUNM register in SMC_PMCTRL.", + "values": [ + { + "name": "VLPR_MODE", + "value": 0, + "description": "Device is configured for VLPR mode on exit from reset." + }, + { + "name": "RUN_MODE", + "value": 1, + "description": "Device is configured for RUN mode on exit from reset." + } + ] + }, + { + "width": 1, + "id": "field00D-bit5", + "name": "FAST_INIT", + "description": "Selects initialization speed on POR, VLLSx, and any system reset.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Fast Initialization: The flash has faster recoveries at the expense of higher current during these times." + } + ] + }, + { + "width": 2, + "id": "field00D-bits6-7", + "name": "BOOTSRC_SEL", + "description": "Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPIN_OPT = 1", + "values": [ + { + "name": "FLASH", + "value": 0, + "description": "Boot from Flash" + }, + { + "name": "ROM_2", + "value": 2, + "description": "Boot from ROM" + }, + { + "name": "ROM", + "value": 3, + "description": "Boot from ROM" + } + ] + } + ] + }, + { + "id": "Reserved00E", + "name": "Reserved 0x00E", + "description": "This field is reserved for internal use", + "offset_int": "0x00E", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved00F", + "name": "Reserved 0x00F", + "description": "This field is reserved for internal use", + "offset_int": "0x00F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/bca.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/bca.json new file mode 100644 index 0000000..7ac299b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/bca.json @@ -0,0 +1,327 @@ +{ + "cpu": "mcxc141", + "groups": [ + { + "group": { + "name": "General regs", + "description": "BCA registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "TAG", + "description": "Tag: Magic number to verify bootloader configuration is valid. Must be set to 'kcfg' (0x6766636B).", + "offset_int": "0", + "default_value_int": "0x6766636B", + "reg_width": 32, + "access": "RO" + }, + { + "id": "Reserved004", + "name": "Reserved 0x004", + "description": "This field is reserved for internal use", + "offset_int": "0x004", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved008", + "name": "Reserved 0x008", + "description": "This field is reserved for internal use", + "offset_int": "0x008", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved00C", + "name": "Reserved 0x00C", + "description": "This field is reserved for internal use", + "offset_int": "0x00C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "field010", + "name": "ENABLED_PERIPHERALS", + "description": "Configuration bitfields of peripherals to enable. Bootloader will enable the peripheral if corresponding bit is set to 1.", + "offset_int": "0x0010", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "LPUART", + "description": "Enable LPUART peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable LPUART peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable LPUART peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit1", + "name": "I2C", + "description": "Enable I2C peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable I2C peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable I2C peripheral" + } + ] + }, + { + "width": 1, + "id": "field010-bit2", + "name": "SPI", + "description": "Enable SPI peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable SPI peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable SPI peripheral" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field010-bit4", + "name": "USB", + "description": "Enable USB peripheral", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable USB peripheral" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable USB peripheral" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "field011", + "name": "I2C_SLAVE_ADDRESS", + "description": "Configuration of I2C slave address", + "offset_int": "0x011", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field011-bits0-7", + "name": "i2cSlaveAddress", + "description": "If not 0xFF, used as the 7-bit I2C slave address. If 0xFF, defaults to 0x10 for I2C slave address." + } + ] + }, + { + "id": "field012", + "name": "PERIPHERAL_DETECTION_TIMEOUT", + "description": "Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds.", + "offset_int": "0x012", + "default_value_int": "0xFFFF", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "field012-bits0-15", + "name": "peripheralDetectionTimeout", + "description": "Timeout in milliseconds for active peripheral detection. If 0xFFFF, defaults to 5 seconds." + } + ] + }, + { + "id": "field014", + "name": "USB", + "description": "Configuration of USB Vendor ID and Product ID", + "offset_int": "0x014", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 16, + "id": "field014-bits0-15", + "name": "usbVid", + "description": "Sets the USB Vendor ID reported by the device during enumeration. If 0xFFFF, it defaults to 0x15A2." + }, + { + "width": 16, + "id": "field014-bits16-31", + "name": "usbPid", + "description": "Sets the USB Product ID reported by the device during enumeration." + } + ] + }, + { + "id": "field018", + "name": "USB_STRINGS_POINTER", + "description": "Sets the USB Strings reported by the device during enumeration. Default string values are described in the USB peripheral section.", + "offset_int": "0x018", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "field01C", + "name": "CLOCK_FLAGS", + "description": "Configuration clockFlags field. The flags in the clockFlags configuration field are enabled if the corresponding bit is cleared (0).", + "offset_int": "0x01C", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field01C-bit0", + "name": "HighSpeed", + "description": "Enable high speed mode (i.e., 48 MHz).", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable high speed." + }, + { + "name": "DISABLE", + "value": 1, + "description": "Disable high speed." + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "field01D", + "name": "CLOCK_DIVIDER", + "description": "Clock divider configuration", + "offset_int": "0x01D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 8, + "id": "field01D-bits0-7", + "name": "clockDivider", + "description": "Inverted value of the divider to use for core and bus clocks when in high speed mode." + } + ] + }, + { + "id": "Reserved01E", + "name": "Reserved 0x01E", + "description": "This field is reserved for internal use", + "offset_int": "0x01E", + "is_reserved": true, + "default_value_int": "0xFFFF", + "reg_width": 16 + }, + { + "id": "Reserved020", + "name": "Reserved 0x020", + "description": "This field is reserved for internal use", + "offset_int": "0x020", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved024", + "name": "Reserved 0x024", + "description": "This field is reserved for internal use", + "offset_int": "0x024", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved028", + "name": "Reserved 0x028", + "description": "This field is reserved for internal use", + "offset_int": "0x028", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved02C", + "name": "Reserved 0x02C", + "description": "This field is reserved for internal use", + "offset_int": "0x02C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved030", + "name": "Reserved 0x030", + "description": "This field is reserved for internal use", + "offset_int": "0x030", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved034", + "name": "Reserved 0x034", + "description": "This field is reserved for internal use", + "offset_int": "0x034", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved038", + "name": "Reserved 0x038", + "description": "This field is reserved for internal use", + "offset_int": "0x038", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + }, + { + "id": "Reserved03C", + "name": "Reserved 0x03C", + "description": "This field is reserved for internal use", + "offset_int": "0x03C", + "is_reserved": true, + "default_value_int": "0xFFFFFFFF", + "reg_width": 32 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/database.yaml new file mode 100644 index 0000000..f8d79f3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/database.yaml @@ -0,0 +1,69 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-c-series-microcontrollers/mcx-c14x-24x-44x-mcus-with-arm-cortex-m0-plus-entry-level-mcus-with-usb-segment-lcd-and-classical-peripherals:MCX-C14x-24x-44x + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x7FFF + external: false + sram-l: + start_int: 0x1FFF_F800 + size_int: 0x7FF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x17FF + external: false + isp: + rom: + interfaces: ["uart", "usb", "spi", "i2c"] + protocol: mboot + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + + # ======== BCA section ======== + bca: + reg_spec: bca.json + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + reg_spec_modification: + field000: + reverse: True + config_as_hexstring: True + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinBca + - Mbi_MixinFcf + - Mbi_ExportMixinApp + images: + xip: + plain: plain_xip diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/fcf.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/fcf.json new file mode 100644 index 0000000..3ac6cbf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc141/fcf.json @@ -0,0 +1,336 @@ +{ + "cpu": "mcxc141", + "groups": [ + { + "group": { + "name": "General regs", + "description": "FCF registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "BACKDOOR_KEY", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFF", + "reg_width": 64, + "description": "Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access." + }, + { + "id": "field008", + "name": "FPROT", + "description": "Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).", + "offset_int": "0x008", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "FPROT3", + "description": "Program Flash Protection Registers (FPROT3)" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "FPROT2", + "description": "Program Flash Protection Registers (FPROT2)" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "FPROT1", + "description": "Program Flash Protection Registers (FPROT1)" + }, + { + "width": 8, + "id": "field008-bits24-31", + "name": "FPROT0", + "description": "Program Flash Protection Registers (FPROT0)" + } + ] + }, + { + "id": "field00C", + "name": "FSEC", + "description": "Flash security byte. Refer to the description of the Flash Security Register (FSEC).", + "offset_int": "0x00C", + "reg_width": 8, + "bitfields": [ + { + "width": 2, + "id": "field00C-bits0-1", + "name": "SEC", + "description": "Flash Security.", + "values": [ + { + "name": "SECURE_0", + "value": 0, + "description": "MCU security status is secure." + }, + { + "name": "SECURE", + "value": 1, + "description": "MCU security status is secure." + }, + { + "name": "UNSECURE", + "value": 2, + "description": "MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)" + }, + { + "name": "SECURE_3", + "value": 3, + "description": "MCU security status is secure." + } + ] + }, + { + "width": 2, + "id": "field00C-bits2-3", + "name": "FSLACC", + "description": "Factory Security Level Access Code.", + "values": [ + { + "name": "GRANTED_0", + "value": 0, + "description": "NXP factory access granted" + }, + { + "name": "DENIED_1", + "value": 1, + "description": "NXP factory access denied" + }, + { + "name": "DENIED_2", + "value": 2, + "description": "NXP factory access denied" + }, + { + "name": "GRANTED_3", + "value": 3, + "description": "NXP factory access granted" + } + ] + }, + { + "width": 2, + "id": "field00C-bits4-5", + "name": "MEEN", + "description": "Mass Erase Enable. Enables and disables mass erase capability of the flash memory module.", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Mass erase is enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Mass erase is enabled" + }, + { + "name": "DISABLED", + "value": 2, + "description": "Mass erase is disabled" + }, + { + "name": "ENABLED_3", + "value": 3, + "description": "Mass erase is enabled" + } + ] + }, + { + "width": 2, + "id": "field00C-bits6-7", + "name": "KEYEN", + "description": "Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.", + "values": [ + { + "name": "DISABLED_0", + "value": 0, + "description": "Backdoor key access disabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)" + }, + { + "name": "ENABLED", + "value": 2, + "description": "Backdoor key access enabled" + }, + { + "name": "DISABLED_3", + "value": 3, + "description": "Backdoor key access disabled" + } + ] + } + ], + "default_value_int": "0xfe" + }, + { + "id": "field00D", + "name": "FOPT", + "description": "Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).", + "offset_int": "0x00D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00D-bit0", + "name": "LPBOOT[0]", + "description": "Configure Core and system clock divider (OUTDIV1) value on exit from reset. Together with LPBOOT[1], controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register, and the state of the RUNM register in SMC_PMCTRL. \nLarger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit. The recovery times are also extended if the FAST_INIT option is not selected.", + "values": [ + { + "name": "DIV_BY_8_OR_2", + "value": 0, + "description": "VLPR mode: Core and system clock divider (OUTDIV1) is 0x7 (divide by 8).\nRUN mode: Core and system clock divider (OUTDIV1) is 0x1 (divide by 2)." + }, + { + "name": "DIV_BY_4_OR_1", + "value": 1, + "description": "VLPR mode: Core and system clock divider (OUTDIV1) is 0x3 (divide by 4).\nRUN mode: Core and system clock divider (OUTDIV1) is 0x0 (divide by 1)." + } + ] + }, + { + "width": 1, + "id": "field00D-bit1", + "name": "BOOTPIN_OPT", + "description": "External pin selects boot options.", + "values": [ + { + "name": "FORCE_FROM_ROM", + "value": 0, + "description": "Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin. RESET pin must be enabled (FOPT[RESET_PIN_CFG] = 1) when this option is selected. NMI pin is sampled at the end of reset (when reset pin negates). If BOOTCFG0 pin is not asserted, Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits." + }, + { + "name": "BOOTSRC_SEL", + "value": 1, + "description": "Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits." + } + ] + }, + { + "width": 1, + "id": "field00D-bit2", + "name": "NMI_DIS", + "description": "Enables/disables control for the NMI function.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "NMI interrupts are always blocked. The associated pin continues to default to NMI pin controls with internal pullup enabled. When NMI pin function is disabled, it cannot be used as a source for low-power mode wake-up." + }, + { + "name": "ENABLE", + "value": 1, + "description": "NMI_b pin/interrupts reset default to enabled." + } + ] + }, + { + "width": 1, + "id": "field00D-bit3", + "name": "RESET_PIN_CFG", + "description": "Enables/disables control for the RESET pin.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "RESET pin is disabled following a POR and cannot be enabled as reset function." + }, + { + "name": "ENABLE", + "value": 1, + "description": "RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled." + } + ] + }, + { + "width": 1, + "id": "field00D-bit4", + "name": "LPBOOT[1]", + "description": "Configure device for VLPR or RUN mode on exit from reset. Together with LPBOOT[0], controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register, and the state of the RUNM register in SMC_PMCTRL.", + "values": [ + { + "name": "VLPR_MODE", + "value": 0, + "description": "Device is configured for VLPR mode on exit from reset." + }, + { + "name": "RUN_MODE", + "value": 1, + "description": "Device is configured for RUN mode on exit from reset." + } + ] + }, + { + "width": 1, + "id": "field00D-bit5", + "name": "FAST_INIT", + "description": "Selects initialization speed on POR, VLLSx, and any system reset.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Slower initialization: The flash initialization will be slower with the benefit of reduced average current during this time. The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Fast Initialization: The flash has faster recoveries at the expense of higher current during these times." + } + ] + }, + { + "width": 2, + "id": "field00D-bits6-7", + "name": "BOOTSRC_SEL", + "description": "Boot Source Selection: these bits select the boot sources if boot pin option bit BOOTPIN_OPT = 1", + "values": [ + { + "name": "FLASH", + "value": 0, + "description": "Boot from Flash" + }, + { + "name": "ROM_2", + "value": 2, + "description": "Boot from ROM" + }, + { + "name": "ROM", + "value": 3, + "description": "Boot from ROM" + } + ] + } + ] + }, + { + "id": "Reserved00E", + "name": "Reserved 0x00E", + "description": "This field is reserved for internal use", + "offset_int": "0x00E", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + }, + { + "id": "Reserved00F", + "name": "Reserved 0x00F", + "description": "This field is reserved for internal use", + "offset_int": "0x00F", + "is_reserved": true, + "default_value_int": "0xFF", + "reg_width": 8 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc142/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc142/database.yaml new file mode 100644 index 0000000..55eecc6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc142/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc141 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0xFFFF + external: false + sram-l: + start_int: 0x1FFF_F000 + size_int: 0xFFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x2FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc143/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc143/database.yaml new file mode 100644 index 0000000..e36b17f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc143/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc141 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0xFFFF + external: false + internal-flash1: + start_int: 0x1_0000 + size_int: 0xFFFF + external: false + sram-l: + start_int: 0x1FFF_F000 + size_int: 0xFFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x2FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc144/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc144/database.yaml new file mode 100644 index 0000000..64f7e0f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc144/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc141 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0x1_FFFF + external: false + internal-flash1: + start_int: 0x2_0000 + size_int: 0x1_FFFF + external: false + sram-l: + start_int: 0x1FFF_E000 + size_int: 0x1FFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x5FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc242/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc242/database.yaml new file mode 100644 index 0000000..55eecc6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc242/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc141 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0xFFFF + external: false + sram-l: + start_int: 0x1FFF_F000 + size_int: 0xFFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x2FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc243/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc243/database.yaml new file mode 100644 index 0000000..152bc43 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc243/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc242 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0xFFFF + external: false + internal-flash1: + start_int: 0x1_0000 + size_int: 0xFFFF + external: false + sram-l: + start_int: 0x1FFF_F000 + size_int: 0xFFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x2FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc244/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc244/database.yaml new file mode 100644 index 0000000..199f233 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc244/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc242 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0x1_FFFF + external: false + internal-flash1: + start_int: 0x2_0000 + size_int: 0x1_FFFF + external: false + sram-l: + start_int: 0x1FFF_E000 + size_int: 0x1FFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x5FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc443/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc443/database.yaml new file mode 100644 index 0000000..152bc43 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc443/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc242 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0xFFFF + external: false + internal-flash1: + start_int: 0x1_0000 + size_int: 0xFFFF + external: false + sram-l: + start_int: 0x1FFF_F000 + size_int: 0xFFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x2FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc444/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc444/database.yaml new file mode 100644 index 0000000..bffb9b2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxc444/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxc443 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash0: + start_int: 0x0 + size_int: 0x1_FFFF + external: false + internal-flash1: + start_int: 0x2_0000 + size_int: 0x1_FFFF + external: false + sram-l: + start_int: 0x1FFF_E000 + size_int: 0x1FFF + external: false + sram-u: + start_int: 0x2000_0000 + size_int: 0x5FFF + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/database.yaml new file mode 100644 index 0000000..60bb80e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/database.yaml @@ -0,0 +1,62 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True + purpose: MCX Series + spsdk_predecessor_name: mcxe24x + web: https://www.nxp.com/products/MCX-E24 + memory_map: + internal-flash_ns: + start_int: "0x0" + size_int: "0x40000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + isp: + flashloader: + protocol: mboot + interfaces: ["uart", "spi"] + +features: + # ======== Blhost section ======== + blhost: {} + + comm_buffer: + address: 0x2000_0000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinFcf + - Mbi_ExportMixinApp + images: + xip: + plain: plain_xip + + # ======== FCF section ======== + fcf: + reg_spec: fcf.json + reg_spec_modification: + field000: + reverse: True + config_as_hexstring: True + + she_scec: { + flash_size_cfg_enabled : False + } diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/fcf.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/fcf.json new file mode 100644 index 0000000..91a902f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe245/fcf.json @@ -0,0 +1,562 @@ +{ + "cpu": "mcxc141", + "groups": [ + { + "group": { + "name": "General regs", + "description": "FCF registers generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "name": "BACKDOOR_KEY", + "offset_int": "0", + "default_value_int": "0xFFFFFFFFFFFFFFFF", + "reg_width": 64, + "description": "Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access." + }, + { + "id": "field008", + "name": "FPROT", + "description": "Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3).", + "offset_int": "0x008", + "default_value_int": "0xFFFFFFFF", + "reg_width": 32, + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "FPROT3", + "description": "Program Flash Protection Registers (FPROT3)" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "FPROT2", + "description": "Program Flash Protection Registers (FPROT2)" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "FPROT1", + "description": "Program Flash Protection Registers (FPROT1)" + }, + { + "width": 8, + "id": "field008-bits24-31", + "name": "FPROT0", + "description": "Program Flash Protection Registers (FPROT0)" + } + ] + }, + { + "id": "field00C", + "name": "FSEC", + "description": "Flash security byte. Refer to the description of the Flash Security Register (FSEC).", + "offset_int": "0x00C", + "reg_width": 8, + "bitfields": [ + { + "width": 2, + "id": "field00C-bits0-1", + "name": "SEC", + "description": "Flash Security.", + "values": [ + { + "name": "SECURE_0", + "value": 0, + "description": "MCU security status is secure." + }, + { + "name": "SECURE", + "value": 1, + "description": "MCU security status is secure." + }, + { + "name": "UNSECURE", + "value": 2, + "description": "MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)" + }, + { + "name": "SECURE_3", + "value": 3, + "description": "MCU security status is secure." + } + ] + }, + { + "width": 2, + "id": "field00C-bits2-3", + "name": "FSLACC", + "description": "Factory Security Level Access Code.", + "values": [ + { + "name": "GRANTED_0", + "value": 0, + "description": "NXP factory access granted" + }, + { + "name": "DENIED_1", + "value": 1, + "description": "NXP factory access denied" + }, + { + "name": "DENIED_2", + "value": 2, + "description": "NXP factory access denied" + }, + { + "name": "GRANTED_3", + "value": 3, + "description": "NXP factory access granted" + } + ] + }, + { + "width": 2, + "id": "field00C-bits4-5", + "name": "MEEN", + "description": "Mass Erase Enable. Enables and disables mass erase capability of the flash memory module.", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Mass erase is enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Mass erase is enabled" + }, + { + "name": "DISABLED", + "value": 2, + "description": "Mass erase is disabled" + }, + { + "name": "ENABLED_3", + "value": 3, + "description": "Mass erase is enabled" + } + ] + }, + { + "width": 2, + "id": "field00C-bits6-7", + "name": "KEYEN", + "description": "Backdoor Key Security Enable. Enables or disables backdoor key access to the flash memory module.", + "values": [ + { + "name": "DISABLED_0", + "value": 0, + "description": "Backdoor key access disabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)" + }, + { + "name": "ENABLED", + "value": 2, + "description": "Backdoor key access enabled" + }, + { + "name": "DISABLED_3", + "value": 3, + "description": "Backdoor key access disabled" + } + ] + } + ], + "default_value_int": "0xfe" + }, + { + "id": "field00D", + "name": "FOPT", + "description": "Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT).", + "offset_int": "0x00D", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00D-bit0", + "name": "LPBOOT", + "description": "Controls the reset value of clock divider of IRC 48 Mhz to feed the Core and platform clocks. Larger divide value selections produce lower average power consumption during POR and reset sequencing and after reset exit.", + "values": [ + { + "name": "DIV_BY_2", + "value": 0, + "description": "Core and system clock divider (OUTDIV1) is 0x1 (divide by 2)." + }, + { + "name": "DIV_BY_1", + "value": 1, + "description": "Core and system clock divider (OUTDIV1) is 0x0 (divide by 1)." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field00D-bit2", + "name": "NMI_PIN_CFG", + "description": "Enables/disables control for the NMI function.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "NMI interrupts are always blocked. The associated pin continues to default to NMI_b pin controls with internal pullup enabled. When NMI_b pin function is disabled, it cannot be used as a source for low-power mode wake-up. If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by writing 0 to NMI_PIN_CFG." + }, + { + "name": "ENABLE", + "value": 1, + "description": "NMI_b pin/interrupts reset default to enabled." + } + ] + }, + { + "width": 1, + "id": "field00D-bit3", + "name": "RESET_PIN_CFG", + "description": "Enables/disables control for the RESET pin.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "RESET_B pin is disabled following a POR and cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp where the MCU drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. This bit is preserved through system resets and low-power modes. When RESET_B pin function is disabled, it cannot be used as a source for low-power mode wake-up." + }, + { + "name": "ENABLE", + "value": 1, + "description": "The port is configured with pullup enabled, passive filter enabled." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + } + ] + }, + { + "id": "field00E", + "name": "FEPROT", + "description": "EEPROM Region Protect. Individual emulated EEPROM regions can be protected from alteration by setting the associated EPROT bit to the protected state. The EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured EEPROM data. In NVM Normal mode: The protection can only be increased, meaning currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data by writing to any protected area in the emulated EEPROM results in a protection violation error and sets the FSTAT[FPVIOL] bit.", + "offset_int": "0x00E", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00E-bit0", + "name": "EPROT0", + "description": "EEPROM Region Protect Bit 0 - Controls protection for 1/8th of the EEPROM data (first region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 0 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 0 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit1", + "name": "EPROT1", + "description": "EEPROM Region Protect Bit 1 - Controls protection for 1/8th of the EEPROM data (second region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 1 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 1 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit2", + "name": "EPROT2", + "description": "EEPROM Region Protect Bit 2 - Controls protection for 1/8th of the EEPROM data (third region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 2 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 2 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit3", + "name": "EPROT3", + "description": "EEPROM Region Protect Bit 3 - Controls protection for 1/8th of the EEPROM data (fourth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 3 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 3 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit4", + "name": "EPROT4", + "description": "EEPROM Region Protect Bit 4 - Controls protection for 1/8th of the EEPROM data (fifth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 4 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 4 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit5", + "name": "EPROT5", + "description": "EEPROM Region Protect Bit 5 - Controls protection for 1/8th of the EEPROM data (sixth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 5 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 5 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit6", + "name": "EPROT6", + "description": "EEPROM Region Protect Bit 6 - Controls protection for 1/8th of the EEPROM data (seventh region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 6 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 6 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00E-bit7", + "name": "EPROT7", + "description": "EEPROM Region Protect Bit 7 - Controls protection for 1/8th of the EEPROM data (eighth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "EEPROM region 7 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "EEPROM region 7 is not protected" + } + ] + } + ] + + }, + { + "id": "field00F", + "name": "FDPROT", + "description": "Data Flash Region Protect. Individual data flash regions can be protected from program and erase operations by setting the associated DPROT bit to the protected state. Each DPROT bit protects one-eighth of the partitioned data flash memory space. The granularity of data flash protection cannot be less than the data flash sector size. If an unused DPROT bit is set to the protected state, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL] bit. Unprotected regions are marked with a 1 and protected regions use a 0. Trying to alter data in any protected area in the data flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit.", + "offset_int": "0x00F", + "default_value_int": "0xFF", + "reg_width": 8, + "bitfields": [ + { + "width": 1, + "id": "field00F-bit0", + "name": "DPROT0", + "description": "Data Flash Region Protect Bit 0 - Controls protection for 1/8th of the data flash (first region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 0 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 0 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit1", + "name": "DPROT1", + "description": "Data Flash Region Protect Bit 1 - Controls protection for 1/8th of the data flash (second region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 1 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 1 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit2", + "name": "DPROT2", + "description": "Data Flash Region Protect Bit 2 - Controls protection for 1/8th of the data flash (third region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 2 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 2 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit3", + "name": "DPROT3", + "description": "Data Flash Region Protect Bit 3 - Controls protection for 1/8th of the data flash (fourth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 3 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 3 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit4", + "name": "DPROT4", + "description": "Data Flash Region Protect Bit 4 - Controls protection for 1/8th of the data flash (fifth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 4 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 4 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit5", + "name": "DPROT5", + "description": "Data Flash Region Protect Bit 5 - Controls protection for 1/8th of the data flash (sixth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 5 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 5 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit6", + "name": "DPROT6", + "description": "Data Flash Region Protect Bit 6 - Controls protection for 1/8th of the data flash (seventh region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 6 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 6 is not protected" + } + ] + }, + { + "width": 1, + "id": "field00F-bit7", + "name": "DPROT7", + "description": "Data Flash Region Protect Bit 7 - Controls protection for 1/8th of the data flash (eighth region)", + "values": [ + { + "name": "PROTECTED", + "value": 0, + "description": "Data Flash region 7 is protected" + }, + { + "name": "UNPROTECTED", + "value": 1, + "description": "Data Flash region 7 is not protected" + } + ] + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe246/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe246/database.yaml new file mode 100644 index 0000000..f77d6e6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe246/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxe245 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe247/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe247/database.yaml new file mode 100644 index 0000000..f77d6e6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe247/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxe245 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe315/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe315/database.yaml new file mode 100644 index 0000000..4c97675 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe315/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxe31b + +info: + memory_map: + internal-flash0: + start_int: "0x40_0000" + size_int: "0x8_0000" + external: false + internal-flash1: + start_int: "0x1000_0000" + size_int: "0x1_0000" + external: false + sram0: + start_int: "0x2040_0000" + size_int: "0x4000" + external: false + non_xip_type: int_ram diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe316/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe316/database.yaml new file mode 100644 index 0000000..023dba5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe316/database.yaml @@ -0,0 +1,26 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxe31b + +info: + memory_map: + internal-flash0: + start_int: "0x40_0000" + size_int: "0x8_0000" + external: false + internal-flash1: + start_int: "0x48_0000" + size_int: "0x8_0000" + external: false + internal-flash2: + start_int: "0x1000_0000" + size_int: "0x1_0000" + external: false + sram0: + start_int: "0x2040_0000" + size_int: "0x8000" + external: false + non_xip_type: int_ram + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe317/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe317/database.yaml new file mode 100644 index 0000000..5a62c0d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe317/database.yaml @@ -0,0 +1,25 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxe31b + +info: + memory_map: + internal-flash0: + start_int: "0x40_0000" + size_int: "0x10_0000" + external: false + internal-flash1: + start_int: "0x50_0000" + size_int: "0x10_0000" + external: false + internal-flash2: + start_int: "0x1000_0000" + size_int: "0x2_0000" + external: false + sram0: + start_int: "0x2040_0000" + size_int: "0x1_8000" + external: false + non_xip_type: int_ram diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe31b/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe31b/database.yaml new file mode 100644 index 0000000..179f9d6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxe31b/database.yaml @@ -0,0 +1,92 @@ +# Copyright 2024-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com/products/MCX-E31 + memory_map: + internal-flash0: + start_int: "0x40_0000" + size_int: "0x10_0000" + external: false + internal-flash1: + start_int: "0x50_0000" + size_int: "0x10_0000" + external: false + internal-flash2: + start_int: "0x60_0000" + size_int: "0x10_0000" + external: false + internal-flash3: + start_int: "0x70_0000" + size_int: "0x10_0000" + external: false + internal-flash4: + start_int: "0x1000_0000" + size_int: "0x2_0000" + external: false + sram0: + start_int: "0x2040_0000" + size_int: "0x2_8000" + external: false + non_xip_type: int_ram + sram1: + start_int: "0x2042_8000" + size_int: "0x2_8000" + external: false + non_xip_type: int_ram + isp: + flashloader: + protocol: mboot + interfaces: ["uart", "spi"] + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2040_1000 + size: 0x1000 + + # ======== Blhost section ======== + blhost: {} + + # ======== MBI section ======== + mbi: + ivt_type: Mbi_MixinHseIvt + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinHseIvt + - Mbi_MixinHseApp + - Mbi_ExportMixinHseApp + - Mbi_MixinHseLifecycle + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinHseIvt + - Mbi_MixinHseApp + - Mbi_MixinHseAppBootHeader + - Mbi_ExportMixinHseSignature + - Mbi_MixinHseLifecycle + - Mbi_ExportMixinHseAppSigned + images: + xip: + plain: plain_xip + signed: signed_xip + + # ======== EdgeLock Enclave section ======== + ele: + ele_device: mboot + + # ======== Hardware Security Engine === ===== + hse: + sub_features: [hse_attribute, key_import, key_catalog, smr] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl253/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl253/database.yaml new file mode 100644 index 0000000..698bbbb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl253/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxl255 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x2_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x8000 + external: false + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x1_E000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl254/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl254/database.yaml new file mode 100644 index 0000000..5d1cb10 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl254/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxl255 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x4_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x1_0000 + external: false + +features: + # ======== PFR section ======== + pfr: + cmpa: # CMPA description + address: 0x3_E000 \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/database.yaml new file mode 100644 index 0000000..7fdf94a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/database.yaml @@ -0,0 +1,118 @@ +# Copyright 2024-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: {} +latest: a1 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x8_0000 + external: false + sram: + start_int: 0x2000_0000 + size_int: 0x2_0000 + external: false + isp: + rom: + protocol: mboot + interfaces: ["uart", "spi", "i2c"] + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + size: 0x1000 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinImageVersion + - Mbi_ExportMixinApp + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + + # ======== DAT section ======== + dat: + dmbox_ap_ix: 1 # Typical Index of debug mailbox access port is 2 + non_standard_statuses: # dictionary of non standard return statuses from various commands + 2: # Command get_crp_level + 0xFFFF_FFFF: ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state + 0xEEBA_04C3: ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available + 0x4939_8D8B: ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available + 0xB0AB_B703: ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available + + # ======== PFR section ======== + pfr: + sub_features: [cmpa] + cmpa: # CMPA description + erase_method: flash_erase + address: 0x7_e000 + size: 256 + reg_spec: pfr_cmpa.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + key_wraps_version: 2 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSBc] + header_version: 2 + oem_share_output_size: 64 + oem_master_share_output_size: 96 + supported_commands: + - erase + - load + - loadKeyBlob + - execute diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/pfr_cmpa.json new file mode 100644 index 0000000..cd90def --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxl255/pfr_cmpa.json @@ -0,0 +1,4591 @@ +{ + "cpu": "mcxl255", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "LPSPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "LPI2C slave ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Core Clock Default value is 48MHz", + "values": [ + { + "name": "FRO_48_MHZ", + "value": 0, + "description": "48Mhz FRO @1v0" + }, + { + "name": "FRO_96_MHZ", + "value": 1, + "description": "96MHz FRO @1v1" + } + ] + }, + { + "width": 2, + "id": "field000-bits14-15", + "name": "AGDET_RE_EN", + "description": "Enablement and arming of security detectors (LVD, HVD, AGDET)", + "values": [ + { + "name": "ENABLED_0b00", + "value": 0, + "description": "Enable AGDET reset" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Don't enable AGDET reset" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Enable AGDET reset" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Enable AGDET reset" + } + ] + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963. If the CMPA header marker is 16'hFFFF and the device is in the Develop lifecycle state, the main flash permission is R/W/X. When the CMPA header marker is valid, the permissions of the sectors of the main flash will depend on the values written for the flash access control. The flash access control values start at offset 0x40 in the CMPA" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 7, + "id": "field004-bits0-6", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. This field should be written to remap field in flash" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. ROM toggles the GPIO pin identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. Note, use QUICK_SET_/CLR_GPIOx field to set the default level of pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field010", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field010-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits12-15", + "name": "UART_ISP_INSTANCE", + "description": "Identifies the LPUART instance used for UART ISP mode" + }, + { + "width": 8, + "id": "field010-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field010-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field010-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate.Baud rate configured during UART ISP mode", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection" + } + ] + } + ] + }, + { + "id": "field014", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field014-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. Identifies the pin to be used as I2C_SCL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field014-bits12-15", + "name": "I2C_ISP_INSTANCE", + "description": "Identifies the LPI2C instance used for I2C ISP mode" + }, + { + "width": 8, + "id": "field014-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. Identifies the pin to be used as I2C_SDA pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field014-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field01C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field01C-bits12-15", + "name": "SPI_ISP_INSTANCE", + "description": "Identifies the LPSPI instance used for SPI ISP mode" + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "field020", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 2, + "id": "field020-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved00024", + "name": "Reserved 0x00024", + "description": "This field is reserved for internal use", + "offset_int": "0x0024", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "ISP_MISC_CFG", + "description": "ISP MISC Configuration", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field02C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field02C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEFINED", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0003C", + "description": "Reserved 00030-0003C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field040", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector", + "offset_int": "0x0040", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field040-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_2000 - 0x00_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x00_4000 - 0x00_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector (offset range 0x00_6000 - 0x00_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x00_A000 - 0x00_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x00_C000 - 0x00_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field040-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x00_E000 - 0x00_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field044", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector", + "offset_int": "0x0044", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field044-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x01_2000 - 0x01_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x01_4000 - 0x01_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector (offset range 0x01_6000 - 0x01_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x01_8000 - 0x01_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x01_A000 - 0x01_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x01_C000 - 0x01_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field044-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x01_E000 - 0x01_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field048", + "name": "FLASH_ACL_16_23", + "description": "Access control for flash sector", + "offset_int": "0x0048", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field048-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x02_2000 - 0x02_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x02_4000 - 0x02_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector (offset range 0x02_6000 - 0x02_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x02_A000 - 0x02_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x02_C000 - 0x02_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field048-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x02_E000 - 0x02_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field04C", + "name": "FLASH_ACL_24_31", + "description": "Access control for flash sector", + "offset_int": "0x004C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field04C-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x03_2000 - 0x03_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x03_4000 - 0x03_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector (offset range 0x03_6000 - 0x03_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x03_A000 - 0x03_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x03_C000 - 0x03_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field04C-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x03_E000 - 0x03_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field050", + "name": "FLASH_ACL_32_39", + "description": "Access control for flash sector", + "offset_int": "0x0050", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field050-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x04_2000 - 0x04_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x04_4000 - 0x04_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector (offset range 0x04_6000 - 0x04_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x04_A000 - 0x04_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x04_C000 - 0x04_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field050-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x04_E000 - 0x04_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field054", + "name": "FLASH_ACL_40_47", + "description": "Access control for flash sector", + "offset_int": "0x0054", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x05_2000 - 0x05_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x05_4000 - 0x05_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector (offset range 0x05_6000 - 0x05_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x05_8000 - 0x05_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x05_A000 - 0x05_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x05_C000 - 0x05_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field054-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x05_E000 - 0x05_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field058", + "name": "FLASH_ACL_48_55", + "description": "Access control for flash sector", + "offset_int": "0x0058", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field058-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x06_2000 - 0x06_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x06_4000 - 0x06_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector (offset range 0x06_6000 - 0x06_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x06_A000 - 0x06_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x06_C000 - 0x06_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field058-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x06_E000 - 0x06_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field05C", + "name": "FLASH_ACL_56_63", + "description": "Access control for flash sector", + "offset_int": "0x005C", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field05C-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_1FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x07_2000 - 0x07_3FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x07_4000 - 0x07_5FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector (offset range 0x07_6000 - 0x07_7FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_9FFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x07_A000 - 0x07_BFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x07_C000 - 0x07_DFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field05C-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x07_E000 - 0x07_FFFF)", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Data flash and unlocked (RW__). Default flash behavior with read and write access only. Instruction fetches (execute access) are blocked and generates security violation. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "Data flash and locked (RW_L). Read and write operations are allowed but execution is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "Read only Memory (ROM) and locked (R_XL). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "Data Read only memory (DROM) and locked (R__L). Read operations is allowed but write & execute are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "Read-Only-Memory (ROM) and un-locked (R_X_). Read & execute operations are allowed but write is blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "eXecute-only Memory (XOM) and un-locked (__X_). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index can be changed to another index by software. This configuration register is unlocked and updatable by application" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "eXecute-Only-Memory (XOM) and locked (__XL). Execute operations are allowed but read & write are blocked. Blocks assigned with this access control index cannot be changed to another index until next reset" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (___L). Read, Write & execute operations are blocked. Once this access control index is assigned to a block, the memory range associated with block is hidden until next reset" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field060", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0060", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0064", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0068", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 1. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x006C", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0070", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port [31:0] pins low after reset. Each bit corresponds to the pin in GPIO port 2. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot.", + "offset_int": "0x0074", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00078-0008C", + "description": "Reserved 00078-0008C" + }, + "registers": [ + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00080", + "name": "Reserved 0x00080", + "description": "This field is reserved for internal use", + "offset_int": "0x0080", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00084", + "name": "Reserved 0x00084", + "description": "This field is reserved for internal use", + "offset_int": "0x0084", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00088", + "name": "Reserved 0x00088", + "description": "This field is reserved for internal use", + "offset_int": "0x0088", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0008C", + "name": "Reserved 0x0008C", + "description": "This field is reserved for internal use", + "offset_int": "0x008C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Read Out Protection", + "description": "Read Out Protection (ROP) configuration" + }, + "registers": [ + { + "id": "field090", + "name": "ROP_STATE", + "description": "Read Out Protection (ROP) State value. Device does not support secure boot, but it does support four levels of Read Out Protection, referred as ROP_STATE. This read out protection is a mechanism that allows user to enable different levels of protection in the system. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled).", + "offset_int": "0x0090", + "default_value_int": "0xFFFFFFFF", + "bitfields": [ + { + "width": 32, + "id": "field090-bits0-31", + "name": "ROP_STATE", + "description": "ROP_STATE[31:0]", + "values": [ + { + "name": "ROP_LEVEL2", + "value": 1228508555, + "description": "ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available" + }, + { + "name": "ROP_LEVEL3", + "value": 2964043523, + "description": "ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available" + }, + { + "name": "ROP_LEVEL1", + "value": 4005168323, + "description": "ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available" + }, + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state" + } + ] + } + ] + }, + { + "id": "field094", + "name": "SBL_PROT", + "description": "Secondary Boot Loader Protection.If the field contains a value other than 0x0000_0000 or 0xFFFF_FFFF, Debug Mailbox commands and ISP commands will not be allowed at In-Field ROP1 and In-Field life cycles.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "SBL_START_ADDR", + "description": "Secondary Boot Loader Start Address.At the end of boot ROM execution, if the user does not wish boot ROM to jump at address 0x0000_0000 (default jump address) of the main flash, this field needs to be programmed with a valid flash jump address.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "ROP_STATE_DP", + "description": "Read Out Protection (ROP) State duplicate value. ROM reads ROP_STATE from ROP_STATE and ROP_STATE_DP on IFR0, does the compare, and if it does not match, resets the device; if match then programs it to SYSCON->ROP_STATE. Any other value then four listed means ROP3-like behavior (debug disabled/locked, ISP disabled). Duplicate of ROP_STATE at offset 0x90", + "offset_int": "0x00A0", + "default_value_int": "0xFFFFFFFF", + "bitfields": [ + { + "width": 32, + "id": "field0A0-bits0-31", + "name": "ROP_STATE_DP", + "description": "ROP_STATE_DP[31:0]", + "values": [ + { + "name": "ROP_LEVEL2", + "value": 1228508555, + "description": "ROP_STATE = 0x4939_8D8B. Debug disabled and locked, cannot be modified by customer, only limited debug mailbox commands available" + }, + { + "name": "ROP_LEVEL3", + "value": 2964043523, + "description": "ROP_STATE = 0xB0AB_B703. Debug disabled and locked, cannot be modified by customer, no debug mailbox commands available" + }, + { + "name": "ROP_LEVEL1", + "value": 4005168323, + "description": "ROP_STATE = 0xEEBA_04C3. Debug disabled and unlocked, can be modified by customer, only limited debug mailbox commands available" + }, + { + "name": "ROP_LEVEL0", + "value": 4294967295, + "description": "ROP_STATE = 0xFFFF_FFFF (erased FLASH value), no ROP. Default for blank state" + } + ] + } + ] + }, + { + "id": "field0A4", + "name": "SBL_PROT_DP", + "description": "Secondary Boot Loader Protection (Duplicate). Duplicate of SBL_PROT at offset 0x94", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "SBL_START_ADDR_DP", + "description": "Duplicate of SBL_START_ADDR at offset 0xA0", + "offset_int": "0x00A8", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000AC-000CC", + "description": "Reserved 000AC-000CC" + }, + "registers": [ + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Secure Installer Token", + "description": "Secure installer token" + }, + "registers": [ + { + "id": "field0D0", + "name": "SI_ERASE_TOKEN0", + "description": "Secure Installer Erase Token [0:31]. Very important: This field is used by boot ROM when the secure installer is erased. Corrupting this field will lead to the region of the flash where the secure installer is located being non-writable and non-readable.", + "offset_int": "0x00D0", + "default_value_int": "0" + }, + { + "id": "field0D4", + "name": "SI_ERASE_TOKEN1", + "description": "Secure Installer Erase Token [32:63]. Very important: This field is used by boot ROM when the secure installer is erased. Corrupting this field will lead to the region of the flash where the secure installer is located being non-writable and non-readable.", + "offset_int": "0x00D4", + "default_value_int": "0" + }, + { + "id": "field0D8", + "name": "SI_ERASE_TOKEN2", + "description": "Secure Installer Erase Token [64:95]. Very important: This field is used by boot ROM when the secure installer is erased. Corrupting this field will lead to the region of the flash where the secure installer is located being non-writable and non-readable.", + "offset_int": "0x00D8", + "default_value_int": "0" + }, + { + "id": "field0DC", + "name": "SI_ERASE_TOKEN3", + "description": "Secure Installer Erase Token [96:127]. Very important: This field is used by boot ROM when the secure installer is erased. Corrupting this field will lead to the region of the flash where the secure installer is located being non-writable and non-readable.", + "offset_int": "0x00DC", + "default_value_int": "0" + }, + { + "id": "field0E0", + "name": "SI_DELETE_TOKEN", + "description": "Secure Installer Delete Token. Token provided by NXP to indicate the desire for the user to erase the secure installer in order to reclaim the flash portion occupied by the secure installer.", + "offset_int": "0x00E0", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000E4-000FC", + "description": "Reserved 000E4-000FC" + }, + "registers": [ + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F0", + "name": "Reserved 0x000F0", + "description": "This field is reserved for internal use", + "offset_int": "0x00F0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn235/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn235/database.yaml new file mode 100644 index 0000000..48ded8c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn235/database.yaml @@ -0,0 +1,39 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn236 + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x80000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x80000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x28000" + external: false + warning_ranges: + - start_int: "0x20020000" + size_int: "0x8000" + warning_msg: RAM above 0x20020000 is not available if SRAM ECC is enabled + sramx: + start_int: "0x4000000" + size_int: "0x8000" + external: false + __comment: Does not work as target `onchip RAM` memory + ifr-bank1_ns: + start_int: "0x1008000" + size_int: "0x8000" + external: false + ifr-bank1_s: + start_int: "0x11008000" + size_int: "0x8000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/database.yaml new file mode 100644 index 0000000..0981f74 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/database.yaml @@ -0,0 +1,344 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + purpose: MCX Series + spsdk_predecessor_name: mcxn23x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X + use_in_doc: True # Remove when the device is available + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x100000" + external: false + internal-flash_s: + start_int: "0x10000000" + size_int: "0x100000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x40000" + external: false + warning_ranges: + - start_int: "0x20030000" + size_int: "0x10000" + warning_msg: RAM above 0x20030000 is not available if SRAM ECC is enabled + sramx: + start_int: "0x4000000" + size_int: "0x18000" + external: false + __comment: Does not work as target `onchip RAM` memory + ifr-bank1_ns: + start_int: "0x1008000" + size_int: "0x8000" + external: false + ifr-bank1_s: + start_int: "0x11008000" + size_int: "0x8000" + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0158 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_7000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== DAT section ======== + dat: + socc: 7 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestCrc + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestCrc + - Mbi_MixinImageSubType + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + reg_spec: pfr_cfpa.json + address: 0x100_0000 + size: 512 + seal_start: field1EC # CFPA_CRC32 + seal_count: 1 + grouped_registers: + - uid: cfpa_dice_cert + name: DICE_Certificate + width: 1152 + config_as_hexstring: true + description: + DICE Certificate field is compounded by 36 32-bit fields and contains + value of DICE Certificate generated by ROM + sub_regs: + - field100 + - field104 + - field108 + - field10C + - field110 + - field114 + - field118 + - field11C + - field120 + - field124 + - field128 + - field12C + - field130 + - field134 + - field138 + - field13C + - field140 + - field144 + - field148 + - field14C + - field150 + - field154 + - field158 + - field15C + - field160 + - field164 + - field168 + - field16C + - field170 + - field174 + - field178 + - field17C + - Reserved00180 + - Reserved00184 + - Reserved00188 + - Reserved0018C + computed_fields: + field000: # HEADER + field000-bits8-15: pfr_reg_inverse_lower_8_bits # INV_CFPA_LC_STATE + field020: # DBG_REVOKE_VU + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_PIN + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field028: # DCFG_CC_SOCU_NS_DFLT + field028-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + reg_spec: pfr_cmpa.json + address: 0x0100_4000 + size: 512 + seal_start: field1F0 # CMPA_CMAC0 + seal_count: 4 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 384 + reversed: true + config_as_hexstring: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key table hash. + Root of Trust Key Hash is SHA256 or SHA384 of RoTK public. Hash algorithm is selected + based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). + Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates + container and signed boot image based on CMPA.RoTKx_Usage. + sub_regs: + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + - field080 + - field084 + - field088 + - field08C + - uid: cmpa_keyblob + name: CUST_MK_SK_KEY_BLOB + width: 384 + reversed: false + config_as_hexstring: true + description: CUST_MK_SK key blob. + CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. + CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. + To store this key into CMPA, SB_STORE_KEY command should be used. + sub_regs: + - field160 + - field164 + - field168 + - field16C + - field170 + - field174 + - field178 + - field17C + - field180 + - field184 + - field188 + - field18C + computed_fields: + field040: # DCFG_CC_SOCU_PIN + field040-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field044: # DCFG_CC_SOCU_DFLT + field044-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + key_wraps_version: 2 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB31] + key_blob_offset: 0x0 + key_blob_command_position: -1 + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + spi_nor: + instances: [7] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi_mbi: + segments: + mbi: 0x00 + recovery_spi_sb31: + segments: + sb31: 0x00 + internal: + segments: + mbi: 0x00 + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: MCXN + prov_method: dispatch_fw + dispatch_method: sb_only + use_additional_data: true + fw_read_address: 0x2000_0100 + ignored_otp_ranges: [11, 22] + clean_method: erase_cmpa + validation_method: max_count=16;max_total_size=16384 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/fuses.json new file mode 100644 index 0000000..72d26d5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/fuses.json @@ -0,0 +1,2769 @@ +{ + "cpu": "MCXN236", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Boot configuration locks" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Boot Configuration Locks", + "index_int": "0", + "bitfields": [ + { + "width": 9 + }, + { + "width": 3, + "id": "fuse0-bits-9-11", + "name": "BOOT_CFG_LOCK[2:0]", + "description": "Boot config lock\nConfigures the locking of EFUSE bits for fuse #3, #4, #5, #6, #7 and fuses #11 - #22. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "PRINCE_CFG_LOCK[2:0]", + "description": "Prince Config Lock\nConfigures the locking EFUSE bits for fuses #23 - #30. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-15-17", + "name": "OSCAA_KEY_LOCK[2:0]", + "description": "OSCAA Key Lock\nConfigures the locking EFUSE bits for fuses #39 - #42. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked001", + "value": 0, + "description": "Unlocked001 - Locked for programming [WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-18-20", + "name": "CUST_LOCK0[2:0]", + "description": "CUST Lock 0\nConfigures the locking of EFUSE bits for fuses #43, #44, #45 and #46. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-21-23", + "name": "CUST_LOCK1[2:0]", + "description": "CUST Lock 1\nConfigures the locking of EFUSE bits for fuses #47, #48, #49 and #50. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-24-26", + "name": "CUST_LOCK2[2:0]", + "description": "CUST Lock 2\nConfigures the locking of EFUSE bits for fuses #51, #52, #53 and #54. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-27-29", + "name": "CUST_LOCK3[2:0]", + "description": "CUST Lock 3\nConfigures the locking EFUSE bits for fuses #55 - #62. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 2 + } + ] + } + ] + }, + { + "group": { + "name": "Configurations", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse1", + "name": "LIFE_CYCLE", + "description": "Life cycle state, debug setting, and ROTK setting", + "index_int": "0x0001", + "bitfields": [ + { + "width": 8, + "id": "fuse1-bits-0-7", + "name": "LIFECYCLE[7:0]", + "description": "Life cycle state.\nThis field can be used to advance life cycle state. Below are the allowed values for this field. Use of other values may lead to bricked state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-8", + "name": "NIDEN_dis", + "description": "Disable Non-secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-9", + "name": "DBGEN_dis", + "description": "Disable Non-secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-10", + "name": "SPIDEN_dis", + "description": "Disable Secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-11", + "name": "SPNIDEN_dis", + "description": "Disable Secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse1-bit-15", + "name": "ISP_CMD_dis", + "description": "Disable Enter ISP Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-16", + "name": "FA_CMD_dis", + "description": "Disable Set FA mode Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-17", + "name": "ME_CMD_dis", + "description": "Disable Mass erase Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-18", + "name": "UUID_CHECK_ENF", + "description": "Enforce UUID checking during debug authentication", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Enable", + "value": 1, + "description": "Always enabled." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse1-bit-20", + "name": "RoTK0_dis", + "description": "Revoke Root of Trust key 0.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-21", + "name": "RoTK1_dis", + "description": "Revoke Root of Trust key 1.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-22", + "name": "RoTK2_dis", + "description": "Revoke Root of Trust key 2.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-23", + "name": "RoTK3_dis", + "description": "Revoke Root of Trust key 3.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 8, + "id": "fuse1-bits-24-31", + "name": "LIFECYCLE_DP[7:0]", + "description": "Duplicate of the LIFECYCLE fuse value.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + } + ] + }, + { + "id": "fuse2", + "name": "KEY_REVOKE", + "description": "Image key revoke and PRINCE, PUF, and NXP provisioning firmware setting", + "index_int": "0x0002", + "bitfields": [ + { + "width": 8, + "id": "fuse2-bits-0-7", + "name": "DBG_KEY_REVOKE[7:0]", + "description": "Debug key revoke.\nThis field is combined with\nCFPA.DBG_REVOKE_VU and CMPA.VENDOR_USAGE fields to form a 32-bit value which is compared with vendor usage field in debug credential certificate. Only if the values match debug access is granted.\nCC_VENDOR_USAGE = { CMPA.VENDOR_USAGE[31:16],\nCFPA.DBG_REVOKE_VU[15:8],\n(CFPA.DBG_REVOKE_VU[7:0] | OTP.DBG_KEY_REVOKE[7:0]) }" + }, + { + "width": 8, + "id": "fuse2-bits-8-15", + "name": "IMAGE_KEY_REVOKE[7:0]", + "description": "Image signing key revoke.\nThis field is combined with\nCFPA.IMAGE_KEY_REVOKE field to form a 32-bit value which is compared with IskCertificate.constraints field during image authentication. If the values don't match image authentication fails.\nISK_CONSTRAINT[31:0] = {CFPA.IMAGE_KEY_REVOKE_VU[23:0], OTP.IMAGE_KEY_REVOKE[7:0] }" + }, + { + "width": 4 + }, + { + "width": 1, + "id": "fuse2-bit-20", + "name": "PUF_ENROLL_DIS", + "description": "Block PUF enrollment.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse2-bit-23", + "name": "DIS_NXP_FW", + "description": "Block NXP signed SB3 loading.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow NXP signed SB3 FW" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable NXP signed SB3 FW" + } + ] + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse3", + "name": "BOOT_CFG", + "description": "ISP pin selection setting and boot configuration setting", + "index_int": "0x0003", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse3-bit-1", + "name": "Boot_flash_Dis", + "description": "Disable boot from internal flash.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from internal flash enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from internal flash disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-2", + "name": "Boot_IFR0_Dis", + "description": "Disable boot from IFR0 (as SBL).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from IFR0 enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from IFR0 disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse3-bit-5", + "name": "RBoot_SPI_Dis", + "description": "Disable recovery boot from external 1-bit SPI flash connected to FlexComm ports.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-6", + "name": "RBoot_IFR0_Dis", + "description": "Disable recovery boot from IFR0 area( 0x0100_8000 to 0x0100_FFFF).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-7", + "name": "PinSel_SPI_RBoot_Dis", + "description": "Disable logic related to forcing recovery boot based on ISP pin state.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-8", + "name": "ISP_UART_Dis", + "description": "Disable UART interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "UART ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "UART ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-9", + "name": "ISP_I2C_Dis", + "description": "Disable I2C interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "I2C ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "I2C ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-10", + "name": "ISP_SPI_Dis", + "description": "Disable SPI interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SPI ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "SPI ISP is disabled." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse3-bit-12", + "name": "ISP_USB1_Dis", + "description": "Disable USB0 interface in ISP mode", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "USB0 ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "USB0 ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-13", + "name": "ISP_CAN_Dis", + "description": "Disable CAN interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "CAN ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "CAN ISP is disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse3-bits-16-17", + "name": "ISP_DISABLE[1:0]", + "description": "Disable ISP mode entry points.\nISP mode can be entered through pin assertion, debug mailbox command, image verification failure and ROM API invocation", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "All entry point allowed." + }, + { + "name": "Disable_ISP_pin", + "value": 1, + "description": "Entry by ISP Pin assertion disabled." + }, + { + "name": "Disable", + "value": 2, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + }, + { + "name": "Disable_0", + "value": 3, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + } + ] + }, + { + "width": 4 + }, + { + "width": 2, + "id": "fuse3-bits-22-23", + "name": "BOOT_SPEED[1:0]", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution.", + "values": [ + { + "name": "CMPA_BOOT_SPEED", + "value": 0, + "description": "Use value from CMPA.BOOT_SPEED" + }, + { + "name": "72MHz FRO", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "144MHz FRO", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "150MHz PLL", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 5, + "id": "fuse3-bits-24-28", + "name": "FLASH_REMAP_SZ[4:0]", + "description": "Flash remap size.\nFLASH_REMAP_SZ defines the size of the secondary boot image\n(the range of flash addresses that will be remapped)in internal flash, where remapped\naddress end = (FLASH_REMAP_SZ + 1) * 32 KB. For example, if FLASH_REMAP_SZ = 2,\nthen the first 96KB of addresses will be remapped to flash bank1 instead of flash bank0\nwhen remap is active. Set this field to 0 if you do not want to use the flash remap feature" + }, + { + "width": 3, + "id": "fuse3-bits-29-31", + "name": "OEM_BANK1_IFR0_USAGE[2:0]", + "description": "Defines flash protection of Bank1_IFR0 area based on usage.\nNote, if the SBL / Recovery image size is more than IFR0 size of 32KB then sectors from user flash can be associated for extended image size using CMPA.REC_IMG_EXT0/1.", + "values": [ + { + "name": "000", + "value": 0, + "description": "Not determined by ROM (MBC fields are modified by OEM code)" + }, + { + "name": "001", + "value": 1, + "description": "Used as OEM Root of Trust image, in other words secondary boot loader (OEM_SBL). MBC protection bits set as RWXL = 1010. Updatable by OEM code later." + }, + { + "name": "010", + "value": 2, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 1011." + }, + { + "name": "011", + "value": 3, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 0011." + }, + { + "name": "100", + "value": 4, + "description": "Used as OEM recovery boot image with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1010 on ROM exiting to user image." + }, + { + "name": "101", + "value": 5, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1011 on ROM exiting to user image." + }, + { + "name": "110", + "value": 6, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0011 on ROM exiting to user image." + }, + { + "name": "111", + "value": 7, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0001 on ROM exiting to user image." + } + ] + } + ] + }, + { + "id": "fuse6", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration 0", + "index_int": "0x0006", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse6-bits-0-1", + "name": "SEC_BOOT_EN[1:0]", + "description": "Secure boot enforcement.\nThis field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign).\nThe Image type field in header indicates the type of verification data (checksum or signature) included in it.\nPlain < CRC32 < CMAC < ECDSA", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed." + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed." + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse6-bits-3-4", + "name": "LP_SEC_BOOT[1:0]", + "description": "Secure boot option for low-power wake from power-down & deep-powerdown.\nFor CFPA/CMPA do CRC check always.", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA." + }, + { + "name": "CHECK_CMAC", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "fuse6-bits-8-9", + "name": "ENF_CNSA[1:0]", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication.\nNote, CMAC image authentication is only allowed in 2b'00 setting.", + "values": [ + { + "name": "ALL_ALLOWED", + "value": 0, + "description": "All algorithm allowed." + }, + { + "name": "LIMITED", + "value": 1, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_0", + "value": 2, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_1", + "value": 3, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-10-11", + "name": "ENF_TZM_PRESET[1:0]", + "description": "TrustZone-M mode.", + "values": [ + { + "name": "IGNORE", + "value": 0, + "description": "Ignored." + }, + { + "name": "ENFORCE", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_0", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_1", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "ITRC_ZEROIZE[1:0]", + "description": "RAM zeroize on ITRC event.\nZeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion & Tamper control signals an intrusion event (ITRC_OUT3).\nNote, when ITRC is re-configured in application then ITRC_OUT4 (CHIP_RESET) should be triggered with at least same events as ITRC_OUT3 (RAM_ZEROIZE).", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action." + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only." + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only." + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "ACTIVE_IMG_PROT[1:0]", + "description": "Protection of active image.\nThis field defines protection of flash area occupied by the active image. Only applicable to internal flash.", + "values": [ + { + "name": "FLASH_ACL_PROTECTION", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings." + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored." + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored." + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "XOM protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-16-17", + "name": "FIPS_SHA_STEN[1:0]", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-18-19", + "name": "FIPS_AES_STEN[1:0]", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-20-21", + "name": "FIPS_ECDSA_STEN[1:0]", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "FIPS_DRBG_STEN[1:0]", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-24-25", + "name": "FIPS_CMAC_STEN[1:0]", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-26-27", + "name": "FIPS_KDF_STEN[1:0]", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-28-29", + "name": "FIPS_PUF_STEN[1:0]", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse7", + "name": "RoTK_USAGE", + "description": "Secure Boot Configuration 1", + "index_int": "0x0007", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse7-bits-0-2", + "name": "RoTK0_Usage[2:0]", + "description": "RoT key 0 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-3-5", + "name": "RoTK1_Usage[2:0]", + "description": "RoT key 1 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-6-8", + "name": "RoTK2_Usage[2:0]", + "description": "RoT key 2 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW_IMG", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-9-11", + "name": "RoTK3_Usage[2:0]", + "description": "RoT key 3 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "SKIP_DICE", + "description": "Skip DICE computation.", + "values": [ + { + "name": "Enable DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "Disable DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 9 + }, + { + "width": 2, + "id": "fuse7-bits-24-25", + "name": "NPX_LOCK_CTX0[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 0 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-26-27", + "name": "NPX_LOCK_CTX1[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 1 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-28-29", + "name": "NPX_LOCK_CTX2[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 2 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-30-31", + "name": "NPX_LOCK_CTX3[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 3 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "Root of trust keys configuration" + }, + "registers": [ + { + "id": "fuse11", + "name": "ROTKH0", + "description": "Root of Trust Keys Table Hash 0 (ROTKH[31:0])", + "index_int": "0x000B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse11-bits-0-31", + "name": "ROTKH[31:0]", + "description": "Root of Trust Keys Table Hash 0 (ROTKH[31:0])\nSHA384 ROTKH[383:352] / SHA56 ROTKH[255:224]" + } + ] + }, + { + "id": "fuse12", + "name": "ROTKH1", + "description": "Root of Trust Keys Table Hash 1 (ROTKH[63:32])", + "index_int": "0x000C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse12-bits-0-31", + "name": "ROTKH[63:32]", + "description": "Root of Trust Keys Table Hash 1 (ROTKH[63:32])\nSHA384 ROTKH[351:320] / SHA56 ROTKH[223:192]" + } + ] + }, + { + "id": "fuse13", + "name": "ROTKH2", + "description": "Root of Trust Keys Table Hash 2 (ROTKH[95:64])", + "index_int": "0x000D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse13-bits-0-31", + "name": "ROTKH[95:64]", + "description": "Root of Trust Keys Table Hash 2 (ROTKH[95:64])\nSHA384 ROTKH[319:288] / SHA56 ROTKH[191:160]" + } + ] + }, + { + "id": "fuse14", + "name": "ROTKH3", + "description": "Root of Trust Keys Table Hash 3 (ROTKH[127:96])", + "index_int": "0x000E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse14-bits-0-31", + "name": "ROTKH[127:96]", + "description": "Root of Trust Keys Table Hash 3 (ROTKH[127:96])\nSHA384 ROTKH[287:256] / SHA56 ROTKH[159:128]" + } + ] + }, + { + "id": "fuse15", + "name": "ROTKH4", + "description": "Root of Trust Keys Table Hash 4 (ROTKH[159:128])", + "index_int": "0x000F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse15-bits-0-31", + "name": "ROTKH[159:128]", + "description": "Root of Trust Keys Table Hash 4 (ROTKH[159:128])\nSHA384 ROTKH[255:224] / SHA56 ROTKH[127:96]" + } + ] + }, + { + "id": "fuse16", + "name": "ROTKH5", + "description": "Root of Trust Keys Table Hash 5 (ROTKH[191:160])", + "index_int": "0x0010", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse16-bits-0-31", + "name": "ROTKH[191:160]", + "description": "Root of Trust Keys Table Hash 5 (ROTKH[191:160])\nSHA384 ROTKH[223:192] / SHA56 ROTKH[95:64]" + } + ] + }, + { + "id": "fuse17", + "name": "ROTKH6", + "description": "Root of Trust Keys Table Hash 6 (ROTKH[223:192])", + "index_int": "0x0011", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse17-bits-0-31", + "name": "ROTKH[223:192]", + "description": "Root of Trust Keys Table Hash 6 (ROTKH[223:192])\nSHA384 ROTKH[191:160] / SHA56 ROTKH[63:32]", + "deprecated_names": [ + "ROTKH[232:192]" + ] + } + ] + }, + { + "id": "fuse18", + "name": "ROTKH7", + "description": "Root of Trust Keys Table Hash 7 (ROTKH[255:224])", + "index_int": "0x0012", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse18-bits-0-31", + "name": "ROTKH[255:224]", + "description": "Root of Trust Keys Table Hash 7 (ROTKH[255:224])\nSHA384 ROTKH[159:128 / SHA56 ROTKH[31:0]" + } + ] + }, + { + "id": "fuse19", + "name": "ROTKH8", + "description": "Root of Trust Keys Table Hash 8 (ROTKH[287:256])", + "index_int": "0x0013", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse19-bits-0-31", + "name": "ROTKH[287:256]", + "description": "Root of Trust Keys Table Hash 8 (ROTKH[287:256])\nSHA384 ROTKH[127:96] / 0" + } + ] + }, + { + "id": "fuse20", + "name": "ROTKH9", + "description": "Root of Trust Keys Table Hash 9 (ROTKH[319:288])", + "index_int": "0x0014", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse20-bits-0-31", + "name": "ROTKH[319:288]", + "description": "Root of Trust Keys Table Hash 9 (ROTKH[319:288])\nSHA384 ROTKH[95:64] / 0" + } + ] + }, + { + "id": "fuse21", + "name": "ROTKH10", + "description": "Root of Trust Keys Table Hash 10 (ROTKH[351:320])", + "index_int": "0x0015", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse21-bits-0-31", + "name": "ROTKH[351:320]", + "description": "Root of Trust Keys Table Hash 10 (ROTKH[351:320])\nSHA384 ROTKH[63:32] / 0" + } + ] + }, + { + "id": "fuse22", + "name": "ROTKH11", + "description": "Root of Trust Keys Table Hash 11 (ROTKH[383:352])", + "index_int": "0x0016", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse22-bits-0-31", + "name": "ROTKH[383:352]", + "description": "Root of Trust Keys Table Hash 11 (ROTKH[383:352])\nSHA384 ROTKH[31:0] / 0" + } + ] + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "Prince Context configuration" + }, + "registers": [ + { + "id": "fuse23", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors 0 - 31)", + "index_int": "0x0017", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse23-bits-0-31", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX0_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key & IV. NPX_CTX0_WD0[31:0]" + } + ] + }, + { + "id": "fuse25", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors 0 - 31)", + "index_int": "0x0019", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse25-bits-0-31", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX1_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key & IV. NPX_CTX1_WD0[31:0]" + } + ] + }, + { + "id": "fuse27", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors 0 - 31)", + "index_int": "0x001B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse27-bits-0-31", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX2_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key & IV. NPX_CTX2_WD0[31:0]" + } + ] + }, + { + "id": "fuse29", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors 0 - 31)", + "index_int": "0x001D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse29-bits-0-31", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX3_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key & IV. NPX_CTX3_WD0[31:0]" + } + ] + } + ] + }, + { + "group": { + "name": "OSCAA", + "description": "OSCAA key configuration" + }, + "registers": [ + { + "id": "fuse39", + "name": "OSCAA_KEY0", + "description": "OSCAA_KEY[31:0]", + "index_int": "0x0027", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse39-bits-0-31", + "name": "OSCAA_KEY0", + "description": "OSCAA_KEY[31:0]" + } + ] + }, + { + "id": "fuse40", + "name": "OSCAA_KEY1", + "description": "OSCAA_KEY[63:32]", + "index_int": "0x0028", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse40-bits-0-31", + "name": "OSCAA_KEY1", + "description": "OSCAA_KEY[63:32]" + } + ] + }, + { + "id": "fuse41", + "name": "OSCAA_KEY2", + "description": "OSCAA_KEY[95:64]", + "index_int": "0x0029", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse41-bits-0-31", + "name": "OSCAA_KEY2", + "description": "OSCAA_KEY[95:64]" + } + ] + }, + { + "id": "fuse42", + "name": "OSCAA_KEY3", + "description": "OSCAA_KEY[127:96]", + "index_int": "0x002A", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse42-bits-0-31", + "name": "OSCAA_KEY3", + "description": "OSCAA_KEY[127:96]" + } + ] + } + ] + }, + { + "group": { + "name": "CUST", + "description": "Customer fuses configuration" + }, + "registers": [ + { + "id": "fuse43", + "name": "GP0", + "description": "General Purpose Fuse 0 (GP0[31:0])", + "index_int": "0x002B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse43-bits-0-31", + "name": "GP0[31:0]", + "description": "General Purpose Fuse 0 (GP0[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse44", + "name": "GP1", + "description": "General Purpose Fuse 1 (GP1[31:0])", + "index_int": "0x002C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse44-bits-0-31", + "name": "GP1[31:0]", + "description": "General Purpose Fuse 1 (GP1[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse45", + "name": "GP2", + "description": "General Purpose Fuse 2 (GP2[31:0])", + "index_int": "0x002D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse45-bits-0-31", + "name": "GP2[31:0]", + "description": "General Purpose Fuse 2 (GP2[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse46", + "name": "GP3", + "description": "General Purpose Fuse 3 (GP3[31:0])", + "index_int": "0x002E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse46-bits-0-31", + "name": "GP3[31:0]", + "description": "General Purpose Fuse 3 (GP3[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse47", + "name": "GP4", + "description": "General Purpose Fuse 4 (GP4[31:0])", + "index_int": "0x002F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse47-bits-0-31", + "name": "GP4[31:0]", + "description": "General Purpose Fuse 4 (GP4[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse48", + "name": "GP5", + "description": "General Purpose Fuse 5 (GP5[31:0])", + "index_int": "0x0030", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse48-bits-0-31", + "name": "GP5[31:0]", + "description": "General Purpose Fuse 5 (GP5[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse49", + "name": "GP6", + "description": "General Purpose Fuse 6 (GP6[31:0])", + "index_int": "0x0031", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse49-bits-0-31", + "name": "GP6[31:0]", + "description": "General Purpose Fuse 6 (GP6[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse50", + "name": "GP7", + "description": "General Purpose Fuse 7 (GP7[31:0])", + "index_int": "0x0032", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse50-bits-0-31", + "name": "GP7[31:0]", + "description": "General Purpose Fuse 7 (GP7[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse51", + "name": "GP8", + "description": "General Purpose Fuse 8 (GP8[31:0])", + "index_int": "0x0033", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse51-bits-0-31", + "name": "GP8[31:0]", + "description": "General Purpose Fuse 8 (GP8[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse52", + "name": "GP9", + "description": "General Purpose Fuse 9 (GP9[31:0])", + "index_int": "0x0034", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse52-bits-0-31", + "name": "GP9[31:0]", + "description": "General Purpose Fuse 9 (GP9[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse53", + "name": "GP10", + "description": "General Purpose Fuse 10 (GP10[31:0])", + "index_int": "0x0035", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse53-bits-0-31", + "name": "GP10[31:0]", + "description": "General Purpose Fuse 10 (GP10[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse54", + "name": "GP11", + "description": "General Purpose Fuse 11 (GP11[31:0])", + "index_int": "0x0036", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse54-bits-0-31", + "name": "GP11[31:0]", + "description": "General Purpose Fuse 11 (GP11[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse55", + "name": "GP12", + "description": "General Purpose Fuse 12 (GP12[31:0])", + "index_int": "0x0037", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse55-bits-0-31", + "name": "GP12[31:0]", + "description": "General Purpose Fuse 12 (GP12[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse56", + "name": "GP13", + "description": "General Purpose Fuse 13 (GP13[31:0])", + "index_int": "0x0038", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse56-bits-0-31", + "name": "GP13[31:0]", + "description": "General Purpose Fuse 13 (GP13[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse57", + "name": "GP14", + "description": "General Purpose Fuse 14 (GP14[31:0])", + "index_int": "0x0039", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse57-bits-0-31", + "name": "GP14[31:0]", + "description": "General Purpose Fuse 14 (GP14[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse58", + "name": "GP15", + "description": "General Purpose Fuse 15 (GP15[31:0])", + "index_int": "0x003A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse58-bits-0-31", + "name": "GP15[31:0]", + "description": "General Purpose Fuse 15 (GP15[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse59", + "name": "GP16", + "description": "General Purpose Fuse 16 (GP16[31:0])", + "index_int": "0x003B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse59-bits-0-31", + "name": "GP16[31:0]", + "description": "General Purpose Fuse 16 (GP16[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse60", + "name": "GP17", + "description": "General Purpose Fuse 17 (GP17[31:0])", + "index_int": "0x003C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse60-bits-0-31", + "name": "GP17[31:0]", + "description": "General Purpose Fuse 17 (GP17[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse61", + "name": "GP18", + "description": "General Purpose Fuse 18 (GP18[31:0])", + "index_int": "0x003D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse61-bits-0-31", + "name": "GP18[31:0]", + "description": "General Purpose Fuse 18 (GP18[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse62", + "name": "GP19", + "description": "General Purpose Fuse 19 (GP19[31:0])", + "index_int": "0x003E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse62-bits-0-31", + "name": "GP19[31:0]", + "description": "General Purpose Fuse 19 (GP19[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse63", + "name": "GP20", + "description": "General Purpose Fuse 20 (GP20[31:0])", + "index_int": "0x003F", + "bitfields": [ + { + "width": 32, + "id": "fuse63-bits-0-31", + "name": "GP20[31:0]", + "description": "General Purpose Fuse 20 (GP20[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse64", + "name": "GP21", + "description": "General Purpose Fuse 21 (GP21[31:0])", + "index_int": "0x0040", + "bitfields": [ + { + "width": 32, + "id": "fuse64-bits-0-31", + "name": "GP21[31:0]", + "description": "General Purpose Fuse 21 (GP21[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse65", + "name": "GP22", + "description": "General Purpose Fuse 22 (GP22[31:0])", + "index_int": "0x0041", + "bitfields": [ + { + "width": 32, + "id": "fuse65-bits-0-31", + "name": "GP22[31:0]", + "description": "General Purpose Fuse 22 (GP22[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse66", + "name": "GP23", + "description": "General Purpose Fuse 23 (GP23[31:0])", + "index_int": "0x0042", + "bitfields": [ + { + "width": 32, + "id": "fuse66-bits-0-31", + "name": "GP23[31:0]", + "description": "General Purpose Fuse 23 (GP23[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse67", + "name": "GP24", + "description": "General Purpose Fuse 24 (GP24[31:0])", + "index_int": "0x0043", + "bitfields": [ + { + "width": 32, + "id": "fuse67-bits-0-31", + "name": "GP24[31:0]", + "description": "General Purpose Fuse 24 (GP24[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse68", + "name": "GP25", + "description": "General Purpose Fuse 25 (GP25[31:0])", + "index_int": "0x0044", + "bitfields": [ + { + "width": 32, + "id": "fuse68-bits-0-31", + "name": "GP25[31:0]", + "description": "General Purpose Fuse 25 (GP25[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse69", + "name": "GP26", + "description": "General Purpose Fuse 26 (GP26[31:0])", + "index_int": "0x0045", + "bitfields": [ + { + "width": 32, + "id": "fuse69-bits-0-31", + "name": "GP26[31:0]", + "description": "General Purpose Fuse 26 (GP26[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse70", + "name": "GP27", + "description": "General Purpose Fuse 27 (GP27[31:0])", + "index_int": "0x0046", + "bitfields": [ + { + "width": 32, + "id": "fuse70-bits-0-31", + "name": "GP27[31:0]", + "description": "General Purpose Fuse 27 (GP27[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse71", + "name": "GP28", + "description": "General Purpose Fuse 28(GP28[31:0])", + "index_int": "0x0047", + "bitfields": [ + { + "width": 32, + "id": "fuse71-bits-0-31", + "name": "GP28[31:0]", + "description": "General Purpose Fuse 28(GP28[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse72", + "name": "GP29", + "description": "General Purpose Fuse 29 (GP29[31:0])", + "index_int": "0x0048", + "bitfields": [ + { + "width": 32, + "id": "fuse72-bits-0-31", + "name": "GP29[31:0]", + "description": "General Purpose Fuse 29 (GP29[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse73", + "name": "GP30", + "description": "General Purpose Fuse 30 (GP30[31:0])", + "index_int": "0x0049", + "bitfields": [ + { + "width": 32, + "id": "fuse73-bits-0-31", + "name": "GP30[31:0]", + "description": "General Purpose Fuse 30 (GP30[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse74", + "name": "GP31", + "description": "General Purpose Fuse 31 (GP31[31:0])", + "index_int": "0x004A", + "bitfields": [ + { + "width": 32, + "id": "fuse74-bits-0-31", + "name": "GP31[31:0]", + "description": "General Purpose Fuse 31 (GP31[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse75", + "name": "GP32", + "description": "General Purpose Fuse 32 (GP32[31:0])", + "index_int": "0x004B", + "bitfields": [ + { + "width": 32, + "id": "fuse75-bits-0-31", + "name": "GP32[31:0]", + "description": "General Purpose Fuse 32 (GP32[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse76", + "name": "GP33", + "description": "General Purpose Fuse 33 (GP33[31:0])", + "index_int": "0x004C", + "bitfields": [ + { + "width": 32, + "id": "fuse76-bits-0-31", + "name": "GP33[31:0]", + "description": "General Purpose Fuse 33 (GP33[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse77", + "name": "GP34", + "description": "General Purpose Fuse 34 (GP34[31:0])", + "index_int": "0x004D", + "bitfields": [ + { + "width": 32, + "id": "fuse77-bits-0-31", + "name": "GP34[31:0]", + "description": "General Purpose Fuse 34 (GP34[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse78", + "name": "GP35", + "description": "General Purpose Fuse 35 (GP35[31:0])", + "index_int": "0x004E", + "bitfields": [ + { + "width": 32, + "id": "fuse78-bits-0-31", + "name": "GP35[31:0]", + "description": "General Purpose Fuse 35 (GP35[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse79", + "name": "GP36", + "description": "General Purpose Fuse 36 (GP36[31:0])", + "index_int": "0x004F", + "bitfields": [ + { + "width": 32, + "id": "fuse79-bits-0-31", + "name": "GP36[31:0]", + "description": "General Purpose Fuse 36 (GP36[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse80", + "name": "GP37", + "description": "General Purpose Fuse 37 (GP37[31:0])", + "index_int": "0x0050", + "bitfields": [ + { + "width": 32, + "id": "fuse80-bits-0-31", + "name": "GP37[31:0]", + "description": "General Purpose Fuse 37 (GP37[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse81", + "name": "GP38", + "description": "General Purpose Fuse 38 (GP38[31:0])", + "index_int": "0x0051", + "bitfields": [ + { + "width": 32, + "id": "fuse81-bits-0-31", + "name": "GP38[31:0]", + "description": "General Purpose Fuse 38 (GP38[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cfpa.json new file mode 100644 index 0000000..452c39e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cfpa.json @@ -0,0 +1,4377 @@ +{ + "cpu": "mcxn236", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "Header", + "description": "CFPA Header", + "offset_int": "0", + "default_value_int": "0x96350000", + "bitfields": [ + { + "width": 8, + "id": "field000-bits0-7", + "name": "CFPA_LC_STATE", + "description": "Life cycle state. This field can be used to advance life cycle state to 0x7, 0xF or 0xCF during development (OTP_LC_STATE = 0x3) for testing deployed states without programming OTP fuse. For actual mass production, be sure to modify the lifecycle through OTP/efuse rather than through CFPA_LC_STATE field. When CFPA is used to advance LC state, then application code should implement hooks, to revert CFPA_LC_STATE field to 0x3 to bring the device back to OEM_DEVELOP state (0x03). One such example is a GPIO interrupt handler invoked on a button press which modified the CFPA_LC_STATE to 0x3. Customer can use the CFPA_LC_STATE to advance the LC to Develop2 (0x7), In-field (0xF) and In-field Locked (0xCF) when the current efuse lifecycle is Develop (0x3). After the CFPA_LC_STATE has been set as advanced lifecycle, the CFPA_LC_STATE will be functional after warming reset the device, not the POR and wakeup reset type. But for the debug port, the following steps are required to make CFPA_LC_STATE effective for the debug port: 1.\tPerform a Power-on Reset while pulling down the ISP pin, to ensure that it directly enters ISP mode after POR. 2.\tThen perform a warm reset, such as a pin reset. Below are the allowed values for this field. Use of other values may lead to bricked state", + "values": [ + { + "name": "USE_LC_STATE_OTP", + "value": 0, + "description": "Use LC state from OTP" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "field locked state" + } + ] + }, + { + "width": 8, + "id": "field000-bits8-15", + "name": "INV_CFPA_LC_STATE", + "description": "Inverted value of CFPA_LC_STATE. This INV_CPFA_LC_STATE ^ CFPA_LC_STATE[7:0] should be 0xFF, otherwise the CPFA_LC_STATE will not be valid", + "calculated": "INVERSE" + }, + { + "width": 16, + "id": "field000-bits16-31", + "name": "CFPA_HEADER", + "description": "CFPA Header marker should be set to 0x9635. After this header is set, all non-zero values will take effect; leaving all values set to 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CFPA header" + } + ] + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "CFPA Page Version.", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 24, + "id": "field004-bits0-23", + "name": "CFPA_page_version", + "description": "CFPA page version. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped. CFPA_PAGE_VERSION may begin at 0x1 and user may manually increment the value by 1 or use value 0xFF_FFFF and ROM will auto-increment this field" + }, + { + "width": 2, + "id": "field004-bits24-25", + "name": "IMG_UPD", + "description": "Image updated. Note: CMAC boot is only supported for internal flash. If using a FlexSPI flash XIP image, then this field should always be left as zero", + "values": [ + { + "name": "NOTHING_CHANGED", + "value": 0, + "description": "No action" + }, + { + "name": "IMAGE0_CMAC_UPDATE", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "IMAGE1_CMAC_UPDATE", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "SBL_IMG_CMAC_UPDATE", + "value": 3, + "description": "Update SBL image CMAC (image in IFR0 0x0100_8000). Value written in IMG0_CMAC field" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field004-bits27-29", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in Develop (0x3) LC state. All other combinations update CMAC field in CMPA page", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "UPDATE_IN_CMPA", + "value": 2, + "description": "Update CMAC field in CMPA page" + }, + { + "name": "TO_OEM_SECURE", + "value": 3, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to Develop2 (0x7)" + }, + { + "name": "TO_OEM_CLOSED", + "value": 5, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to In-Field (0xF)" + }, + { + "name": "TO_OEM_LOCKED", + "value": 6, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to In-Field Locked (0xCF)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field004-bit31", + "name": "DICE_UPD", + "description": "Update DICE certificate during next boot", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "GENERATE_CERTIFICATE", + "value": 1, + "description": "Generate certificate" + } + ] + } + ] + }, + { + "id": "field008", + "name": "Secure_FW_Version", + "description": "Secure Firmware version. This monotonic counter field tracks the firmware version of secure partition. ROM uses this field to enforce anti-rollback checking during secure boot and secure update (SB3 header). For image authentication pass during secure boot the FW version in image manifest must be equal or greater than this value. During secure update and recovery boot the version number in SB3 header Must be equal or greater than the value in this field. Apart from SB3 header check, user can enforce anti-rollback check during SB3 processing by using 'kSB3_COMMAND_fwVersionCheck' SB command with 'kNBOOT_CNT_secure' counter ID parameter, in SB3 file.", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "Secure_firmware_version", + "description": "Secure Firmware version. This monotonic counter field tracks the firmware version of secure partition. ROM uses this field to enforce anti-rollback checking during secure boot and secure update (SB3 header). For image authentication pass during secure boot the FW version in image manifest must be equal or greater than this value. During secure update & recovery boot the version number in SB3 header Must be equal or greater than the value in this field. Apart from SB3 header check, user can enforce anti-rollback check during SB3 processing by using \"kSB3_COMMAND_fwVersionCheck\" SB command with 'kNBOOT_CNT_secure' counter ID parameter, in SB3 file" + }, + { + "width": 16 + } + ] + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware version. This monotonic counter field can be used to track the firmware version of non-secure partition. An anti-rollback check can be enforced during update by using this field and 'kSB3_COMMAND_fwVersionCheck' SB command with 'kNBOOT_CNT_nonsecure' counter ID parameter, in SB3 file.", + "offset_int": "0x000C", + "default_value_int": "0" + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field014", + "name": "SECBOOT_FLAGS", + "description": "Secure BOOT Flags.", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RoTK0_EN", + "description": "Root of Trust Key 0 Enable. Determines if ROTK0 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "RoTK1_EN", + "description": "Root of Trust Key 1 Enable. Determines if ROTK1 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "RoTK2_EN", + "description": "Root of Trust Key 2 Enable. Determines if ROTK2 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "RoTK3_EN", + "description": "Root of Trust Key 3 Enable. Determines if ROTK3 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 20 + }, + { + "width": 4, + "id": "field014-bits28-31", + "name": "OEM_RETURN_ERASE_DONE", + "description": "OEM assets erase done flag. ROM sets this field to 0xA after erasing the user flash and OEM assets. This operation is done on first boot after OTP_LC_STATE is advanced to 0x1F or higher states. On every boot ROM checks if LC_STATE is greater or equal to 0x1F and this field is empty in active CFPA page, then it erases OEM assets and updates this field in CFPA before freezing CFPA pages and enabling debug access. If the field is already set to 0xA then it proceeds without erasing user flash area" + } + ] + }, + { + "id": "field018", + "name": "IMAGE_KEY_REVOKE", + "description": "Image Key Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 24, + "id": "field018-bits0-23", + "name": "Image_key_revocation_ID", + "description": "Image signing key revocation counter. This monotonically increasing unary encode counter (e.g., 0x0, 0x1, 0x3, 0x7, 0xF...) field is used by boot ROM to enforce image signing key (ISK) certificate revocation policy. Boot ROM accepts an ISK certificate as valid only if the \"constraint\" field in ISK certificate is the same or greater than the ISK revocation counter. The 32-bit ISK revocation counter is formed using 8 bits of IMAGE_KEY_REVOKE[7:0] field in OTP as MSB bits and lower 24 bits from this field. ISK certificate validation is done as part of boot, FW update (SB3) and recovery (SB3) image authentication" + }, + { + "width": 8 + } + ] + }, + { + "id": "field01C", + "name": "LP_VECTOR_ADDR", + "description": "Vector address when waking from power-down and deep power down states when CMPA.LP_SEC_BOOT is set to 2b'10.", + "offset_int": "0x001C", + "default_value_int": "0" + }, + { + "id": "field020", + "name": "DBG_REVOKE_VU", + "description": "Debug Revoke Vendor Usage.", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field020-bits0-15", + "name": "Debug_certificate_revocation_counter", + "deprecated_names": [ + "FIELD" + ], + "description": "Debug certificate revocation counter. This monotonic counter field is used for revoking debug certificates. As part of debug authentication, CC_VU field in debug certificate/credential is checked against DCFG_VENDOR_USAGE value. The 32-bit DCFG_VENDOR_USAGE is formed using upper 16 bit of CMPA.VENDOR_USAGE and lower 16 bits of this field" + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of Bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field028-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field028-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field030", + "name": "MCTR_NPX_CTX0", + "description": "Erase counter for Prince region 0. Monotonic erase counter for NPX region 0. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX0. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field034", + "name": "MCTR_NPX_CTX1", + "description": "Erase counter for Prince region 1. Monotonic erase counter for NPX region 1. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX1. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field038", + "name": "MCTR_NPX_CTX2", + "description": "Erase counter for Prince region 2. Monotonic erase counter for NPX region 2. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX2. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "MCTR_NPX_CTX3", + "description": "Erase counter for Prince region 3. Monotonic erase counter for NPX region 3. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX3. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x003C", + "default_value_int": "0" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field060", + "name": "ERR_AUTH_FAIL_COUNT", + "description": "Authentication failure counter. This monotonic counter field is incremented by boot ROM on authentication failure during boot, SB3, or debug authentication (Monotonic counter).", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ERR_ITRC_COUNT", + "description": "Tamper event counter. This monotonic counter field is incremented by boot ROM whenever the reset cause during boot is detected as - ITRC reset caused by security sensors or - WDT 0/1 reset or - Tamper pin reset.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00068-0007C", + "description": "Reserved 00068-0007C" + }, + "registers": [ + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined monotonic counters configuration" + }, + "registers": [ + { + "id": "field080", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "MFLAG_CUST_0", + "description": "Customer defined Monotonic flags 0 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "MFLAG_CUST_1", + "description": "Customer defined Monotonic flags 1 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "MFLAG_CUST_2", + "description": "Customer defined Monotonic flags 2 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A8", + "default_value_int": "0" + }, + { + "id": "field0AC", + "name": "MFLAG_CUST_3", + "description": "Customer defined Monotonic flags 3 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00AC", + "default_value_int": "0" + }, + { + "id": "field0B0", + "name": "MFLAG_CUST_4", + "description": "Customer defined Monotonic flags 4 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B0", + "default_value_int": "0" + }, + { + "id": "field0B4", + "name": "MFLAG_CUST_5", + "description": "Customer defined Monotonic flags 5 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "MFLAG_CUST_6", + "description": "Customer defined Monotonic flags 6 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "field0BC", + "name": "MFLAG_CUST_7", + "description": "Customer defined Monotonic flags 7 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00BC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash access control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field0C0", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C0", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C0-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_7FFF). Select one of the 8 pre-defined access control attributes for the given Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector. (offset range 0x01_8000 - 0x01_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C4", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C4", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C4-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector. (offset range 0x05_8000 - 0x05_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C8", + "name": "FLASH_ACL_16_23", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C8", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C8-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector. (offset range 0x09_8000 - 0x09_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0CC", + "name": "FLASH_ACL_24_31", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00CC", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0CC-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector. (offset range 0x0D_8000 - 0x0D_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W/X unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "R + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 000D0-000DC", + "description": "Reserved 000D0-000DC" + }, + "registers": [ + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CMAC", + "description": "CMAC fields" + }, + "registers": [ + { + "id": "field0E0", + "name": "IMG0_CMAC0", + "description": "Die unique CMAC[31:0] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0E4", + "name": "IMG0_CMAC1", + "description": "Die unique CMAC[63:32] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0E8", + "name": "IMG0_CMAC2", + "description": "Die unique CMAC[95:64] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0EC", + "name": "IMG0_CMAC3", + "description": "Die unique CMAC[127:96] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F0", + "name": "IMG1_CMAC0", + "description": "Die unique CMAC[31:0] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F4", + "name": "IMG1_CMAC1", + "description": "Die unique CMAC[63:32] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F8", + "name": "IMG1_CMAC2", + "description": "Die unique CMAC[95:64] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0FC", + "name": "IMG1_CMAC3", + "description": "Die unique CMAC[127:96] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00FC", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "DICE", + "description": "DICE certificate configuration" + }, + "registers": [ + { + "id": "field100", + "name": "DICE_Certificate0", + "description": "DICE Certificate register", + "offset_int": "0x0100", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits0-7", + "name": "X_coordinate_of_public_key_Qx[31]", + "deprecated_names": [ + "X coordinate of public key Qx[31]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits8-15", + "name": "X_coordinate_of_public_key_Qx[30]", + "deprecated_names": [ + "X coordinate of public key Qx[30]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits16-23", + "name": "X_coordinate_of_public_key_Qx[29]", + "deprecated_names": [ + "X coordinate of public key Qx[29]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits24-31", + "name": "X_coordinate_of_public_key_Qx[28]", + "deprecated_names": [ + "X coordinate of public key Qx[28]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field104", + "name": "DICE_Certificate1", + "description": "DICE Certificate register", + "offset_int": "0x0104", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits0-7", + "name": "X_coordinate_of_public_key_Qx[27]", + "deprecated_names": [ + "X coordinate of public key Qx[27]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits8-15", + "name": "X_coordinate_of_public_key_Qx[26]", + "deprecated_names": [ + "X coordinate of public key Qx[26]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits16-23", + "name": "X_coordinate_of_public_key_Qx[25]", + "deprecated_names": [ + "X coordinate of public key Qx[25]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits24-31", + "name": "X_coordinate_of_public_key_Qx[24]", + "deprecated_names": [ + "X coordinate of public key Qx[24]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field108", + "name": "DICE_Certificate2", + "description": "DICE Certificate register", + "offset_int": "0x0108", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits0-7", + "name": "X_coordinate_of_public_key_Qx[23]", + "deprecated_names": [ + "X coordinate of public key Qx[23]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field108-bits8-15", + "name": "X_coordinate_of_public_key_Qx[22]", + "deprecated_names": [ + "X coordinate of public key Qx[22]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field108-bits16-23", + "name": "X_coordinate_of_public_key_Qx[21]", + "deprecated_names": [ + "X coordinate of public key Qx[21]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field108-bits24-31", + "name": "X_coordinate_of_public_key_Qx[20]", + "deprecated_names": [ + "X coordinate of public key Qx[20]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field10C", + "name": "DICE_Certificate3", + "description": "DICE Certificate register", + "offset_int": "0x010C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits0-7", + "name": "X_coordinate_of_public_key_Qx[19]", + "deprecated_names": [ + "X coordinate of public key Qx[19]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field10C-bits8-15", + "name": "X_coordinate_of_public_key_Qx[18]", + "deprecated_names": [ + "X coordinate of public key Qx[18]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field10C-bits16-23", + "name": "X_coordinate_of_public_key_Qx[17]", + "deprecated_names": [ + "X coordinate of public key Qx[17]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field10C-bits24-31", + "name": "X_coordinate_of_public_key_Qx[16]", + "deprecated_names": [ + "X coordinate of public key Qx[16]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field110", + "name": "DICE_Certificate4", + "description": "DICE Certificate register", + "offset_int": "0x0110", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits0-7", + "name": "X_coordinate_of_public_key_Qx[15]", + "deprecated_names": [ + "X coordinate of public key Qx[15]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field110-bits8-15", + "name": "X_coordinate_of_public_key_Qx[14]", + "deprecated_names": [ + "X coordinate of public key Qx[14]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field110-bits16-23", + "name": "X_coordinate_of_public_key_Qx[13]", + "deprecated_names": [ + "X coordinate of public key Qx[13]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field110-bits24-31", + "name": "X_coordinate_of_public_key_Qx[12]", + "deprecated_names": [ + "X coordinate of public key Qx[12]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field114", + "name": "DICE_Certificate5", + "description": "DICE Certificate register", + "offset_int": "0x0114", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits0-7", + "name": "X_coordinate_of_public_key_Qx[11]", + "deprecated_names": [ + "X coordinate of public key Qx[11]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field114-bits8-15", + "name": "X_coordinate_of_public_key_Qx[10]", + "deprecated_names": [ + "X coordinate of public key Qx[10]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field114-bits16-23", + "name": "X_coordinate_of_public_key_Qx[9]", + "deprecated_names": [ + "X coordinate of public key Qx[9]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field114-bits24-31", + "name": "X_coordinate_of_public_key_Qx[8]", + "deprecated_names": [ + "X coordinate of public key Qx[8]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field118", + "name": "DICE_Certificate6", + "description": "DICE Certificate register", + "offset_int": "0x0118", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits0-7", + "name": "X_coordinate_of_public_key_Qx[7]", + "deprecated_names": [ + "X coordinate of public key Qx[7]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field118-bits8-15", + "name": "X_coordinate_of_public_key_Qx[6]", + "deprecated_names": [ + "X coordinate of public key Qx[6]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field118-bits16-23", + "name": "X_coordinate_of_public_key_Qx[5]", + "deprecated_names": [ + "X coordinate of public key Qx[5]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field118-bits24-31", + "name": "X_coordinate_of_public_key_Qx[4]", + "deprecated_names": [ + "X coordinate of public key Qx[4]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field11C", + "name": "DICE_Certificate7", + "description": "DICE Certificate register", + "offset_int": "0x011C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits0-7", + "name": "X_coordinate_of_public_key_Qx[3]", + "deprecated_names": [ + "X coordinate of public key Qx[3]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field11C-bits8-15", + "name": "X_coordinate_of_public_key_Qx[2]", + "deprecated_names": [ + "X coordinate of public key Qx[2]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field11C-bits16-23", + "name": "X_coordinate_of_public_key_Qx[1]", + "deprecated_names": [ + "X coordinate of public key Qx[1]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field11C-bits24-31", + "name": "X_coordinate_of_public_key_Qx[0]", + "deprecated_names": [ + "X coordinate of public key Qx[0]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field120", + "name": "DICE_Certificate8", + "description": "DICE Certificate register", + "offset_int": "0x0120", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[31]", + "deprecated_names": [ + "Y coordinate of public key Qy[31]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[30]", + "deprecated_names": [ + "Y coordinate of public key Qy[30]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[29]", + "deprecated_names": [ + "Y coordinate of public key Qy[29]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[28]", + "deprecated_names": [ + "Y coordinate of public key Qy[28]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field124", + "name": "DICE_Certificate9", + "description": "DICE Certificate register", + "offset_int": "0x0124", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[27]", + "deprecated_names": [ + "Y coordinate of public key Qy[27]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field124-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[26]", + "deprecated_names": [ + "Y coordinate of public key Qy[26]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field124-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[25]", + "deprecated_names": [ + "Y coordinate of public key Qy[25]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field124-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[24]", + "deprecated_names": [ + "Y coordinate of public key Qy[24]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field128", + "name": "DICE_Certificate10", + "description": "DICE Certificate register", + "offset_int": "0x0128", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[23]", + "deprecated_names": [ + "Y coordinate of public key Qy[23]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[22]", + "deprecated_names": [ + "Y coordinate of public key Qy[22]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[21]", + "deprecated_names": [ + "Y coordinate of public key Qy[21]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[20]", + "deprecated_names": [ + "Y coordinate of public key Qy[20]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field12C", + "name": "DICE_Certificate11", + "description": "DICE Certificate register", + "offset_int": "0x012C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[19]", + "deprecated_names": [ + "Y coordinate of public key Qy[19]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[18]", + "deprecated_names": [ + "Y coordinate of public key Qy[18]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[17]", + "deprecated_names": [ + "Y coordinate of public key Qy[17]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[16]", + "deprecated_names": [ + "Y coordinate of public key Qy[16]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field130", + "name": "DICE_Certificate12", + "description": "DICE Certificate register", + "offset_int": "0x0130", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[15]", + "deprecated_names": [ + "Y coordinate of public key Qy[15]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field130-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[14]", + "deprecated_names": [ + "Y coordinate of public key Qy[14]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field130-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[13]", + "deprecated_names": [ + "Y coordinate of public key Qy[13]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field130-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[12]", + "deprecated_names": [ + "Y coordinate of public key Qy[12]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field134", + "name": "DICE_Certificate13", + "description": "DICE Certificate register", + "offset_int": "0x0134", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[11]", + "deprecated_names": [ + "Y coordinate of public key Qy[11]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[10]", + "deprecated_names": [ + "Y coordinate of public key Qy[10]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[9]", + "deprecated_names": [ + "Y coordinate of public key Qy[9]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[8]", + "deprecated_names": [ + "Y coordinate of public key Qy[8]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field138", + "name": "DICE_Certificate14", + "description": "DICE Certificate register", + "offset_int": "0x0138", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[7]", + "deprecated_names": [ + "Y coordinate of public key Qy[7]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[6]", + "deprecated_names": [ + "Y coordinate of public key Qy[6]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[5]", + "deprecated_names": [ + "Y coordinate of public key Qy[5]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[4]", + "deprecated_names": [ + "Y coordinate of public key Qy[4]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field13C", + "name": "DICE_Certificate15", + "description": "DICE Certificate register", + "offset_int": "0x013C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits0-7", + "name": "Y_coordinate_of_public_key_Qy[3]", + "deprecated_names": [ + "Y coordinate of public key Qy[3]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits8-15", + "name": "Y_coordinate_of_public_key_Qy[2]", + "deprecated_names": [ + "Y coordinate of public key Qy[2]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits16-23", + "name": "Y_coordinate_of_public_key_Qy[1]", + "deprecated_names": [ + "Y coordinate of public key Qy[1]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits24-31", + "name": "Y_coordinate_of_public_key_Qy[0]", + "deprecated_names": [ + "Y coordinate of public key Qy[0]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field140", + "name": "DICE_Certificate16", + "description": "DICE Certificate register", + "offset_int": "0x0140", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits0-7", + "name": "ECDSA_SIG_R[31]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field140-bits8-15", + "name": "ECDSA_SIG_R[30]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field140-bits16-23", + "name": "ECDSA_SIG_R[29]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field140-bits24-31", + "name": "ECDSA_SIG_R[28]", + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field144", + "name": "DICE_Certificate17", + "description": "DICE Certificate register", + "offset_int": "0x0144", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits0-7", + "name": "ECDSA_SIG_R[27]", + "description": "R component of ECDSA P-256 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"description": "DICE Certificate register", + "offset_int": "0x0150", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits0-7", + "name": "ECDSA_SIG_R[15]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits8-15", + "name": "ECDSA_SIG_R[14]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits16-23", + "name": "ECDSA_SIG_R[13]", + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits24-31", + "name": "ECDSA_SIG_R[12]", + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field154", + "name": "DICE_Certificate21", + "description": "DICE Certificate register", + "offset_int": "0x0154", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits0-7", + "name": "ECDSA_SIG_R[11]", + "description": "R component of ECDSA P-256 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"description": "DICE Certificate register", + "offset_int": "0x0160", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits0-7", + "name": "ECDSA_SIG_S[31]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits8-15", + "name": "ECDSA_SIG_S[30]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits16-23", + "name": "ECDSA_SIG_S[29]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits24-31", + "name": "ECDSA_SIG_S[28]", + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field164", + "name": "DICE_Certificate25", + "description": "DICE Certificate register", + "offset_int": "0x0164", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits0-7", + "name": "ECDSA_SIG_S[27]", + "description": "S component of ECDSA P-256 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"description": "DICE Certificate register", + "offset_int": "0x0170", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits0-7", + "name": "ECDSA_SIG_S[15]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits8-15", + "name": "ECDSA_SIG_S[14]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits16-23", + "name": "ECDSA_SIG_S[13]", + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits24-31", + "name": "ECDSA_SIG_S[12]", + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field174", + "name": "DICE_Certificate29", + "description": "DICE Certificate register", + "offset_int": "0x0174", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits0-7", + "name": "ECDSA_SIG_S[11]", + "description": "S component of ECDSA P-256 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"0x01A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CRC32 of CFPA page data from offset . ROM updates this field along with CFPA_CMAC on subsequent boot after page update. ROM uses this field based on CMPA.LP_SEC_BOOT field option.", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cmpa.json new file mode 100644 index 0000000..f39dbc2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/pfr_cmpa.json @@ -0,0 +1,3393 @@ +{ + "cpu": "mcxn236", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 2, + "id": "field000-bits0-1", + "name": "BOOT_SRC", + "description": "Primary boot source", + "values": [ + { + "name": "INTERNAL_FLASH_0B00", + "value": 0, + "description": "Internal flash" + }, + { + "name": "SECONDARY_BOOTLOADER", + "value": 2, + "description": "Secondary Boot loader in Bank1 IFR0 (32KB)" + }, + { + "name": "INTERNAL_FLASH_0B11", + "value": 3, + "description": "Internal flash" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + }, + { + "name": "USB1_HID", + "value": 5, + "description": "USB1 HID" + }, + { + "name": "CAN_ISP", + "value": 6, + "description": "CAN ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits8-9", + "name": "REC_BOOT_SRC", + "description": "Recovery boot source", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Recovery boot disabled" + }, + { + "name": "XIP_IMAGE", + "value": 1, + "description": "XIP image in Bank1 IFR0 (32KB)" + }, + { + "name": "SB3_IMAGE", + "value": 2, + "description": "SB3 image in 1-bit SPI flash connected to FlexComm. FC7 used for this function by default" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution", + "values": [ + { + "name": "FRO_48_MHZ", + "value": 0, + "description": "48 MHz FRO @ 1.0V" + }, + { + "name": "FRO_72_MHZ", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "FRO_144_MHZ", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "PLL_150_MHZ", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "id": "field000-bits16-31", + "name": "CMPA_HEADER", + "deprecated_names": [ + "HEADER" + ], + "description": "CMPA Header marker should be set to 0x5963. After this header is set, all non-zero values will take effect; leaving all settings at 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CMPA header value" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = (FLASH_REMAP_SIZE + 1)" + }, + { + "width": 3, + "id": "field004-bits5-7", + "name": "OEM_BANK1_IFR0_PROT", + "description": "Defines flash protection of Bank1_IFR0 area based on usage. The MBC module is used to configure the access protections as readable (R), writeable (W), and/or executable (X). The access protections can also be configured as locked (L) which prevents later application code from changing the access protection configuration. The final MBC protection bits used for Bank1_IFR0 depend on the boot mode configuration, the boot path that is selected and the device life cycle state. The access This field will only modify the MBC protection bits for the Bank1_IFR0 area after the life cycle is advanced out of Develop. In the Develop life cycle state this field has no effect. For example, if using the In-Field life cycle and Bank1_IFR0 is being used as a recovery boot image (REC_BOOT_SRC = 1) and OEM_BANK1_IFR0_PROT value = 5 is selected), then for a regular boot using the primary image Bank1_IFR0 is mapped to GLBAC2. If the primary boot fails, and the recovery path is taken, then Bank1_IFR0 is mapped to GLBAC4 instead. Note: Settings 5-7 should not be used if Bank1_IFR0 is used as OEM_SBL (BOOT_SRC = 2). In Develop life cycle - All settings: MBC protection bits set as RWXL = 1110 (GLBAC0) In other life cycles –", + "values": [ + { + "name": "OEM_ROM_RWXL_CODE", + "value": 0, + "description": "Not determined by ROM (MBC fields are modified by OEM code)" + }, + { + "name": "OEM_ROOT_RWXL_1010", + "value": 1, + "description": "Used as OEM Root of Trust image, in other words secondary boot loader (OEM_SBL). MBC protection bits set as RWXL = 1010. Updatable by OEM code later" + }, + { + "name": "OEM_SBL_RWXL_1011", + "value": 2, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 1011" + }, + { + "name": "OEM_SBL_RWXL_0011", + "value": 3, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 0011" + }, + { + "name": "OEM_REC_RWXL_1010", + "value": 4, + "description": "Used as OEM recovery boot image with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1010 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_1011", + "value": 5, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1011 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_0011", + "value": 6, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0011 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_0001", + "value": 7, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0001 on ROM exiting to user image" + } + ] + }, + { + "width": 2, + "id": "field004-bits8-9", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_FT_ENTRY", + "description": "Disable ISP mode entry through image authentication failure", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "REC_BOOT_LED", + "description": "Assert on recovery boot. ROM drives the GPIO pin high, identified by this field whenever primary boot fails and fall through to recovery boot source. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin high identified by this field whenever primary boot fails and execution falls through to ISP mode. [[4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. ROM drives the GPIO pin high identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: ISP mode peripheral detection timeout value in seconds. If a non-zero value is program and peripheral activity is not detected within the number of seconds specified here, then the device will go to power down mode to conserve power" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_COUNT", + "description": "WDOG timeout: Upper 16 bits of 24-bit count value in WWDT0_TC register Timeout value in seconds. The lower 8 bits of WWDT0_TC are set to 0. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code" + } + ] + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field018", + "name": "REC_SPI_FLASH_CFG0", + "description": "Recovery SPI Flash Configuration 0", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field018-bits0-7", + "name": "REC_SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits8-11", + "name": "REC_SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field018-bits12-15", + "name": "REC_SPI_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field018-bits16-23", + "name": "REC_SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits24-27", + "name": "REC_SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field01C", + "name": "REC_SPI_FLASH_CFG1", + "description": "Recovery SPI Flash Configuration 1", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "REC_SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "REC_SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "REC_SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "REC_SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field01C-bits28-29", + "name": "REC_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "REC_BOOT_PIN_CUST", + "description": "Use customer defined pins for 1-bit SPI recovery boot pins", + "values": [ + { + "name": "DEFAULT_ROM_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUSTOMER_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_ROM_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_ROM_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + }, + { + "id": "field020", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_RX_PIN" + }, + { + "width": 4, + "id": "field020-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_TX_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field024", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field024-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. Identifies the pin to be used as I2C_SCL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SCL_PIN" + }, + { + "width": 4, + "id": "field024-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for I2C ISP mode" + }, + { + "width": 8, + "id": "field024-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. Identifies the pin to be used as I2C_SDA pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SDA_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field028", + "name": "ISP_CAN_CFG", + "description": "ISP CAN Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "CAN_RX_PIN", + "description": "Override default CAN RX ISP pin. Identifies the pin to be used as CAN_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "CAN_RX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by CAN_RX_PIN" + }, + { + "width": 4, + "id": "field028-bits12-15", + "name": "CAN_ISP_INST", + "description": "Identifies the instance used for CAN ISP mode" + }, + { + "width": 8, + "id": "field028-bits16-23", + "name": "CAN_TX_PIN", + "description": "Override default CAN TX ISP pin. Identifies the pin to be used as CAN_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits24-27", + "name": "CAN_TX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by CAN_TX_PIN" + }, + { + "width": 4, + "id": "field028-bits28-31", + "name": "CAN_BAUD_RATE", + "description": "CAN baud rate. Baud rate configured during CAN ISP mode", + "values": [ + { + "name": "AUTO_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "KBPS_AUTO_0B0101", + "value": 5, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B0110", + "value": 6, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B0111", + "value": 7, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1000", + "value": 8, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1001", + "value": 9, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1010", + "value": 10, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1011", + "value": 11, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1100", + "value": 12, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1101", + "value": 13, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1110", + "value": 14, + "description": "1000 kbps and auto baud detection" + }, + { + "name": "KBPS_AUTO_0B1111", + "value": 15, + "description": "1000 kbps and auto baud detection" + } + ] + } + ] + }, + { + "id": "field02C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field02C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field02C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field030", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0030", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field030-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field030-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field030-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2 + } + ] + }, + { + "id": "field034", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0034", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field034-bits0-15", + "name": "USB_Vendor_ID", + "description": "Customer defined USB vendor ID used during USB-ISP mode device enumeration" + }, + { + "width": 16, + "id": "field034-bits16-31", + "name": "USB_Product_ID", + "description": "Customer defined USB product ID used during USB-ISP mode device enumeration" + } + ] + }, + { + "id": "field038", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0038", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field038-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USBx_VBUS_DETECT ISP pin. Identifies the pin to be used as USBx_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field038-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by USBx_VBUS_PIN" + }, + { + "width": 4 + }, + { + "width": 3, + "id": "field038-bits16-18", + "name": "EXT_XTAL_CLK", + "description": "USB PHY input clock frequency. For USB high speed PHY external XTAL input is needed. This field specifies the frequency of XTAL used on board. • 000 - 24MHz input clock (Divide by 20) • 001 - 30MHz input clock (Divide by 16) • 010 - 32MHz input clock (Divide by 15) • 011 - Reserved • 100 - 20MHz input clock (Divide by 24) • 101 - 19.2MHz input clock (Divide by 25) • 110 - 16MHz input clock (Divide by 30) - Default option when CMPA is blank. • 111 - 12MHz input clock (Divide by 40)", + "values": [ + { + "name": "XTAL_24MHZ", + "value": 0, + "description": "24MHz input clock (Divide by 20)" + }, + { + "name": "XTAL_30MHZ", + "value": 1, + "description": "30MHz input clock (Divide by 16)" + }, + { + "name": "XTAL_32MHZ", + "value": 2, + "description": "32MHz input clock (Divide by 15)" + }, + { + "name": "XTAL_20MHZ", + "value": 4, + "description": "20MHz input clock (Divide by 24)" + }, + { + "name": "XTAL_19_2MHZ", + "value": 5, + "description": "19.2MHz input clock (Divide by 25)" + }, + { + "name": "XTAL_16MHZ", + "value": 6, + "description": "16MHz input clock (Divide by 30) - Default option when CMPA is blank" + }, + { + "name": "XTAL_12MHZ", + "value": 7, + "description": "12MHz input clock (Divide by 40)" + } + ] + }, + { + "width": 1, + "id": "field038-bit19", + "name": "PRE_DIV", + "description": "Enable Pre-divider. Needed to support 48MHz and other high speed crystals", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 12 + } + ] + }, + { + "id": "field03C", + "name": "ISP_MISC_CFG", + "description": "ISP Miscellaneous Configuration", + "offset_int": "0x003C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field03C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field03C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins" + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect" + }, + { + "name": "USB1_VBUS", + "value": 2, + "description": "Customer defined GPIO for USB1_VBUS detect" + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector" + } + ] + }, + { + "width": 2, + "id": "field03C-bits24-25", + "name": "ISP_CAN_CUST", + "description": "Use customer defined CAN ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + }, + { + "id": "field040", + "name": "CC_SOCU_PIN", + "description": "Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0040", + "deprecated_names": [ + "DCFG_CC_SOCU_PIN" + ], + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field040-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field040-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 1, + "id": "field040-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field040-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field044", + "name": "CC_SOCU_DFLT", + "description": "Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0044", + "deprecated_names": [ + "DCFG_CC_SOCU_DFLT" + ], + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field044-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field044-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 16, + "id": "field044-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field048", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0048", + "default_value_int": "0", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field048-bits16-31", + "name": "VENDOR_USAGE", + "description": "Vendor Usage [31:16]. Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area (CFPA.DBG_REVOKE_VU)" + } + ] + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field050", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x0050", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "SEC_BOOT_EN", + "description": "Secure boot enforcement. This field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign). The Image type field in header indicates the type of verification data (checksum or signature) included in it. Note: Plain < CRC32 < CMAC < ECDSA", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed" + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed" + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed" + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits3-4", + "name": "LP_SEC_BOOT", + "description": "Secure boot option for low-power wake from power-down and deep-powerdown. For CFPA/CMPA do CRC check always", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA" + }, + { + "name": "CMAC_CHECK", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "field050-bits8-9", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication. Note, CMAC image authentication is only allowed in 2b'00 setting", + "values": [ + { + "name": "ALL_ALLOWED_0B00", + "value": 0, + "description": "All algorithm allowed" + }, + { + "name": "LIMITED_0B01", + "value": 1, + "description": "384 keys, SHA384 & AES256 algorithms are used" + }, + { + "name": "LIMITED_0B10", + "value": 2, + "description": "384 keys, SHA384 & AES256 algorithms are used" + }, + { + "name": "LIMITED_0B11", + "value": 3, + "description": "384 keys, SHA384 & AES256 algorithms are used" + } + ] + }, + { + "width": 2, + "id": "field050-bits10-11", + "name": "ENF_TZM_PRESET", + "description": "Enforce TrustZone-M mode", + "values": [ + { + "name": "IGNORE_0B00", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_0B01", + "value": 1, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_0B10", + "value": 2, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_0B11", + "value": 3, + "description": "Enforce preset TZM data in image manifest" + } + ] + }, + { + "width": 2, + "id": "field050-bits12-13", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event. Zeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion and Tamper control signals an intrusion event (ITRC_OUT3). Note, when ITRC is re-configured in application then ITRC_OUT4 (CHIP_RESET) should be triggered with at least same events as ITRC_OUT3 (RAM_ZEROIZE)", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only" + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only" + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot" + } + ] + }, + { + "width": 2, + "id": "field050-bits14-15", + "name": "ACTIVE_IMG_PROT", + "description": "Protection of active image. This field defines protection of flash area occupied by the active image. Only applicable to internal flash", + "values": [ + { + "name": "FLASH_ACL_PROTECTION", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings" + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored" + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored" + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "XOM protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored" + } + ] + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits18-19", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits24-25", + "name": "FIPS_CMAC_STEN", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits28-29", + "name": "FIPS_PUF_STEN", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "cycle" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field054", + "name": "RoTK_USAGE", + "description": "Root of Trust Key Usage", + "offset_int": "0x0054", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "RoTK0_Usage", + "description": "RoT key 0 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits3-5", + "name": "RoTK1_Usage", + "description": "RoT key 1 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits6-8", + "name": "RoTK2_Usage", + "description": "RoT key 2 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits9-11", + "name": "RoTK3_Usage", + "description": "RoT key 3 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 1, + "id": "field054-bit12", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "field054-bit13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "field054-bit14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field054-bits16-17", + "name": "REG0_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 0. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits18-19", + "name": "REG1_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 1. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits20-21", + "name": "REG2_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 2. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits22-23", + "name": "REG3_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 3. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits24-25", + "name": "NPX_LOCK_CTX0", + "description": "Lock on-chip flash NPX PRINCE context 0 settings. Note: when locking a region recommendation is to also enable erase checking using the REG0_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits26-27", + "name": "NPX_LOCK_CTX1", + "description": "Lock on-chip flash NPX PRINCE context 1 settings. Note: when locking a region recommendation is to also enable erase checking using the REG1_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits28-29", + "name": "NPX_LOCK_CTX2", + "description": "Lock on-chip flash NPX PRINCE context 2 settings. Note: when locking a region recommendation is to also enable erase checking using the REG2_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits30-31", + "name": "NPX_LOCK_CTX3", + "description": "Lock on-chip flash NPX PRINCE context 3 settings. Note: when locking a region recommendation is to also enable erase checking using the REG3_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00058-0005C", + "description": "Reserved 00058-0005C" + }, + "registers": [ + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "Root of Trust Key Hash 0", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "Root of Trust Key Hash 1", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "Root of Trust Key Hash 2", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "Root of Trust Key Hash 3", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "Root of Trust Key Hash 4", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "Root of Trust Key Hash 5", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "Root of Trust Key Hash 6", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "Root of Trust Key Hash 7", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field080", + "name": "ROTKH8", + "description": "Root of Trust Key Hash 8", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "ROTKH9", + "description": "Root of Trust Key Hash 9", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "ROTKH10", + "description": "Root of Trust Key Hash 10", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "ROTKH11", + "description": "Root of Trust Key Hash 11", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "NPX_CTX", + "description": "NPX_CTX fields" + }, + "registers": [ + { + "id": "field090", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "Reserved00094", + "name": "Reserved 0x00094", + "description": "This field is reserved for internal use", + "offset_int": "0x0094", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field098", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "Reserved0009C", + "name": "Reserved 0x0009C", + "description": "This field is reserved for internal use", + "offset_int": "0x009C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "Reserved000A4", + "name": "Reserved 0x000A4", + "description": "This field is reserved for internal use", + "offset_int": "0x00A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors", + "offset_int": "0x00A8", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 000AC-000EC", + "description": "Reserved 000AC-000EC" + }, + "registers": [ + { + "id": "Reserved000AC", + "name": "Reserved 0x000AC", + "description": "This field is reserved for internal use", + "offset_int": "0x00AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B0", + "name": "Reserved 0x000B0", + "description": "This field is reserved for internal use", + "offset_int": "0x00B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B4", + "name": "Reserved 0x000B4", + "description": "This field is reserved for internal use", + "offset_int": "0x00B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000B8", + "name": "Reserved 0x000B8", + "description": "This field is reserved for internal use", + "offset_int": "0x00B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000BC", + "name": "Reserved 0x000BC", + "description": "This field is reserved for internal use", + "offset_int": "0x00BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C0", + "name": "Reserved 0x000C0", + "description": "This field is reserved for internal use", + "offset_int": "0x00C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C4", + "name": "Reserved 0x000C4", + "description": "This field is reserved for internal use", + "offset_int": "0x00C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000C8", + "name": "Reserved 0x000C8", + "description": "This field is reserved for internal use", + "offset_int": "0x00C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000CC", + "name": "Reserved 0x000CC", + "description": "This field is reserved for internal use", + "offset_int": "0x00CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D0", + "name": "Reserved 0x000D0", + "description": "This field is reserved for internal use", + "offset_int": "0x00D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D4", + "name": "Reserved 0x000D4", + "description": "This field is reserved for internal use", + "offset_int": "0x00D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000D8", + "name": "Reserved 0x000D8", + "description": "This field is reserved for internal use", + "offset_int": "0x00D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000DC", + "name": "Reserved 0x000DC", + "description": "This field is reserved for internal use", + "offset_int": "0x00DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E0", + "name": "Reserved 0x000E0", + "description": "This field is reserved for internal use", + "offset_int": "0x00E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E4", + "name": "Reserved 0x000E4", + "description": "This field is reserved for internal use", + "offset_int": "0x00E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000E8", + "name": "Reserved 0x000E8", + "description": "This field is reserved for internal use", + "offset_int": "0x00E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000EC", + "name": "Reserved 0x000EC", + "description": "This field is reserved for internal use", + "offset_int": "0x00EC", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "REC_IMG", + "description": "Recovery image extended sectors configuration" + }, + "registers": [ + { + "id": "field0F0", + "name": "REC_IMG_EXT0", + "description": "Bitmap mask to indicate sectors included in recovery image (sectors .Recovery image is programmed in BANK1_IFR0. But if the image size is more than 32KB, this field can be used to indicate sectors to include in recovery image.ROM will configure flash protection setting for these sectors the same as BANK1_IFR0 before exiting to user code. The protection settings are managed through CMPA.OEM_BANK1_IFR0_PROT. The lower 8 sectors are excluded from this mask to avoid conflicts with dual image boot feature.", + "offset_int": "0x00F0", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 1, + "id": "field0F0-bit8", + "name": "REC_IMG_EXT0_SEC8", + "description": "REC_IMG_EXT0_SEC set protection for memory in range 0x40000:0x47FFF" + }, + { + "width": 1, + "id": "field0F0-bit9", + "name": "REC_IMG_EXT0_SEC9", + "description": "REC_IMG_EXT0_SEC9 set protection for memory in range 0x48000:0x4FFFF" + }, + { + "width": 1, + "id": "field0F0-bit10", + "name": "REC_IMG_EXT0_SEC10", + "description": "REC_IMG_EXT0_SEC10 set protection for memory in range 0x50000:0x57FFF" + }, + { + "width": 1, + "id": "field0F0-bit11", + "name": "REC_IMG_EXT0_SEC11", + "description": "REC_IMG_EXT0_SEC11 set protection for memory in range 0x58000:0x5FFFF" + }, + { + "width": 1, + "id": "field0F0-bit12", + "name": "REC_IMG_EXT0_SEC12", + "description": "REC_IMG_EXT0_SEC12 set protection for memory in range 0x60000:0x67FFF" + }, + { + "width": 1, + "id": "field0F0-bit13", + "name": "REC_IMG_EXT0_SEC13", + "description": "REC_IMG_EXT0_SEC13 set protection for memory in range 0x68000:0x6FFFF" + }, + { + "width": 1, + "id": "field0F0-bit14", + "name": "REC_IMG_EXT0_SEC14", + "description": "REC_IMG_EXT0_SEC14 set protection for memory in range 0x70000:0x77FFF" + }, + { + "width": 1, + "id": "field0F0-bit15", + "name": "REC_IMG_EXT0_SEC15", + "description": "REC_IMG_EXT0_SEC15 set protection for memory in range 0x78000:0x7FFFF" + }, + { + "width": 1, + "id": "field0F0-bit16", + "name": "REC_IMG_EXT0_SEC16", + "description": "REC_IMG_EXT0_SEC16 set protection for memory in range 0x80000:0x87FFF" + }, + { + "width": 1, + "id": "field0F0-bit17", + "name": "REC_IMG_EXT0_SEC17", + "description": "REC_IMG_EXT0_SEC17 set protection for memory in range 0x88000:0x8FFFF" + }, + { + "width": 1, + "id": "field0F0-bit18", + "name": "REC_IMG_EXT0_SEC18", + "description": "REC_IMG_EXT0_SEC18 set protection for memory in range 0x90000:0x97FFF" + }, + { + "width": 1, + "id": "field0F0-bit19", + "name": "REC_IMG_EXT0_SEC19", + "description": "REC_IMG_EXT0_SEC19 set protection for memory in range 0x98000:0x9FFFF" + }, + { + "width": 1, + "id": "field0F0-bit20", + "name": "REC_IMG_EXT0_SEC20", + "description": "REC_IMG_EXT0_SEC20 set protection for memory in range 0xA0000:0xA7FFF" + }, + { + "width": 1, + "id": "field0F0-bit21", + "name": "REC_IMG_EXT0_SEC21", + "description": "REC_IMG_EXT0_SEC21 set protection for memory in range 0xA8000:0xAFFFF" + }, + { + "width": 1, + "id": "field0F0-bit22", + "name": "REC_IMG_EXT0_SEC22", + "description": "REC_IMG_EXT0_SEC22 set protection for memory in range 0xB0000:0xB7FFF" + }, + { + "width": 1, + "id": "field0F0-bit23", + "name": "REC_IMG_EXT0_SEC23", + "description": "REC_IMG_EXT0_SEC23 set protection for memory in range 0xB8000:0xBFFFF" + }, + { + "width": 1, + "id": "field0F0-bit24", + "name": "REC_IMG_EXT0_SEC24", + "description": "REC_IMG_EXT0_SEC24 set protection for memory in range 0xC0000:0xC7FFF" + }, + { + "width": 1, + "id": "field0F0-bit25", + "name": "REC_IMG_EXT0_SEC25", + "description": "REC_IMG_EXT0_SEC25 set protection for memory in range 0xC8000:0xCFFFF" + }, + { + "width": 1, + "id": "field0F0-bit26", + "name": "REC_IMG_EXT0_SEC26", + "description": "REC_IMG_EXT0_SEC26 set protection for memory in range 0xD0000:0xD7FFF" + }, + { + "width": 1, + "id": "field0F0-bit27", + "name": "REC_IMG_EXT0_SEC27", + "description": "REC_IMG_EXT0_SEC27 set protection for memory in range 0xD8000:0xDFFFF" + }, + { + "width": 1, + "id": "field0F0-bit28", + "name": "REC_IMG_EXT0_SEC28", + "description": "REC_IMG_EXT0_SEC28 set protection for memory in range 0xE0000:0xE7FFF" + }, + { + "width": 1, + "id": "field0F0-bit29", + "name": "REC_IMG_EXT0_SEC29", + "description": "REC_IMG_EXT0_SEC29 set protection for memory in range 0xE8000:0xEFFFF" + }, + { + "width": 1, + "id": "field0F0-bit30", + "name": "REC_IMG_EXT0_SEC30", + "description": "REC_IMG_EXT0_SEC30 set protection for memory in range 0xF0000:0xF7FFF" + }, + { + "width": 1, + "id": "field0F0-bit31", + "name": "REC_IMG_EXT0_SEC31", + "description": "REC_IMG_EXT0_SEC31 set protection for memory in range 0xF8000:0xFFFFF" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 000F4-0011C", + "description": "Reserved 000F4-0011C" + }, + "registers": [ + { + "id": "Reserved000F4", + "name": "Reserved 0x000F4", + "description": "This field is reserved for internal use", + "offset_int": "0x00F4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field120", + "name": "QUICK_SET_GPIO_0", + "description": "Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_0 and QUICK_CLR_GPIO_0 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0120", + "default_value_int": "0" + }, + { + "id": "field124", + "name": "QUICK_CLR_GPIO_0", + "description": "Drive GPIO 0 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_0 and QUICK_CLR_GPIO_0 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0124", + "default_value_int": "0" + }, + { + "id": "field128", + "name": "QUICK_SET_GPIO_1", + "description": "Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_1 and QUICK_CLR_GPIO_1 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0128", + "default_value_int": "0" + }, + { + "id": "field12C", + "name": "QUICK_CLR_GPIO_1", + "description": "Drive GPIO 1 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_1 and QUICK_CLR_GPIO_1 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x012C", + "default_value_int": "0" + }, + { + "id": "field130", + "name": "QUICK_SET_GPIO_2", + "description": "Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_2 and QUICK_CLR_GPIO_2 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0130", + "default_value_int": "0" + }, + { + "id": "field134", + "name": "QUICK_CLR_GPIO_2", + "description": "Drive GPIO 2 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_2 and QUICK_CLR_GPIO_2 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0134", + "default_value_int": "0" + }, + { + "id": "field138", + "name": "QUICK_SET_GPIO_3", + "description": "Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_3 and QUICK_CLR_GPIO_3 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0138", + "default_value_int": "0" + }, + { + "id": "field13C", + "name": "QUICK_CLR_GPIO_3", + "description": "Drive GPIO 3 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_3 and QUICK_CLR_GPIO_3 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x013C", + "default_value_int": "0" + }, + { + "id": "field140", + "name": "QUICK_SET_GPIO_4", + "description": "Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_4 and QUICK_CLR_GPIO_4 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0140", + "default_value_int": "0" + }, + { + "id": "field144", + "name": "QUICK_CLR_GPIO_4", + "description": "Drive GPIO 4 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_4 and QUICK_CLR_GPIO_4 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0144", + "default_value_int": "0" + }, + { + "id": "field148", + "name": "QUICK_SET_GPIO_5", + "description": "Drive GPIO 5 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_5 and QUICK_CLR_GPIO_5 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0148", + "default_value_int": "0" + }, + { + "id": "field14C", + "name": "QUICK_CLR_GPIO_5", + "description": "Drive GPIO 5 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_5 and QUICK_CLR_GPIO_5 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x014C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00150-0015C", + "description": "Reserved 00150-0015C" + }, + "registers": [ + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CUST_MK_SK", + "description": "CUST_MK_SK key blob" + }, + "registers": [ + { + "id": "field160", + "name": "CUST_MK_SK0", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0160", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB0" + ], + "default_value_int": "0" + }, + { + "id": "field164", + "name": "CUST_MK_SK1", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0164", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB1" + ], + "default_value_int": "0" + }, + { + "id": "field168", + "name": "CUST_MK_SK2", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0168", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB2" + ], + "default_value_int": "0" + }, + { + "id": "field16C", + "name": "CUST_MK_SK3", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x016C", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB3" + ], + "default_value_int": "0" + }, + { + "id": "field170", + "name": "CUST_MK_SK4", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0170", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB4" + ], + "default_value_int": "0" + }, + { + "id": "field174", + "name": "CUST_MK_SK5", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0174", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB5" + ], + "default_value_int": "0" + }, + { + "id": "field178", + "name": "CUST_MK_SK6", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0178", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB6" + ], + "default_value_int": "0" + }, + { + "id": "field17C", + "name": "CUST_MK_SK7", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x017C", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB7" + ], + "default_value_int": "0" + }, + { + "id": "field180", + "name": "CUST_MK_SK8", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0180", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB8" + ], + "default_value_int": "0" + }, + { + "id": "field184", + "name": "CUST_MK_SK9", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0184", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB9" + ], + "default_value_int": "0" + }, + { + "id": "field188", + "name": "CUST_MK_SK10", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x0188", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB10" + ], + "default_value_int": "0" + }, + { + "id": "field18C", + "name": "CUST_MK_SK11", + "description": "CUST_MK_SK key blob 0", + "offset_int": "0x018C", + "deprecated_names": [ + "CUST_MK_SK_KEY_BLOB11" + ], + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00190-001E8", + "description": "Reserved 00190-001E8" + }, + "registers": [ + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CMPA_CRC32", + "description": "CRC32 of CMPA page data from offset . ROM updates this field along with CMPA_CMAC. ROM uses this field based on CMPA.LP_SEC_BOOT field option.", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CMAC", + "description": "CMAC fields" + }, + "registers": [ + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/tz.json new file mode 100644 index 0000000..f0d63f3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn236/tz.json @@ -0,0 +1,1661 @@ +{ + "cpu": "mcxn236", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "FLASH 02 Memory Rule Register (flash02_mem_rule)", + "description": "TrustZone register - FLASH 02 Memory Rule Register (flash02_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "FLASH 03 Memory Rule Register (flash03_mem_rule)", + "description": "TrustZone register - FLASH 03 Memory Rule Register (flash03_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "description": "TrustZone register - RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "description": "TrustZone register - RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "description": "TrustZone register - RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAMA Memory Rule Register (rama_mem_rule)", + "description": "TrustZone register - RAMA Memory Rule Register (rama_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAMB Memory Rule Register (ramb_mem_rule)", + "description": "TrustZone register - RAMB Memory Rule Register (ramb_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "description": "TrustZone register - RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "description": "TrustZone register - RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "description": "TrustZone register - RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "description": "TrustZone register - RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAME Memory Rule Register 0 (rame_mem_rule0)", + "description": "TrustZone register - RAME Memory Rule Register 0 (rame_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAME Memory Rule Register 1 (rame_mem_rule1)", + "description": "TrustZone register - RAME Memory Rule Register 1 (rame_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "description": "TrustZone register - AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "default_value_int": "0x3333" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "description": "TrustZone register - Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "description": "TrustZone register - Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "description": "TrustZone register - Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "default_value_int": "0x2aaaaa" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "CM33 Lock Control Register 0 (cm33_lock_reg0)", + "description": "TrustZone register - CM33 Lock Control Register 0 (cm33_lock_reg0)", + "default_value_int": "0x800002aa" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "description": "TrustZone register - MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "default_value_int": "0x7777" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "description": "TrustZone register - MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "default_value_int": "0x5500" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "description": "TrustZone register - MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "default_value_int": "0x1100" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "description": "TrustZone register - GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "description": "TrustZone register - GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "GPIO0 Lock Register (gpio0_lock)", + "description": "TrustZone register - GPIO0 Lock Register (gpio0_lock)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "description": "TrustZone register - GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "description": "TrustZone register - GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "GPIO1 Lock Register (gpio1_lock)", + "description": "TrustZone register - GPIO1 Lock Register (gpio1_lock)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "description": "TrustZone register - GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "description": "TrustZone register - GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "GPIO2 Lock Register (gpio2_lock)", + "description": "TrustZone register - GPIO2 Lock Register (gpio2_lock)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "description": "TrustZone register - GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Privilege(gpio3_pcnp)", + "description": "TrustZone register - GPIO3 Pin Control Non-Privilege(gpio3_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "GPIO3 Lock Register (gpio3_lock)", + "description": "TrustZone register - GPIO3 Lock Register (gpio3_lock)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "description": "TrustZone register - GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "description": "TrustZone register - GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "GPIO4 Lock Register (gpio4_lock)", + "description": "TrustZone register - GPIO4 Lock Register (gpio4_lock)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "description": "TrustZone register - GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "description": "TrustZone register - GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "GPIO5 Lock Register (gpio5_lock)", + "description": "TrustZone register - GPIO5 Lock Register (gpio5_lock)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn247/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn247/database.yaml new file mode 100644 index 0000000..f80b10f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn247/database.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn526/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn526/database.yaml new file mode 100644 index 0000000..f80b10f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn526/database.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn527/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn527/database.yaml new file mode 100644 index 0000000..f80b10f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn527/database.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn536/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn536/database.yaml new file mode 100644 index 0000000..f80b10f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn536/database.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn537/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn537/database.yaml new file mode 100644 index 0000000..f80b10f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn537/database.yaml @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn546/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn546/database.yaml new file mode 100644 index 0000000..f2c5725 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn546/database.yaml @@ -0,0 +1,8 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn946 + +info: + spsdk_predecessor_name: mcxn54x diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn547/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn547/database.yaml new file mode 100644 index 0000000..e8384af --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn547/database.yaml @@ -0,0 +1,8 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn947 + +info: + spsdk_predecessor_name: mcxn54x diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/database.yaml new file mode 100644 index 0000000..2913cdc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/database.yaml @@ -0,0 +1,396 @@ +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True + purpose: MCX Series + # Web page of MCU representative + web: https://www.nxp.com + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x100000" + external: false + sram: + start_int: "0x20000000" + size_int: "0x40000" + external: false + non_xip_type: int_ram + isp: + rom: + protocol: mboot + interfaces: ["usb", "uart", "spi", "i2c", "can"] + usb: + - vid: 0x1FC9 + pid: 0x014F + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2002_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab_v2_48_bytes" + + ahab: &ahab_common_config + sub_features: [certificate_supported] + container_types: [2] # Supported container types + containers_max_cnt: 1 + image_types_mapping: {} + certificate_type: 32bit_fuse_version # The certificate with full 32-bit fuse version support + allow_empty_hash: False # Some chips allow empty image hash in OEM Open LC + core_ids: + CORTEX_M33: [1, "cortex-m33", "Cortex M33 - Boot core"] + + valid_offset_minimal_alignment: 4 + extra_containers: [] + image_hash_types: [sha384] # Supported image hash types + iae_has_signed_offsets: True # There is a special cases when the Container is after images + + # ======== DAT section ======== + dat: + socc: 0x4D430007 # SOCC identification + auth_beacon_length: 2 # The length in bytes of authentication beacon + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True # Flag to indicate SHA256 is always used for DAT + used_beacons_on_ele: True # The DAT ELE implementation is using certificate and authentication beacons + vu_instead_fuse_version: True # The DAT ELE implementation is using Vendor usage name instead of Fuse Version + ele_cnt_version: 2 # DAT container is based on New AHAB container version 2 + sub_features: ["ele_pqc", "ssf_cert"] + dac_rot_type: ecc_pqc_sha521_truncated # The Dac packet is using truncated SHA512 hash and in case of 2 signatures + test_address: 0x2002_8000 + dmbox_ap_ix: 2 + command_delays: # Additional standard command delays per individual DM commands [seconds] + ERASE_FLASH: 0.5 + DBG_AUTH_START: 1.0 + # Memory addresses for SSF certificate data + ssf_cert: + ecdsa_puk_address: 0x3002_2000 # Address for ECDSA PUK + ecdsa_puk_size: 0x60 # Size for ECDSA PUK (96 bytes) + hybrid_puk_address: 0x3002_2100 # Address for Hybrid PUK + hybrid_puk_size: 0xA80 # Size for Hybrid PUK (2688 bytes) + ahab: *ahab_common_config + + # ======== Fuses description section ======== + fuses: + grouped_registers: + - uid: rkth + name: RKTH + width: 384 + config_as_hexstring: true + reversed: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key + table hash. For ECC P-256 keys RKTH is a 32-byte SHA-256 digest of four + SHA-256 digests computed over four OEM public keys (OEM has four + private-public key pairs in case one of its private keys becomes + compromised) or in case that ECC P-384 keys are used, RKTH is 48-byte + SHA-384 digest. + sub_regs: + - fuse11 + - fuse12 + - fuse13 + - fuse14 + - fuse15 + - fuse16 + - fuse17 + - fuse18 + - fuse19 + - fuse20 + - fuse21 + - fuse22 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneV2 + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersionHiddenImageVersion + - Mbi_ExportMixinAppTrustZoneV2 + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneV2 + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersionHiddenImageVersion + - Mbi_ExportMixinAppTrustZoneV2 + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneV2 + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersionHiddenImageVersion + - Mbi_ExportMixinAppTrustZoneV2 + - Mbi_ExportMixinCrcSignEnd + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneV2 + - Mbi_MixinFwVersionHiddenImageVersion + - Mbi_ExportMixinAppTrustZoneV2 + - Mbi_ExportMixinCrcSignEnd + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinTrustZoneV2 + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersionHiddenImageVersion + - Mbi_MixinAppCrc + - Mbi_MixinAhab + - Mbi_ExportMixinAppTzCrcAhab + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + ahab: + <<: *ahab_common_config + oem_images_max_cnt: 3 + image_types: + application: + CRC_CHECK: [0x01, crc_check, CRC fast data check] + EXECUTABLE: [0x03, executable, Executable Image] + TZ_DATA: [0x05, tz_data, Trust Zone Preset data] + + # ======== Secure binary v4.0 section ======== + sb40: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + - reset + + variable_block_length: true + commands_block_length: 4096 + supports_compression: true + + ahab: + <<: *ahab_common_config + oem_images_max_cnt: 1 + image_types: + application: + SB40_DESCRIPTOR: [0x0f, secure_binary_4, Secure binary 4.0] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + + # ======== TrustZone section ======== + tz: + version: v2 # TrustZone configuration version v2.0 + + # ======== DICE configuration ======== + dice: + buffer_address: 0x2000_2000 + buffer_size: 0x1000 + rkth_length: 64 + rkth_truncated_length: 48 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB4] + key_blob_offset: 0 + key_blob_command_position: -1 + key_wraps_version: 2 + devbuff_wrapped_cust_mk_sk_key_size: 0x30 + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + - reset + + # ======== PFR section ======== + pfr: + sub_features: [ifr, cmpa, cfpa] + ifr: + address: 0x10000000 + reg_spec: ifr0.json + reg_spec_modification: + field100: # CFPA IMG_CMAC_CACHE + reverse: True + config_as_hexstring: True + field110: # CFPA NBU_IMG_CMAC_CACHE + reverse: True + config_as_hexstring: True + field260: # CMPA ROTKH + reverse: True + config_as_hexstring: True + field290: # CMPA CUST_MK_SK_KEY_BLOB + reverse: True + config_as_hexstring: True + field2c0: # CMPA PQC_ROTKH + reverse: True + config_as_hexstring: True + cmpa: + address: 0x100_4000 + reg_spec: pfr_cmpa.json + reg_spec_modification: + field260: # CMPA ROTKH + reverse: True + config_as_hexstring: True + field290: # CMPA CUST_MK_SK_KEY_BLOB + reverse: True + config_as_hexstring: True + field2c0: # CMPA PQC_ROTKH + reverse: True + config_as_hexstring: True + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 384 + reversed: true + config_as_hexstring: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key table hash. + Root of Trust Key Hash is SHA256 or SHA384 of RoTK public. Hash algorithm is selected + based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). + Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates + container and signed boot image based on CMPA.RoTKx_Usage. + sub_regs: + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + - field080 + - field084 + - field088 + - field08C + - uid: cmpa_keyblob + name: CUST_MK_SK_KEY_BLOB + width: 384 + reversed: false + config_as_hexstring: true + description: CUST_MK_SK key blob. + CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. + CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. + To store this key into CMPA, SB_STORE_KEY command should be used. + sub_regs: + - field160 + - field164 + - field168 + - field16C + - field170 + - field174 + - field178 + - field17C + - field180 + - field184 + - field188 + - field18C + - uid: cmpa_pqc_rotkh + name: PQC_ROTKH + width: 384 + reversed: true + config_as_hexstring: true + description: + PQC_ROTKH field is compounded by 12 32-bit fields and contains Root key table hash. + Root of Trust Key Hash is SHA256 or SHA384 of RoTK public. Same RoTKs and RoTKTH values are shared between debug authentication, SB4 firmware updates + container and signed boot image based on CMPA.RoTKx_Usage. + sub_regs: + - field190 + - field194 + - field198 + - field19C + - field1A0 + - field1A4 + - field1A8 + - field1AC + - field1B0 + - field1B4 + - field1B8 + - field1BC + computed_fields: + field040: # DCFG_CC_SOCU_PIN + field040-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field044: # DCFG_CC_SOCU_DFLT + field044-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + cfpa: + address: 0x100_0000 + reg_spec: pfr_cfpa.json + reg_spec_modification: + field0E0: # CFPA IMG0 CMAC + reverse: True + config_as_hexstring: True + field0F0: # CFPA IMG1 CMAC + reverse: True + config_as_hexstring: True + field1F0: # CFPA CMAC + reverse: True + config_as_hexstring: True + computed_fields: + field000: # HEADER + field000-bits8-15: pfr_reg_inverse_lower_8_bits # INV_CFPA_LC_STATE + field020: # DBG_REVOKE_VU + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_PIN + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field028: # DCFG_CC_SOCU_NS_DFLT + field028-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: MCXN + prov_method: dispatch_fw + dispatch_method: sb_only + use_additional_data: true + fw_read_address: 0x2000_0100 + ignored_otp_ranges: [11, 22] + validation_method: max_count=16;max_total_size=16384 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/fuses.json new file mode 100644 index 0000000..f56dff9 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/fuses.json @@ -0,0 +1,3186 @@ +{ + "cpu": "mcxn556s", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Boot configuration locks" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Boot configuration locks", + "index_int": "0", + "bitfields": [ + { + "width": 9 + }, + { + "width": 3, + "id": "fuse0-bits-9-11", + "name": "BOOT_CFG_LOCK[2:0]", + "description": "Boot config Lock\nConfigures the locking of EFUSE bits in the address range 800 to 1439.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: Reserved.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "PRINCE_CFG_LOCK[2:0]", + "description": "Prince Config Lock\nConfigures the locking of EFUSE bits in the address range 1440 to 1951.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: Reserved", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-18-20", + "name": "CUST_LOCK0[2:0]", + "description": "CUST Lock 0\nConfigures the locking of EFUSE bits in the address range 2080 to 2207.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: Reserved", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-21-23", + "name": "CUST_LOCK1[2:0]", + "description": "CUST Lock 1\nConfigures the locking of EFUSE bits in the address range 2208 to 2335.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: Reserved", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-24-26", + "name": "CUST_LOCK2[2:0]", + "description": "CUST Lock 2\nConfigures the locking of EFUSE bits in the address range 2336 to 2463.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: Reserved", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-27-29", + "name": "CUST_LOCK3[2:0]", + "description": "CUST Lock 3\nConfigures the locking of EFUSE bits in the address range 2464 to 2719.\n• bit 0: When set, blocks programming.\n• bit 1: Reserved\n• bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 2 + } + ] + } + ] + }, + { + "group": { + "name": "Configurations", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse1", + "name": "LIFE_CYCLE", + "description": "Boot configuration", + "index_int": "0x0001", + "bitfields": [ + { + "width": 8, + "id": "fuse1-bits-0-7", + "name": "LIFECYCLE[7:0]", + "description": "Life cycle state.\nThis field can be used to advance life cycle state.\n\nBelow are the allowed values for this field. Use of other values may lead to bricked state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank state" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-8", + "name": "NIDEN_dis", + "description": "Non-secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-9", + "name": "DBGEN_dis", + "description": "Non-secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-10", + "name": "SPIDEN_dis", + "description": "Secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-11", + "name": "SPNIDEN_dis", + "description": "Secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-12", + "name": "CPU1_NIDEN_dis", + "description": "CPU1 non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-13", + "name": "CPU1_DBG_dis", + "description": "CPU1 invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-14", + "name": "DSP_DBGEN_dis", + "description": "DSP debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-15", + "name": "ISP_CMD_dis", + "description": "Enter ISP Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-16", + "name": "FA_CMD_dis", + "description": "Set FA mode Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-17", + "name": "ME_CMD_dis", + "description": "Mass erase Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-18", + "name": "UUID_CHECK_ENF", + "description": "Enforce UUID checking during debug authentication.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Enable", + "value": 1, + "description": "Always enabled." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse1-bit-20", + "name": "RoTK0_dis", + "description": "Revoke Root of Trust key 0.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-21", + "name": "RoTK1_dis", + "description": "Revoke Root of Trust key 1.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-22", + "name": "RoTK2_dis", + "description": "Revoke Root of Trust key 2.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-23", + "name": "RoTK3_dis", + "description": "Revoke Root of Trust key 3.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 8, + "id": "fuse1-bits-24-31", + "name": "LIFECYCLE_DP[7:0]", + "description": "Duplicate of the LIFECYCLE fuse value. Should be same with LIFECYCLE.\n\nBelow are the allowed values for this field. Use of other values may lead to bricked state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank state" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + } + ] + }, + { + "id": "fuse2", + "name": "KEY_REVOKE", + "description": "Boot configuration", + "index_int": "0x0002", + "bitfields": [ + { + "width": 8, + "id": "fuse2-bits-0-7", + "name": "DBG_KEY_REVOKE[7:0]", + "description": "Debug key revoke.\nThis field is combined with\nCFPA.DBG_REVOKE_VU and CMPA.VENDOR_USAGE fields to form a 32-bit value which is compared with vendor usage field in debug credential certificate. Only if the values match debug access is granted.\nCC_VENDOR_USAGE = { CMPA.VENDOR_USAGE[31:16],\nCFPA.DBG_REVOKE_VU[15:8],\n(CFPA.DBG_REVOKE_VU[7:0] | OTP.DBG_KEY_REVOKE[7:0]) };" + }, + { + "width": 8, + "id": "fuse2-bits-8-15", + "name": "IMAGE_KEY_REVOKE[7:0]", + "description": "Image signing key revoke.\nThis field is combined with\nCFPA.IMAGE_KEY_REVOKE field to form a 32-bit value which is compared with IskCertificate.constraints field during image authentication. If the values don't match image authentication fails.\n\nISK_CONSTRAINT[31:0] = {CFPA.IMAGE_KEY_REVOKE_VU[23:0], OTP.IMAGE_KEY_REVOKE[7:0] };" + }, + { + "width": 4 + }, + { + "width": 1, + "id": "fuse2-bit-20", + "name": "PUF_ENROLL_DIS", + "description": "Block PUF enrollment.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse2-bit-23", + "name": "DIS_NXP_FW", + "description": "Block NXP signed SB3 loading.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow NXP signed SB3 FW" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable NXP signed SB3 FW" + } + ] + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse3", + "name": "BOOT_CFG", + "description": "Boot configuration", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse3-bit-0", + "name": "Boot_FlexSPI_Dis", + "description": "ROM code will not manage these fields, but SDK driver can manage these.\n\nFlexSPI boot disable.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "FlexSPI boot is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "FlexSPI boot is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-1", + "name": "Boot_flash_Dis", + "description": "Boot from internal flash.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from internal flash enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from internal flash disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-2", + "name": "Boot_IFR0_Dis", + "description": "Boot from IFR0 (as SBL).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from IFR0 enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from IFR0 disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse3-bit-5", + "name": "Rec_Boot_SPI_Dis", + "description": "Recovery boot from external 1-bit SPI flash connected to FlexComm ports.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-6", + "name": "Rec_Boot_IFR0_Dis", + "description": "Recovery boot from IFR0 area( 0x0100_8000 to 0x0100_FFFF).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-7", + "name": "PinSel_SPI_Rec_Boot_Dis", + "description": "Disable logic related to forcing recovery boot based on ISP pin state.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-8", + "name": "ISP_UART_Dis", + "description": "Disable UART interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "UART ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "UART ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-9", + "name": "ISP_I2C_Dis", + "description": "Disable I2C interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "I2C ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "I2C ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-10", + "name": "ISP_SPI_Dis", + "description": "Disable SPI interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SPI ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "SPI ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-11", + "name": "ISP_USB0_Dis", + "description": "Disable USB0 interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "USB0 ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "USB0 ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-12", + "name": "ISP_USB1_Dis", + "description": "Disable USB1 interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "USB1 ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "USB1 ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-13", + "name": "ISP_CAN_Dis", + "description": "Disable CAN interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "CAN ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "CAN ISP is disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse3-bits-16-17", + "name": "ISP_DISABLE", + "description": "Disable ISP mode entry points\nISP mode can be entered through pin assertion, debug mailbox command, image verification failure and ROM API invocation", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "All entry point allowed." + }, + { + "name": "Disable_ISP_pin", + "value": 1, + "description": "Entry by ISP Pin assertion disabled." + }, + { + "name": "Disable", + "value": 2, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + }, + { + "name": "Disable_0", + "value": 3, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + } + ] + }, + { + "width": 4 + }, + { + "width": 2, + "id": "fuse3-bits-22-23", + "name": "BOOT_SPEED[1:0]", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution.", + "values": [ + { + "name": "CMPA_BOOT_SPEED", + "value": 0, + "description": "Use value from CMPA.BOOT_SPEED" + }, + { + "name": "72MHz FRO", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "144MHz FRO", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "150MHz PLL", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 5, + "id": "fuse3-bits-24-28", + "name": "FLASH_REMAP_SZ[4:0]", + "description": "Flash remap size.\nFLASH_REMAP_SZ defines the size of the secondary boot image\n(the range of flash addresses that will be remapped)in internal flash, where remapped\naddress end = (FLASH_REMAP_SZ + 1) * 32 KB. For example, if FLASH_REMAP_SZ = 2,\nthen the first 96KB of addresses will be remapped to flash bank1 instead of flash bank0\nwhen remap is active. Set this field to 0 if you do not want to use the flash remap feature" + }, + { + "width": 3, + "id": "fuse3-bits-29-31", + "name": "OEM_BANK1_IFR0_USAGE", + "description": "Defines flash protection of Bank1_IFR0 area based on usage.\n\nNote, if the SBL / Recovery image size is more than IFR0 size of 32KB then sectors from user flash can be associated for extended image size using CMPA.REC_IMG_EXT0/1.", + "values": [ + { + "name": "000", + "value": 0, + "description": "Not determined by ROM (MBC fields are modified by OEM code)" + }, + { + "name": "001", + "value": 1, + "description": "Used as OEM Root of Trust image, in other words secondary boot loader (OEM_SBL). MBC protection bits set as RWXL = 1010. Updatable by OEM code later." + }, + { + "name": "010", + "value": 2, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 1011." + }, + { + "name": "011", + "value": 3, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 0011." + }, + { + "name": "100", + "value": 4, + "description": "Used as OEM recovery boot image with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1010 on ROM exiting to user image." + }, + { + "name": "101", + "value": 5, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1011 on ROM exiting to user image." + }, + { + "name": "110", + "value": 6, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0011 on ROM exiting to user image." + }, + { + "name": "111", + "value": 7, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0001 on ROM exiting to user image." + } + ] + } + ] + }, + { + "id": "fuse4", + "name": "FLEXSPI_BOOT_CFG0", + "description": "Boot configuration", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse4-bit-0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type.\nNote, this field is used when FLEXSPI_AUTO_PROBE_EN is set.", + "values": [ + { + "name": "QuadSPI NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "Macronix Octal", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "Micron Octal", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "Adesto Octal", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types\n\n\nThis field is always used irrespective of FLEXSPI_AUTO_PROBE_EN value.", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI_ADDR_3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER_1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER_3V3" + }, + { + "name": "FlexSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FlexSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "fuse4-bits-7-10", + "name": "FLEXSPI_DUMMY_CYCLES[3:0]", + "description": "Quad/Octal-SPI dummy cycles for read command.\n\nIf a non-zero value is programmed in this field, then the value is used to override the default number of dummy cycles for a fast read command read from the serial flash’s SFDP information.\n\nNote: this field is only used if FLEXSPI_AUTO_PROBE_EN is set." + }, + { + "width": 3, + "id": "fuse4-bits-11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Q/O-SPI flash interface frequency.\nNote, this field is used when FLEXSPI_AUTO_PROBE_EN is set.", + "values": [ + { + "name": "75Mhz", + "value": 0, + "description": "75Mhz" + }, + { + "name": "60Mhz", + "value": 1, + "description": "60Mhz" + }, + { + "name": "50Mhz", + "value": 2, + "description": "50Mhz" + }, + { + "name": "100Mhz", + "value": 3, + "description": "100Mhz" + } + ] + }, + { + "width": 1, + "id": "fuse4-bit-14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use O/QSPI_RESET_PIN to reset the flash device.", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "EN_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-15-17", + "name": "FLEXSPI_RESET_GPIO_PORT[2:0]", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO port number to use for O/QSPI reset function." + }, + { + "width": 5, + "id": "fuse4-bits-18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "GPIO pin number to use for O/QSPI reset function." + }, + { + "width": 2, + "id": "fuse4-bits-23-24", + "name": "FLEXSPI_HOLD_TIME[1:0]", + "description": "Delay after reset before accessing Quad/Octal-SPI flash devices.\nNote, for POR in addition to this wait time FLEXSPI_PWR_HOLD_TIME is added.", + "values": [ + { + "name": "500us", + "value": 0, + "description": "Wait for 500 microseconds." + }, + { + "name": "1ms", + "value": 1, + "description": "Wait for 1 millisecond." + }, + { + "name": "3ms", + "value": 2, + "description": "Wait for 3 milliseconds." + }, + { + "name": "10ms", + "value": 3, + "description": "Wait for 10 milliseconds." + } + ] + }, + { + "width": 4, + "id": "fuse4-bits-25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field.", + "values": [ + { + "name": "No delay", + "value": 0, + "description": "No delay" + }, + { + "name": "100us", + "value": 1, + "description": "Waits additional 100 microseconds." + }, + { + "name": "500us", + "value": 2, + "description": "Waits additional 500 microseconds." + }, + { + "name": "1ms", + "value": 3, + "description": "Waits additional 1 millisecond." + }, + { + "name": "10ms", + "value": 4, + "description": "Waits additional 10 milliseconds." + }, + { + "name": "20ms", + "value": 5, + "description": "Waits additional 20 milliseconds." + }, + { + "name": "40ms", + "value": 6, + "description": "Waits additional 40 milliseconds." + }, + { + "name": "60ms", + "value": 7, + "description": "Waits additional 60 milliseconds." + }, + { + "name": "80ms", + "value": 8, + "description": "Waits additional 80 milliseconds." + }, + { + "name": "100ms", + "value": 9, + "description": "Waits additional 100 milliseconds." + }, + { + "name": "120ms", + "value": 10, + "description": "Waits additional 120 milliseconds." + }, + { + "name": "140ms", + "value": 11, + "description": "Waits additional 140 milliseconds." + }, + { + "name": "160ms", + "value": 12, + "description": "Waits additional 160 milliseconds." + }, + { + "name": "180ms", + "value": 13, + "description": "Waits additional 180 milliseconds." + }, + { + "name": "200ms", + "value": 14, + "description": "Waits additional 200 milliseconds." + }, + { + "name": "220ms", + "value": 15, + "description": "Waits additional 220 milliseconds." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse4-bit-31", + "name": "PORT_SEL", + "description": "Defines which FlexSPI portA/B is used for boot.", + "values": [ + { + "name": "Port A", + "value": 0, + "description": "Port A" + }, + { + "name": "Port B", + "value": 1, + "description": "Port B" + } + ] + } + ] + }, + { + "id": "fuse5", + "name": "FLEXSPI_BOOT_CFG1", + "description": "Boot configuration", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse5-bits-0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS).\nThe value provided here is loaded into the FLEXSPIn_DLLnCR." + }, + { + "width": 10, + "id": "fuse5-bits-7-16", + "name": "FLEXSPI_IMAGE_OFFSET[9:0]", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset.\nThis allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset.\n\nFlLEXSPI_IMAGE_OFFSET field specifies the offset location of the second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.\nIf this field is left blank boot ROM will not enable FlexSPI remap feature.\n\nThe physical flash offset is computed as below:\n\nphysical offset = FLEXSPI_IMAGE_OFFSET * 256KByte;" + }, + { + "width": 4, + "id": "fuse5-bits-17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.\n\n\nb'0000 Remap size = FLEXSPI_IMAGE_OFFSET * 256KByte;\" SIZE_OFFSET \"Size of the remapped area (aka second half) is same as first half. It is determined by FLEXSPI_IMAGE_OFFSET Field.\nb'0001 SIZE_1MB Size of remapped area is 1MByte.\nb'0010 SIZE_2MB Size of remapped area is 2MByte.\nb'0011 SIZE_3MB Size of remapped area is 3MByte.\nb'0100 SIZE_4MB Size of remapped area is 4MByte.\nb'0101 SIZE_5MB Size of remapped area is 5MByte.\nb'0110 SIZE_6MB Size of remapped area is 6MByte.\nb'0111 SIZE_7MB Size of remapped area is 7MByte.\nb'1000 SIZE_8MB Size of remapped area is 8MByte.\nb'1001 SIZE_9MB Size of remapped area is 9MByte.\nb'1010 SIZE_10MB Size of remapped area is 10MByte.\nb'1011 SIZE_11MB Size of remapped area is 11MByte.\nb'1100 SIZE_12MB Size of remapped area is 12MByte.\nb'1101 SIZE_256KB Size of remapped area is 256KByte.\nb'1110 SIZE_512KB Size of remapped area is 512KByte.\nb'1111 SIZE_768KB Size of remapped area is 768KByte.\n\nNOTE: FlexSPI remap size cannot exceed the start address of boot image 1." + }, + { + "width": 11 + } + ] + }, + { + "id": "fuse6", + "name": "SEC_BOOT_CFG", + "description": "Boot configuration", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse6-bits-0-1", + "name": "SEC_BOOT_EN", + "description": "Secure boot enforcement.\nThis field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign).\nThe Image type field in header indicates the type of verification data (checksum or signature) included in it.\n\nPlain < CRC32 < CMAC < ECDSA", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed." + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed." + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse6-bits-3-4", + "name": "LP_SEC_BOOT", + "description": "Secure boot option for low-power wake from power-down & deep-powerdown.\nFor CFPA/CMPA do CRC check always.", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA." + }, + { + "name": "CHECK_CMAC", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "fuse6-bits-8-9", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication.\nNote, CMAC image authentication is only allowed in 2b'00 setting.", + "values": [ + { + "name": "ALL_ALLOWED", + "value": 0, + "description": "All algorithm allowed." + }, + { + "name": "LIMITED", + "value": 1, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_0", + "value": 2, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_1", + "value": 3, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-10-11", + "name": "ENF_TZM_PRESET", + "description": "TrustZone-M mode.", + "values": [ + { + "name": "IGNORE", + "value": 0, + "description": "Ignored." + }, + { + "name": "ENFORCE", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_0", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_1", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event.\nZeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion & Tamper control signals an intrusion event (ITRC_OUT3).\nNote, when ITRC is re-configured in application then ITRC_OUT4 (CHIP_RESET) should be triggered with at least same events as ITRC_OUT3 (RAM_ZEROIZE) .", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action." + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only." + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only." + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "ACTIVE_IMG_PROT", + "description": "Protection of active image.\nThis field defines protection of flash area occupied by the active image. Only applicable to internal flash.", + "values": [ + { + "name": "FLASH_ACL_PROTECTION", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings." + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored." + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored." + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-16-17", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-18-19", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-20-21", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-24-25", + "name": "FIPS_CMAC_STEN", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-26-27", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-28-29", + "name": "FIPS_PUF_STEN", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse7", + "name": "RotK_USAGE", + "description": "Boot configuration", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse7-bits-0-2", + "name": "RoTK0_Usage[2:0]", + "description": "RoT key 0 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as boot image and FW update CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as boot image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-3-5", + "name": "RoTK1_Usage[2:0]", + "description": "RoT key 1 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as boot image and FW update CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as boot image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-6-8", + "name": "RoTK2_Usage[2:0]", + "description": "RoT key 2 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW_IMG", + "value": 2, + "description": "Usable as boot image and FW update CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as boot image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-9-11", + "name": "RoTK3_Usage[2:0]", + "description": "RoT key 3 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as boot image and FW update CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as boot image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "SKIP_DICE", + "description": "Skip DICE computation.", + "values": [ + { + "name": "Enable DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "Disable DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 9 + }, + { + "width": 2, + "id": "fuse7-bits-24-25", + "name": "NPX_LOCK_CTX0", + "description": "Lock on-chip flash NPX PRINCE context 0 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-26-27", + "name": "NPX_LOCK_CTX1", + "description": "Lock on-chip flash NPX PRINCE context 1 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-28-29", + "name": "NPX_LOCK_CTX2", + "description": "Lock on-chip flash NPX PRINCE context 2 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bit" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-30-31", + "name": "NPX_LOCK_CTX3", + "description": "Lock on-chip flash NPX PRINCE context 3 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + } + ] + }, + { + "id": "Reserved8", + "name": "Reserved 0x8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0xA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "Root of trust keys configuration" + }, + "registers": [ + { + "id": "fuse11", + "name": "ROTKH[31:0]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x000B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse12", + "name": "ROTKH[63:32]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse13", + "name": "ROTKH[95:64]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x000D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse14", + "name": "ROTKH[127:96]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x000E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse15", + "name": "ROTKH[159:128]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse16", + "name": "ROTKH[191:160]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0010", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse17", + "name": "ROTKH[223:192]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0011", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse18", + "name": "ROTKH[255:224]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0012", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse19", + "name": "ROTKH[287:256]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0013", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse20", + "name": "ROTKH[319:288]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0014", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse21", + "name": "ROTKH[351:320]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0015", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + }, + { + "id": "fuse22", + "name": "ROTKH[383:352]", + "description": "Root of trust keys configuration. Root of Trust Key Hash is SHA256 or SHA384 of RoTKpublic. Hash algorithm is selected based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates container and signed boot image based on CMPA.RoTKx_Usage.", + "index_int": "0x0016", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200" + } + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "Prince Context configuration" + }, + "registers": [ + { + "id": "fuse23", + "name": "NPX_CTX0_WD0", + "description": "Prince Context configuration", + "index_int": "0x0017", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse23-bits-0-31", + "name": "NPX_CTX0_WD0[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX0_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key & IV." + } + ] + }, + { + "id": "fuse24", + "name": "NPX_CTX0_WD1", + "description": "Prince Context configuration", + "index_int": "0x0018", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse24-bits-0-31", + "name": "NPX_CTX0_WD1[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX0_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key & IV." + } + ] + }, + { + "id": "fuse25", + "name": "NPX_CTX1_WD0", + "description": "Prince Context configuration", + "index_int": "0x0019", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse25-bits-0-31", + "name": "NPX_CTX1_WD0[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX1_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key & IV." + } + ] + }, + { + "id": "fuse26", + "name": "NPX_CTX1_WD1", + "description": "Prince Context configuration", + "index_int": "0x001A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse26-bits-0-31", + "name": "NPX_CTX1_WD1[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX1_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key & IV." + } + ] + }, + { + "id": "fuse27", + "name": "NPX_CTX2_WD0", + "description": "Prince Context configuration", + "index_int": "0x001B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse27-bits-0-31", + "name": "NPX_CTX2_WD0[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX2_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key & IV." + } + ] + }, + { + "id": "fuse28", + "name": "NPX_CTX2_WD1", + "description": "Prince Context configuration", + "index_int": "0x001C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse28-bits-0-31", + "name": "NPX_CTX2_WD1[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX2_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key & IV." + } + ] + }, + { + "id": "fuse29", + "name": "NPX_CTX3_WD0", + "description": "Prince Context configuration", + "index_int": "0x001D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse29-bits-0-31", + "name": "NPX_CTX3_WD0[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX3_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key & IV." + } + ] + }, + { + "id": "fuse30", + "name": "NPX_CTX3_WD1", + "description": "Prince Context configuration", + "index_int": "0x001E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse30-bits-0-31", + "name": "NPX_CTX3_WD1[31:0]", + "description": "ROM copies this value to NPX->VMAPCTX3_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key & IV." + } + ] + }, + { + "id": "fuse31", + "name": "IPED_CTX_CRC32", + "description": "Prince Context configuration", + "index_int": "0x001F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse31-bits-0-31", + "name": "IPED_CTX_CRC32[31:0]", + "description": "User has to program CRC32 of IPED context configuration data present in CMPA (0x0100_40B0 - 0x0100_40EF) to have ROM do integrity check of IPED configuration data before using. This check is done only when this field is non-zero." + } + ] + }, + { + "id": "fuse32", + "name": "IPED_GP1", + "description": "Prince Context configuration", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "IPED_GP1[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse33", + "name": "IPED_GP2", + "description": "Prince Context configuration", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse33-bits-0-31", + "name": "IPED_GP2[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse34", + "name": "IPED_GP3", + "description": "Prince Context configuration", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "IPED_GP3[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse35", + "name": "IPED_GP4", + "description": "Prince Context configuration", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse35-bits-0-31", + "name": "IPED_GP4[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse36", + "name": "IPED_GP5", + "description": "Prince Context configuration", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse36-bits-0-31", + "name": "IPED_GP5[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse37", + "name": "IPED_GP6", + "description": "Prince Context configuration", + "index_int": "0x0025", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse37-bits-0-31", + "name": "IPED_GP6[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + }, + { + "id": "fuse38", + "name": "IPED_GP7", + "description": "Prince Context configuration", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse38-bits-0-31", + "name": "IPED_GP7[31:0]", + "description": "General purpose fuse words available for customer use which are locked by PRINCE_CFG_LOCK." + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x27-0x2a", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved39", + "name": "Reserved 0x27", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0027", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved40", + "name": "Reserved 0x28", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0028", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved41", + "name": "Reserved 0x29", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0029", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved42", + "name": "Reserved 0x2A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002A", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "CUST", + "description": "Customer fuses configuration" + }, + "registers": [ + { + "id": "fuse43", + "name": "GP0", + "description": "Customer fuses configuration", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse43-bits-0-31", + "name": "GP0[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse44", + "name": "GP1", + "description": "Customer fuses configuration", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse44-bits-0-31", + "name": "GP1[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse45", + "name": "GP2", + "description": "Customer fuses configuration", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse45-bits-0-31", + "name": "GP2[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse46", + "name": "GP3", + "description": "Customer fuses configuration", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse46-bits-0-31", + "name": "GP3[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse47", + "name": "GP4", + "description": "Customer fuses configuration", + "index_int": "0x002F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse47-bits-0-31", + "name": "GP4[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse48", + "name": "GP5", + "description": "Customer fuses configuration", + "index_int": "0x0030", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse48-bits-0-31", + "name": "GP5[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse49", + "name": "GP6", + "description": "Customer fuses configuration", + "index_int": "0x0031", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse49-bits-0-31", + "name": "GP6[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse50", + "name": "GP7", + "description": "Customer fuses configuration", + "index_int": "0x0032", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse50-bits-0-31", + "name": "GP7[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse51", + "name": "GP8", + "description": "Customer fuses configuration", + "index_int": "0x0033", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse51-bits-0-31", + "name": "GP8[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse52", + "name": "GP9", + "description": "Customer fuses configuration", + "index_int": "0x0034", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse52-bits-0-31", + "name": "GP9[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse53", + "name": "GP10", + "description": "Customer fuses configuration", + "index_int": "0x0035", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse53-bits-0-31", + "name": "GP10[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse54", + "name": "GP11", + "description": "Customer fuses configuration", + "index_int": "0x0036", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse54-bits-0-31", + "name": "GP11[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse55", + "name": "GP12", + "description": "Customer fuses configuration", + "index_int": "0x0037", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse55-bits-0-31", + "name": "GP12[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse56", + "name": "GP13", + "description": "Customer fuses configuration", + "index_int": "0x0038", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse56-bits-0-31", + "name": "GP13[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse57", + "name": "GP14", + "description": "Customer fuses configuration", + "index_int": "0x0039", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse57-bits-0-31", + "name": "GP14[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse58", + "name": "GP15", + "description": "Customer fuses configuration", + "index_int": "0x003A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse58-bits-0-31", + "name": "GP15[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse59", + "name": "GP16", + "description": "Customer fuses configuration", + "index_int": "0x003B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse59-bits-0-31", + "name": "GP16[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse60", + "name": "GP17", + "description": "Customer fuses configuration", + "index_int": "0x003C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse60-bits-0-31", + "name": "GP17[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse61", + "name": "GP18", + "description": "Customer fuses configuration", + "index_int": "0x003D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse61-bits-0-31", + "name": "GP18[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse62", + "name": "GP19", + "description": "Customer fuses configuration", + "index_int": "0x003E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse62-bits-0-31", + "name": "GP19[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse63", + "name": "GP20", + "description": "Customer fuses configuration", + "index_int": "0x003F", + "bitfields": [ + { + "width": 32, + "id": "fuse63-bits-0-31", + "name": "GP20[31:0]", + "description": "General purpose fuse bits available for customer use." + } + ] + }, + { + "id": "fuse64", + "name": "GP21", + "description": "Customer fuses configuration", + "index_int": "0x0040", + "bitfields": [ + { + "width": 32, + "id": "fuse64-bits-0-31", + "name": "GP21[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse65", + "name": "GP22", + "description": "Customer fuses configuration", + "index_int": "0x0041", + "bitfields": [ + { + "width": 32, + "id": "fuse65-bits-0-31", + "name": "GP22[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse66", + "name": "GP23", + "description": "Customer fuses configuration", + "index_int": "0x0042", + "bitfields": [ + { + "width": 32, + "id": "fuse66-bits-0-31", + "name": "GP23[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse67", + "name": "GP24", + "description": "Customer fuses configuration", + "index_int": "0x0043", + "bitfields": [ + { + "width": 32, + "id": "fuse67-bits-0-31", + "name": "GP24[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse68", + "name": "GP25", + "description": "Customer fuses configuration", + "index_int": "0x0044", + "bitfields": [ + { + "width": 32, + "id": "fuse68-bits-0-31", + "name": "GP25[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse69", + "name": "GP26", + "description": "Customer fuses configuration", + "index_int": "0x0045", + "bitfields": [ + { + "width": 32, + "id": "fuse69-bits-0-31", + "name": "GP26[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse70", + "name": "GP27", + "description": "Customer fuses configuration", + "index_int": "0x0046", + "bitfields": [ + { + "width": 32, + "id": "fuse70-bits-0-31", + "name": "GP27[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse71", + "name": "GP28", + "description": "Customer fuses configuration", + "index_int": "0x0047", + "bitfields": [ + { + "width": 32, + "id": "fuse71-bits-0-31", + "name": "GP28[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse72", + "name": "GP29", + "description": "Customer fuses configuration", + "index_int": "0x0048", + "bitfields": [ + { + "width": 32, + "id": "fuse72-bits-0-31", + "name": "GP29[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse73", + "name": "GP30", + "description": "Customer fuses configuration", + "index_int": "0x0049", + "bitfields": [ + { + "width": 32, + "id": "fuse73-bits-0-31", + "name": "GP30[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse74", + "name": "GP31", + "description": "Customer fuses configuration", + "index_int": "0x004A", + "bitfields": [ + { + "width": 32, + "id": "fuse74-bits-0-31", + "name": "GP31[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse75", + "name": "GP32", + "description": "Customer fuses configuration", + "index_int": "0x004B", + "bitfields": [ + { + "width": 32, + "id": "fuse75-bits-0-31", + "name": "GP32[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse76", + "name": "GP33", + "description": "Customer fuses configuration", + "index_int": "0x004C", + "bitfields": [ + { + "width": 32, + "id": "fuse76-bits-0-31", + "name": "GP33[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse77", + "name": "GP34", + "description": "Customer fuses configuration", + "index_int": "0x004D", + "bitfields": [ + { + "width": 32, + "id": "fuse77-bits-0-31", + "name": "GP34[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse78", + "name": "GP35", + "description": "Customer fuses configuration", + "index_int": "0x004E", + "bitfields": [ + { + "width": 32, + "id": "fuse78-bits-0-31", + "name": "GP35[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse79", + "name": "GP36", + "description": "Customer fuses configuration", + "index_int": "0x004F", + "bitfields": [ + { + "width": 32, + "id": "fuse79-bits-0-31", + "name": "GP36[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse80", + "name": "GP37", + "description": "Customer fuses configuration", + "index_int": "0x0050", + "bitfields": [ + { + "width": 32, + "id": "fuse80-bits-0-31", + "name": "GP37[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse81", + "name": "GP38", + "description": "Customer fuses configuration", + "index_int": "0x0051", + "bitfields": [ + { + "width": 32, + "id": "fuse81-bits-0-31", + "name": "GP38[31:0]", + "description": "General purpose fuse words available for customer use." + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cfpa.json new file mode 100644 index 0000000..f5fa07a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cfpa.json @@ -0,0 +1,5119 @@ +{ + "cpu": "mcxn556s", + "groups": [ + { + "group": { + "name": "CFPA", + "description": "Customer In-Field Configuration Area." + }, + "registers": [ + { + "id": "field000", + "name": "Header", + "description": "header", + "offset_int": "0", + "default_value_int": "0x96350000", + "bitfields": [ + { + "width": 8, + "id": "field000-bits0-7", + "name": "CFPA_LC_STATE", + "description": "Life cycle state. This field can be used to advance life cycle state to 0x7, 0xF or 0xCF during development (OTP_LC_STATE = 0x3) for testing deployed states without programming OTP fuse. For actual mass production, be sure to modify the lifecycle through OTP/efuse rather than through CFPA_LC_STATE field. When CFPA is used to advance LC state, then application code should implement hooks, to revert CFPA_LC_STATE field to 0x3 to bring the device back to OEM_DEVELOP state (0x03). One such example is a GPIO interrupt handler invoked on a button press which modified the CFPA_LC_STATE to 0x3. Customer can use the CFPA_LC_STATE to advance the LC to Develop2 (0x7), In-field (0xF) and In-field Locked (0xCF) when the current efuse lifecycle is Develop (0x3). After the CFPA_LC_STATE has been set as advanced lifecycle, the CFPA_LC_STATE will be functional after warming reset the device, not the POR and wakeup reset type. But for the debug port, the following steps are required to make CFPA_LC_STATE effective for the debug port: 1.\tPerform a Power-on Reset while pulling down the ISP pin, to ensure that it directly enters ISP mode after POR. 2.\tThen perform a warm reset, such as a pin reset. Below are the allowed values for this field. Use of other values may lead to bricked state", + "values": [ + { + "name": "USE_LC_STATE_FROM_OTP", + "value": 0, + "description": "Use LC state from OTP" + }, + { + "name": "DEVELOP__STATE", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP_2_STATE", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN-FIELD_STATE", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN-FIELD_LOCKED_STATE", + "value": 207, + "description": "In-field locked state" + } + ] + }, + { + "width": 8, + "id": "field000-bits8-15", + "name": "INV_CFPA_LC_STATE", + "description": "Inverted value of CFPA_LC_STATE. This INV_CPFA_LC_STATE ^ CFPA_LC_STATE[7:0] should be 0xFF, otherwise the CPFA_LC_STATE will not be valid", + "calculated": "INVERSE" + }, + { + "width": 16, + "id": "field000-bits16-31", + "name": "Header", + "description": "After this header is set, all non-zero values will take effect; leaving all values set to 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CFPA header", + "values": [ + { + "name": "DEFAULT", + "value": 38453, + "description": "CFPA Header marker should be set to 0x9635" + } + ] + } + ] + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "cfpa page version", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 24, + "id": "field004-bits0-23", + "name": "CFPA_page_version", + "description": "CFPA page version. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped. CFPA_PAGE_VERSION may begin at 0x1 and user may manually increment the value by 1 or use value 0xFF_FFFF and ROM will auto-increment this field" + }, + { + "width": 2, + "id": "field004-bits24-25", + "name": "IMG_UPD", + "description": "Image updated", + "values": [ + { + "name": "No action", + "value": 0, + "description": "No action" + }, + { + "name": "Update Img 0 CMAC", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "Update Img 1 CMAC", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "Update SBL Img CMAC", + "value": 3, + "description": "Update SBL image CMAC (image in IFR0 0x0100_8000). Value written in IMG0_CMAC field" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field004-bits27-29", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in Develop (0x3) LC state" + }, + { + "width": 1, + "id": "field004-bit30", + "name": "DICE_KEY_UPD_ALIAS", + "description": "Update DICE key during next boot", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "GENERATE_DICE_KEY", + "value": 1, + "description": "Generate DICE key" + } + ] + }, + { + "width": 1, + "id": "field004-bit31", + "name": "DICE_UPD", + "description": "Update DICE certificate during next boot", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "GENERATE_CERTIFICATE", + "value": 1, + "description": "Generate certificate" + } + ] + } + ] + }, + { + "id": "field008", + "name": "Secure_FW_Version", + "description": "secure fw version", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "Secure_firmware_version", + "description": "Secure Firmware version. This monotonic counter field tracks the firmware version of secure partition. ROM uses this field to enforce anti-rollback checking during secure boot and secure update (SB3 header). For image authentication pass during secure boot the FW version in image manifest must be equal or greater than this value. During secure update & recovery boot the version number in SB3 header Must be equal or greater than the value in this field. Apart from SB3 header check, user can enforce anti-rollback check during SB3 processing by using \"kSB3_COMMAND_fwVersionCheck\" SB command with 'kNBOOT_CNT_secure' counter ID parameter, in SB3 file" + }, + { + "width": 16 + } + ] + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware version. This monotonic counter field can be used to track the firmware version of non-secure partition. An anti-rollback check can be enforced during update by using this field and \"kSB3_COMMAND_fwVersionCheck\" SB command with 'kNBOOT_CNT_nonsecure' counter ID parameter, in SB3 file.", + "offset_int": "0x000C", + "default_value_int": "0" + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field014", + "name": "SECBOOT_FLAGS", + "description": "secboot flags", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable. Determines if ROTK0 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable. Determines if ROTK1 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable. Determines if ROTK2 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable. Determines if ROTK3 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits8-9", + "name": "PQC_RoTK0_EN", + "description": "RoT Key 0 enable. Determines if ROTK0 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits10-11", + "name": "PQC_RoTK1_EN", + "description": "RoT Key 1 enable. Determines if ROTK1 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits12-13", + "name": "PQC_RoTK2_EN", + "description": "RoT Key 2 enable. Determines if ROTK2 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits14-15", + "name": "PQC_RoTK3_EN", + "description": "RoT Key 3 enable. Determines if ROTK3 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "field014-bits28-31", + "name": "OEM_RETURN_ERASE_DONE", + "description": "OEM assets erase done flag. ROM sets this field to 0xA after erasing the user flash and OEM assets. This operation is done on first boot after OTP_LC_STATE is advanced to 0x1F or higher states. On every boot ROM checks if LC_STATE is greater or equal to 0x1F and this field is empty in active CFPA page, then it erases OEM assets and updates this field in CFPA before freezing CFPA pages and enabling debug access. If the field is already set to 0xA then it proceeds without erasing user flash area" + } + ] + }, + { + "id": "field018", + "name": "IMAGE_KEY_REVOKE", + "description": "image key revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 24, + "id": "field018-bits0-23", + "name": "Image_key_revocation_ID", + "description": "Image signing key revocation counter. This monotonically increasing unary encode counter (e.g., 0x0, 0x1, 0x3, 0x7, 0xF...) field is used by boot ROM to enforce image signing key (ISK) certificate revocation policy. Boot ROM accepts an ISK certificate as valid only if the \"constraint\" field in ISK certificate is the same or greater than the ISK revocation counter. The 32-bit ISK revocation counter is formed using 8 bits of IMAGE_KEY_REVOKE[7:0] field in OTP as MSB bits and lower 24 bits from this field. ISK certificate validation is done as part of boot, FW update (SB3) and recovery (SB3) image authentication" + }, + { + "width": 8 + } + ] + }, + { + "id": "field01C", + "name": "LP_VECTOR_ADDR", + "description": "lp vector addr", + "offset_int": "0x001C", + "default_value_int": "0" + }, + { + "id": "field020", + "name": "DBG_REVOKE_VU", + "description": "dbg revoke vu", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field020-bits0-15", + "name": "Debug_certificate_revocation_counter", + "description": "Debug certificate revocation counter. This monotonic counter field is used for revoking debug certificates. As part of debug authentication, CC_VU field in debug certificate/credential is checked against DCFG_VENDOR_USAGE value. The 32-bit DCFG_VENDOR_USAGE is formed using upper 16 bit of CMPA.VENDOR_USAGE and lower 16 bits of this field" + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "Inverse_value", + "description": "inverse value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, for ease of development, Level 1 customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access.", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug enable CoolFlex debug", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase cmd enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 non-invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "All Devices", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "Matching UUID", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "Inverse_value", + "description": "inverse value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access.", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field028-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug. Enable CoolFlux debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field028-bits16-31", + "name": "Inverse_value", + "description": "inverse value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field030", + "name": "MCTR_NPX_CTX0", + "description": "mctr npx ctx0", + "offset_int": "0x0030", + "default_value_int": "0" + }, + { + "id": "field034", + "name": "MCTR_NPX_CTX1", + "description": "MCTR NPX CTX1", + "offset_int": "0x0034", + "default_value_int": "0" + }, + { + "id": "field038", + "name": "MCTR_NPX_CTX2", + "description": "mctr npx ctx2", + "offset_int": "0x0038", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "MCTR_NPX_CTX3", + "description": "mctr npx ctx3", + "offset_int": "0x003C", + "default_value_int": "0" + }, + { + "id": "field040", + "name": "MCTR_IPED_CTX0", + "description": "ROM code will not manage these fields, but SDK driver can manage these.", + "offset_int": "0x0040", + "default_value_int": "0" + }, + { + "id": "field044", + "name": "MCTR_IPED_CTX1", + "description": "MCTR IPED CTX1", + "offset_int": "0x0044", + "default_value_int": "0" + }, + { + "id": "field048", + "name": "MCTR_IPED_CTX2", + "description": "mctr iped ctx2", + "offset_int": "0x0048", + "default_value_int": "0" + }, + { + "id": "field04C", + "name": "MCTR_IPED_CTX3", + "description": "mctr iped ctx3", + "offset_int": "0x004C", + "default_value_int": "0" + }, + { + "id": "field050", + "name": "MCTR_IPED_CTX4", + "description": "mctr iped ctx4", + "offset_int": "0x0050", + "default_value_int": "0" + }, + { + "id": "field054", + "name": "MCTR_IPED_CTX5", + "description": "mctr iped ctx5", + "offset_int": "0x0054", + "default_value_int": "0" + }, + { + "id": "field058", + "name": "MCTR_IPED_CTX6", + "description": "mctr iped ctx6", + "offset_int": "0x0058", + "default_value_int": "0" + }, + { + "id": "field05C", + "name": "MCTR_IPED_CTX7", + "description": "mctr iped ctx7", + "offset_int": "0x005C", + "default_value_int": "0" + }, + { + "id": "field060", + "name": "ERR_AUTH_FAIL_COUNT", + "description": "err auth fail count", + "offset_int": "0x0060", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ERR_ITRC_COUNT", + "description": "err itrc count", + "offset_int": "0x0064", + "default_value_int": "0" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field080", + "name": "MCTR_CUST_CTR0", + "description": "mctr cust ctr0", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "MCTR_CUST_CTR1", + "description": "MCTR CUST CTR1", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "MCTR_CUST_CTR2", + "description": "mctr cust ctr2", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "MCTR_CUST_CTR3", + "description": "mctr cust ctr3", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "MCTR_CUST_CTR4", + "description": "mctr cust ctr4", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "MCTR_CUST_CTR5", + "description": "mctr cust ctr5", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "MCTR_CUST_CTR6", + "description": "mctr cust ctr6", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "MCTR_CUST_CTR7", + "description": "mctr cust ctr7", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "MFLAG_CUST_0", + "description": "mflag cust 0", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "MFLAG_CUST_1", + "description": "MFLAG CUST 1", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "MFLAG_CUST_2", + "description": "mflag cust 2", + "offset_int": "0x00A8", + "default_value_int": "0" + }, + { + "id": "field0AC", + "name": "MFLAG_CUST_3", + "description": "mflag cust 3", + "offset_int": "0x00AC", + "default_value_int": "0" + }, + { + "id": "field0B0", + "name": "MFLAG_CUST_4", + "description": "mflag cust 4", + "offset_int": "0x00B0", + "default_value_int": "0" + }, + { + "id": "field0B4", + "name": "MFLAG_CUST_5", + "description": "mflag cust 5", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "MFLAG_CUST_6", + "description": "mflag cust 6", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "field0BC", + "name": "MFLAG_CUST_7", + "description": "mflag cust 7", + "offset_int": "0x00BC", + "default_value_int": "0" + }, + { + "id": "field0C0", + "name": "FLASH_ACL_0_7", + "description": "flash acl 0 7", + "offset_int": "0x00C0", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C0-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_7FFF). Select one of the 8 pre-defined access control attributes for the given Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector. (offset range 0x01_8000 - 0x01_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C4", + "name": "FLASH_ACL_8_15", + "description": "flash acl 8 15", + "offset_int": "0x00C4", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C4-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector. (offset range 0x05_8000 - 0x05_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C8", + "name": "FLASH_ACL_16_23", + "description": "flash acl 16 23", + "offset_int": "0x00C8", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0C8-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector. (offset range 0x09_8000 - 0x09_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0CC", + "name": "FLASH_ACL_24_31", + "description": "FLASH ACL 24 31", + "offset_int": "0x00CC", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0CC-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector. (offset range 0x0D_8000 - 0x0D_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D0", + "name": "FLASH_ACL_32_39", + "description": "flash acl 32 39", + "offset_int": "0x00D0", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0D0-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x10_0000 - 0x10_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x10_8000 - 0x10_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x11_0000 - 0x11_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector. (offset range 0x11_8000 - 0x11_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x12_0000 - 0x12_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x12_8000 - 0x12_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x13_0000 - 0x13_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x13_8000 - 0x13_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D4", + "name": "FLASH_ACL_40_47", + "description": "flash acl 40 47", + "offset_int": "0x00D4", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0D4-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x14_0000 - 0x14_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x14_8000 - 0x14_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x15_0000 - 0x15_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector. (offset range 0x15_8000 - 0x15_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x16_0000 - 0x16_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x16_8000 - 0x16_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x17_0000 - 0x17_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x17_8000 - 0x17_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D8", + "name": "FLASH_ACL_48_55", + "description": "flash acl 48 55", + "offset_int": "0x00D8", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0D8-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x18_0000 - 0x18_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x18_8000 - 0x18_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x19_0000 - 0x19_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector. (offset range 0x19_8000 - 0x19_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x1A_0000 - 0x1A_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x1A_8000 - 0x1A_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x1B_0000 - 0x1B_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x1B_8000 - 0x1B_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0DC", + "name": "FLASH_ACL_55_63", + "description": "flash acl 55 63", + "offset_int": "0x00DC", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field0DC-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x1C_0000 - 0x1C_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x1C_8000 - 0x1C_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x1D_0000 - 0x1D_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector. (offset range 0x1D_8000 - 0x1D_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x1E_0000 - 0x1E_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x1E_8000 - 0x1E_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x1F_0000 - 0x1F_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x1F_8000 - 0x1F_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. • If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. ○ 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) • If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "FLASH_RW_LOCKED", + "value": 1, + "description": "Data flash memory with this setting: R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "ROM with this setting: RX + locked" + }, + { + "name": "DROM_LOCKED", + "value": 3, + "description": "Data read-only memory (DROM) with this setting: ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "ROM with this setting: RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM with this setting: XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM with this setting: XOM + locked" + }, + { + "name": "HIDDEN", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0E0", + "name": "IMG0_CMAC0", + "description": "img0 cmac", + "offset_int": "0x00E0", + "default_value_int": "0" + }, + { + "id": "field0E4", + "name": "IMG0_CMAC1", + "description": "img0 cmac", + "offset_int": "0x00E4", + "default_value_int": "0" + }, + { + "id": "field0E8", + "name": "IMG0_CMAC2", + "description": "img0 cmac", + "offset_int": "0x00E8", + "default_value_int": "0" + }, + { + "id": "field0EC", + "name": "IMG0_CMAC3", + "description": "img0 cmac", + "offset_int": "0x00EC", + "default_value_int": "0" + }, + { + "id": "field0F0", + "name": "IMG1_CMAC0", + "description": "img1 cmac", + "offset_int": "0x00F0", + "default_value_int": "0" + }, + { + "id": "field0F4", + "name": "IMG1_CMAC1", + "description": "img1 cmac", + "offset_int": "0x00F4", + "default_value_int": "0" + }, + { + "id": "field0F8", + "name": "IMG1_CMAC2", + "description": "img1 cmac", + "offset_int": "0x00F8", + "default_value_int": "0" + }, + { + "id": "field0FC", + "name": "IMG1_CMAC3", + "description": "img1 cmac", + "offset_int": "0x00FC", + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00120", + "name": "Reserved 0x00120", + "description": "This field is reserved for internal use", + "offset_int": "0x0120", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field190", + "name": "IPED_GCM_AAD_CTX0", + "description": "ROM code will not manage these fields, but SDK driver can manage these.", + "offset_int": "0x0190", + "default_value_int": "0" + }, + { + "id": "field194", + "name": "IPED_GCM_AAD_CTX1", + "description": "IPED GCM AAD CTX1", + "offset_int": "0x0194", + "default_value_int": "0" + }, + { + "id": "field198", + "name": "IPED_GCM_AAD_CTX2", + "description": "iped gcm aad ctx2", + "offset_int": "0x0198", + "default_value_int": "0" + }, + { + "id": "field19C", + "name": "IPED_GCM_AAD_CTX3", + "description": "iped gcm aad ctx3", + "offset_int": "0x019C", + "default_value_int": "0" + }, + { + "id": "field1A0", + "name": "IPED_GCM_AAD_CTX4", + "description": "iped gcm aad ctx4", + "offset_int": "0x01A0", + "default_value_int": "0" + }, + { + "id": "field1A4", + "name": "IPED_GCM_AAD_CTX5", + "description": "iped gcm aad ctx5", + "offset_int": "0x01A4", + "default_value_int": "0" + }, + { + "id": "field1A8", + "name": "IPED_GCM_AAD_CTX6", + "description": "iped gcm aad ctx6", + "offset_int": "0x01A8", + "default_value_int": "0" + }, + { + "id": "field1AC", + "name": "IPED_GCM_AAD_CTX7", + "description": "iped gcm aad ctx7", + "offset_int": "0x01AC", + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "cfpa crc32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "cfpa0 cmac", + "offset_int": "0x01F0", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CFPA0 CMAC1", + "offset_int": "0x01F4", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CFPA0 CMAC2", + "offset_int": "0x01F8", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CFPA0 CMAC3", + "offset_int": "0x01FC", + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cmpa.json new file mode 100644 index 0000000..411a341 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn556s/pfr_cmpa.json @@ -0,0 +1,3674 @@ +{ + "cpu": "mcxn556s", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "boot cfg", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 2, + "id": "field000-bits0-1", + "name": "BOOT_SRC", + "description": "Primary boot source", + "values": [ + { + "name": "INTERNAL_FLASH_0", + "value": 0, + "description": "Internal flash" + }, + { + "name": "SECONDARY_BOOTLOADER", + "value": 2, + "description": "Secondary Boot loader in Bank1 IFR0 (32KB)" + }, + { + "name": "INTERNAL_FLASH_3", + "value": 3, + "description": "Internal flash" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE_ISP", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE_ISP", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + }, + { + "name": "USB1_HID", + "value": 5, + "description": "USB1 HID" + }, + { + "name": "CAN_ISP", + "value": 6, + "description": "CAN ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits8-9", + "name": "REC_BOOT_SRC", + "description": "Recovery boot source", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Recovery boot disabled" + }, + { + "name": "XIP img", + "value": 1, + "description": "XIP image in Bank1 IFR0 (32KB)" + }, + { + "name": "SB3 img", + "value": 2, + "description": "SB3 image in 1-bit SPI flash connected to default FlexComm. FC7" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution", + "values": [ + { + "name": "48_MHZ_FRO_@_1.0V", + "value": 0, + "description": "48 MHz FRO @ 1.0V" + }, + { + "name": "72_MHZ_FRO_@_1.1V", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "144_MHZ_FRO_@_1.2V", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "150_MHZ_PLL_@_1.2V", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "id": "field000-bits16-31", + "name": "Header", + "description": "After this header is set, all non-zero values will take effect; leaving all settings at 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CMPA header value", + "values": [ + { + "name": "DEFAULT", + "value": 22883, + "description": "CMPA Header marker should be set to 0x9635" + } + ] + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "flash cfg", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = (FLASH_REMAP_SIZE + 1)" + }, + { + "width": 3, + "id": "field004-bits5-7", + "name": "OEM_BANK1_IFR0_PROT", + "description": "Defines flash protection of Bank1_IFR0 area based on usage. The MBC module is used to configure the access protections as readable (R), writeable (W), and/or executable (X). The access protections can also be configured as locked (L) which prevents later application code from changing the access protection configuration. The final MBC protection bits used for Bank1_IFR0 depend on the boot mode configuration, the boot path that is selected and the device life cycle state. The access This field will only modify the MBC protection bits for the Bank1_IFR0 area after the life cycle is advanced out of Develop. In the Develop life cycle state this field has no effect. For example, if using the In-Field life cycle and Bank1_IFR0 is being used as a recovery boot image (REC_BOOT_SRC = 1) and OEM_BANK1_IFR0_PROT value = 5 is selected), then for a regular boot using the primary image Bank1_IFR0 is mapped to GLBAC2. If the primary boot fails, and the recovery path is taken, then Bank1_IFR0 is mapped to GLBAC4 instead. Note: Settings 5-7 should not be used if Bank1_IFR0 is used as OEM_SBL (BOOT_SRC = 2). In Develop life cycle - All settings: MBC protection bits set as RWXL = 1110 (GLBAC0) In other life cycles –" + }, + { + "width": 2, + "id": "field004-bits8-9", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ISP_ENTRY_ALLOWED_0", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_DISABLED", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ISP_ENTRY_ALLOWED_2", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_ALLOWED_3", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ISP_ENTRY_ALLOWED_0", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_DISABLED", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ISP_ENTRY_ALLOWED_2", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_ALLOWED_3", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ISP_ENTRY_ALLOWED_0", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_DISABLED", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ISP_ENTRY_ALLOWED_2", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_ALLOWED_3", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_FT_ENTRY", + "description": "Disable ISP mode entry on image authentication failure", + "values": [ + { + "name": "ISP_ENTRY_ALLOWED_0", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_DISABLED", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ISP_ENTRY_ALLOWED_2", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ISP_ENTRY_ALLOWED_3", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "boot led status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "REC_BOOT_LED", + "description": "Assert on recovery boot. ROM drives the GPIO pin high, identified by this field whenever primary boot fails and fall through to recovery boot source. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin high identified by this field whenever primary boot fails and execution falls through to ISP mode. [[4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. ROM drives the GPIO pin high identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00" + }, + { + "width": 8 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "boot timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: ISP mode peripheral detection timeout value in seconds. If a non-zero value is program and peripheral activity is not detected within the number of seconds specified here, then the device will go to power down mode to conserve power" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_COUNT", + "description": "WDOG timeout: Upper 16 bits of 24-bit count value in WWDT0_TC register Timeout value in seconds. The lower 8 bits of WWDT0_TC are set to 0. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code" + } + ] + }, + { + "id": "field010", + "name": "FLEXSPI_CFG0", + "description": "ROM code will not manage these fields, but SDK driver can manage these.", + "offset_int": "0x0010", + "default_value_int": "0", + "deprecated_names": ["FLEXSPI_BOOT_CFG0"], + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable" + }, + { + "width": 3, + "id": "field010-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type" + }, + { + "width": 3, + "id": "field010-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types" + }, + { + "width": 4, + "id": "field010-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command. If a non-zero value is programmed in this field, then the value is used to override the default number of dummy cycles for a fast read command read from the serial flash’s SFDP information. Note: this field is only used if FLEXSPI_AUTO_PROBE_EN is set" + }, + { + "width": 3, + "id": "field010-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Q/O-SPI flash interface frequency" + }, + { + "width": 1, + "id": "field010-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use O/QSPI_RESET_PIN to reset the flash device" + }, + { + "width": 3, + "id": "field010-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO port number to use for O/QSPI reset function" + }, + { + "width": 5, + "id": "field010-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO pin number to use for O/QSPI reset function" + }, + { + "width": 2, + "id": "field010-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "Delay after reset before accessing Quad/Octal-SPI flash devices. Note, for POR in addition to this wait time FLEXSPI_PWR_HOLD_TIME is added" + }, + { + "width": 4, + "id": "field010-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field" + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit31", + "name": "PORT_SEL", + "description": "Defines which FlexSPI portA/B is used for boot", + "values": [ + { + "name": "PORT_A", + "value": 0, + "description": "Port A" + }, + { + "name": "PORT_B", + "value": 1, + "description": "Port B" + } + ] + } + ] + }, + { + "id": "field014", + "name": "FLEXSPI_CFG1", + "description": "ROM code will not manage these fields, but SDK driver can manage these.", + "offset_int": "0x0014", + "default_value_int": "0", + "deprecated_names": ["FLEXSPI_BOOT_CFG1"], + "bitfields": [ + { + "width": 7, + "id": "field014-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS). The value provided here is loaded into the FLEXSPIn_DLLnCR" + }, + { + "width": 10, + "id": "field014-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FlLEXSPI_IMAGE_OFFSET field specifies the offset location of the second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. If this field is left blank boot ROM will not enable FlexSPI remap feature. The physical flash offset is computed as below: physical offset = FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field014-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. b'0000 Remap size = FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 11 + } + ] + }, + { + "id": "field018", + "name": "REC_SPI_FLASH_CFG0", + "description": "rec spi flash cfg0", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field018-bits0-7", + "name": "REC_SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits8-11", + "name": "REC_SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field018-bits12-15", + "name": "REC_SPI_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field018-bits16-23", + "name": "REC_SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits24-27", + "name": "REC_SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field01C", + "name": "REC_SPI_FLASH_CFG1", + "description": "REC SPI FLASH CFG1", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "REC_SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "REC_SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "REC_SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "REC_SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field01C-bits28-29", + "name": "REC_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "REC_BOOT_PIN_CUST", + "description": "Use customer defined pins for 1-bit SPI recovery boot pins" + } + ] + }, + { + "id": "field020", + "name": "ISP_UART_CFG", + "description": "isp uart cfg", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_RX_PIN" + }, + { + "width": 4, + "id": "field020-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_TX_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field024", + "name": "ISP_I2C_CFG", + "description": "isp i2c cfg", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field024-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. Identifies the pin to be used as I2C_SCL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SCL_PIN" + }, + { + "width": 4, + "id": "field024-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for I2C ISP mode" + }, + { + "width": 8, + "id": "field024-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. Identifies the pin to be used as I2C_SDA pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SDA_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved00028", + "name": "Reserved 0x00028", + "description": "This field is reserved for internal use", + "offset_int": "0x0028", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field02C", + "name": "ISP_SPI_CFG0", + "description": "isp spi cfg0", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field02C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field02C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field030", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI CFG1", + "offset_int": "0x0030", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field030-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field030-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field030-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2 + } + ] + }, + { + "id": "field034", + "name": "ISP_USB_ID", + "description": "isp usb id", + "offset_int": "0x0034", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field034-bits0-15", + "name": "USB_Vendor_ID", + "description": "Customer defined USB vendor ID used during USB-ISP mode device enumeration" + }, + { + "width": 16, + "id": "field034-bits16-31", + "name": "USB_Product_ID", + "description": "Customer defined USB product ID used during USB-ISP mode device enumeration" + } + ] + }, + { + "id": "field038", + "name": "ISP_USB_CFG", + "description": "isp usb cfg", + "offset_int": "0x0038", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field038-bits0-7", + "name": "USBx_VBUS_PIN", + "description": "Override default USBx_VBUS_DETECT ISP pin. Identifies the pin to be used as USBx_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field038-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by USBx_VBUS_PIN" + }, + { + "width": 4 + }, + { + "width": 3, + "id": "field038-bits16-18", + "name": "EXT_XTAL_CLK", + "description": "USB PHY input clock frequency. For USB high speed PHY external XTAL input is needed. This field specifies the frequency of XTAL used on board. • 000 - 24MHz input clock (Divide by 20) - Default option when CMPA is blank. • 001 - 30MHz input clock (Divide by 16) • 010 - 32MHz input clock (Divide by 15) • 011 - Reserved • 100 - 20MHz input clock (Divide by 24) • 101 - 19.2MHz input clock (Divide by 25) • 110 - 16MHz input clock (Divide by 30) • 111 - 12MHz input clock (Divide by 40)" + }, + { + "width": 1, + "id": "field038-bit19", + "name": "PRE_DIV", + "description": "Enable Pre-divider. Needed to support 48MHz and other high speed crystals" + }, + { + "width": 12 + } + ] + }, + { + "id": "field03C", + "name": "ISP_MISC_CFG", + "description": "isp misc cfg", + "offset_int": "0x003C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field03C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field03C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode" + }, + { + "width": 2, + "id": "field03C-bits24-25", + "name": "ISP_CAN_CUST", + "description": "Use customer defined CAN ISP pins" + }, + { + "width": 2, + "id": "field03C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins" + }, + { + "width": 2, + "id": "field03C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins" + }, + { + "width": 2, + "id": "field03C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins" + } + ] + }, + { + "id": "field040", + "name": "CC_SOCU_PIN", + "description": "cc socu pin", + "offset_int": "0x0040", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field040-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field040-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit7", + "name": "FA_CMD_EN", + "description": "FA cmd enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase cmd enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 debug enable", + "values": [ + { + "name": "USE_DAP_TO_ENABLE", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 1, + "id": "field040-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "All devices", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "Matching UUID", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field040-bits16-31", + "name": "Inverse_value", + "description": "inverse value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field044", + "name": "CC_SOCU_DFLT", + "description": "cc socu dflt", + "offset_int": "0x0044", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field044-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field044-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 5 + }, + { + "width": 16, + "id": "field044-bits16-31", + "name": "Inverse_value", + "description": "inverse value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field048", + "name": "VENDOR_USAGE", + "description": "vendor usage", + "offset_int": "0x0048", + "default_value_int": "0", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field048-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area (CFPA.DBG_REVOKE_VU)" + } + ] + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field050", + "name": "SECURE_BOOT_CFG", + "description": "secure boot cfg", + "offset_int": "0x0050", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "SEC_BOOT_EN", + "description": "Secure boot enforcement. This field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign). The Image type field in header indicates the type of verification data (checksum or signature) included in it", + "values": [ + { + "name": "All", + "value": 0, + "description": "All Image types are allowed" + }, + { + "name": "CRC32 or signed", + "value": 1, + "description": "Only CRC32 or cryptographically signed (CMAC or ECDSA or MLDSA) images are allowed" + }, + { + "name": "Signed only", + "value": 2, + "description": "Only cryptographically Signed (CMAC or ECDSA or MLDSA) images are allowed" + }, + { + "name": "PKI signed only", + "value": 3, + "description": "Only PKI signed (ECDSA or MLDSA) images are allowed" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits3-4", + "name": "LP_SEC_BOOT", + "description": "LP_SEC_BOOT: Secure boot option for low-power wake from power-down & deep-power down. For CFPA/CMPA do CRC check always", + "values": [ + { + "name": "Same as cold boot", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CFPA-CMPA & CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image. Uses AHB_CRC image type to check image CRC and loads TZ-M preset data if present before jumping to the image" + }, + { + "name": "CFPA-CMPA & vector addr", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA" + }, + { + "name": "CFPA-CMPA & CMAC", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image. Uses AHB_CRC image type to check image CRC and loads TZ-M preset data if present before jumping to the image" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits6-7", + "name": "DICE_CSR_KEY_TYPE", + "description": "Define the DICE csr and key generation type", + "values": [ + { + "name": "ECC_P384_KEYS_0", + "value": 0, + "description": "Generate DICE ECC P-384 keys" + }, + { + "name": "ECC_P384_KEYS_1", + "value": 1, + "description": "Generate DICE ECC P-384 keys" + }, + { + "name": "SHA384_AND_MLDSA_KEYS_2", + "value": 2, + "description": "Generate DICE SHA384 & MLDSA keys" + }, + { + "name": "SHA384_AND_MLDSA_KEYS_3", + "value": 3, + "description": "Generate DICE SHA384 & MLDSA keys" + } + ] + }, + { + "width": 2, + "id": "field050-bits8-9", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication", + "values": [ + { + "name": "AT_LEAST_CNSA10_0", + "value": 0, + "description": "At least CNSA 1.0 algorithms are used. (ECC P-384, SHA384 & AES256)" + }, + { + "name": "AT_LEAST_CNSA10_1", + "value": 1, + "description": "At least CNSA 1.0 algorithms are used. (ECC P-384, SHA384 & AES256)" + }, + { + "name": "ONLY_CNSA20_2", + "value": 2, + "description": "Only CNSA 2.0 algorithms are used.(ECDSA P-384 + MLDSA-87, ML-KEM, SHA384 & AES256)" + }, + { + "name": "ONLY_CNSA20_3", + "value": 3, + "description": "Only CNSA 2.0 algorithms are used.(ECDSA P-384 + MLDSA-87, ML-KEM, SHA384 & AES256)" + } + ] + }, + { + "width": 2, + "id": "field050-bits10-11", + "name": "ENF_TZM_PRESET", + "description": "TrustZone-M mode", + "values": [ + { + "name": "IGNORED", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCED_1", + "value": 1, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCED_2", + "value": 2, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCED_3", + "value": 3, + "description": "Enforce preset TZM data in image manifest" + } + ] + }, + { + "width": 2, + "id": "field050-bits12-13", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event. Zeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion & Tamper control signals an intrusion event (ITRC_OUT3)", + "values": [ + { + "name": "No action", + "value": 0, + "description": "No action" + }, + { + "name": "Always on ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only" + }, + { + "name": "On ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only" + }, + { + "name": "Always on all reset boot", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot" + } + ] + }, + { + "width": 2, + "id": "field050-bits14-15", + "name": "ACTIVE_IMG_PROT", + "description": "Protection of active image. This field defines protection of flash area occupied by the active image. Only applicable to internal flash", + "values": [ + { + "name": "CFPA Flash", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings" + }, + { + "name": "Write with sticky lock", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored" + }, + { + "name": "Write without sticky lock", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored" + }, + { + "name": "XOM with sticky lock", + "value": 3, + "description": "XOM protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored" + } + ] + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits18-19", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits24-25", + "name": "FIPS_HMAC_STEN", + "description": "Enable self-test for HMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for KDF & CMAC blocks on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits28-29", + "name": "FIPS_PUF_STEN", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "not included" + }, + { + "name": "Boot on failure", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "ISP on failure", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "Lock on failure", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field054", + "name": "RoTK_USAGE", + "description": "rotk usage", + "offset_int": "0x0054", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "RoTK0_Usage", + "description": "RoT key 0 usage properties", + "values": [ + { + "name": "Usable", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key" + }, + { + "name": "Debug", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "Img boot fw", + "value": 2, + "description": "Usable as boot image and FW update CA only" + }, + { + "name": "Debug boot fw img", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA" + }, + { + "name": "Img fw update key", + "value": 4, + "description": "Usable as boot image key and FW update key only" + }, + { + "name": "Boot image key", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "Fw update img key", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "Key slot not used", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits3-5", + "name": "RoTK1_Usage", + "description": "RoT key 1 usage properties", + "values": [ + { + "name": "Usable", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key" + }, + { + "name": "Debug", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "Img boot fw", + "value": 2, + "description": "Usable as boot image and FW update CA only" + }, + { + "name": "Debug boot fw img", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA" + }, + { + "name": "Img fw update key", + "value": 4, + "description": "Usable as boot image key and FW update key only" + }, + { + "name": "Boot image key", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "Fw update img key", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "Key slot not used", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits6-8", + "name": "RoTK2_Usage", + "description": "RoT key 2 usage properties", + "values": [ + { + "name": "Usable", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key" + }, + { + "name": "Debug", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "Img boot fw", + "value": 2, + "description": "Usable as boot image and FW update CA only" + }, + { + "name": "Debug boot fw img", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA" + }, + { + "name": "Img fw update key", + "value": 4, + "description": "Usable as boot image key and FW update key only" + }, + { + "name": "Boot image key", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "Fw update img key", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "Key slot not used", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits9-11", + "name": "RoTK3_Usage", + "description": "RoT key 3 usage properties", + "values": [ + { + "name": "Usable", + "value": 0, + "description": "Usable as debug CA, boot image CA, FW update CA, boot image and FW update key" + }, + { + "name": "Debug", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "Img boot fw", + "value": 2, + "description": "Usable as boot image and FW update CA only" + }, + { + "name": "Debug boot fw img", + "value": 3, + "description": "Usable as debug, boot image, and FW image CA" + }, + { + "name": "Img fw update key", + "value": 4, + "description": "Usable as boot image key and FW update key only" + }, + { + "name": "Boot image key", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "Fw update img key", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "Key slot not used", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 1, + "id": "field054-bit12", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "field054-bit13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "field054-bit14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field054-bits16-17", + "name": "REG0_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 0. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check" + }, + { + "width": 2, + "id": "field054-bits18-19", + "name": "REG1_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 2. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check" + }, + { + "width": 2, + "id": "field054-bits20-21", + "name": "REG2_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 2. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check" + }, + { + "width": 2, + "id": "field054-bits22-23", + "name": "REG3_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 3. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check" + }, + { + "width": 2, + "id": "field054-bits24-25", + "name": "NPX_LOCK_CTX0", + "description": "Lock on-chip flash NPX PRINCE context 0 settings", + "values": [ + { + "name": "REGION_IS_NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "REGION_IS_LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits26-27", + "name": "NPX_LOCK_CTX1", + "description": "Lock on-chip flash NPX PRINCE context 1 settings", + "values": [ + { + "name": "REGION_IS_NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "REGION_IS_LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits28-29", + "name": "NPX_LOCK_CTX2", + "description": "Lock on-chip flash NPX PRINCE context 2 settings", + "values": [ + { + "name": "REGION_IS_NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "REGION_IS_LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits30-31", + "name": "NPX_LOCK_CTX3", + "description": "Lock on-chip flash NPX PRINCE context 3 settings", + "values": [ + { + "name": "REGION_IS_NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "REGION_IS_LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "REGION_IS_LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + } + ] + }, + { + "id": "field058", + "name": "DICE_CSR_SRAM_ADDR", + "description": "dice csr sram addr", + "offset_int": "0x0058", + "default_value_int": "0" + }, + { + "id": "field05C", + "name": "DICE_ALIAS_KEY_SRAM_ADDR", + "description": "dice alias key sram addr", + "offset_int": "0x005C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "rotkh[383:352]", + "offset_int": "0x0060", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "rotkh[351:320]", + "offset_int": "0x0064", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "rotkh[319:288]", + "offset_int": "0x0068", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "rotkh[287:256]", + "offset_int": "0x006C", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "rotkh[255:224]", + "offset_int": "0x0070", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "rotkh[223:192]", + "offset_int": "0x0074", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "rotkh[191:160]", + "offset_int": "0x0078", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "rotkh[159:128]", + "offset_int": "0x007C", + "default_value_int": "0" + }, + { + "id": "field080", + "name": "ROTKH8", + "description": "rotkh[127:96]", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "ROTKH9", + "description": "rotkh[95:64]", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "ROTKH10", + "description": "rotkh[63:32]", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "ROTKH11", + "description": "rotkh[31:0]", + "offset_int": "0x008C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Prince", + "description": "Prince configuration" + }, + "registers": [ + { + "id": "field090", + "name": "NPX_CTX0_WD0", + "description": "npx ctx0 wd0", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "NPX_CTX0_WD1", + "description": "NPX CTX0 WD1", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "NPX_CTX1_WD0", + "description": "npx ctx1 wd0", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "NPX_CTX1_WD1", + "description": "NPX CTX1 WD1", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "NPX_CTX2_WD0", + "description": "npx ctx2 wd0", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "NPX_CTX2_WD1", + "description": "NPX CTX2 WD1", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "NPX_CTX3_WD0", + "description": "npx ctx3 wd0", + "offset_int": "0x00A8", + "default_value_int": "0" + }, + { + "id": "field0AC", + "name": "NPX_CTX3_WD1", + "description": "NPX CTX3 WD1", + "offset_int": "0x00AC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED" + }, + "registers": [ + { + "id": "field0B0", + "name": "IPED0_START", + "description": "ROM code will not manage these fields, but SDK driver can manage these.", + "offset_int": "0x00B0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0B0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0B0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B0-bits8-31", + "name": "IPED_CTX0_START_ADDR", + "description": "Upper 24-bits of IPED region 0 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0B4", + "name": "IPED0_END", + "description": "iped0 end", + "offset_int": "0x00B4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0B4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B4-bits8-31", + "name": "IPED_CTX0_END_ADDR", + "description": "Upper 24-bits of IPED region 0 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0B8", + "name": "IPED1_START", + "description": "iped1 start", + "offset_int": "0x00B8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0B8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0B8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B8-bits8-31", + "name": "IPED_CTX1_START_ADDR", + "description": "Upper 24-bits of IPED region 1 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0BC", + "name": "IPED1_END", + "description": "iped1 end", + "offset_int": "0x00BC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0BC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0BC-bits8-31", + "name": "IPED_CTX1_END_ADDR", + "description": "Upper 24-bits of IPED region 1 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C0", + "name": "IPED2_START", + "description": "iped2 start", + "offset_int": "0x00C0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0C0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0C0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C0-bits8-31", + "name": "IPED_CTX2_START_ADDR", + "description": "Upper 24-bits of IPED region 2 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C4", + "name": "IPED2_END", + "description": "iped2 end", + "offset_int": "0x00C4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0C4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C4-bits8-31", + "name": "IPED_CTX2_END_ADDR", + "description": "Upper 24-bits of IPED region 2 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C8", + "name": "IPED3_START", + "description": "iped3 start", + "offset_int": "0x00C8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0C8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0C8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C8-bits8-31", + "name": "IPED_CTX3_START_ADDR", + "description": "Upper 24-bits of IPED region 3 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0CC", + "name": "IPED3_END", + "description": "iped3 end", + "offset_int": "0x00CC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0CC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0CC-bits8-31", + "name": "IPED_CTX3_END_ADDR", + "description": "Upper 24-bits of IPED region 3 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D0", + "name": "IPED4_START", + "description": "iped4 start", + "offset_int": "0x00D0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0D0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0D0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D0-bits8-31", + "name": "IPED_CTX4_START_ADDR", + "description": "Upper 24-bits of IPED region 4 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D4", + "name": "IPED4_END", + "description": "iped4 end", + "offset_int": "0x00D4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0D4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D4-bits8-31", + "name": "IPED_CTX4_END_ADDR", + "description": "Upper 24-bits of IPED region 4 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D8", + "name": "IPED5_START", + "description": "iped5 start", + "offset_int": "0x00D8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0D8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0D8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D8-bits8-31", + "name": "IPED_CTX5_START_ADDR", + "description": "Upper 24-bits of IPED region 5 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0DC", + "name": "IPED5_END", + "description": "iped5 end", + "offset_int": "0x00DC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0DC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0DC-bits8-31", + "name": "IPED_CTX5_END_ADDR", + "description": "Upper 24-bits of IPED region 5 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E0", + "name": "IPED6_START", + "description": "iped6 start", + "offset_int": "0x00E0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0E0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0E0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E0-bits8-31", + "name": "IPED_CTX6_START_ADDR", + "description": "Upper 24-bits of IPED region 6 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E4", + "name": "IPED6_END", + "description": "iped6 end", + "offset_int": "0x00E4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0E4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E4-bits8-31", + "name": "IPED_CTX6_END_ADDR", + "description": "Upper 24-bits of IPED region 6 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E8", + "name": "IPED7_START", + "description": "iped7 start", + "offset_int": "0x00E8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0E8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0E8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "BUS_ERROR_ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "BUS_ERROR_DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E8-bits8-31", + "name": "IPED_CTX7_START_ADDR", + "description": "Upper 24-bits of IPED region 7 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0EC", + "name": "IPED7_END", + "description": "iped7 end", + "offset_int": "0x00EC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0EC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the IPED context settings", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_1", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_2", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_3", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0EC-bits8-31", + "name": "IPED_CTX7_END_ADDR", + "description": "Upper 24-bits of IPED region 7 end address. Lower 8 address bits are always 0" + } + ] + } + ] + }, + { + "group": { + "name": "Recovery Image", + "description": "Recovery Image" + }, + "registers": [ + { + "id": "field0F0", + "name": "REC_IMG_EXT0", + "description": "rec img ext0", + "offset_int": "0x00F0", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field0F0-bits8-31", + "name": "REC_IMG_EXT0", + "description": "Bitmap mask to indicate sectors included in recovery image. Recovery image is programmed in BANK1_IFR0. But if the image size is more than 32KB, this field can be used to indicate sectors to include in recovery image. ROM will configure flash protection setting for these sectors the same as BANK1_IFR0 before exiting to user code. The protection settings are managed through CMPA.OEM_BANK1_IFR0_PROT. The lower 8 sectors are excluded from this mask to avoid conflicts with dual image boot feature" + } + ] + }, + { + "id": "field0F4", + "name": "REC_IMG_EXT1", + "description": "REC IMG EXT1", + "offset_int": "0x00F4", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 24, + "id": "field0F4-bits8-31", + "name": "REC_IMG_EXT1", + "description": "rec img ext1 (bitmap mask for recovery image extended sectors 40 -63)" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 000F8-00011C", + "description": "Reserved 000F8-00011C" + }, + "registers": [ + { + "id": "field0F8", + "name": "PROV_FW_SRAM_ADDR", + "description": "prov fw sram addr", + "offset_int": "0x00F8", + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field120", + "name": "QUICK_SET_GPIO_0", + "description": "quick set gpio 0", + "offset_int": "0x0120", + "default_value_int": "0" + }, + { + "id": "field124", + "name": "QUICK_CLR_GPIO_0", + "description": "quick clr gpio 0", + "offset_int": "0x0124", + "default_value_int": "0" + }, + { + "id": "field128", + "name": "QUICK_SET_GPIO_1", + "description": "QUICK SET GPIO 1", + "offset_int": "0x0128", + "default_value_int": "0" + }, + { + "id": "field12C", + "name": "QUICK_CLR_GPIO_1", + "description": "QUICK CLR GPIO 1", + "offset_int": "0x012C", + "default_value_int": "0" + }, + { + "id": "field130", + "name": "QUICK_SET_GPIO_2", + "description": "quick set gpio 2", + "offset_int": "0x0130", + "default_value_int": "0" + }, + { + "id": "field134", + "name": "QUICK_CLR_GPIO_2", + "description": "quick clr gpio 2", + "offset_int": "0x0134", + "default_value_int": "0" + }, + { + "id": "field138", + "name": "QUICK_SET_GPIO_3", + "description": "quick set gpio 3", + "offset_int": "0x0138", + "default_value_int": "0" + }, + { + "id": "field13C", + "name": "QUICK_CLR_GPIO_3", + "description": "quick clr gpio 3", + "offset_int": "0x013C", + "default_value_int": "0" + }, + { + "id": "field140", + "name": "QUICK_SET_GPIO_4", + "description": "quick set gpio 4", + "offset_int": "0x0140", + "default_value_int": "0" + }, + { + "id": "field144", + "name": "QUICK_CLR_GPIO_4", + "description": "quick clr gpio 4", + "offset_int": "0x0144", + "default_value_int": "0" + }, + { + "id": "field148", + "name": "QUICK_SET_GPIO_5", + "description": "quick set gpio 5", + "offset_int": "0x0148", + "default_value_int": "0" + }, + { + "id": "field14C", + "name": "QUICK_CLR_GPIO_5", + "description": "quick clr gpio 5", + "offset_int": "0x014C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Challenge", + "description": "Challenge" + }, + "registers": [ + { + "id": "field150", + "name": "CHALLENGE_0", + "description": "challenge 0", + "offset_int": "0x0150", + "default_value_int": "0" + }, + { + "id": "field154", + "name": "CHALLENGE_1", + "description": "CHALLENGE 1", + "offset_int": "0x0154", + "default_value_int": "0" + }, + { + "id": "field158", + "name": "CHALLENGE_2", + "description": "challenge 2", + "offset_int": "0x0158", + "default_value_int": "0" + }, + { + "id": "field15C", + "name": "CHALLENGE_3", + "description": "challenge 3", + "offset_int": "0x015C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CUST_MK_SK", + "description": "CUST_MK_SK key blob" + }, + "registers": [ + { + "id": "field160", + "name": "CUST_MK_SK0", + "description": "cust mk sk key blob", + "offset_int": "0x0160", + "default_value_int": "0" + }, + { + "id": "field164", + "name": "CUST_MK_SK1", + "description": "cust mk sk key blob", + "offset_int": "0x0164", + "default_value_int": "0" + }, + { + "id": "field168", + "name": "CUST_MK_SK2", + "description": "cust mk sk key blob", + "offset_int": "0x0168", + "default_value_int": "0" + }, + { + "id": "field16C", + "name": "CUST_MK_SK3", + "description": "cust mk sk key blob", + "offset_int": "0x016C", + "default_value_int": "0" + }, + { + "id": "field170", + "name": "CUST_MK_SK4", + "description": "cust mk sk key blob", + "offset_int": "0x0170", + "default_value_int": "0" + }, + { + "id": "field174", + "name": "CUST_MK_SK5", + "description": "cust mk sk key blob", + "offset_int": "0x0174", + "default_value_int": "0" + }, + { + "id": "field178", + "name": "CUST_MK_SK6", + "description": "cust mk sk key blob", + "offset_int": "0x0178", + "default_value_int": "0" + }, + { + "id": "field17C", + "name": "CUST_MK_SK7", + "description": "cust mk sk key blob", + "offset_int": "0x017C", + "default_value_int": "0" + }, + { + "id": "field180", + "name": "CUST_MK_SK8", + "description": "cust mk sk key blob", + "offset_int": "0x0180", + "default_value_int": "0" + }, + { + "id": "field184", + "name": "CUST_MK_SK9", + "description": "cust mk sk key blob", + "offset_int": "0x0184", + "default_value_int": "0" + }, + { + "id": "field188", + "name": "CUST_MK_SK10", + "description": "cust mk sk key blob", + "offset_int": "0x0188", + "default_value_int": "0" + }, + { + "id": "field18C", + "name": "CUST_MK_SK11", + "description": "cust mk sk key blob", + "offset_int": "0x018C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "PQC RoTKH", + "description": "PQC Root of Trust Keys Table hash" + }, + "registers": [ + { + "id": "field190", + "name": "PQC_ROTKH0", + "description": "pqc rotkh[383:352]", + "offset_int": "0x0190", + "default_value_int": "0" + }, + { + "id": "field194", + "name": "PQC_ROTKH1", + "description": "pqc rotkh[351:320]", + "offset_int": "0x0194", + "default_value_int": "0" + }, + { + "id": "field198", + "name": "PQC_ROTKH2", + "description": "pqc rotkh[319:288]", + "offset_int": "0x0198", + "default_value_int": "0" + }, + { + "id": "field19C", + "name": "PQC_ROTKH3", + "description": "pqc rotkh[287:256]", + "offset_int": "0x019C", + "default_value_int": "0" + }, + { + "id": "field1A0", + "name": "PQC_ROTKH4", + "description": "pqc rotkh[255:224]", + "offset_int": "0x01A0", + "default_value_int": "0" + }, + { + "id": "field1A4", + "name": "PQC_ROTKH5", + "description": "pqc rotkh[223:192]", + "offset_int": "0x01A4", + "default_value_int": "0" + }, + { + "id": "field1A8", + "name": "PQC_ROTKH6", + "description": "pqc rotkh[191:160]", + "offset_int": "0x01A8", + "default_value_int": "0" + }, + { + "id": "field1AC", + "name": "PQC_ROTKH7", + "description": "pqc rotkh[159:128]", + "offset_int": "0x01AC", + "default_value_int": "0" + }, + { + "id": "field1B0", + "name": "PQC_ROTKH8", + "description": "pqc rotkh[127:96]", + "offset_int": "0x01B0", + "default_value_int": "0" + }, + { + "id": "field1B4", + "name": "PQC_ROTKH9", + "description": "pqc rotkh[95:64]", + "offset_int": "0x01B4", + "default_value_int": "0" + }, + { + "id": "field1B8", + "name": "PQC_ROTKH10", + "description": "pqc rotkh[63:32]", + "offset_int": "0x01B8", + "default_value_int": "0" + }, + { + "id": "field1BC", + "name": "PQC_ROTKH11", + "description": "pqc rotkh[31:0]", + "offset_int": "0x01BC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 001C0-0001E8", + "description": "Reserved 001C0-0001E8" + }, + "registers": [ + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CMPA CRC32", + "description": "CMPA CRC32" + }, + "registers": [ + { + "id": "field1EC", + "name": "CMPA_CRC32", + "description": "cmpa crc32", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CMPA CMAC", + "description": "CMPA CMAC" + }, + "registers": [ + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "cmpa cmac", + "offset_int": "0x01F0", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMPA CMAC1", + "offset_int": "0x01F4", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMPA CMAC2", + "offset_int": "0x01F8", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMPA CMAC3", + "offset_int": "0x01FC", + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn557s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn557s/database.yaml new file mode 100644 index 0000000..8e05918 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn557s/database.yaml @@ -0,0 +1,13 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn556s + +# General MCU information +info: + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x200000" + external: false \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/database.yaml new file mode 100644 index 0000000..1a1a9fe --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/database.yaml @@ -0,0 +1,487 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: + features: + dat: + socc: 6 + pfr: + cfpa: + reg_spec: pfr_cfpa_a0.json + cmpa: + reg_spec: pfr_cmpa_a0.json + tz: + reg_spec: tz_a0.json + a1: + features: + pfr: + cfpa: + reg_spec: pfr_cfpa_a1.json + cmpa: + reg_spec: pfr_cmpa_a1.json + tz: + reg_spec: tz_a1.json + dice: + reg_spec: dice_had_a1.json +latest: a1 + +# General MCU information +info: + use_in_doc: True + purpose: MCX Series + spsdk_predecessor_name: mcxn9xx + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series/mcx-n94x-and-n54x-mcus-with-dual-core-arm-cortex-m33-edgelock-secure-subsystem-and-neural-processing-unit:MCX-N94X-N54X + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x100000" + external: false + flexspi_ns: + start_int: "0x80000000" + size_int: "0x8000000" + external: true + flexspi_s: + start_int: "0x90000000" + size_int: "0x8000000" + external: true + mirror_of: flexspi_ns + internal-flash_s: + start_int: "0x10000000" + size_int: "0x100000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x40000" + external: false + non_xip_type: int_ram + sramx: + start_int: "0x4000000" + size_int: "0x18000" + external: false + __comment: Does not work as target `onchip RAM` memory + ifr-bank1_ns: + start_int: "0x1008000" + size_int: "0x8000" + external: false + ifr-bank1_s: + start_int: "0x11008000" + size_int: "0x8000" + external: false + isp: + rom: + protocol: mboot + interfaces: ["usb", "uart", "spi", "i2c", "can"] + usb: + - vid: 0x1FC9 + pid: 0x014F + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x20007000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== DAT section ======== + dat: + socc: 7 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestCrc + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0x100_0000 + size: 512 + seal_start: field1EC # CFPA_CRC32 + seal_count: 1 + grouped_registers: + - uid: cfpa_dice_cert + name: DICE_Certificate + width: 1152 + config_as_hexstring: true + description: + DICE Certificate field is compounded by 36 32-bit fields and contains + value of DICE Certificate generated by ROM + sub_regs: + - field100 + - field104 + - field108 + - field10C + - field110 + - field114 + - field118 + - field11C + - field120 + - field124 + - field128 + - field12C + - field130 + - field134 + - field138 + - field13C + - field140 + - field144 + - field148 + - field14C + - field150 + - field154 + - field158 + - field15C + - field160 + - field164 + - field168 + - field16C + - field170 + - field174 + - field178 + - field17C + - Reserved00180 + - Reserved00184 + - Reserved00188 + - Reserved0018C + computed_fields: + field000: # HEADER + field000-bits8-15: pfr_reg_inverse_lower_8_bits # INV_CFPA_LC_STATE + field020: # DBG_REVOKE_VU + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_PIN + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field028: # DCFG_CC_SOCU_NS_DFLT + field028-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x0100_4000 + size: 512 + seal_start: field1F0 # CMPA_CMAC0 + seal_count: 4 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 384 + reversed: true + config_as_hexstring: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key table hash. + Root of Trust Key Hash is SHA256 or SHA384 of RoTK public. Hash algorithm is selected + based on RoTK EC type (secp256r1 -> SHA256 or secp384r1 -> SHA384). + Same RoTKs and RoTKTH values are shared between debug authentication, SB3.1 firmware updates + container and signed boot image based on CMPA.RoTKx_Usage. + sub_regs: + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + - field080 + - field084 + - field088 + - field08C + - uid: cmpa_keyblob + name: CUST_MK_SK_KEY_BLOB + width: 384 + reversed: false + config_as_hexstring: true + description: CUST_MK_SK key blob. + CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. + CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. + To store this key into CMPA, SB_STORE_KEY command should be used. + sub_regs: + - field160 + - field164 + - field168 + - field16C + - field170 + - field174 + - field178 + - field17C + - field180 + - field184 + - field188 + - field18C + computed_fields: + field040: # DCFG_CC_SOCU_PIN + field040-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field044: # DCFG_CC_SOCU_DFLT + field044-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + reg_spec_modification: + field0B0: + bitfields: + field0B0-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0B4: + bitfields: + field0B4-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0B8: + bitfields: + field0B8-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0BC: + bitfields: + field0BC-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0C0: + bitfields: + field0C0-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0C4: + bitfields: + field0C4-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0C8: + bitfields: + field0C8-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0CC: + bitfields: + field0CC-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0D0: + bitfields: + field0D0-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0D4: + bitfields: + field0D4-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0D8: + bitfields: + field0D8-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0DC: + bitfields: + field0DC-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0E0: + bitfields: + field0E0-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0E4: + bitfields: + field0E4-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0E8: + bitfields: + field0E8-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + field0EC: + bitfields: + field0EC-bits8-31: + config_processor: + SHIFT_RIGHT:COUNT=8;DESC=ROM only uses upper 24bits to address + IPED region. In config file use full 32b address. + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== Bootable image section ======== + bootable_image: + mem_types: + flexspi_nor: + image_pattern: ones + segments: + fcb: 0x0400 + image_version_ap: 0x0600 + mbi: 0x1000 + recovery_spi_sb31: + segments: + sb31: 0x00 + recovery_spi_mbi: + segments: + mbi: 0x00 + internal: + segments: + mbi: 0x00 + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + key_wraps_version: 2 + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB31] + key_blob_offset: 0x0 + key_blob_command_position: -1 + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - loadCMAC + - copy + - loadHashLocking + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + recommended_flow: + - programLifeCycleFuse: + address: 1 + value: 0x03000003 + - loadCMPA: + address: 0x0100_4000 + - loadCFPA: + address: 0x100_0000 + - loadKeyBlob: + offset: 0x0 + + # ======== TrustZone section ======== + tz: {} + + # ======== DICE configuration ======== + dice: + buffer_address: 0x2002_0050 + buffer_size: 0x1000 + csr_address: 0x0100_0100 + csr_length: 208 + response_length: 324 + rkth_length: 32 + rkth_truncated_length: 32 + need_reset: true + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: MCXN + prov_method: dispatch_fw + dispatch_method: sb_only + use_additional_data: true + fw_read_address: 0x2000_0100 + ignored_otp_ranges: [11, 22] + clean_method: erase_cmpa + validation_method: max_count=16;max_total_size=16384 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + spi_nor: + instances: [0] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/dice_had_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/dice_had_a1.json new file mode 100644 index 0000000..b18114b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/dice_had_a1.json @@ -0,0 +1,1068 @@ +{ + "cpu": "MCXN946", + "groups": [ + { + "group": { + "name": "DICE HAD registers", + "description": "Registers used by DICE attestation." + }, + "registers": [ + { + "id": "field9D0", + "offset_int": "0x000", + "reg_width": 32, + "name": "ELS_AS_CFG0", + "description": "ELS AS Configuration", + "default_value_int": "0xc0255", + "bitfields": [ + { + "id": "field9D0-bits0-7", + "width": 8, + "name": "CFG_LC_STATE", + "access": "RO", + "description": "LC state configuration bit" + }, + { + "width": 1 + }, + { + "id": "field9D0-bit9", + "width": 1, + "name": "CFG_LVD_CORE_RESET_ENABLED", + "access": "RO", + "description": "When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1." + }, + { + "width": 1 + }, + { + "id": "field9D0-bit11", + "width": 1, + "name": "CFG_LVD_CORE_IRQ_ENABLED", + "access": "RO", + "description": "When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit12", + "width": 1, + "name": "CFG_WDT0_ENABLED", + "access": "RO", + "description": "When WatchDog Timer 0 is activated, this bit indicates state 1" + }, + { + "id": "field9D0-bit13", + "width": 1, + "name": "CFG_CWDT0_ENABLED", + "access": "RO", + "description": "When Code WatchDog Timer 0 is activated, this bit indicates state 1" + }, + { + "id": "field9D0-bit14", + "width": 1, + "name": "CFG_ELS_GDET_ENABLED", + "access": "RO", + "description": "When either GDET is enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit15", + "width": 1, + "name": "CFG_ANA_GDET_RESET_ENABLED", + "access": "RO", + "description": "When SPC analog glitch detect reset is enabled, this bit indicates state 1" + }, + { + "id": "field9D0-bit16", + "width": 1, + "name": "CFG_ANA_GDET_IRQ_ENABLED", + "access": "RO", + "description": "When SPC analog glitch detect IRQ is enabled, this bit indicates state 1" + }, + { + "id": "field9D0-bit17", + "width": 1, + "name": "CFG_TAMPER_DET_ENABLED", + "access": "RO", + "description": "When tamper detector is enabled in TDET, this bit indicates state 1." + }, + { + "id": "field9D0-bit18", + "width": 1, + "name": "CFG_LVD_VSYS_RESET_ENABLED", + "access": "RO", + "description": "When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit19", + "width": 1, + "name": "CFG_LVD_VDDIO_RESET_ENABLED", + "access": "RO", + "description": "When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit20", + "width": 1, + "name": "CFG_LVD_VSYS_IRQ_ENABLED", + "access": "RO", + "description": "When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit21", + "width": 1, + "name": "CFG_LVD_VDDIO_IRQ_ENABLED", + "access": "RO", + "description": "When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1." + }, + { + "id": "field9D0-bit22", + "width": 1, + "name": "CFG_WDT1_ENABLED", + "access": "RO", + "description": "When WatchDog Timer 1 is activated, this bit indicates state 1." + }, + { + "id": "field9D0-bit23", + "width": 1, + "name": "CFG_CWDT1_ENABLED", + "access": "RO", + "description": "When Code WatchDog Timer 1 is activated, this bit indicates state 1." + }, + { + "id": "field9D0-bit24", + "width": 1, + "name": "CFG_TEMPTAMPER_DET_ENABLED", + "access": "RO", + "description": "When temperature tamper detector is enabled in VBAT, this bit indicates state 1." + }, + { + "id": "field9D0-bit25", + "width": 1, + "name": "CFG_VOLTAMPER_DET_ENABLED", + "access": "RO", + "description": "When voltage tamper detector is enabled in VBAT, this bit indicates state 1." + }, + { + "id": "field9D0-bit26", + "width": 1, + "name": "CFG_LHTTAMPER_DET_ENABLED", + "access": "RO", + "description": "When light tamper detector is enabled in VBAT, this bit indicates state 1." + }, + { + "id": "field9D0-bit27", + "width": 1, + "name": "CFG_CLKTAMPER_DET_ENABLED", + "access": "RO", + "description": "When clk tamper detector is enabled in VBAT, this bit indicates state 1." + }, + { + "id": "field9D0-bit28", + "width": 1, + "name": "CFG_QK_DISABLE_ENROLL", + "access": "RO", + "description": "When QK PUF \"qk_disable_enroll\" input is driven 1, this bit indicates state 1" + }, + { + "id": "field9D0-bit29", + "width": 1, + "name": "CFG_QK_DISABLE_WRAP", + "access": "RO", + "description": "When QK PUF \"qk_disable_wrap\" input is driven 1, this bit indicates state 1" + }, + { + "width": 2 + } + ] + }, + { + "id": "field9D4", + "offset_int": "0x004", + "reg_width": 32, + "name": "ELS_AS_CFG1", + "description": "ELS AS Configuration1", + "default_value_int": "0x140002", + "bitfields": [ + { + "width": 1 + }, + { + "id": "field9D4-bit1", + "width": 1, + "name": "CFG_SEC_DIS_STRICT_MODE", + "access": "RO", + "description": "When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1" + }, + { + "id": "field9D4-bit2", + "width": 1, + "name": "CFG_SEC_DIS_VIOL_ABORT", + "access": "RO", + "description": "When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit3", + "width": 1, + "name": "CFG_SEC_ENA_NS_PRIV_CHK", + "access": "RO", + "description": "When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit4", + "width": 1, + "name": "CFG_SEC_ENA_S_PRIV_CHK", + "access": "RO", + "description": "When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit5", + "width": 1, + "name": "CFG_SEC_ENA_SEC_CHK", + "access": "RO", + "description": "When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit6", + "width": 1, + "name": "CFG_SEC_IDAU_ALLNS", + "access": "RO", + "description": "When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this bit indicates state 1" + }, + { + "width": 1 + }, + { + "id": "field9D4-bit8", + "width": 1, + "name": "CFG_SEC_LOCK_NS_MPU", + "access": "RO", + "description": "When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit9", + "width": 1, + "name": "CFG_SEC_LOCK_NS_VTOR", + "access": "RO", + "description": "When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit10", + "width": 1, + "name": "CFG_SEC_LOCK_S_MPU", + "access": "RO", + "description": "When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit11", + "width": 1, + "name": "CFG_SEC_LOCK_S_VTAIRCR", + "access": "RO", + "description": "When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bit12", + "width": 1, + "name": "CFG_SEC_LOCK_SAU", + "access": "RO", + "description": "When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1" + }, + { + "id": "field9D4-bits13-20", + "width": 8, + "name": "METAL_VERSION", + "access": "RO", + "description": "metal version" + }, + { + "id": "field9D4-bits21-24", + "width": 4, + "name": "ROM_PATCH_VERSION", + "access": "RO", + "description": "ROM patch version" + }, + { + "width": 1 + }, + { + "id": "field9D4-bit26", + "width": 1, + "name": "CFG_HVD_CORE_RESET_ENABLED", + "access": "RO", + "description": "When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1." + }, + { + "id": "field9D4-bit27", + "width": 1, + "name": "CFG_HVD_CORE_IRQ_ENABLED", + "access": "RO", + "description": "When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1." + }, + { + "id": "field9D4-bit28", + "width": 1, + "name": "CFG_HVD_VSYS_RESET_ENABLED", + "access": "RO", + "description": "When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1." + }, + { + "id": "field9D4-bit29", + "width": 1, + "name": "CFG_HVD_VDDIO_RESET_ENABLED", + "access": "RO", + "description": "When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1." + }, + { + "id": "field9D4-bit30", + "width": 1, + "name": "CFG_HVD_VSYS_IRQ_ENABLED", + "access": "RO", + "description": "When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1." + }, + { + "id": "field9D4-bit31", + "width": 1, + "name": "CFG_HVD_VDDIO_IRQ_ENABLED", + "access": "RO", + "description": "When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1." + } + ] + }, + { + "id": "field9D8", + "offset_int": "0x008", + "reg_width": 32, + "name": "ELS_AS_CFG2", + "description": "ELS configuration command enable bit", + "default_value_int": "0xffffffff" + }, + { + "id": "field9E0", + "offset_int": "0x010", + "reg_width": 32, + "name": "ELS_AS_ST0", + "description": "ELS AS State Register", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field9E0-bits0-3", + "width": 4, + "name": "ST_TEMPORAL_STATE", + "access": "RO", + "description": "TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register" + }, + { + "id": "field9E0-bit4", + "width": 1, + "name": "ST_CPU0_DBGEN", + "access": "RO", + "description": "When CPU0 (CM33) \"dbgen\" input is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit5", + "width": 1, + "name": "ST_CPU0_NIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"niden\" input is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit6", + "width": 1, + "name": "ST_CPU0_SPIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"spiden\" input is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit7", + "width": 1, + "name": "ST_CPU0_SPNIDEN", + "access": "RO", + "description": "When CPU0 (CM33) \"spniden\" input is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit8", + "width": 1, + "name": "ST_CPU1_DBGEN", + "access": "RO", + "description": "When CPU1 (CM33) \"dbgen\" input is state 1, this bit indicates state 1." + }, + { + "id": "field9E0-bit9", + "width": 1, + "name": "ST_CPU1_NIDEN", + "access": "RO", + "description": "When CPU1 (CM33) \"niden\" input is state 1, this bit indicates state 1." + }, + { + "id": "field9E0-bit10", + "width": 1, + "name": "ST_DAP_ENABLE_CPU0", + "access": "RO", + "description": "When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1" + }, + { + "id": "field9E0-bit11", + "width": 1, + "name": "ST_DAP_ENABLE_CPU1", + "access": "RO", + "description": "When DAP to AP1 for CPU1 (CM33) debug access is allowed, this bit indicates state 1." + }, + { + "id": "field9E0-bit12", + "width": 1, + "name": "ST_DAP_ENABLE_DSP", + "access": "RO", + "description": "When DAP to AP3 for DSP (CoolFlux) debug access is allowed, this bit indicates state 1" + }, + { + "width": 1 + }, + { + "id": "field9E0-bit14", + "width": 1, + "name": "ST_ALLOW_TEST_ACCESS", + "access": "RO", + "description": "When JTAG TAP access is allowed, this bit indicates state 1." + }, + { + "id": "field9E0-bit15", + "width": 1, + "name": "ST_XO32K_FAILED", + "access": "RO", + "description": "When XO32K oscillation fail flag is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit16", + "width": 1, + "name": "ST_XO40M_FAILED", + "access": "RO", + "description": "When XO40M oscillation fail flag is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bit17", + "width": 1, + "name": "ST_IFR_LOAD_FAILED", + "access": "RO", + "description": "When IFR load fail flag is state 1, this bit indicates state 1" + }, + { + "id": "field9E0-bits18-21", + "width": 4, + "name": "ST_GLITCH_DETECT_FLAG", + "access": "RO", + "description": "GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output." + }, + { + "width": 10 + } + ] + }, + { + "id": "field9E4", + "offset_int": "0x014", + "reg_width": 32, + "name": "ELS_AS_ST1", + "description": "ELS AS State1", + "default_value_int": "0x5024f", + "bitfields": [ + { + "id": "field9E4-bits0-3", + "width": 4, + "name": "ST_QK_PUF_SCORE", + "access": "RO", + "description": "These register bits indicate the state of \"qk_puf_score[3:0]\" outputs from QK PUF block" + }, + { + "id": "field9E4-bit4", + "width": 1, + "name": "ST_QK_ZEROIZED", + "access": "RO", + "description": "This register bit indicates the state of \"qk_zeroized\" output from QK PUF block" + }, + { + "id": "field9E4-bit5", + "width": 1, + "name": "ST_MAIN_CLK_IS_EXT", + "access": "RO", + "description": "When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1" + }, + { + "id": "field9E4-bits6-7", + "width": 2, + "name": "ST_DCDC_VOUT", + "access": "RO", + "description": "VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V" + }, + { + "id": "field9E4-bits8-9", + "width": 2, + "name": "ST_DCDC_DS", + "access": "RO", + "description": "DCDC drive strength setting. Default is normal drive." + }, + { + "id": "field9E4-bits10-11", + "width": 2, + "name": "ST_BOOT_MODE", + "access": "RO", + "description": "ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP mode during boot, ISP pin should be pull down when out of reset." + }, + { + "id": "field9E4-bits12-15", + "width": 4, + "name": "ST_BOOT_RETRY_CNT", + "access": "RO", + "description": "BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register" + }, + { + "id": "field9E4-bits16-17", + "width": 2, + "name": "ST_LDO_CORE_VOUT", + "access": "RO", + "description": "VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V" + }, + { + "id": "field9E4-bits18-19", + "width": 2, + "name": "ST_LDO_CORE_DS", + "access": "RO", + "description": "LDO_CORE drive strength setting. Default is normal drive." + }, + { + "width": 12 + } + ] + }, + { + "id": "field9F8", + "offset_int": "0x028", + "reg_width": 32, + "name": "ELS_AS_FLAG0", + "description": "ELS AS Flag0", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field9F8-bit0", + "width": 1, + "name": "FLAG_AP_ENABLE_CPU0", + "access": "RO", + "description": "This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug access. The register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit1", + "width": 1, + "name": "FLAG_AP_ENABLE_CPU1", + "access": "RO", + "description": "This flag bit is set as 1 when DAP enables AP1 for CPU1 (CM33) debug access. The register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit2", + "width": 1, + "name": "FLAG_AP_ENABLE_DSP", + "access": "RO", + "description": "This flag bit is set as 1 when DAP enables AP3 for DSP (CoolFlux) debug access. The register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit3", + "width": 1, + "name": "EFUSE_ATTACK_DETECT", + "access": "RO", + "description": "OTPC can output attack_detect signal when it detects attack when load shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status can be recorded.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "width": 1 + }, + { + "id": "field9F8-bit5", + "width": 1, + "name": "FLAG_LVD_CORE_OCCURRED", + "access": "RO", + "description": "This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "width": 2 + }, + { + "id": "field9F8-bit8", + "width": 1, + "name": "FLAG_WDT0_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit9", + "width": 1, + "name": "FLAG_CWDT0_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit10", + "width": 1, + "name": "FLAG_WDT0_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit11", + "width": 1, + "name": "FLAG_CWDT0_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit12", + "width": 1, + "name": "FLAG_QK_ERROR", + "access": "RO", + "description": "This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit13", + "width": 1, + "name": "FLAG_ELS_GLITCH_DETECTED", + "access": "RO", + "description": "This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit14", + "width": 1, + "name": "FLAG_ANA_GLITCH_DETECTED", + "access": "RO", + "description": "This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON block. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit15", + "width": 1, + "name": "FLAG_TAMPER_EVENT_DETECTED", + "access": "RO", + "description": "This flag bit is set as 1 when tamper event is flagged from TDET. This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is cleared by software.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit16", + "width": 1, + "name": "FLAG_FLASH_ECC_INVALID", + "access": "RO", + "description": "This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit17", + "width": 1, + "name": "FLAG_SEC_VIOL_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit18", + "width": 1, + "name": "FLAG_CPU0_NS_C_ACC_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when CPU0 (CM33) makes non-secure code transactions. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit19", + "width": 1, + "name": "FLAG_CPU0_NS_D_ACC_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when CPU0 (CM33) makes non-secure data transactions. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit20", + "width": 1, + "name": "FLAG_LVD_VSYS_OCCURRED", + "access": "RO", + "description": "This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit21", + "width": 1, + "name": "FLAG_LVD_VDDIO_OCCURRED", + "access": "RO", + "description": "This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit22", + "width": 1, + "name": "FLAG_WDT1_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit23", + "width": 1, + "name": "FLAG_CWDT1_RESET_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled and reset event is triggered. This register is cleared 0 by AO domain POR.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit24", + "width": 1, + "name": "FLAG_WDT1_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit25", + "width": 1, + "name": "FLAG_CWDT1_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit26", + "width": 1, + "name": "FLAG_TEMPTAMPER_DET_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when temperature temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit27", + "width": 1, + "name": "FLAG_VOLTAMPER_DET_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when voltage temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit28", + "width": 1, + "name": "FLAG_LHTTAMPER_DET_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when light temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "id": "field9F8-bit29", + "width": 1, + "name": "FLAG_CLKTAMPER_DET_IRQ_OCCURRED", + "access": "RO", + "description": "This flag bit is set as 1 when clock temper IRQ is enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Not Triggered" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Triggered" + } + ] + }, + { + "width": 2 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fcb_flexspi_nor.json new file mode 100644 index 0000000..3e03f7a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fcb_flexspi_nor.json @@ -0,0 +1,25587 @@ +{ + "cpu": "MCXN946", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details ", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same ", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3 ", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false ", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution ", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size ", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Reserved2_0", + "deprecated_names": ["reserve2_0"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Reserved2_1", + "deprecated_names": ["reserve2_1"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Reserved2_2", + "deprecated_names": ["reserve2_2"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Reserved2_3", + "deprecated_names": ["reserve2_3"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Reserved2_4", + "deprecated_names": ["reserve2_4"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Reserved2_5", + "deprecated_names": ["reserve2_5"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Reserved2_6", + "deprecated_names": ["reserve2_6"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Reserved2_7", + "deprecated_names": ["reserve2_7"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Reserved2_8", + "deprecated_names": ["reserve2_8"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "Reserved2_9", + "deprecated_names": ["reserve2_9"], + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fuses.json new file mode 100644 index 0000000..582277e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/fuses.json @@ -0,0 +1,3341 @@ +{ + "cpu": "MCXN946", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Boot configuration locks" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Boot Configuration Locks", + "index_int": "0", + "bitfields": [ + { + "width": 9 + }, + { + "width": 3, + "id": "fuse0-bits-9-11", + "name": "BOOT_CFG_LOCK[2:0]", + "description": "Boot config lock\nConfigures the locking of EFUSE bits for fuse #3, #4, #5, #6, #7 and fuses #11 - #22. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "PRINCE_CFG_LOCK[2:0]", + "description": "Prince Config Lock\nConfigures the locking EFUSE bits for fuses #23 - #38. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-18-20", + "name": "CUST_LOCK0[2:0]", + "description": "CUST Lock 0\nConfigures the locking of EFUSE bits for fuses #43, #44, #45 and #46. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-21-23", + "name": "CUST_LOCK1[2:0]", + "description": "CUST Lock 1\nConfigures the locking of EFUSE bits for fuses #47, #48, #49 and #50. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-24-26", + "name": "CUST_LOCK2[2:0]", + "description": "CUST Lock 2\nConfigures the locking of EFUSE bits for fuses #51, #52, #53 and #54. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-27-29", + "name": "CUST_LOCK3[2:0]", + "description": "CUST Lock 3\nConfigures the locking EFUSE bits for fuses #55 - #62. - bit 0: When set, blocks programming. - bit 1: Reserved. - bit 2: When set, blocks reading.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WriteLocked", + "value": 1, + "description": "Locked for programming [WP]" + }, + { + "name": "ReadLocked", + "value": 4, + "description": "Locked for reading [RP]" + }, + { + "name": "ReadWriteLocked", + "value": 5, + "description": "Locked for reading and programming [RP+WP]" + } + ] + }, + { + "width": 2 + } + ] + } + ] + }, + { + "group": { + "name": "Configurations", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse1", + "name": "LIFE_CYCLE", + "description": "Life cycle state, debug setting, and ROTK setting", + "index_int": "0x0001", + "bitfields": [ + { + "width": 8, + "id": "fuse1-bits-0-7", + "name": "LIFECYCLE[7:0]", + "description": "Life cycle state.\nThis field can be used to advance life cycle state. Below are the allowed values for this field. Use of other values may lead to bricked state.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-8", + "name": "NIDEN_dis", + "description": "Disable Non-secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-9", + "name": "DBGEN_dis", + "description": "Disable Non-secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-10", + "name": "SPIDEN_dis", + "description": "Disable Secure invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-11", + "name": "SPNIDEN_dis", + "description": "Disable Secure non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-12", + "name": "CPU1_NIDEN_dis", + "description": "Disable CPU1 non-invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-13", + "name": "CPU1_DBG_dis", + "description": "Disable CPU1 invasive debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-14", + "name": "DSP_DBGEN_dis", + "description": "Disable DSP debug.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-15", + "name": "ISP_CMD_dis", + "description": "Disable Enter ISP Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-16", + "name": "FA_CMD_dis", + "description": "Disable Set FA mode Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-17", + "name": "ME_CMD_dis", + "description": "Disable Mass erase Debug mailbox command.", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Disable", + "value": 1, + "description": "Disabled permanently" + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-18", + "name": "UUID_CHECK_ENF", + "description": "Enforce UUID checking during debug authentication", + "values": [ + { + "name": "Check CMPA", + "value": 0, + "description": "Check CMPA.CC_SOCU_xxx fields." + }, + { + "name": "Enable", + "value": 1, + "description": "Always enabled." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse1-bit-20", + "name": "RoTK0_dis", + "description": "Revoke Root of Trust key 0.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-21", + "name": "RoTK1_dis", + "description": "Revoke Root of Trust key 1.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-22", + "name": "RoTK2_dis", + "description": "Revoke Root of Trust key 2.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse1-bit-23", + "name": "RoTK3_dis", + "description": "Revoke Root of Trust key 3.", + "values": [ + { + "name": "Check CFPA", + "value": 0, + "description": "Check CFPA." + }, + { + "name": "Revoke", + "value": 1, + "description": "Key is revoked." + } + ] + }, + { + "width": 8, + "id": "fuse1-bits-24-31", + "name": "LIFECYCLE_DP[7:0]", + "description": "Duplicate of the LIFECYCLE fuse value.", + "values": [ + { + "name": "BLANK", + "value": 0, + "description": "Blank" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return OEM state" + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "Failure Analysis state" + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state" + } + ] + } + ] + }, + { + "id": "fuse2", + "name": "KEY_REVOKE", + "description": "Image key revoke and PRINCE, PUF, and NXP provisioning firmware setting", + "index_int": "0x0002", + "bitfields": [ + { + "width": 8, + "id": "fuse2-bits-0-7", + "name": "DBG_KEY_REVOKE[7:0]", + "description": "Debug key revoke.\nThis field is combined with\nCFPA.DBG_REVOKE_VU and CMPA.VENDOR_USAGE fields to form a 32-bit value which is compared with vendor usage field in debug credential certificate. Only if the values match debug access is granted.\nCC_VENDOR_USAGE = { CMPA.VENDOR_USAGE[31:16],\nCFPA.DBG_REVOKE_VU[15:8],\n(CFPA.DBG_REVOKE_VU[7:0] | OTP.DBG_KEY_REVOKE[7:0]) }" + }, + { + "width": 8, + "id": "fuse2-bits-8-15", + "name": "IMAGE_KEY_REVOKE[7:0]", + "description": "Image signing key revoke.\nThis field is combined with\nCFPA.IMAGE_KEY_REVOKE field to form a 32-bit value which is compared with IskCertificate.constraints field during image authentication. If the values don't match image authentication fails.\nISK_CONSTRAINT[31:0] = {CFPA.IMAGE_KEY_REVOKE_VU[23:0], OTP.IMAGE_KEY_REVOKE[7:0] }" + }, + { + "width": 4 + }, + { + "width": 1, + "id": "fuse2-bit-20", + "name": "PUF_ENROLL_DIS", + "description": "Block PUF enrollment.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow PUF enroll operation" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable PUF enroll operation" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse2-bit-23", + "name": "DIS_NXP_FW", + "description": "Block NXP signed SB3 loading.", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow NXP signed SB3 FW" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable NXP signed SB3 FW" + } + ] + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse3", + "name": "BOOT_CFG", + "description": "ISP pin selection setting and boot configuration setting", + "index_int": "0x0003", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse3-bit-0", + "name": "Boot_FlexSPI_Dis", + "description": "FlexSPI boot disable.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "FlexSPI boot is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "FlexSPI boot is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-1", + "name": "Boot_flash_Dis", + "description": "Disable boot from internal flash.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from internal flash enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from internal flash disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-2", + "name": "Boot_IFR0_Dis", + "description": "Disable boot from IFR0 (as SBL).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Boot from IFR0 enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "Boot from IFR0 disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse3-bit-5", + "name": "Rec_Boot_SPI_Dis", + "description": "Disable recovery boot from external 1-bit SPI flash connected to FlexComm ports.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-6", + "name": "Rec_Boot_IFR0_Dis", + "description": "Disable recovery boot from IFR0 area( 0x0100_8000 to 0x0100_FFFF).", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-7", + "name": "PinSel_SPI_Rec_Boot_Dis", + "description": "Disable logic related to forcing recovery boot based on ISP pin state.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-8", + "name": "ISP_UART_Dis", + "description": "Disable UART interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "UART ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "UART ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-9", + "name": "ISP_I2C_Dis", + "description": "Disable I2C interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "I2C ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "I2C ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-10", + "name": "ISP_SPI_Dis", + "description": "Disable SPI interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SPI ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "SPI ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-11", + "name": "ISP_USB0_Dis", + "description": "Disable USB0 interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "USB0 ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "USB0 ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-12", + "name": "ISP_USB1_Dis", + "description": "Disable USB0 interface in ISP mode", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "USB0 ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "USB0 ISP is disabled." + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-13", + "name": "ISP_CAN_Dis", + "description": "Disable CAN interface in ISP mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "CAN ISP is enabled." + }, + { + "name": "Disable", + "value": 1, + "description": "CAN ISP is disabled." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse3-bits-16-17", + "name": "ISP_DISABLE[1:0]", + "description": "Disable ISP mode entry points.\nISP mode can be entered through pin assertion, debug mailbox command, image verification failure and ROM API invocation", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "All entry point allowed." + }, + { + "name": "Disable_ISP_pin", + "value": 1, + "description": "Entry by ISP Pin assertion disabled." + }, + { + "name": "Disable", + "value": 2, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + }, + { + "name": "Disable_0", + "value": 3, + "description": "Entry by ISP Pin assertion and debug mailbox command disabled." + } + ] + }, + { + "width": 4 + }, + { + "width": 2, + "id": "fuse3-bits-22-23", + "name": "BOOT_SPEED[1:0]", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution.", + "values": [ + { + "name": "CMPA_BOOT_SPEED", + "value": 0, + "description": "Use value from CMPA.BOOT_SPEED" + }, + { + "name": "72MHz FRO", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "144MHz FRO", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "150MHz PLL", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 5, + "id": "fuse3-bits-24-28", + "name": "FLASH_REMAP_SZ[4:0]", + "description": "Flash remap size.\nFLASH_REMAP_SZ defines the size of the secondary boot image\n(the range of flash addresses that will be remapped)in internal flash, where remapped\naddress end = (FLASH_REMAP_SZ + 1) * 32 KB. For example, if FLASH_REMAP_SZ = 2,\nthen the first 96KB of addresses will be remapped to flash bank1 instead of flash bank0\nwhen remap is active. Set this field to 0 if you do not want to use the flash remap feature" + }, + { + "width": 3, + "id": "fuse3-bits-29-31", + "name": "OEM_BANK1_IFR0_USAGE[2:0]", + "description": "Defines flash protection of Bank1_IFR0 area based on usage.\nNote, if the SBL / Recovery image size is more than IFR0 size of 32KB then sectors from user flash can be associated for extended image size using CMPA.REC_IMG_EXT0/1.", + "values": [ + { + "name": "000", + "value": 0, + "description": "Not determined by ROM (MBC fields are modified by OEM code)" + }, + { + "name": "001", + "value": 1, + "description": "Used as OEM Root of Trust image, in other words secondary boot loader (OEM_SBL). MBC protection bits set as RWXL = 1010. Updatable by OEM code later." + }, + { + "name": "010", + "value": 2, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 1011." + }, + { + "name": "011", + "value": 3, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 0011." + }, + { + "name": "100", + "value": 4, + "description": "Used as OEM recovery boot image with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1010 on ROM exiting to user image." + }, + { + "name": "101", + "value": 5, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1011 on ROM exiting to user image." + }, + { + "name": "110", + "value": 6, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0011 on ROM exiting to user image." + }, + { + "name": "111", + "value": 7, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0001 on ROM exiting to user image." + } + ] + } + ] + }, + { + "id": "fuse4", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "index_int": "0x0004", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse4-bit-0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-1-3", + "name": "FLEXSPI_PROBE_TYPE[2:0]", + "description": "Quad/Octal-SPI flash probe type.\nNote, this field is used when FLEXSPI_AUTO_PROBE_EN is set.", + "values": [ + { + "name": "QuadSPI NOR", + "value": 0, + "description": "QuadSpi NOR" + }, + { + "name": "Macronix Octal", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "Micron Octal", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "Adesto Octal", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-4-6", + "name": "FLEXSPI_FLASH_TYPE[2:0]", + "description": "Define typical Serial NOR Flash types\nThis field is always used irrespective of FLEXSPI_AUTO_PROBE_EN value.", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI_ADDR_3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER_1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER_3V3" + }, + { + "name": "FlexSPI_DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "FlexSPI_DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "fuse4-bits-7-10", + "name": "FLEXSPI_DUMMY_CYCLES[3:0]", + "description": "Quad/Octal-SPI dummy cycles for read command.\nIf a non-zero value is programmed in this field, then the value is used to override the default number of dummy cycles for a fast read command read from the serial flash's SFDP information.\nNote: this field is only used if FLEXSPI_AUTO_PROBE_EN is set." + }, + { + "width": 3, + "id": "fuse4-bits-11-13", + "name": "FLEXSPI_FREQUENCY[2:0]", + "description": "Q/O-SPI flash interface frequency.\nNote, this field is used when FLEXSPI_AUTO_PROBE_EN is set.", + "values": [ + { + "name": "75Mhz", + "value": 0, + "description": "75Mhz" + }, + { + "name": "60Mhz", + "value": 1, + "description": "60Mhz" + }, + { + "name": "50Mhz", + "value": 2, + "description": "50Mhz" + }, + { + "name": "100Mhz", + "value": 3, + "description": "100Mhz" + } + ] + }, + { + "width": 1, + "id": "fuse4-bit-14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use O/QSPI_RESET_PIN to reset the flash device.", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available.)" + }, + { + "name": "EN_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN).)" + } + ] + }, + { + "width": 3, + "id": "fuse4-bits-15-17", + "name": "FLEXSPI_RESET_GPIO_PORT[2:0]", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO port number to use for O/QSPI reset function." + }, + { + "width": 5, + "id": "fuse4-bits-18-22", + "name": "FLEXSPI_RESET_GPIO_PIN[4:0]", + "description": "GPIO pin number to use for O/QSPI reset function." + }, + { + "width": 2, + "id": "fuse4-bits-23-24", + "name": "FLEXSPI_HOLD_TIME[1:0]", + "description": "Delay after reset before accessing Quad/Octal-SPI flash devices.\nNote, for POR in addition to this wait time FLEXSPI_PWR_HOLD_TIME is added.", + "values": [ + { + "name": "500us", + "value": 0, + "description": "Wait for 500 microseconds." + }, + { + "name": "1ms", + "value": 1, + "description": "Wait for 1 millisecond." + }, + { + "name": "3ms", + "value": 2, + "description": "Wait for 3 milliseconds." + }, + { + "name": "10ms", + "value": 3, + "description": "Wait for 10 milliseconds." + } + ] + }, + { + "width": 4, + "id": "fuse4-bits-25-28", + "name": "FLEXSPI_PWR_HOLD_TIME[3:0]", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field.", + "values": [ + { + "name": "No delay", + "value": 0, + "description": "No delay" + }, + { + "name": "100us", + "value": 1, + "description": "Waits additional 100 microseconds." + }, + { + "name": "500us", + "value": 2, + "description": "Waits additional 500 microseconds." + }, + { + "name": "1ms", + "value": 3, + "description": "Waits additional 1 millisecond." + }, + { + "name": "10ms", + "value": 4, + "description": "Waits additional 10 milliseconds." + }, + { + "name": "20ms", + "value": 5, + "description": "Waits additional 20 milliseconds." + }, + { + "name": "40ms", + "value": 6, + "description": "Waits additional 40 milliseconds." + }, + { + "name": "60ms", + "value": 7, + "description": "Waits additional 60 milliseconds." + }, + { + "name": "80ms", + "value": 8, + "description": "Waits additional 80 milliseconds." + }, + { + "name": "100ms", + "value": 9, + "description": "Waits additional 100 milliseconds." + }, + { + "name": "120ms", + "value": 10, + "description": "Waits additional 120 milliseconds." + }, + { + "name": "140ms", + "value": 11, + "description": "Waits additional 140 milliseconds." + }, + { + "name": "160ms", + "value": 12, + "description": "Waits additional 160 milliseconds." + }, + { + "name": "180ms", + "value": 13, + "description": "Waits additional 180 milliseconds." + }, + { + "name": "200ms", + "value": 14, + "description": "Waits additional 200 milliseconds." + }, + { + "name": "220ms", + "value": 15, + "description": "Waits additional 220 milliseconds." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse4-bit-31", + "name": "PORT_SEL", + "description": "Defines which FlexSPI portA/B is used for boot.", + "values": [ + { + "name": "Port A", + "value": 0, + "description": "Port A" + }, + { + "name": "Port B", + "value": 1, + "description": "Port B" + } + ] + } + ] + }, + { + "id": "fuse5", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "index_int": "0x0005", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse5-bits-0-6", + "name": "FLEXSPI_DELAY_CELL_NUM[6:0]", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS).\nThe value provided here is loaded into the FLEXSPIn_DLLnCR." + }, + { + "width": 10, + "id": "fuse5-bits-7-16", + "name": "FLEXSPI_IMAGE_OFFSET[9:0]", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset.\nThis allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset.\nFlLEXSPI_IMAGE_OFFSET field specifies the offset location of the second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.\nIf this field is left blank boot ROM will not enable FlexSPI remap feature.\nThe physical flash offset is computed as below:\nphysical offset = FLEXSPI_IMAGE_OFFSET * 256KByte" + }, + { + "width": 4, + "id": "fuse5-bits-17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE[3:0]", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped\nNOTE: FlexSPI remap size cannot exceed the start address of boot image 1.\nb'0000 Remap size = FLEXSPI_IMAGE_OFFSET * 256KByte\n\" SIZE_OFFSET \"Size of the remapped area (aka second half) is same as first half. It is determined by FLEXSPI_IMAGE_OFFSET Field.\nb'0001 SIZE_1MB Size of remapped area is 1MByte.\nb'0010 SIZE_2MB Size of remapped area is 2MByte.\nb'0011 SIZE_3MB Size of remapped area is 3MByte.\nb'0100 SIZE_4MB Size of remapped area is 4MByte.\nb'0101 SIZE_5MB Size of remapped area is 5MByte.\nb'0110 SIZE_6MB Size of remapped area is 6MByte.\nb'0111 SIZE_7MB Size of remapped area is 7MByte.\nb'1000 SIZE_8MB Size of remapped area is 8MByte.\nb'1001 SIZE_9MB Size of remapped area is 9MByte.\nb'1010 SIZE_10MB Size of remapped area is 10MByte.\nb'1011 SIZE_11MB Size of remapped area is 11MByte.\nb'1100 SIZE_12MB Size of remapped area is 12MByte.\nb'1101 SIZE_256KB Size of remapped area is 256KByte.\nb'1110 SIZE_512KB Size of remapped area is 512KByte.\nb'1111 SIZE_768KB Size of remapped area is 768KByte." + }, + { + "width": 11 + } + ] + }, + { + "id": "fuse6", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration 0", + "index_int": "0x0006", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse6-bits-0-1", + "name": "SEC_BOOT_EN[1:0]", + "description": "Secure boot enforcement.\nThis field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign).\nThe Image type field in header indicates the type of verification data (checksum or signature) included in it.\nPlain < CRC32 < CMAC < ECDSA", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed." + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed." + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse6-bits-3-4", + "name": "LP_SEC_BOOT[1:0]", + "description": "Secure boot option for low-power wake from power-down & deep-powerdown.\nFor CFPA/CMPA do CRC check always.", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA." + }, + { + "name": "CHECK_CMAC", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "fuse6-bits-8-9", + "name": "ENF_CNSA[1:0]", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication.\nNote, CMAC image authentication is only allowed in 2b'00 setting.", + "values": [ + { + "name": "ALL_ALLOWED", + "value": 0, + "description": "All algorithm allowed." + }, + { + "name": "LIMITED", + "value": 1, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_0", + "value": 2, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + }, + { + "name": "LIMITED_1", + "value": 3, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-10-11", + "name": "ENF_TZM_PRESET[1:0]", + "description": "TrustZone-M mode.", + "values": [ + { + "name": "IGNORE", + "value": 0, + "description": "Ignored." + }, + { + "name": "ENFORCE", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_0", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_1", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "ITRC_ZEROIZE[1:0]", + "description": "RAM zeroize on ITRC event.\nZeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion & Tamper control signals an intrusion event (ITRC_OUT3).\nNote, when ITRC is re-configured in application then ITRC_OUT4 (CHIP_RESET) should be triggered with at least same events as ITRC_OUT3 (RAM_ZEROIZE).", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action." + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only." + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only." + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "ACTIVE_IMG_PROT[1:0]", + "description": "Protection of active image.\nThis field defines protection of flash area occupied by the active image. Only applicable to internal flash.", + "values": [ + { + "name": "FLASH_ACL_PROTECTION", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings." + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored." + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored." + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "XOM protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-16-17", + "name": "FIPS_SHA_STEN[1:0]", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-18-19", + "name": "FIPS_AES_STEN[1:0]", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-20-21", + "name": "FIPS_ECDSA_STEN[1:0]", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "FIPS_DRBG_STEN[1:0]", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-24-25", + "name": "FIPS_CMAC_STEN[1:0]", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-26-27", + "name": "FIPS_KDF_STEN[1:0]", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-28-29", + "name": "FIPS_PUF_STEN[1:0]", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS].", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse7", + "name": "RoTK_USAGE", + "description": "Secure Boot Configuration 1", + "index_int": "0x0007", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse7-bits-0-2", + "name": "RoTK0_Usage[2:0]", + "description": "RoT key 0 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-3-5", + "name": "RoTK1_Usage[2:0]", + "description": "RoT key 1 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-6-8", + "name": "RoTK2_Usage[2:0]", + "description": "RoT key 2 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW_IMG", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-9-11", + "name": "RoTK3_Usage[2:0]", + "description": "RoT key 3 usage properties.", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "SKIP_DICE", + "description": "Skip DICE computation.", + "values": [ + { + "name": "Enable DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "Disable DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 9 + }, + { + "width": 2, + "id": "fuse7-bits-24-25", + "name": "NPX_LOCK_CTX0[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 0 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-26-27", + "name": "NPX_LOCK_CTX1[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 1 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-28-29", + "name": "NPX_LOCK_CTX2[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 2 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-30-31", + "name": "NPX_LOCK_CTX3[1:0]", + "description": "Lock on-chip flash NPX PRINCE context 3 settings.\nFlash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked." + }, + { + "name": "LOCKED_NO_ERASE_CHECK", + "value": 1, + "description": "Region is locked. But no erase check." + }, + { + "name": "LOCKED", + "value": 2, + "description": "Region is locked. Erase check enabled." + }, + { + "name": "LOCKED_0", + "value": 3, + "description": "Region is locked. Erase check enabled." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "Root of trust keys configuration" + }, + "registers": [ + { + "id": "fuse11", + "name": "ROTKH0", + "description": "Root of Trust Keys Table Hash 0 (ROTKH[31:0])", + "index_int": "0x000B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse11-bits-0-31", + "name": "ROTKH[31:0]", + "description": "Root of Trust Keys Table Hash 0 (ROTKH[31:0])\nSHA384 ROTKH[383:352] / SHA56 ROTKH[255:224]" + } + ] + }, + { + "id": "fuse12", + "name": "ROTKH1", + "description": "Root of Trust Keys Table Hash 1 (ROTKH[63:32])", + "index_int": "0x000C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse12-bits-0-31", + "name": "ROTKH[63:32]", + "description": "Root of Trust Keys Table Hash 1 (ROTKH[63:32])\nSHA384 ROTKH[351:320] / SHA56 ROTKH[223:192]" + } + ] + }, + { + "id": "fuse13", + "name": "ROTKH2", + "description": "Root of Trust Keys Table Hash 2 (ROTKH[95:64])", + "index_int": "0x000D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse13-bits-0-31", + "name": "ROTKH[95:64]", + "description": "Root of Trust Keys Table Hash 2 (ROTKH[95:64])\nSHA384 ROTKH[319:288] / SHA56 ROTKH[191:160]" + } + ] + }, + { + "id": "fuse14", + "name": "ROTKH3", + "description": "Root of Trust Keys Table Hash 3 (ROTKH[127:96])", + "index_int": "0x000E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse14-bits-0-31", + "name": "ROTKH[127:96]", + "description": "Root of Trust Keys Table Hash 3 (ROTKH[127:96])\nSHA384 ROTKH[287:256] / SHA56 ROTKH[159:128]" + } + ] + }, + { + "id": "fuse15", + "name": "ROTKH4", + "description": "Root of Trust Keys Table Hash 4 (ROTKH[159:128])", + "index_int": "0x000F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse15-bits-0-31", + "name": "ROTKH[159:128]", + "description": "Root of Trust Keys Table Hash 4 (ROTKH[159:128])\nSHA384 ROTKH[255:224] / SHA56 ROTKH[127:96]" + } + ] + }, + { + "id": "fuse16", + "name": "ROTKH5", + "description": "Root of Trust Keys Table Hash 5 (ROTKH[191:160])", + "index_int": "0x0010", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse16-bits-0-31", + "name": "ROTKH[191:160]", + "description": "Root of Trust Keys Table Hash 5 (ROTKH[191:160])\nSHA384 ROTKH[223:192] / SHA56 ROTKH[95:64]" + } + ] + }, + { + "id": "fuse17", + "name": "ROTKH6", + "description": "Root of Trust Keys Table Hash 6 (ROTKH223:192])", + "index_int": "0x0011", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse17-bits-0-31", + "name": "ROTKH[223:192]", + "description": "Root of Trust Keys Table Hash 6 (ROTKH[223:192])\nSHA384 ROTKH[191:160] / SHA56 ROTKH[63:32]", + "deprecated_names": [ + "ROTKH[232:192]" + ] + } + ] + }, + { + "id": "fuse18", + "name": "ROTKH7", + "description": "Root of Trust Keys Table Hash 7 (ROTKH[255:224])", + "index_int": "0x0012", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse18-bits-0-31", + "name": "ROTKH[255:224]", + "description": "Root of Trust Keys Table Hash 7 (ROTKH[255:224])\nSHA384 ROTKH[159:128 / SHA56 ROTKH[31:0]" + } + ] + }, + { + "id": "fuse19", + "name": "ROTKH8", + "description": "Root of Trust Keys Table Hash 8 (ROTKH[287:256])", + "index_int": "0x0013", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse19-bits-0-31", + "name": "ROTKH[287:256]", + "description": "Root of Trust Keys Table Hash 8 (ROTKH[287:256])\nSHA384 ROTKH[127:96] / 0" + } + ] + }, + { + "id": "fuse20", + "name": "ROTKH9", + "description": "Root of Trust Keys Table Hash 9 (ROTKH[319:288])", + "index_int": "0x0014", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse20-bits-0-31", + "name": "ROTKH[319:288]", + "description": "Root of Trust Keys Table Hash 9 (ROTKH[319:288])\nSHA384 ROTKH[95:64] / 0" + } + ] + }, + { + "id": "fuse21", + "name": "ROTKH10", + "description": "Root of Trust Keys Table Hash 10 (ROTKH[351:320])", + "index_int": "0x0015", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse21-bits-0-31", + "name": "ROTKH[351:320]", + "description": "Root of Trust Keys Table Hash 10 (ROTKH[351:320])\nSHA384 ROTKH[63:32] / 0" + } + ] + }, + { + "id": "fuse22", + "name": "ROTKH11", + "description": "Root of Trust Keys Table Hash 11 (ROTKH[383:352])", + "index_int": "0x0016", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse22-bits-0-31", + "name": "ROTKH[383:352]", + "description": "Root of Trust Keys Table Hash 11 (ROTKH[383:352])\nSHA384 ROTKH[31:0] / 0" + } + ] + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "Prince Context configuration" + }, + "registers": [ + { + "id": "fuse23", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors 0 - 31)", + "index_int": "0x0017", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse23-bits-0-31", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX0_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key & IV. NPX_CTX0_WD0[31:0]" + } + ] + }, + { + "id": "fuse24", + "name": "NPX_CTX0_WD1", + "description": "Bitmap mask for NPX Prince context 0 (sectors 32 - 63)", + "index_int": "0x0018", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse24-bits-0-31", + "name": "NPX_CTX0_WD1", + "description": "Bitmap mask for NPX Prince context 0 (sectors 32 - 63)\nROM copies this value to NPX->VMAPCTX0_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key & IV. NPX_CTX0_WD1[31:0]" + } + ] + }, + { + "id": "fuse25", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors 0 - 31)", + "index_int": "0x0019", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse25-bits-0-31", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX1_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key & IV. NPX_CTX1_WD0[31:0]" + } + ] + }, + { + "id": "fuse26", + "name": "NPX_CTX1_WD1", + "description": "Bitmap mask for NPX Prince context 1 (sectors 32 - 63)", + "index_int": "0x001A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse26-bits-0-31", + "name": "NPX_CTX1_WD1", + "description": "Bitmap mask for NPX Prince context 1 (sectors 32 - 63)\nROM copies this value to NPX->VMAPCTX1_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key & IV. NPX_CTX1_WD1[31:0]" + } + ] + }, + { + "id": "fuse27", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors 0 - 31)", + "index_int": "0x001B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse27-bits-0-31", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX2_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key & IV. NPX_CTX2_WD0[31:0]" + } + ] + }, + { + "id": "fuse28", + "name": "NPX_CTX2_WD1", + "description": "Bitmap mask for NPX Prince context 2 (sectors 32 - 63)", + "index_int": "0x001C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse28-bits-0-31", + "name": "NPX_CTX2_WD1", + "description": "Bitmap mask for NPX Prince context 2 (sectors 32 - 63)\nROM copies this value to NPX->VMAPCTX2_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key & IV. NPX_CTX2_WD1[31:0]" + } + ] + }, + { + "id": "fuse29", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors 0 - 31)", + "index_int": "0x001D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse29-bits-0-31", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors 0 - 31)\nROM copies this value to NPX->VMAPCTX3_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key & IV. NPX_CTX3_WD0[31:0]" + } + ] + }, + { + "id": "fuse30", + "name": "NPX_CTX3_WD1", + "description": "Bitmap mask for NPX Prince context 3 (sectors 32 - 63)", + "index_int": "0x001E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse30-bits-0-31", + "name": "NPX_CTX3_WD1", + "description": "Bitmap mask for NPX Prince context 3 (sectors 32 - 63)\nROM copies this value to NPX->VMAPCTX3_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key & IV. NPX_CTX3_WD1[31:0]" + } + ] + }, + { + "id": "fuse31", + "name": "IPED_CTX_CRC32", + "description": "CRC-32/MPEG-2 value of the IPED regions start and end address setting", + "index_int": "0x001F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse31-bits-0-31", + "name": "IPED_CTX_CRC32", + "description": "CRC-32/MPEG-2 value of the IPED regions start and end address setting\nUser has to program CRC32 of IPED context configuration data present in CMPA (0x0100_40B0 - 0x0100_40EF) to have ROM do integrity check of IPED configuration data before using. This check is done only when this field is non-zero.IPED_CTX_CRC32[31:0]" + } + ] + }, + { + "id": "fuse32", + "name": "IPED_GP1", + "description": "General Purpose Fuse 1 (IPED_GP1[31:0])", + "index_int": "0x0020", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "IPED_GP1[31:0]", + "description": "General Purpose Fuse 1 (IPED_GP1[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse33", + "name": "IPED_GP2", + "description": "General Purpose Fuse 2 (IPED_GP2[31:0])", + "index_int": "0x0021", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse33-bits-0-31", + "name": "IPED_GP2[31:0]", + "description": "General Purpose Fuse 2 (IPED_GP2[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse34", + "name": "IPED_GP3", + "description": "General Purpose Fuse 3 (IPED_GP3[31:0])", + "index_int": "0x0022", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "IPED_GP3[31:0]", + "description": "General Purpose Fuse 3 (IPED_GP3[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse35", + "name": "IPED_GP4", + "description": "General Purpose Fuse 4 (IPED_GP4[31:0])", + "index_int": "0x0023", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse35-bits-0-31", + "name": "IPED_GP4[31:0]", + "description": "General Purpose Fuse 4 (IPED_GP4[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse36", + "name": "IPED_GP5", + "description": "General Purpose Fuse 5 (IPED_GP5[31:0])", + "index_int": "0x0024", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse36-bits-0-31", + "name": "IPED_GP5[31:0]", + "description": "General Purpose Fuse 5 (IPED_GP5[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse37", + "name": "IPED_GP6", + "description": "General Purpose Fuse 6 (IPED_GP6[31:0])", + "index_int": "0x0025", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse37-bits-0-31", + "name": "IPED_GP6[31:0]", + "description": "General Purpose Fuse 6 (IPED_GP6[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse38", + "name": "IPED_GP7", + "description": "General Purpose Fuse 7 (IPED_GP7[31:0])", + "index_int": "0x0026", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse38-bits-0-31", + "name": "IPED_GP7[31:0]", + "description": "General Purpose Fuse 7 (IPED_GP7[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + } + ] + }, + { + "group": { + "name": "CUST", + "description": "Customer fuses configuration" + }, + "registers": [ + { + "id": "fuse43", + "name": "GP0", + "description": "General Purpose Fuse 0 (GP0[31:0])", + "index_int": "0x002B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse43-bits-0-31", + "name": "GP0[31:0]", + "description": "General Purpose Fuse 0 (GP0[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse44", + "name": "GP1", + "description": "General Purpose Fuse 1 (GP1[31:0])", + "index_int": "0x002C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse44-bits-0-31", + "name": "GP1[31:0]", + "description": "General Purpose Fuse 1 (GP1[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse45", + "name": "GP2", + "description": "General Purpose Fuse 2 (GP2[31:0])", + "index_int": "0x002D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse45-bits-0-31", + "name": "GP2[31:0]", + "description": "General Purpose Fuse 2 (GP2[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse46", + "name": "GP3", + "description": "General Purpose Fuse 3 (GP3[31:0])", + "index_int": "0x002E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "read_lock_int": "0x00100000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse46-bits-0-31", + "name": "GP3[31:0]", + "description": "General Purpose Fuse 3 (GP3[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse47", + "name": "GP4", + "description": "General Purpose Fuse 4 (GP4[31:0])", + "index_int": "0x002F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse47-bits-0-31", + "name": "GP4[31:0]", + "description": "General Purpose Fuse 4 (GP4[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse48", + "name": "GP5", + "description": "General Purpose Fuse 5 (GP5[31:0])", + "index_int": "0x0030", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse48-bits-0-31", + "name": "GP5[31:0]", + "description": "General Purpose Fuse 5 (GP5[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse49", + "name": "GP6", + "description": "General Purpose Fuse 6 (GP6[31:0])", + "index_int": "0x0031", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse49-bits-0-31", + "name": "GP6[31:0]", + "description": "General Purpose Fuse 6 (GP6[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse50", + "name": "GP7", + "description": "General Purpose Fuse 7 (GP7[31:0])", + "index_int": "0x0032", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse50-bits-0-31", + "name": "GP7[31:0]", + "description": "General Purpose Fuse 7 (GP7[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse51", + "name": "GP8", + "description": "General Purpose Fuse 8 (GP8[31:0])", + "index_int": "0x0033", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse51-bits-0-31", + "name": "GP8[31:0]", + "description": "General Purpose Fuse 8 (GP8[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse52", + "name": "GP9", + "description": "General Purpose Fuse 9 (GP9[31:0])", + "index_int": "0x0034", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse52-bits-0-31", + "name": "GP9[31:0]", + "description": "General Purpose Fuse 9 (GP9[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse53", + "name": "GP10", + "description": "General Purpose Fuse 10 (GP10[31:0])", + "index_int": "0x0035", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse53-bits-0-31", + "name": "GP10[31:0]", + "description": "General Purpose Fuse 10 (GP10[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse54", + "name": "GP11", + "description": "General Purpose Fuse 11 (GP11[31:0])", + "index_int": "0x0036", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x04000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse54-bits-0-31", + "name": "GP11[31:0]", + "description": "General Purpose Fuse 11 (GP11[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse55", + "name": "GP12", + "description": "General Purpose Fuse 12 (GP12[31:0])", + "index_int": "0x0037", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse55-bits-0-31", + "name": "GP12[31:0]", + "description": "General Purpose Fuse 12 (GP12[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse56", + "name": "GP13", + "description": "General Purpose Fuse 13 (GP13[31:0])", + "index_int": "0x0038", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse56-bits-0-31", + "name": "GP13[31:0]", + "description": "General Purpose Fuse 13 (GP13[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse57", + "name": "GP14", + "description": "General Purpose Fuse 14 (GP14[31:0])", + "index_int": "0x0039", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse57-bits-0-31", + "name": "GP14[31:0]", + "description": "General Purpose Fuse 14 (GP14[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse58", + "name": "GP15", + "description": "General Purpose Fuse 15 (GP15[31:0])", + "index_int": "0x003A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse58-bits-0-31", + "name": "GP15[31:0]", + "description": "General Purpose Fuse 15 (GP15[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse59", + "name": "GP16", + "description": "General Purpose Fuse 16 (GP16[31:0])", + "index_int": "0x003B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse59-bits-0-31", + "name": "GP16[31:0]", + "description": "General Purpose Fuse 16 (GP16[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse60", + "name": "GP17", + "description": "General Purpose Fuse 17 (GP17[31:0])", + "index_int": "0x003C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse60-bits-0-31", + "name": "GP17[31:0]", + "description": "General Purpose Fuse 17 (GP17[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse61", + "name": "GP18", + "description": "General Purpose Fuse 18 (GP18[31:0])", + "index_int": "0x003D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse61-bits-0-31", + "name": "GP18[31:0]", + "description": "General Purpose Fuse 18 (GP18[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse62", + "name": "GP19", + "description": "General Purpose Fuse 19 (GP19[31:0])", + "index_int": "0x003E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x08000000", + "read_lock_int": "0x20000000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse62-bits-0-31", + "name": "GP19[31:0]", + "description": "General Purpose Fuse 19 (GP19[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse63", + "name": "GP20", + "description": "General Purpose Fuse 20 (GP20[31:0])", + "index_int": "0x003F", + "bitfields": [ + { + "width": 32, + "id": "fuse63-bits-0-31", + "name": "GP20[31:0]", + "description": "General Purpose Fuse 20 (GP20[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse64", + "name": "GP21", + "description": "General Purpose Fuse 21 (GP21[31:0])", + "index_int": "0x0040", + "bitfields": [ + { + "width": 32, + "id": "fuse64-bits-0-31", + "name": "GP21[31:0]", + "description": "General Purpose Fuse 21 (GP21[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse65", + "name": "GP22", + "description": "General Purpose Fuse 22 (GP22[31:0])", + "index_int": "0x0041", + "bitfields": [ + { + "width": 32, + "id": "fuse65-bits-0-31", + "name": "GP22[31:0]", + "description": "General Purpose Fuse 22 (GP22[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse66", + "name": "GP23", + "description": "General Purpose Fuse 23 (GP23[31:0])", + "index_int": "0x0042", + "bitfields": [ + { + "width": 32, + "id": "fuse66-bits-0-31", + "name": "GP23[31:0]", + "description": "General Purpose Fuse 23 (GP23[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse67", + "name": "GP24", + "description": "General Purpose Fuse 24 (GP24[31:0])", + "index_int": "0x0043", + "bitfields": [ + { + "width": 32, + "id": "fuse67-bits-0-31", + "name": "GP24[31:0]", + "description": "General Purpose Fuse 24 (GP24[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse68", + "name": "GP25", + "description": "General Purpose Fuse 25 (GP25[31:0])", + "index_int": "0x0044", + "bitfields": [ + { + "width": 32, + "id": "fuse68-bits-0-31", + "name": "GP25[31:0]", + "description": "General Purpose Fuse 25 (GP25[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse69", + "name": "GP26", + "description": "General Purpose Fuse 26 (GP26[31:0])", + "index_int": "0x0045", + "bitfields": [ + { + "width": 32, + "id": "fuse69-bits-0-31", + "name": "GP26[31:0]", + "description": "General Purpose Fuse 26 (GP26[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse70", + "name": "GP27", + "description": "General Purpose Fuse 27 (GP27[31:0])", + "index_int": "0x0046", + "bitfields": [ + { + "width": 32, + "id": "fuse70-bits-0-31", + "name": "GP27[31:0]", + "description": "General Purpose Fuse 27 (GP27[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse71", + "name": "GP28", + "description": "General Purpose Fuse 28(GP28[31:0])", + "index_int": "0x0047", + "bitfields": [ + { + "width": 32, + "id": "fuse71-bits-0-31", + "name": "GP28[31:0]", + "description": "General Purpose Fuse 28(GP28[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse72", + "name": "GP29", + "description": "General Purpose Fuse 29 (GP29[31:0])", + "index_int": "0x0048", + "bitfields": [ + { + "width": 32, + "id": "fuse72-bits-0-31", + "name": "GP29[31:0]", + "description": "General Purpose Fuse 29 (GP29[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse73", + "name": "GP30", + "description": "General Purpose Fuse 30 (GP30[31:0])", + "index_int": "0x0049", + "bitfields": [ + { + "width": 32, + "id": "fuse73-bits-0-31", + "name": "GP30[31:0]", + "description": "General Purpose Fuse 30 (GP30[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse74", + "name": "GP31", + "description": "General Purpose Fuse 31 (GP31[31:0])", + "index_int": "0x004A", + "bitfields": [ + { + "width": 32, + "id": "fuse74-bits-0-31", + "name": "GP31[31:0]", + "description": "General Purpose Fuse 31 (GP31[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse75", + "name": "GP32", + "description": "General Purpose Fuse 32 (GP32[31:0])", + "index_int": "0x004B", + "bitfields": [ + { + "width": 32, + "id": "fuse75-bits-0-31", + "name": "GP32[31:0]", + "description": "General Purpose Fuse 32 (GP32[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse76", + "name": "GP33", + "description": "General Purpose Fuse 33 (GP33[31:0])", + "index_int": "0x004C", + "bitfields": [ + { + "width": 32, + "id": "fuse76-bits-0-31", + "name": "GP33[31:0]", + "description": "General Purpose Fuse 33 (GP33[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse77", + "name": "GP34", + "description": "General Purpose Fuse 34 (GP34[31:0])", + "index_int": "0x004D", + "bitfields": [ + { + "width": 32, + "id": "fuse77-bits-0-31", + "name": "GP34[31:0]", + "description": "General Purpose Fuse 34 (GP34[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse78", + "name": "GP35", + "description": "General Purpose Fuse 35 (GP35[31:0])", + "index_int": "0x004E", + "bitfields": [ + { + "width": 32, + "id": "fuse78-bits-0-31", + "name": "GP35[31:0]", + "description": "General Purpose Fuse 35 (GP35[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse79", + "name": "GP36", + "description": "General Purpose Fuse 36 (GP36[31:0])", + "index_int": "0x004F", + "bitfields": [ + { + "width": 32, + "id": "fuse79-bits-0-31", + "name": "GP36[31:0]", + "description": "General Purpose Fuse 36 (GP36[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse80", + "name": "GP37", + "description": "General Purpose Fuse 37 (GP37[31:0])", + "index_int": "0x0050", + "bitfields": [ + { + "width": 32, + "id": "fuse80-bits-0-31", + "name": "GP37[31:0]", + "description": "General Purpose Fuse 37 (GP37[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + }, + { + "id": "fuse81", + "name": "GP38", + "description": "General Purpose Fuse 38 (GP38[31:0])", + "index_int": "0x0051", + "bitfields": [ + { + "width": 32, + "id": "fuse81-bits-0-31", + "name": "GP38[31:0]", + "description": "General Purpose Fuse 38 (GP38[31:0])\nGeneral purpose fuse words available for customer use." + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a0.json new file mode 100644 index 0000000..2049992 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a0.json @@ -0,0 +1,2399 @@ +{ + "cpu": "MCXN946", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "Description of Header register", + "offset_int": "0", + "default_value_int": "0x96350000", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field000-bits0-7", + "name": "CFPA_LC_STATE", + "description": "CFPA_LC_STATE." + }, + { + "width": 8, + "id": "field000-bits8-15", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + }, + { + "width": 16, + "access": "RO", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CFPA Header marker should be set to 0x9635" + } + ] + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "Description of CFPA_PAGE_VERSION register", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 24, + "id": "field004-bits0-23", + "name": "CFPA_PAGE_VERSION", + "description": "CFPA page version" + }, + { + "width": 2, + "id": "field004-bits24-25", + "name": "IMG_UPD", + "description": "Image_updated", + "values": [ + { + "name": "NOTHING_CHANGED", + "value": 0, + "description": "No action" + }, + { + "name": "IMAGE0_CMAC_UPDATE", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "IMAGE1_CMAC_UPDATE", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "SBL_IMG_CMAC_UPDATE", + "value": 3, + "description": "Update SBL Image CMAC" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field004-bits27-29", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in OEM_OPEN (0x3) LC state.", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "UPDATE_IN_CMPA", + "value": 2, + "description": "Update CMAC field in CMPA page. " + }, + { + "name": "TO_OEM_SECURE", + "value": 3, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_SECURE (0x7)" + }, + { + "name": "TO_OEM_CLOSED", + "value": 5, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_CLOSED (0xF)." + }, + { + "name": "TO_OEM_LOCKED", + "value": 6, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to OEM_LOCKED (0xCF)." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field004-bit31", + "name": "DICE_UPD", + "description": "Update DICE certificate during next boot.", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "GENERATE_CERTIFICATE", + "value": 1, + "description": "Generate certificate. " + } + ] + } + ] + }, + { + "id": "field008", + "name": "Secure_FW_Version", + "description": "Description of Secure_FW_Version register", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Description of NS_FW_Version register", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "Recovery_FW_Version", + "description": "Description of Recovery_FW_Version register", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field014", + "name": "SECBOOT_FLAGS", + "description": "Description of SECBOOT_FLAGS register", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RoTK0_EN", + "description": "Root of Trust Key 0 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_2", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "REVOKED_3", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "RoTK1_EN", + "description": "Root of Trust Key 1 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_2", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "REVOKED_3", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "RoTK2_EN", + "description": "Root of Trust Key 2 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_2", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "REVOKED_3", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "RoTK3_EN", + "description": "Root of Trust Key 3 Enable", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_2", + "value": 2, + "description": "Key Revoked" + }, + { + "name": "REVOKED_3", + "value": 3, + "description": "Key Revoked" + } + ] + }, + { + "width": 20 + }, + { + "width": 4, + "id": "field014-bits28-31", + "name": "OEM_RETURN_ERASE_DONE", + "description": "OEM_RETURN_ERASE_DONE" + } + ] + }, + { + "id": "field018", + "name": "IMAGE_KEY_REVOKE", + "description": "Image Key Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 24, + "id": "field018-bits0-23", + "name": "IMAGE_KEY_REVOKE_ID", + "description": "Image Key Revocation ID (Monotonic counter)" + }, + { + "width": 8 + } + ] + }, + { + "id": "field01C", + "name": "LP_VECTOR_ADDR", + "description": "Vector address when waking from power-down and deep power down states.", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field020", + "name": "DBG_REVOKE_VU", + "description": "Debug Revoke Vendor Usage", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field020-bits0-15", + "name": "VENDOR_USAGE", + "description": "Debug Vendor Usage" + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Disable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 1, + "id": "field024-bit15", + "name": "UUID_CHECK", + "description": "UUID Check", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value of Bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field028-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 debug enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 5 + }, + { + "width": 16, + "id": "field028-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field030", + "name": "MCTR_NPX_CTX0", + "description": "Erase count for internal Prince region 0 (Monotonic counter)", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field034", + "name": "MCTR_NPX_CTX1", + "description": "Erase count for internal Prince region 1 (Monotonic counter)", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field038", + "name": "MCTR_NPX_CTX2", + "description": "Erase count for internal Prince region 2 (Monotonic counter)", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field03C", + "name": "MCTR_NPX_CTX3", + "description": "Erase count for internal Prince region 3 (Monotonic counter)", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field040", + "name": "MCTR_IPED_CTX0", + "description": "Erase count for external Prince region 0 (Monotonic counter)", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field044", + "name": "MCTR_IPED_CTX1", + "description": "Erase count for external Prince region 1 (Monotonic counter)", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field048", + "name": "MCTR_IPED_CTX2", + "description": "Erase count for external Prince region 2 (Monotonic counter)", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field04C", + "name": "MCTR_IPED_CTX3", + "description": "Erase count for external Prince region 3 (Monotonic counter)", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "MCTR_IPED_CTX4", + "description": "Erase count for external Prince region 4 (Monotonic counter)", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "MCTR_IPED_CTX5", + "description": "Erase count for external Prince region 5 (Monotonic counter)", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field058", + "name": "MCTR_IPED_CTX6", + "description": "Erase count for external Prince region 6 (Monotonic counter)", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "MCTR_IPED_CTX7", + "description": "Erase count for external Prince region 7 (Monotonic counter)", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field060", + "name": "ERR_AUTH_FAIL_COUNT", + "description": "Authentication failure counter during boot, SB3, debug authentication (Monotonic counter)", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ERR_ITRC_COUNT", + "description": "Tamper event counter (ITRC reset, WDT reset, WDT reset, GDET reset, Tamper pin) (Monotonic counter)", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ERR_CFG_FAIL_COUNT", + "description": "Configuration check failure counter during CMPA, CFPA, ROM patch, TRNG, PUF start (Monotonic counter)", + "offset_int": "0x0068", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ERR_CONT3", + "description": "Reserved error counter (Monotonic counter)", + "offset_int": "0x006C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "ERR_CONT4", + "description": "Reserved error counter (Monotonic counter)", + "offset_int": "0x0070", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "ERR_CONT5", + "description": "Reserved error counter (Monotonic counter)", + "offset_int": "0x0074", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "ERR_CONT6", + "description": "Reserved error counter (Monotonic counter)", + "offset_int": "0x0078", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "ERR_CONT7", + "description": "Reserved error counter (Monotonic counter)", + "offset_int": "0x007C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2", + "offset_int": "0x0088", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3", + "offset_int": "0x008C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "MFLAG_CUST_0", + "description": "Customer defined Monotonic flags 0 (once a bit is set the newer version of the page should have the flag set.)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "MFLAG_CUST_1", + "description": "Customer defined Monotonic flags 1", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "MFLAG_CUST_2", + "description": "Customer defined Monotonic flags 2", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "MFLAG_CUST_3", + "description": "Customer defined Monotonic flags 3", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "MFLAG_CUST_4", + "description": "Customer defined Monotonic flags 4", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "MFLAG_CUST_5", + "description": "Customer defined Monotonic flags 5", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "MFLAG_CUST_6", + "description": "Customer defined Monotonic flags 6", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "MFLAG_CUST_7", + "description": "Customer defined Monotonic flags 7", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C0", + "name": "FLASH_ACL_0_7", + "description": "Description of FLASH_ACL_0_7 register", + "offset_int": "0x00C0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0C0-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C4", + "name": "FLASH_ACL_8_15", + "description": "Description of FLASH_ACL_8_15 register", + "offset_int": "0x00C4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0C4-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C8", + "name": "FLASH_ACL_16_23", + "description": "Description of FLASH_ACL_16_23 register", + "offset_int": "0x00C8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0C8-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0CC", + "name": "FLASH_ACL_24_31", + "description": "Description of FLASH_ACL_24_31 register", + "offset_int": "0x00CC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0CC-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D0", + "name": "FLASH_ACL_32_39", + "description": "Description of FLASH_ACL_32_39 register", + "offset_int": "0x00D0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0D0-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D4", + "name": "FLASH_ACL_40_47", + "description": "Description of FLASH_ACL_40_47 register", + "offset_int": "0x00D4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0D4-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D8", + "name": "FLASH_ACL_48_55", + "description": "Description of FLASH_ACL_48_55 register", + "offset_int": "0x00D8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0D8-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0DC", + "name": "FLASH_ACL_56_63", + "description": "Description of FLASH_ACL_55_63 register", + "offset_int": "0x00DC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field0DC-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector." + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector." + }, + { + "width": 1 + } + ] + }, + { + "id": "field0E0", + "name": "SBL_IMG0_CMAC0", + "description": "Image 0 CMAC 0", + "offset_int": "0x00E0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E4", + "name": "SBL_IMG0_CMAC1", + "description": "Image 0 CMAC 1", + "offset_int": "0x00E4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E8", + "name": "SBL_IMG0_CMAC2", + "description": "Image 0 CMAC 2", + "offset_int": "0x00E8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0EC", + "name": "SBL_IMG0_CMAC3", + "description": "Image 0 CMAC 3", + "offset_int": "0x00EC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F0", + "name": "IMG1_CMAC0", + "description": "Image 1 CMAC 0", + "offset_int": "0x00F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F4", + "name": "IMG1_CMAC1", + "description": "Image 1 CMAC 1", + "offset_int": "0x00F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F8", + "name": "IMG1_CMAC2", + "description": "Image 1 CMAC 2", + "offset_int": "0x00F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0FC", + "name": "IMG1_CMAC3", + "description": "Image 1 CMAC 3", + "offset_int": "0x00FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field100", + "name": "DICE_Certificate", + "description": "DICE Certificate register", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00104-0018C", + "description": "Reserved 00104-0018C" + }, + "registers": [ + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00120", + "name": "Reserved 0x00120", + "description": "This field is reserved for internal use", + "offset_int": "0x0120", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00124", + "name": "Reserved 0x00124", + "description": "This field is reserved for internal use", + "offset_int": "0x0124", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00128", + "name": "Reserved 0x00128", + "description": "This field is reserved for internal use", + "offset_int": "0x0128", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0012C", + "name": "Reserved 0x0012C", + "description": "This field is reserved for internal use", + "offset_int": "0x012C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00130", + "name": "Reserved 0x00130", + "description": "This field is reserved for internal use", + "offset_int": "0x0130", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00134", + "name": "Reserved 0x00134", + "description": "This field is reserved for internal use", + "offset_int": "0x0134", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00138", + "name": "Reserved 0x00138", + "description": "This field is reserved for internal use", + "offset_int": "0x0138", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0013C", + "name": "Reserved 0x0013C", + "description": "This field is reserved for internal use", + "offset_int": "0x013C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00140", + "name": "Reserved 0x00140", + "description": "This field is reserved for internal use", + "offset_int": "0x0140", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00144", + "name": "Reserved 0x00144", + "description": "This field is reserved for internal use", + "offset_int": "0x0144", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00148", + "name": "Reserved 0x00148", + "description": "This field is reserved for internal use", + "offset_int": "0x0148", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0014C", + "name": "Reserved 0x0014C", + "description": "This field is reserved for internal use", + "offset_int": "0x014C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00160", + "name": "Reserved 0x00160", + "description": "This field is reserved for internal use", + "offset_int": "0x0160", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "IPED_GCM_AAD_CTX0", + "description": "Additional Authentication Data for IPED context 0", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "IPED_GCM_AAD_CTX1", + "description": "Additional Authentication Data for IPED context 1", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "IPED_GCM_AAD_CTX2", + "description": "Additional Authentication Data for IPED context 2", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "IPED_GCM_AAD_CTX3", + "description": "Additional Authentication Data for IPED context 3", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "IPED_GCM_AAD_CTX4", + "description": "Additional Authentication Data for IPED context 4", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "IPED_GCM_AAD_CTX5", + "description": "Additional Authentication Data for IPED context 5", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "IPED_GCM_AAD_CTX6", + "description": "Additional Authentication Data for IPED context 6", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "IPED_GCM_AAD_CTX7", + "description": "Additional Authentication Data for IPED context 7", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 001B0-001E8", + "description": "Reserved 001B0-001E8" + }, + "registers": [ + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CFPA _CRC[31:0] used during low-power wake.", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "CFPA0 CMAC 0", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CFPA0 CMAC 1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CFPA0 CMAC 2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CFPA0 CMAC 3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a1.json new file mode 100644 index 0000000..d6a9308 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cfpa_a1.json @@ -0,0 +1,6300 @@ +{ + "cpu": "mcxn946", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "Header", + "description": "CFPA Header", + "offset_int": "0", + "default_value_int": "0x96350000", + "bitfields": [ + { + "width": 8, + "id": "field000-bits0-7", + "name": "CFPA_LC_STATE", + "description": "Life cycle state. This field can be used to advance life cycle state to 0x7, 0xF or 0xCF during development (OTP_LC_STATE = 0x3) for testing deployed states without programming OTP fuse. When CFPA is used to advance LC state, then application code should implement hooks, to revert CFPA_LC_STATE field to 0x3 to bring the device back to OEM_DEVELOP state (0x03). One such example is a GPIO interrupt handler invoked on a button press which modified the CFPA_LC_STATE to 0x3. Below are the allowed values for this field. Use of other values may lead to bricked state", + "values": [ + { + "name": "USE_LC_STATE_OTP", + "value": 0, + "description": "Use LC state from OTP" + }, + { + "name": "DEVELOP", + "value": 3, + "description": "Develop state" + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Develop 2 state" + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field state" + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "In-field locked state" + } + ] + }, + { + "width": 8, + "id": "field000-bits8-15", + "name": "INV_CFPA_LC_STATE", + "description": "Inverted value of CFPA_LC_STATE. This INV_CPFA_LC_STATE ^ CFPA_LC_STATE[7:0] should be 0xFF, otherwise the CPFA_LC_STATE will not be valid", + "calculated": "INVERSE" + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "CFPA_HEADER", + "description": "CFPA Header marker should be set to 0x9635. After this header is set, all non-zero values will take effect; leaving all values set to 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CFPA header" + } + ] + }, + { + "id": "field004", + "name": "CFPA_PAGE_VERSION", + "description": "CFPA Page Version.", + "offset_int": "0x0004", + "default_value_int": "0x00FFFFFF", + "bitfields": [ + { + "width": 24, + "id": "field004-bits0-23", + "name": "CFPA_page_version", + "description": "CFPA page version. Boot ROM uses this field to determine the active CFPA page by comparing the values in this field for the two CFPA pages. The page with higher version number is picked as active page if it passes the CMAC authentication. This field is updated by ROM whenever CFPA page is updated. Write '0xFF_FFFF' to auto increment current CFPA page version value (by ROM)" + }, + { + "width": 2, + "id": "field004-bits24-25", + "name": "IMG_UPD", + "description": "Image updated. Note: CMAC boot is only supported for internal flash. If using a FlexSPI flash XIP image, then this field should always be left as zero", + "values": [ + { + "name": "NOTHING_CHANGED", + "value": 0, + "description": "No action" + }, + { + "name": "IMAGE0_CMAC_UPDATE", + "value": 1, + "description": "Update image 0 CMAC" + }, + { + "name": "IMAGE1_CMAC_UPDATE", + "value": 2, + "description": "Update image 1 CMAC" + }, + { + "name": "SBL_IMG_CMAC_UPDATE", + "value": 3, + "description": "Update SBL image CMAC (image in IFR0 0x0100_8000). Value written in IMG0_CMAC field" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field004-bits27-29", + "name": "CMPA_UPD", + "description": "CMPA page updated through ROM API. Thus compute CMAC on sub-sequent boot. This field is checked only in Develop (0x3) LC state. All other combinations update CMAC field in CMPA page", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "UPDATE_IN_CMPA", + "value": 2, + "description": "Update CMAC field in CMPA page" + }, + { + "name": "TO_OEM_SECURE", + "value": 3, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to Develop2 (0x7)" + }, + { + "name": "TO_OEM_CLOSED", + "value": 5, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to In-Field (0xF)" + }, + { + "name": "TO_OEM_LOCKED", + "value": 6, + "description": "Update CMAC field in CMPA page and OTP. Advance OTP_LC_STATE to In-Field Locked (0xCF)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field004-bit31", + "name": "DICE_UPD", + "description": "Update DICE certificate during next boot", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "GENERATE_CERTIFICATE", + "value": 1, + "description": "Generate certificate" + } + ] + } + ] + }, + { + "id": "field008", + "name": "Secure_FW_Version", + "description": "Secure Firmware version. This monotonic counter field tracks the firmware version of secure partition. ROM uses this field to enforce anti-rollback checking during secure boot and secure update (SB3 header). For image authentication pass during secure boot the FW version in image manifest must be equal or greater than this value. During secure update and recovery boot the version number in SB3 header Must be equal or greater than the value in this field. Apart from SB3 header check, user can enforce anti-rollback check during SB3 processing by using 'kSB3_COMMAND_fwVersionCheck' SB command with 'kNBOOT_CNT_secure' counter ID parameter, in SB3 file.", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field008-bits0-15", + "name": "Secure_firmware_version", + "description": "Secure Firmware version. This monotonic counter field tracks the firmware version of secure partition. ROM uses this field to enforce anti-rollback checking during secure boot and secure update (SB3 header). For image authentication pass during secure boot the FW version in image manifest must be equal or greater than this value. During secure update & recovery boot the version number in SB3 header Must be equal or greater than the value in this field. Apart from SB3 header check, user can enforce anti-rollback check during SB3 processing by using \"kSB3_COMMAND_fwVersionCheck\" SB command with 'kNBOOT_CNT_secure' counter ID parameter, in SB3 file" + }, + { + "width": 16 + } + ] + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure Firmware version. This monotonic counter field can be used to track the firmware version of non-secure partition. An anti-rollback check can be enforced during update by using this field and 'kSB3_COMMAND_fwVersionCheck' SB command with 'kNBOOT_CNT_nonsecure' counter ID parameter, in SB3 file.", + "offset_int": "0x000C", + "default_value_int": "0" + }, + { + "id": "Reserved00010", + "name": "Reserved 0x00010", + "description": "This field is reserved for internal use", + "offset_int": "0x0010", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field014", + "name": "SECBOOT_FLAGS", + "description": "Secure BOOT Flags.", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RoTK0_EN", + "description": "Root of Trust Key 0 Enable. Determines if ROTK0 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "RoTK1_EN", + "description": "Root of Trust Key 1 Enable. Determines if ROTK1 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "RoTK2_EN", + "description": "Root of Trust Key 2 Enable. Determines if ROTK2 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "RoTK3_EN", + "description": "Root of Trust Key 3 Enable. Determines if ROTK3 can be used during secure boot", + "values": [ + { + "name": "ENABLED_0", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED_1", + "value": 1, + "description": "Enabled" + }, + { + "name": "KEY_REVOKED_2", + "value": 2, + "description": "Key revoked" + }, + { + "name": "KEY_REVOKED_3", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 20 + }, + { + "width": 4, + "id": "field014-bits28-31", + "name": "OEM_RETURN_ERASE_DONE", + "description": "OEM assets erase done flag. ROM sets this field to 0xA after erasing the user flash and OEM assets. This operation is done on first boot after OTP_LC_STATE is advanced to 0x1F or higher states. On every boot ROM checks if LC_STATE is greater or equal to 0x1F and this field is empty in active CFPA page, then it erases OEM assets and updates this field in CFPA before freezing CFPA pages and enabling debug access. If the field is already set to 0xA then it proceeds without erasing user flash area" + } + ] + }, + { + "id": "field018", + "name": "IMAGE_KEY_REVOKE", + "description": "Image Key Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 24, + "id": "field018-bits0-23", + "name": "Image_key_revocation_ID", + "description": "Image signing key revocation counter. This monotonically increasing unary encode counter (e.g., 0x0, 0x1, 0x3, 0x7, 0xF...) field is used by boot ROM to enforce image signing key (ISK) certificate revocation policy. Boot ROM accepts an ISK certificate as valid only if the \"constraint\" field in ISK certificate is the same or greater than the ISK revocation counter. The 32-bit ISK revocation counter is formed using 8 bits of IMAGE_KEY_REVOKE[7:0] field in OTP as MSB bits and lower 24 bits from this field. ISK certificate validation is done as part of boot, FW update (SB3) and recovery (SB3) image authentication" + }, + { + "width": 8 + } + ] + }, + { + "id": "field01C", + "name": "LP_VECTOR_ADDR", + "description": "Vector address when waking from power-down and deep power down states when CMPA.LP_SEC_BOOT is set to 2b'10.", + "offset_int": "0x001C", + "default_value_int": "0" + }, + { + "id": "field020", + "name": "DBG_REVOKE_VU", + "description": "Debug Revoke Vendor Usage.", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field020-bits0-15", + "name": "Debug_certificate_revocation_counter", + "deprecated_names": [ + "FIELD" + ], + "description": "Debug certificate revocation counter. This monotonic counter field is used for revoking debug certificates. As part of debug authentication, CC_VU field in debug certificate/credential is checked against DCFG_VENDOR_USAGE value. The 32-bit DCFG_VENDOR_USAGE is formed using upper 16 bit of CMPA.VENDOR_USAGE and lower 16 bits of this field" + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, for ease of development, Level 1 customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access.", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug enable CoolFlex debug", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field024-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access.", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field028-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug enable CoolFlex debug", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field028-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16, + "id": "field028-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value of [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "Reserved0002C", + "name": "Reserved 0x0002C", + "description": "This field is reserved for internal use", + "offset_int": "0x002C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field030", + "name": "MCTR_NPX_CTX0", + "description": "Erase counter for Prince region 0. Monotonic erase counter for NPX region 0. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX0. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0030", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field034", + "name": "MCTR_NPX_CTX1", + "description": "Erase counter for Prince region 1. Monotonic erase counter for NPX region 1. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX1. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0034", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field038", + "name": "MCTR_NPX_CTX2", + "description": "Erase counter for Prince region 2. Monotonic erase counter for NPX region 2. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX2. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0038", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field03C", + "name": "MCTR_NPX_CTX3", + "description": "Erase counter for Prince region 3. Monotonic erase counter for NPX region 3. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by NPX for encryption/decryption is computed by ROM bootloader and incorporates device UUID, NPX region number and MCTR_NPX_CTX3. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x003C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field040", + "name": "MCTR_IPED_CTX0", + "description": "Monotonic erase counter for IPED region 0. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX0. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0040", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field044", + "name": "MCTR_IPED_CTX1", + "description": "Monotonic erase counter for IPED region 1. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX1. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0044", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field048", + "name": "MCTR_IPED_CTX2", + "description": "Monotonic erase counter for IPED region 2. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX2. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0048", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field04C", + "name": "MCTR_IPED_CTX3", + "description": "Monotonic erase counter for IPED region 3. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX3. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x004C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field050", + "name": "MCTR_IPED_CTX4", + "description": "Monotonic erase counter for IPED region 4. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX4. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0050", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field054", + "name": "MCTR_IPED_CTX5", + "description": "Monotonic erase counter for IPED region 5. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX5. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0054", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field058", + "name": "MCTR_IPED_CTX6", + "description": "Monotonic erase counter for IPED region 6. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX6. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x0058", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field05C", + "name": "MCTR_IPED_CTX7", + "description": "Monotonic erase counter for IPED region 7. This value is used by bootloader to dynamically compute region IV. This counter will increment by one, during each erase cycle of the corresponding flash region. User should not write anything in this field. This field is entirely handled by ROM. Final IV value for given region used by IPED for encryption/decryption is computed by ROM bootloader and incorporates device UUID, IPED region number and MCTR_IPED_CTX7. Application should always use ROM APIs to erase whole Prince region to keep IV consistent.", + "offset_int": "0x005C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field060", + "name": "ERR_AUTH_FAIL_COUNT", + "description": "Authentication failure counter. This monotonic counter field is incremented by boot ROM on authentication failure during boot, SB3, or debug authentication (Monotonic counter).", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ERR_ITRC_COUNT", + "description": "Tamper event counter. This monotonic counter field is incremented by boot ROM whenever the reset cause during boot is detected as - ITRC reset caused by security sensors or - WDT 0/1 reset or - Tamper pin reset.", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00068-0007C", + "description": "Reserved 00068-0007C" + }, + "registers": [ + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field080", + "name": "MCTR_CUST_CTR0", + "description": "Customer defined Monotonic counter 0 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0080", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "MCTR_CUST_CTR1", + "description": "Customer defined Monotonic counter 1 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0084", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "MCTR_CUST_CTR2", + "description": "Customer defined Monotonic counter 2 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0088", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "MCTR_CUST_CTR3", + "description": "Customer defined Monotonic counter 3 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x008C", + "default_value_int": "0" + }, + { + "id": "field090", + "name": "MCTR_CUST_CTR4", + "description": "Customer defined Monotonic counter 4 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "MCTR_CUST_CTR5", + "description": "Customer defined Monotonic counter 5 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "MCTR_CUST_CTR6", + "description": "Customer defined Monotonic counter 6 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "MCTR_CUST_CTR7", + "description": "Customer defined Monotonic counter 7 for application use. ROM enforces monotonic increment check during CFPA-CMAC page update. If the new counter value is less than the value in active CFPA page, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "MFLAG_CUST_0", + "description": "Customer defined Monotonic flags 0 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "MFLAG_CUST_1", + "description": "Customer defined Monotonic flags 1 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "MFLAG_CUST_2", + "description": "Customer defined Monotonic flags 2 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00A8", + "default_value_int": "0" + }, + { + "id": "field0AC", + "name": "MFLAG_CUST_3", + "description": "Customer defined Monotonic flags 3 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00AC", + "default_value_int": "0" + }, + { + "id": "field0B0", + "name": "MFLAG_CUST_4", + "description": "Customer defined Monotonic flags 4 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B0", + "default_value_int": "0" + }, + { + "id": "field0B4", + "name": "MFLAG_CUST_5", + "description": "Customer defined Monotonic flags 5 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B4", + "default_value_int": "0" + }, + { + "id": "field0B8", + "name": "MFLAG_CUST_6", + "description": "Customer defined Monotonic flags 6 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00B8", + "default_value_int": "0" + }, + { + "id": "field0BC", + "name": "MFLAG_CUST_7", + "description": "Customer defined Monotonic flags 7 for application use. Once a bit is set in this field it should be set on sub-sequent updates of the page. ROM emulates One Time Programmable (OTP) bits behavior during CFPA-CMAC update. Compared to current value, if the new value has bit cleared, then the update is rejected and CMAC signing is skipped.", + "offset_int": "0x00BC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Flash Access Control", + "description": "Flash access control" + }, + "registers": [ + { + "id": "field0C0", + "name": "FLASH_ACL_0_7", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C0", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0C0-bits0-2", + "name": "ACL_SEC_0", + "description": "Access control for flash sector (offset range 0x00_0000 - 0x00_7FFF). Select one of the 8 pre-defined access control attributes for the given Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits4-6", + "name": "ACL_SEC_1", + "description": "Access control for flash sector (offset range 0x00_8000 - 0x00_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits8-10", + "name": "ACL_SEC_2", + "description": "Access control for flash sector (offset range 0x01_0000 - 0x01_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits12-14", + "name": "ACL_SEC_3", + "description": "Access control for flash sector. (offset range 0x01_8000 - 0x01_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits16-18", + "name": "ACL_SEC_4", + "description": "Access control for flash sector (offset range 0x02_0000 - 0x02_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits20-22", + "name": "ACL_SEC_5", + "description": "Access control for flash sector (offset range 0x02_8000 - 0x02_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits24-26", + "name": "ACL_SEC_6", + "description": "Access control for flash sector (offset range 0x03_0000 - 0x03_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C0-bits28-30", + "name": "ACL_SEC_7", + "description": "Access control for flash sector (offset range 0x03_8000 - 0x03_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C4", + "name": "FLASH_ACL_8_15", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C4", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0C4-bits0-2", + "name": "ACL_SEC_8", + "description": "Access control for flash sector (offset range 0x04_0000 - 0x04_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits4-6", + "name": "ACL_SEC_9", + "description": "Access control for flash sector (offset range 0x04_8000 - 0x04_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits8-10", + "name": "ACL_SEC_10", + "description": "Access control for flash sector (offset range 0x05_0000 - 0x05_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits12-14", + "name": "ACL_SEC_11", + "description": "Access control for flash sector. (offset range 0x05_8000 - 0x05_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits16-18", + "name": "ACL_SEC_12", + "description": "Access control for flash sector (offset range 0x06_0000 - 0x06_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits20-22", + "name": "ACL_SEC_13", + "description": "Access control for flash sector (offset range 0x06_8000 - 0x06_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits24-26", + "name": "ACL_SEC_14", + "description": "Access control for flash sector (offset range 0x07_0000 - 0x07_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C4-bits28-30", + "name": "ACL_SEC_15", + "description": "Access control for flash sector (offset range 0x07_8000 - 0x07_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0C8", + "name": "FLASH_ACL_16_23", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00C8", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0C8-bits0-2", + "name": "ACL_SEC_16", + "description": "Access control for flash sector (offset range 0x08_0000 - 0x08_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits4-6", + "name": "ACL_SEC_17", + "description": "Access control for flash sector (offset range 0x08_8000 - 0x08_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits8-10", + "name": "ACL_SEC_18", + "description": "Access control for flash sector (offset range 0x09_0000 - 0x09_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits12-14", + "name": "ACL_SEC_19", + "description": "Access control for flash sector. (offset range 0x09_8000 - 0x09_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits16-18", + "name": "ACL_SEC_20", + "description": "Access control for flash sector (offset range 0x0A_0000 - 0x0A_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits20-22", + "name": "ACL_SEC_21", + "description": "Access control for flash sector (offset range 0x0A_8000 - 0x0A_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits24-26", + "name": "ACL_SEC_22", + "description": "Access control for flash sector (offset range 0x0B_0000 - 0x0B_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0C8-bits28-30", + "name": "ACL_SEC_23", + "description": "Access control for flash sector (offset range 0x0B_8000 - 0x0B_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0CC", + "name": "FLASH_ACL_24_31", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00CC", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0CC-bits0-2", + "name": "ACL_SEC_24", + "description": "Access control for flash sector (offset range 0x0C_0000 - 0x0C_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits4-6", + "name": "ACL_SEC_25", + "description": "Access control for flash sector (offset range 0x0C_8000 - 0x0C_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits8-10", + "name": "ACL_SEC_26", + "description": "Access control for flash sector (offset range 0x0D_0000 - 0x0D_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits12-14", + "name": "ACL_SEC_27", + "description": "Access control for flash sector. (offset range 0x0D_8000 - 0x0D_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits16-18", + "name": "ACL_SEC_28", + "description": "Access control for flash sector (offset range 0x0E_0000 - 0x0E_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits20-22", + "name": "ACL_SEC_29", + "description": "Access control for flash sector (offset range 0x0E_8000 - 0x0E_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits24-26", + "name": "ACL_SEC_30", + "description": "Access control for flash sector (offset range 0x0F_0000 - 0x0F_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0CC-bits28-30", + "name": "ACL_SEC_31", + "description": "Access control for flash sector (offset range 0x0F_8000 - 0x0F_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D0", + "name": "FLASH_ACL_32_39", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00D0", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0D0-bits0-2", + "name": "ACL_SEC_32", + "description": "Access control for flash sector (offset range 0x10_0000 - 0x10_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits4-6", + "name": "ACL_SEC_33", + "description": "Access control for flash sector (offset range 0x10_8000 - 0x10_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits8-10", + "name": "ACL_SEC_34", + "description": "Access control for flash sector (offset range 0x11_0000 - 0x11_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits12-14", + "name": "ACL_SEC_35", + "description": "Access control for flash sector. (offset range 0x11_8000 - 0x11_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits16-18", + "name": "ACL_SEC_36", + "description": "Access control for flash sector (offset range 0x12_0000 - 0x12_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits20-22", + "name": "ACL_SEC_37", + "description": "Access control for flash sector (offset range 0x12_8000 - 0x12_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits24-26", + "name": "ACL_SEC_38", + "description": "Access control for flash sector (offset range 0x13_0000 - 0x13_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D0-bits28-30", + "name": "ACL_SEC_39", + "description": "Access control for flash sector (offset range 0x13_8000 - 0x13_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D4", + "name": "FLASH_ACL_40_47", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00D4", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0D4-bits0-2", + "name": "ACL_SEC_40", + "description": "Access control for flash sector (offset range 0x14_0000 - 0x14_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits4-6", + "name": "ACL_SEC_41", + "description": "Access control for flash sector (offset range 0x14_8000 - 0x14_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits8-10", + "name": "ACL_SEC_42", + "description": "Access control for flash sector (offset range 0x15_0000 - 0x15_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits12-14", + "name": "ACL_SEC_43", + "description": "Access control for flash sector. (offset range 0x15_8000 - 0x15_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits16-18", + "name": "ACL_SEC_44", + "description": "Access control for flash sector (offset range 0x16_0000 - 0x16_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits20-22", + "name": "ACL_SEC_45", + "description": "Access control for flash sector (offset range 0x16_8000 - 0x16_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits24-26", + "name": "ACL_SEC_46", + "description": "Access control for flash sector (offset range 0x17_0000 - 0x17_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D4-bits28-30", + "name": "ACL_SEC_47", + "description": "Access control for flash sector (offset range 0x17_8000 - 0x17_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0D8", + "name": "FLASH_ACL_48_55", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00D8", + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0D8-bits0-2", + "name": "ACL_SEC_48", + "description": "Access control for flash sector (offset range 0x18_0000 - 0x18_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits4-6", + "name": "ACL_SEC_49", + "description": "Access control for flash sector (offset range 0x18_8000 - 0x18_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits8-10", + "name": "ACL_SEC_50", + "description": "Access control for flash sector (offset range 0x19_0000 - 0x19_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits12-14", + "name": "ACL_SEC_51", + "description": "Access control for flash sector. (offset range 0x19_8000 - 0x19_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits16-18", + "name": "ACL_SEC_52", + "description": "Access control for flash sector (offset range 0x1A_0000 - 0x1A_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits20-22", + "name": "ACL_SEC_53", + "description": "Access control for flash sector (offset range 0x1A_8000 - 0x1A_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits24-26", + "name": "ACL_SEC_54", + "description": "Access control for flash sector (offset range 0x1B_0000 - 0x1B_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0D8-bits28-30", + "name": "ACL_SEC_55", + "description": "Access control for flash sector (offset range 0x1B_8000 - 0x1B_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "field0DC", + "name": "FLASH_ACL_56_63", + "description": "Access control for flash sector .Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. - If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. - 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) - If current sector ACL value is 0, 4, or 5 then any new value is permitted.", + "offset_int": "0x00DC", + "deprecated_names": [ + "FLASH_ACL_55_63" + ], + "default_value_int": "0x44444444", + "bitfields": [ + { + "width": 3, + "id": "field0DC-bits0-2", + "name": "ACL_SEC_56", + "description": "Access control for flash sector (offset range 0x1C_0000 - 0x1C_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits4-6", + "name": "ACL_SEC_57", + "description": "Access control for flash sector (offset range 0x1C_8000 - 0x1C_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits8-10", + "name": "ACL_SEC_58", + "description": "Access control for flash sector (offset range 0x1D_0000 - 0x1D_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits12-14", + "name": "ACL_SEC_59", + "description": "Access control for flash sector. (offset range 0x1D_8000 - 0x1D_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits16-18", + "name": "ACL_SEC_60", + "description": "Access control for flash sector (offset range 0x1E_0000 - 0x1E_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)1" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits20-22", + "name": "ACL_SEC_61", + "description": "Access control for flash sector (offset range 0x1E_8000 - 0x1E_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits24-26", + "name": "ACL_SEC_62", + "description": "Access control for flash sector (offset range 0x1F_0000 - 0x1F_7FFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field0DC-bits28-30", + "name": "ACL_SEC_63", + "description": "Access control for flash sector (offset range 0x1F_8000 - 0x1F_FFFF). Select one of the 8 pre-defined access control attributes for the given sector. Access attributes control read, write and execute access along with sticky lock protection. After a locked access level is selected, the sub-sequent updates of this field can be done with higher lock level only. \u2022 If current sector ACL value (GLBACn index) is greater than the new value, then it is permitted except if the new value is 4 or 5. \u25cb 7 (___L) > 6 (__XL) > 3 (R__L) > 2 (R_XL) > 1 (RW_L) > 0 (RWX_) \u2022 If current sector ACL value is 0, 4, or 5 then any new value is permitted", + "values": [ + { + "name": "DEFAULT_RW_UNLOCKED", + "value": 0, + "description": "Default flash memory behavior (R/W unlocked)" + }, + { + "name": "DATA_RW_LOCKED", + "value": 1, + "description": "R/W + locked" + }, + { + "name": "ROM_RX_LOCKED", + "value": 2, + "description": "RX + locked" + }, + { + "name": "DATA_ROM_LOCKED", + "value": 3, + "description": "ROM + locked" + }, + { + "name": "ROM_RX_UNLOCKED", + "value": 4, + "description": "RX unlocked" + }, + { + "name": "XOM_UNLOCKED", + "value": 5, + "description": "XOM unlocked" + }, + { + "name": "XOM_LOCKED", + "value": 6, + "description": "XOM + locked" + }, + { + "name": "NO_ACCESS_LOCKED", + "value": 7, + "description": "Hidden (no access + locked)" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "IMG_CMAC", + "description": "Image CMAC fields" + }, + "registers": [ + { + "id": "field0E0", + "name": "IMG0_CMAC0", + "description": "Die unique CMAC[31:0] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0E4", + "name": "IMG0_CMAC1", + "description": "Die unique CMAC[63:32] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0E8", + "name": "IMG0_CMAC2", + "description": "Die unique CMAC[95:64] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00E8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0EC", + "name": "IMG0_CMAC3", + "description": "Die unique CMAC[127:96] of image 0. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 0 range when IMG_UPD field is set to 2b'01. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F0", + "name": "IMG1_CMAC0", + "description": "Die unique CMAC[31:0] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F4", + "name": "IMG1_CMAC1", + "description": "Die unique CMAC[63:32] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0F8", + "name": "IMG1_CMAC2", + "description": "Die unique CMAC[95:64] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field0FC", + "name": "IMG1_CMAC3", + "description": "Die unique CMAC[127:96] of image 1. This field is managed by ROM and user application should not modify it. ROM calculates and stores die specific CMAC for image 1 range when IMG_UPD field is set to 2b'10. ROM calculates image CMAC only if the image passes ECDSA authentication check. On sub-sequent boots image authentication done using CMAC, based on SECURE_BOOT_CFG setting.", + "offset_int": "0x00FC", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "DICE", + "description": "DICE certificate" + }, + "registers": [ + { + "id": "field100", + "name": "DICE_Certificate0", + "description": "DICE Certificate register", + "offset_int": "0x0100", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits0-7", + "name": "X_COORD_PUB_KEY_QX_31", + "deprecated_names": [ + "X coordinate of public key Qx[31]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits8-15", + "name": "X_COORD_PUB_KEY_QX_30", + "deprecated_names": [ + "X coordinate of public key Qx[30]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits16-23", + "name": "X_COORD_PUB_KEY_QX_29", + "deprecated_names": [ + "X coordinate of public key Qx[29]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field100-bits24-31", + "name": "X_COORD_PUB_KEY_QX_28", + "deprecated_names": [ + "X coordinate of public key Qx[28]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field104", + "name": "DICE_Certificate1", + "description": "DICE Certificate register", + "offset_int": "0x0104", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits0-7", + "name": "X_COORD_PUB_KEY_QX_27", + "deprecated_names": [ + "X coordinate of public key Qx[27]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits8-15", + "name": "X_COORD_PUB_KEY_QX_26", + "deprecated_names": [ + "X coordinate of public key Qx[26]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits16-23", + "name": "X_COORD_PUB_KEY_QX_25", + "deprecated_names": [ + "X coordinate of public key Qx[25]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field104-bits24-31", + "name": "X_COORD_PUB_KEY_QX_24", + "deprecated_names": [ + "X coordinate of public key Qx[24]" + ], + "description": "X coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field108", + "name": "DICE_Certificate2", + "description": "DICE Certificate register", + "offset_int": "0x0108", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits0-7", + "name": "X_COORD_PUB_KEY_QX_23", + "deprecated_names": [ + "X coordinate of public key Qx[23]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field108-bits8-15", + "name": "X_COORD_PUB_KEY_QX_22", + "deprecated_names": [ + "X coordinate of public key Qx[22]" + ], + "description": "X coordinate of ECDSA P-256 public key" + }, + { + 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+ "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_30", + "deprecated_names": [ + "Y coordinate of public key Qy[30]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_29", + "deprecated_names": [ + "Y coordinate of public key Qy[29]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field120-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_28", + "deprecated_names": [ + "Y coordinate of public key Qy[28]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field124", + "name": "DICE_Certificate9", + "description": "DICE Certificate register", + "offset_int": "0x0124", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_27", + 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"field128-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_23", + "deprecated_names": [ + "Y coordinate of public key Qy[23]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_22", + "deprecated_names": [ + "Y coordinate of public key Qy[22]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_21", + "deprecated_names": [ + "Y coordinate of public key Qy[21]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field128-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_20", + "deprecated_names": [ + "Y coordinate of public key Qy[20]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field12C", + "name": "DICE_Certificate11", + "description": "DICE Certificate register", + "offset_int": "0x012C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_19", + "deprecated_names": [ + "Y coordinate of public key Qy[19]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_18", + "deprecated_names": [ + "Y coordinate of public key Qy[18]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_17", + "deprecated_names": [ + "Y coordinate of public key Qy[17]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field12C-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_16", + "deprecated_names": [ + "Y coordinate of public key Qy[16]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field130", + "name": "DICE_Certificate12", + "description": "DICE Certificate register", + "offset_int": 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"description": "DICE Certificate register", + "offset_int": "0x0134", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_11", + "deprecated_names": [ + "Y coordinate of public key Qy[11]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_10", + "deprecated_names": [ + "Y coordinate of public key Qy[10]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_9", + "deprecated_names": [ + "Y coordinate of public key Qy[9]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field134-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_8", + "deprecated_names": [ + "Y coordinate of public key Qy[8]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field138", + "name": "DICE_Certificate14", + "description": "DICE Certificate register", + "offset_int": "0x0138", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_7", + "deprecated_names": [ + "Y coordinate of public key Qy[7]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_6", + "deprecated_names": [ + "Y coordinate of public key Qy[6]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_5", + "deprecated_names": [ + "Y coordinate of public key Qy[5]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field138-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_4", + "deprecated_names": [ + "Y coordinate of public key Qy[4]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + } + ] + }, + { + "id": "field13C", + "name": "DICE_Certificate15", + "description": "DICE Certificate register", + "offset_int": "0x013C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits0-7", + "name": "Y_COORD_PUB_KEY_QY_3", + "deprecated_names": [ + "Y coordinate of public key Qy[3]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits8-15", + "name": "Y_COORD_PUB_KEY_QY_2", + "deprecated_names": [ + "Y coordinate of public key Qy[2]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits16-23", + "name": "Y_COORD_PUB_KEY_QY_1", + "deprecated_names": [ + "Y coordinate of public key Qy[1]" + ], + "description": "Y coordinate of ECDSA P-256 public key" + }, + { + "width": 8, + "id": "field13C-bits24-31", + "name": "Y_COORD_PUB_KEY_QY_0", + "deprecated_names": [ + "Y coordinate of public key Qy[0]" + ], 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register", + "offset_int": "0x014C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits0-7", + "name": "ECDSA_SIG_R_19", + "deprecated_names": [ + "ECDSA_SIG_R[19]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field14C-bits8-15", + "name": "ECDSA_SIG_R_18", + "deprecated_names": [ + "ECDSA_SIG_R[18]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field14C-bits16-23", + "name": "ECDSA_SIG_R_17", + "deprecated_names": [ + "ECDSA_SIG_R[17]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field14C-bits24-31", + "name": "ECDSA_SIG_R_16", + "deprecated_names": [ + "ECDSA_SIG_R[16]" + ], + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field150", + "name": "DICE_Certificate20", + "description": "DICE Certificate register", + "offset_int": "0x0150", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits0-7", + "name": "ECDSA_SIG_R_15", + "deprecated_names": [ + "ECDSA_SIG_R[15]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits8-15", + "name": "ECDSA_SIG_R_14", + "deprecated_names": [ + "ECDSA_SIG_R[14]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits16-23", + "name": "ECDSA_SIG_R_13", + "deprecated_names": [ + "ECDSA_SIG_R[13]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field150-bits24-31", + "name": "ECDSA_SIG_R_12", + "deprecated_names": [ + "ECDSA_SIG_R[12]" + ], + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field154", + "name": "DICE_Certificate21", + "description": "DICE Certificate register", + "offset_int": "0x0154", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits0-7", + "name": "ECDSA_SIG_R_11", + "deprecated_names": [ + "ECDSA_SIG_R[11]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field154-bits8-15", + "name": "ECDSA_SIG_R_10", + "deprecated_names": [ + "ECDSA_SIG_R[10]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field154-bits16-23", + "name": "ECDSA_SIG_R_9", + "deprecated_names": [ + "ECDSA_SIG_R[9]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field154-bits24-31", + "name": "ECDSA_SIG_R_8", + "deprecated_names": [ + "ECDSA_SIG_R[8]" + ], + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field158", + "name": "DICE_Certificate22", + "description": "DICE Certificate register", + "offset_int": "0x0158", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits0-7", + "name": "ECDSA_SIG_R_7", + "deprecated_names": [ + "ECDSA_SIG_R[7]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field158-bits8-15", + "name": "ECDSA_SIG_R_6", + "deprecated_names": [ + "ECDSA_SIG_R[6]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field158-bits16-23", + "name": "ECDSA_SIG_R_5", + "deprecated_names": [ + "ECDSA_SIG_R[5]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field158-bits24-31", + "name": "ECDSA_SIG_R_4", + "deprecated_names": [ + "ECDSA_SIG_R[4]" + ], + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field15C", + "name": "DICE_Certificate23", + "description": "DICE Certificate register", + "offset_int": "0x015C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits0-7", + "name": "ECDSA_SIG_R_3", + "deprecated_names": [ + "ECDSA_SIG_R[3]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field15C-bits8-15", + "name": "ECDSA_SIG_R_2", + "deprecated_names": [ + "ECDSA_SIG_R[2]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field15C-bits16-23", + "name": "ECDSA_SIG_R_1", + "deprecated_names": [ + "ECDSA_SIG_R[1]" + ], + "description": "R component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field15C-bits24-31", + "name": "ECDSA_SIG_R_0", + "deprecated_names": [ + "ECDSA_SIG_R[0]" + ], + "description": "R component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field160", + "name": "DICE_Certificate24", + "description": "DICE Certificate register", + "offset_int": "0x0160", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits0-7", + "name": "ECDSA_SIG_S_31", + "deprecated_names": [ + "ECDSA_SIG_S[31]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits8-15", + "name": "ECDSA_SIG_S_30", + "deprecated_names": [ + "ECDSA_SIG_S[30]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits16-23", + "name": "ECDSA_SIG_S_29", + "deprecated_names": [ + "ECDSA_SIG_S[29]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field160-bits24-31", + "name": "ECDSA_SIG_S_28", + "deprecated_names": [ + "ECDSA_SIG_S[28]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field164", + "name": "DICE_Certificate25", + "description": "DICE Certificate register", + "offset_int": "0x0164", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits0-7", + "name": "ECDSA_SIG_S_27", + "deprecated_names": [ + "ECDSA_SIG_S[27]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field164-bits8-15", + "name": "ECDSA_SIG_S_26", + "deprecated_names": [ + "ECDSA_SIG_S[26]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field164-bits16-23", + "name": "ECDSA_SIG_S_25", + "deprecated_names": [ + "ECDSA_SIG_S[25]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field164-bits24-31", + "name": "ECDSA_SIG_S_24", + "deprecated_names": [ + "ECDSA_SIG_S[24]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field168", + "name": "DICE_Certificate26", + "description": "DICE Certificate register", + "offset_int": "0x0168", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits0-7", + "name": "ECDSA_SIG_S_23", + "deprecated_names": [ + "ECDSA_SIG_S[23]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field168-bits8-15", + "name": "ECDSA_SIG_S_22", + "deprecated_names": [ + "ECDSA_SIG_S[22]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field168-bits16-23", + "name": "ECDSA_SIG_S_21", + "deprecated_names": [ + "ECDSA_SIG_S[21]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field168-bits24-31", + "name": "ECDSA_SIG_S_20", + "deprecated_names": [ + "ECDSA_SIG_S[20]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field16C", + "name": "DICE_Certificate27", + "description": "DICE Certificate register", + "offset_int": "0x016C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits0-7", + "name": "ECDSA_SIG_S_19", + "deprecated_names": [ + "ECDSA_SIG_S[19]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field16C-bits8-15", + "name": "ECDSA_SIG_S_18", + "deprecated_names": [ + "ECDSA_SIG_S[18]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field16C-bits16-23", + "name": "ECDSA_SIG_S_17", + "deprecated_names": [ + "ECDSA_SIG_S[17]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field16C-bits24-31", + "name": "ECDSA_SIG_S_16", + "deprecated_names": [ + "ECDSA_SIG_S[16]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field170", + "name": "DICE_Certificate28", + "description": "DICE Certificate register", + "offset_int": "0x0170", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits0-7", + "name": "ECDSA_SIG_S_15", + "deprecated_names": [ + "ECDSA_SIG_S[15]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits8-15", + "name": "ECDSA_SIG_S_14", + "deprecated_names": [ + "ECDSA_SIG_S[14]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits16-23", + "name": "ECDSA_SIG_S_13", + "deprecated_names": [ + "ECDSA_SIG_S[13]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field170-bits24-31", + "name": "ECDSA_SIG_S_12", + "deprecated_names": [ + "ECDSA_SIG_S[12]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field174", + "name": "DICE_Certificate29", + "description": "DICE Certificate register", + "offset_int": "0x0174", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits0-7", + "name": "ECDSA_SIG_S_11", + "deprecated_names": [ + "ECDSA_SIG_S[11]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field174-bits8-15", + "name": "ECDSA_SIG_S_10", + "deprecated_names": [ + "ECDSA_SIG_S[10]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field174-bits16-23", + "name": "ECDSA_SIG_S_9", + "deprecated_names": [ + "ECDSA_SIG_S[9]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field174-bits24-31", + "name": "ECDSA_SIG_S_8", + "deprecated_names": [ + "ECDSA_SIG_S[8]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field178", + "name": "DICE_Certificate30", + "description": "DICE Certificate register", + "offset_int": "0x0178", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits0-7", + "name": "ECDSA_SIG_S_7", + "deprecated_names": [ + "ECDSA_SIG_S[7]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field178-bits8-15", + "name": "ECDSA_SIG_S_6", + "deprecated_names": [ + "ECDSA_SIG_S[6]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field178-bits16-23", + "name": "ECDSA_SIG_S_5", + "deprecated_names": [ + "ECDSA_SIG_S[5]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field178-bits24-31", + "name": "ECDSA_SIG_S_4", + "deprecated_names": [ + "ECDSA_SIG_S[4]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + }, + { + "id": "field17C", + "name": "DICE_Certificate31", + "description": "DICE Certificate register", + "offset_int": "0x017C", + "access": "RO", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits0-7", + "name": "ECDSA_SIG_S_3", + "deprecated_names": [ + "ECDSA_SIG_S[3]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field17C-bits8-15", + "name": "ECDSA_SIG_S_2", + "deprecated_names": [ + "ECDSA_SIG_S[2]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field17C-bits16-23", + "name": "ECDSA_SIG_S_1", + "deprecated_names": [ + "ECDSA_SIG_S[1]" + ], + "description": "S component of ECDSA P-256 signature" + }, + { + "width": 8, + "id": "field17C-bits24-31", + "name": "ECDSA_SIG_S_0", + "deprecated_names": [ + "ECDSA_SIG_S[0]" + ], + "description": "S component of ECDSA P-256 signature" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00180-0018C", + "description": "Reserved 00180-0018C" + }, + "registers": [ + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED GCM AAD context configuration" + }, + "registers": [ + { + "id": "field190", + "name": "IPED_GCM_AAD_CTX0", + "description": "Additional Authentication Data for IPED context 0. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x0190", + "default_value_int": "0" + }, + { + "id": "field194", + "name": "IPED_GCM_AAD_CTX1", + "description": "Additional Authentication Data for IPED context 1. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x0194", + "default_value_int": "0" + }, + { + "id": "field198", + "name": "IPED_GCM_AAD_CTX2", + "description": "Additional Authentication Data for IPED context 2. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x0198", + "default_value_int": "0" + }, + { + "id": "field19C", + "name": "IPED_GCM_AAD_CTX3", + "description": "Additional Authentication Data for IPED context 3. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x019C", + "default_value_int": "0" + }, + { + "id": "field1A0", + "name": "IPED_GCM_AAD_CTX4", + "description": "Additional Authentication Data for IPED context 4. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x01A0", + "default_value_int": "0" + }, + { + "id": "field1A4", + "name": "IPED_GCM_AAD_CTX5", + "description": "Additional Authentication Data for IPED context 5. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x01A4", + "default_value_int": "0" + }, + { + "id": "field1A8", + "name": "IPED_GCM_AAD_CTX6", + "description": "Additional Authentication Data for IPED context 6. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x01A8", + "default_value_int": "0" + }, + { + "id": "field1AC", + "name": "IPED_GCM_AAD_CTX7", + "description": "Additional Authentication Data for IPED context 7. Use CRC32 value of any un-encrypted data associated with this context.", + "offset_int": "0x01AC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 001B0-001E8", + "description": "Reserved 001B0-001E8" + }, + "registers": [ + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC - CMAC", + "description": "CRC32 and CMAC CFPA securing" + }, + "registers": [ + { + "id": "field1EC", + "name": "CFPA_CRC32", + "description": "CRC32 of CFPA page data from offset . ROM updates this field along with CFPA_CMAC on subsequent boot after page update. ROM uses this field based on CMPA.LP_SEC_BOOT field option.", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F0", + "name": "CFPA0_CMAC0", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CFPA0_CMAC1", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CFPA0_CMAC2", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CFPA0_CMAC3", + "description": "CMAC[31:0] of CFPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a0.json new file mode 100644 index 0000000..c7b8844 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a0.json @@ -0,0 +1,4368 @@ +{ + "cpu": "MCXN946", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field000-bits0-1", + "name": "DEFAULT_BOOT_SOURCE", + "description": "Primary boot source", + "values": [ + { + "name": "INTERNAL_FLASH_0b00", + "value": 0, + "description": "Internal flash" + }, + { + "name": "FLEXSPI_FLASH_XIP", + "value": 1, + "description": "FlexSPI-A flash XIP image" + }, + { + "name": "SECONDARY_BOOT_LOADE", + "value": 2, + "description": "SECONDARY_BOOT_LOADER_0b10: Secondary Boot loader in Bank1 IFR0 (32KB)" + }, + { + "name": "INTERNAL_FLASH_0b11", + "value": 3, + "description": "Internal flash" + } + ] + }, + { + "width": 2 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_INTERFACE", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0_HID" + }, + { + "name": "USB1_HID", + "value": 5, + "description": "USB1_HID" + }, + { + "name": "CAN_ISP", + "value": 6, + "description": "CAN ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits8-9", + "name": "RECOVERY_BOOT_SOURCE", + "description": "Recovery boot source", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Recovery boot disabled" + }, + { + "name": "XIP_IMAGE", + "value": 1, + "description": "XIP image in Bank1 IFR0 (32KB)" + }, + { + "name": "SB3_IMAGE", + "value": 2, + "description": "SB3 image in 1-bit SPI flash connected to FlexComm overlapped with FlexSPI A" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "CORE_CLOCK", + "description": "Core Clock", + "values": [ + { + "name": "MHZ48_FRO", + "value": 0, + "description": "48Mhz FRO @1v0" + }, + { + "name": "MHZ72_FRO", + "value": 1, + "description": "72MHz FRO @1v0" + }, + { + "name": "MHZ144_FRO", + "value": 2, + "description": "144MHz FRO @1v0" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "RO", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SZ", + "description": "Flash remap size.This field should be written to remap field in flash." + }, + { + "width": 3, + "id": "field004-bits5-7", + "name": "OEM_BANK1_IFR0_PROT", + "description": "Defines protection for Bank1_IFR0.Set RWXL = 1010 when jumping to Bank1_IFR0 address.", + "values": [ + { + "name": "RWXL_1010", + "value": 0, + "description": "Set to RWXL = 1010 on user image exit." + }, + { + "name": "RWXL_1011", + "value": 1, + "description": "Set to RWXL = 1011 on user image exit." + }, + { + "name": "RWXL_0011", + "value": 2, + "description": "Set to RWXL = 0011 on user image exit." + }, + { + "name": "RWXL_0001", + "value": 3, + "description": "Set to RWXL = 0001 on user image exit." + } + ] + }, + { + "width": 2, + "id": "field004-bits8-9", + "name": "ISP_FT_ENTRY", + "description": "Authentication failure", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command.", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0b00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0b10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0b11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "BOOT_LED_STATUS", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "REC_BOOT_LED", + "description": "Assert on recovery boot. ROM drives the GPIO pin identified by this field whenever primary boot fails and fall through to recovery boot source." + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin identified by this field whenever primary boot fails and execution falls through to ISP mode." + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. ROM toggles the GPIO pin identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. Note, use QUICK_SET_/CLR_GPIOx field to set the default level of pin." + }, + { + "width": 8 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "BOOT_TIMERS", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout:Timeout value in seconds. When a non-zero value is programmed in this field ROM uses it as idle timeout value to enter power-down state to conserve power." + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_COUNT", + "description": "WDOG timeout:Upper 16 bits of 24-bit count value in WWDT_TC register Timeout value in seconds. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code." + } + ] + }, + { + "id": "field010", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FLEXSPI_BOOT_CFG0", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "FLEXSPI_AUTO_PROBE", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field010-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type.", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIC_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field010-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI_ADDR_3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER_1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER_3V3" + }, + { + "name": "DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field010-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command." + }, + { + "width": 3, + "id": "field010-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Q/O-SPI flash interface frequency.", + "values": [ + { + "name": "MHZ_50", + "value": 0, + "description": "50Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60Mhz" + }, + { + "name": "MHZ_80", + "value": 2, + "description": "80Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100Mhz" + }, + { + "name": "MHZ_120", + "value": 4, + "description": "120Mhz" + }, + { + "name": "MHZ_133", + "value": 5, + "description": "133Mhz" + }, + { + "name": "MHZ_166", + "value": 6, + "description": "166Mhz" + }, + { + "name": "MHZ_200", + "value": 7, + "description": "200Mhz" + } + ] + }, + { + "width": 1, + "id": "field010-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use QSPI_RESET_PIN to reset the flash device.", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available" + }, + { + "name": "EN_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN)" + } + ] + }, + { + "width": 3, + "id": "field010-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "GPIO port number to use for O/QSPI reset function" + }, + { + "width": 5, + "id": "field010-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "GPIO pin number to use for O/QSPI reset function" + }, + { + "width": 2, + "id": "field010-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "Wait time before access to Serial Flash.", + "values": [ + { + "name": "WAIT_500US", + "value": 0, + "description": "Wait for 500 micro seconds." + }, + { + "name": "WAIT_1MS", + "value": 1, + "description": "Wait for 1 mili seconds." + }, + { + "name": "WAIT_3MS", + "value": 2, + "description": "Wait for 3 mili seconds." + }, + { + "name": "WAIT_10MS", + "value": 3, + "description": "Wait for 10 mili seconds." + } + ] + }, + { + "width": 4, + "id": "field010-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100US", + "value": 1, + "description": "Waits additional 100 micro-seconds." + }, + { + "name": "WAIT_500US", + "value": 2, + "description": "Waits additional 500 micro-seconds." + }, + { + "name": "WAIT_1MS", + "value": 3, + "description": "Waits additional 1 mili-seconds." + }, + { + "name": "WAIT_10MS", + "value": 4, + "description": "Waits additional 10 mili-seconds." + }, + { + "name": "WAIT_20MS", + "value": 5, + "description": "Waits additional 20 mili-seconds." + }, + { + "name": "WAIT_40MS", + "value": 6, + "description": "Waits additional 40 mili-seconds." + }, + { + "name": "WAIT_60MS", + "value": 7, + "description": "Waits additional 60 mili-seconds." + }, + { + "name": "WAIT_80MS", + "value": 8, + "description": "Waits additional 80 mili-seconds." + }, + { + "name": "WAIT_100MS", + "value": 9, + "description": "Waits additional 100 mili-seconds." + }, + { + "name": "WAIT_120MS", + "value": 10, + "description": "Waits additional 120 mili-seconds." + }, + { + "name": "WAIT_140MS", + "value": 11, + "description": "Waits additional 140 mili-seconds." + }, + { + "name": "WAIT_160MS", + "value": 12, + "description": "Waits additional 160 mili-seconds." + }, + { + "name": "WAIT_180MS", + "value": 13, + "description": "Waits additional 180 mili-seconds." + }, + { + "name": "WAIT_200MS", + "value": 14, + "description": "Waits additional 200 mili-seconds." + }, + { + "name": "WAIT_220MS", + "value": 15, + "description": "Waits additional 220 mili-seconds." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit31", + "name": "PORT_SEL", + "description": "Defined which FlexSPI portA/B is used for boot.", + "values": [ + { + "name": "PORT_A", + "value": 0, + "description": "PORT A" + }, + { + "name": "PORT_B", + "value": 1, + "description": "PORT B" + } + ] + } + ] + }, + { + "id": "field014", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FLEXSPI_BOOT_CFG1", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 7, + "id": "field014-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS)" + }, + { + "width": 10, + "id": "field014-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "Any offset in memory mapped Q/Octal-SPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset." + }, + { + "width": 4, + "id": "field014-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped QSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "Remap size = FLEXSPI_IMAGE_OFFSET * 256KByte;" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "SIZE_1MB Size of remapped area is 1MByte" + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "SIZE_2MB Size of remapped area is 2MByte" + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "SIZE_3MB Size of remapped area is 3MByte" + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "SIZE_4MB Size of remapped area is 4MByte" + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "SIZE_5MB Size of remapped area is 5MByte" + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "SIZE_6MB Size of remapped area is 6MByte" + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "SIZE_7MB Size of remapped area is 7MByte" + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "SIZE_8MB Size of remapped area is 8MByte" + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "SIZE_9MB Size of remapped area is 9MByte" + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "SIZE_10MB Size of remapped area is 10MByte" + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "SIZE_11MB Size of remapped area is 11MByte" + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "SIZE_12MB Size of remapped area is 12MByte" + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "SIZE_256KB Size of remapped area is 256KByte" + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "SIZE_512KB Size of remapped area is 512KByte" + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "SIZE_768KB Size of remapped area is 768KByte" + } + ] + }, + { + "width": 11 + } + ] + }, + { + "id": "field018", + "name": "REC_SPI_FLASH_CFG0", + "description": "REC_SPI_FLASH_CFG0", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field018-bits0-7", + "name": "REC_SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin.Identifies the pin to be used as SPI_SCK pin." + }, + { + "width": 4, + "id": "field018-bits8-11", + "name": "REC_SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field018-bits12-15", + "name": "REC_SPI_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field018-bits16-23", + "name": "REC_SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin" + }, + { + "width": 4, + "id": "field018-bits24-27", + "name": "REC_SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "field01C", + "name": "REC_SPI_FLASH_CFG1", + "description": "REC_SPI_FLASH_CFG1", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "REC_SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "REC_SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "REC_SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin." + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "REC_SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 2, + "id": "field01C-bits28-29", + "name": "REC_SPI_SSEL_X", + "description": "SPI chip select number." + }, + { + "width": 2 + } + ] + }, + { + "id": "field020", + "name": "ISP_UART_CFG", + "description": "ISP_UART_CFG", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin." + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field020-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode." + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin." + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field020-bits28-31", + "name": "UART_BAUD_RATE", + "description": "UART baud rate.Baud rate configured during UART ISP mode.", + "values": [ + { + "name": "AUTO_BAUD_DETECTION", + "value": 0, + "description": "Auto baud detection." + } + ] + } + ] + }, + { + "id": "field024", + "name": "ISP_I2C_CFG", + "description": "ISP_I2C_CFG", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field024-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin." + }, + { + "width": 4, + "id": "field024-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field024-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for I2C ISP mode" + }, + { + "width": 8, + "id": "field024-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin" + }, + { + "width": 4, + "id": "field024-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "field028", + "name": "ISP_CAN_CFG", + "description": "ISP_CAN_CFG", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "CAN_RX_PIN", + "description": "Override default CAN RX ISP pin." + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "CAN_RX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field028-bits12-15", + "name": "CAN_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for CAN ISP mode." + }, + { + "width": 8, + "id": "field028-bits16-23", + "name": "CAN_TX_PIN", + "description": "Override default CAN TX ISP pin." + }, + { + "width": 4, + "id": "field028-bits24-27", + "name": "CAN_TX_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4, + "id": "field028-bits28-31", + "name": "CAN_BAUD_RATE", + "description": "CAN baud rate.Baud rate configured during CAN ISP mode. Default: Auto baud detection.", + "values": [ + { + "name": "AUTO_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 1M)" + }, + { + "name": "KBPS_10", + "value": 1, + "description": "10 kbps" + }, + { + "name": "KBPS_20", + "value": 2, + "description": "20 kbps" + }, + { + "name": "KBPS_50", + "value": 3, + "description": "50 kbps" + }, + { + "name": "KBPS_125", + "value": 4, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 5, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 6, + "description": "500 kbps" + }, + { + "name": "KBPS_800", + "value": 7, + "description": "800 kbps" + }, + { + "name": "KBPS_1000", + "value": 8, + "description": "1,000 kbps" + } + ] + } + ] + }, + { + "id": "field02C", + "name": "ISP_SPI_CFG0", + "description": "ISP_SPI_CFG0", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI SCK ISP pin." + }, + { + "width": 4, + "id": "field02C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4, + "id": "field02C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field02C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI MOSI ISP pin" + }, + { + "width": 4, + "id": "field02C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 4 + } + ] + }, + { + "id": "field030", + "name": "ISP_SPI_CFG1", + "description": "ISP_SPI_CFG1", + "offset_int": "0x0030", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field030-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI MISO ISP pin." + }, + { + "width": 4, + "id": "field030-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field030-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI SSEL ISP pin" + }, + { + "width": 4, + "id": "field030-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the pin mux function slot." + }, + { + "width": 2, + "id": "field030-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number." + }, + { + "width": 2 + } + ] + }, + { + "id": "field034", + "name": "ISP_USB_ID", + "description": "ISP_USB_ID", + "offset_int": "0x0034", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field034-bits0-15", + "name": "USB_Vendor_ID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "field034-bits16-31", + "name": "USB_Product_ID", + "description": "USB Product ID" + } + ] + }, + { + "id": "field038", + "name": "ISP_USB_CFG", + "description": "ISP_USB_CFG", + "offset_int": "0x0038", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field038-bits0-7", + "name": "USB0_VBUS_PIN", + "description": "Override default USB VBUS MISO ISP pin." + }, + { + "width": 4, + "id": "field038-bits8-11", + "name": "USB0_VBUS_FUNC_SLOT", + "description": "Identifies the pin mux function slot" + }, + { + "width": 4 + }, + { + "width": 3, + "id": "field038-bits16-18", + "name": "EXT_XTAL_CLK", + "description": "USB PHY input clock frequency. For USB high speed PHY external XTAL input is needed. This field specifies the frequency of XTAL used on board.", + "values": [ + { + "name": "XTAL_32MHZ", + "value": 0, + "description": "32MHz input clock (Divide by 15)" + }, + { + "name": "XTAL_30MHZ", + "value": 1, + "description": "30MHz input clock (Divide by 16)" + }, + { + "name": "XTAL_20MHZ", + "value": 4, + "description": "20MHz input clock (Divide by 24)" + }, + { + "name": "XTAL_19_2MHZ", + "value": 5, + "description": "19.2MHz input clock (Divide by 25)" + }, + { + "name": "XTAL_16MHZ", + "value": 6, + "description": "16MHz input clock (Divide by 30)" + }, + { + "name": "XTAL_12MHZ", + "value": 7, + "description": "12MHz input clock (Divide by 40) " + } + ] + }, + { + "width": 1, + "id": "field038-bit19", + "name": "PRE_DIV", + "description": "Enable Pre-divider. Needed to support 48MHz and other high speed crystals." + }, + { + "width": 12 + } + ] + }, + { + "id": "field03C", + "name": "ISP_MISC_CFG", + "description": "ISP_MISC_CFG", + "offset_int": "0x003C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 8, + "id": "field03C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address. A 7-bit Address used for selecting our device on shared I2C bus system.By default ROM uses 0x10 as slave address." + }, + { + "width": 16 + }, + { + "width": 2, + "id": "field03C-bits24-25", + "name": "ISP_CAN_CUST", + "description": "Use customer defined CAN ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins.", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined." + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + }, + { + "id": "field040", + "name": "DCFG_CC_SOCU_PIN", + "description": "Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0040", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field040-bit0", + "name": "NIDEN", + "description": "Non-secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field040-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Boot Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Disable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 1, + "id": "field040-bit15", + "name": "UUID_CHECK", + "description": "UUID Check" + }, + { + "width": 16, + "id": "field040-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field044", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0044", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field044-bit0", + "name": "NIDEN", + "description": "Non Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit1", + "name": "DBGEN", + "description": "Non-secure Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit2", + "name": "SPNIDEN", + "description": "Secure Non-invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit3", + "name": "SPIDEN", + "description": "Secure Invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field044-bit5", + "name": "DSP_DBGEN", + "description": "DSP Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit6", + "name": "ISP_CMD_EN", + "description": "ISP Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 5 + }, + { + "width": 16, + "id": "field044-bits16-31", + "name": "INVERSE_VALUE", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field048", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0048", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field048-bits16-31", + "name": "VENDOR_USAGE", + "description": "Vendor Usage [31:16]" + } + ] + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field050", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x0050", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "SEC_BOOT_EN", + "description": "Secure boot enforcement. This field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign).", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed." + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed." + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed." + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits3-4", + "name": "LP_SEC_BOOT", + "description": "Secure boot option for low-power wake from power-down and deep-powerdown.For PFR/ROMP do CRC check always.", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for PFR and CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for PFR and jump to vector address specified in CFPA." + }, + { + "name": "CMAC_CHECK", + "value": 3, + "description": "CRC check for PFR and CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "field050-bits8-9", + "name": "ENF_CNSA", + "description": "Enforce CNSA", + "values": [ + { + "name": "ECC_P256", + "value": 0, + "description": "ECC P-256 keys" + }, + { + "name": "ECC_P384_0", + "value": 1, + "description": "ECC P-384 keys, SHA384 and AES256" + }, + { + "name": "ECC_P384_1", + "value": 2, + "description": "ECC P-384 keys, SHA384 and AES256" + }, + { + "name": "ECC_P384_2", + "value": 3, + "description": "ECC P-384 keys, SHA384 and AES256" + } + ] + }, + { + "width": 2, + "id": "field050-bits10-11", + "name": "ENF_TZM_PRESET", + "description": "Enforce TrustZone-M Preset", + "values": [ + { + "name": "IGNORE_0b00", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_0b01", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_0b10", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_0b11", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2, + "id": "field050-bits12-13", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event. Zeroize long-term storage RAM (AO_RAM) on subsequent boot when Intrusion and Tamper control signals an intrusion event.", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action." + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only." + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC and AO RAM on ITRC event only." + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC and AO RAM on all reset boot." + } + ] + }, + { + "width": 2, + "id": "field050-bits14-15", + "name": "ACTIVE_IMG_PROT", + "description": "Protection of active image. This field defines protection of flash area occupied by active image. Only applicable to internal flash.", + "values": [ + { + "name": "NO_PROTECTION", + "value": 0, + "description": "No protection after from ACL list." + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock." + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock." + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "XOM protect active image area with sticky lock. " + } + ] + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "FIPS_SHA_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits18-19", + "name": "FIPS_AES_STEN", + "description": "FIPS_AES_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "FIPS_ECDSA_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "FIPS_DRBG_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits24-25", + "name": "FIPS_CMAC_STEN", + "description": "FIPS_CMAC_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "FIPS_KDF_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2, + "id": "field050-bits28-29", + "name": "FIPS_PUF_STEN", + "description": "FIPS_PUF_STEN", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "Not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery." + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle." + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field054", + "name": "RoTK_USAGE", + "description": "Root of Trust Key Usage", + "offset_int": "0x0054", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "RoTK0_Usage", + "description": "RoTK0_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field054-bits3-5", + "name": "RoTK1_Usage", + "description": "RoTK1_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field054-bits6-8", + "name": "RoTK2_Usage", + "description": "RoTK2_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "field054-bits9-11", + "name": "RoTK3_Usage", + "description": "RoTK3_Usage", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 1, + "id": "field054-bit12", + "name": "SKIP_DICE", + "description": "Skip DICE computation.", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "field054-bit13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "Not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "Included" + } + ] + }, + { + "width": 1, + "id": "field054-bit14", + "name": "DICE_INC_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "Not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "Included" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field054-bits16-17", + "name": "REG0_ERASE_CHECK_EN", + "description": "Region 0 Erase Check Enable", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLED_0b01", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits18-19", + "name": "REG1_ERASE_CHECK_EN", + "description": "Region 1 Erase Check Enable", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLED_0b01", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits20-21", + "name": "REG2_ERASE_CHECK_EN", + "description": "Region 2 Erase Check Enable", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLED_0b01", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits22-23", + "name": "REG3_ERASE_CHECK_EN", + "description": "Region 3 Erase Check Enable", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Check is disabled" + }, + { + "name": "ENABLED_0b01", + "value": 1, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Check is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits24-25", + "name": "NPX_LOCK_CTX0", + "description": "Lock onchip flash NPX PRINCE context 0 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked. " + }, + { + "name": "LOCKED_NO_ERASE_CHEC", + "value": 1, + "description": "LOCKED_NO_ERASE_CHECK: Region is locked. But no erase check." + }, + { + "name": "LOCKED_ERASE_CHECK_EN", + "value": 2, + "description": "LOCKED_ERASE_CHECK_EN_0: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_ERASE_CHECK_EN_1", + "value": 3, + "description": "LOCKED_ERASE_CHECK_EN_1: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + }, + { + "width": 2, + "id": "field054-bits26-27", + "name": "NPX_LOCK_CTX1", + "description": "Lock onchip flash NPX PRINCE context 1 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked. " + }, + { + "name": "LOCKED_NO_ERASE_CHEC", + "value": 1, + "description": "LOCKED_NO_ERASE_CHECK: Region is locked. But no erase check." + }, + { + "name": "LOCKED_ERASE_CHECK_E", + "value": 2, + "description": "LOCKED_ERASE_CHECK_EN_0: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_ERASE_CHECK_EN_1", + "value": 3, + "description": "LOCKED_ERASE_CHECK_EN_1: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + }, + { + "width": 2, + "id": "field054-bits28-29", + "name": "NPX_LOCK_CTX2", + "description": "Lock onchip flash NPX PRINCE context 2 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked. " + }, + { + "name": "LOCKED_NO_ERASE_CHEC", + "value": 1, + "description": "LOCKED_NO_ERASE_CHECK: Region is locked. But no erase check." + }, + { + "name": "LOCKED_ERASE_CHECK_E", + "value": 2, + "description": "LOCKED_ERASE_CHECK_EN_0: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_ERASE_CHECK_EN_1", + "value": 3, + "description": "LOCKED_ERASE_CHECK_EN_1: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + }, + { + "width": 2, + "id": "field054-bits30-31", + "name": "NPX_LOCK_CTX3", + "description": "Lock onchip flash NPX PRINCE context 3 settings.", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Region is not locked. " + }, + { + "name": "LOCKED_NO_ERASE_CHEC", + "value": 1, + "description": "LOCKED_NO_ERASE_CHECK: Region is locked. But no erase check." + }, + { + "name": "LOCKED_ERASE_CHECK_E", + "value": 2, + "description": "LOCKED_ERASE_CHECK_EN_0: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + }, + { + "name": "LOCKED_ERASE_CHECK_EN_1", + "value": 3, + "description": "LOCKED_ERASE_CHECK_EN_1: Region is locked. Erase check enabled. Flash programming ROM API enforces the erase check. When erase check is enabled all sectors selected in the context should be erased together and only contiguous sectors can be selected in context bitmap." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00058-0005C", + "description": "Reserved 00058-0005C" + }, + "registers": [ + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "Root of Trust Key Hash 0", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "Root of Trust Key Hash 1", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "Root of Trust Key Hash 2", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "Root of Trust Key Hash 3", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "Root of Trust Key Hash 4", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "Root of Trust Key Hash 5", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "Root of Trust Key Hash 6", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "Root of Trust Key Hash 7", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field080", + "name": "ROTKH8", + "description": "Root of Trust Key Hash 8", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "ROTKH9", + "description": "Root of Trust Key Hash 9", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "ROTKH10", + "description": "Root of Trust Key Hash 10", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "ROTKH11", + "description": "Root of Trust Key Hash 11", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors 0 -31)", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "NPX_CTX0_WD1", + "description": "Bitmap mask for NPX Prince context 0 (sectors 32 - 63)", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors 0 -31)", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "NPX_CTX1_WD1", + "description": "Bitmap mask for NPX Prince context 1 (sectors 32 - 63)", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors 0 -31)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "NPX_CTX2_WD1", + "description": "Bitmap mask for NPX Prince context 2 (sectors 32 - 63)", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors 0 -31)", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "NPX_CTX3_WD1", + "description": "Bitmap mask for NPX Prince context 3 (sectors 32 - 63)", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED fields" + }, + "registers": [ + { + "id": "field0B0", + "name": "IPED0_START", + "description": "IPED region 0 Start", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0B0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0B0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B0-bits8-31", + "name": "IPED_CTX0_START_ADDR", + "description": "IPED_CTX0_START_ADDR" + } + ] + }, + { + "id": "field0B4", + "name": "IPED0_END", + "description": "IPED region 0 End", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0B4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B4-bits8-31", + "name": "IPED_CTX0_END_ADDR", + "description": "IPED_CTX0_END_ADDR" + } + ] + }, + { + "id": "field0B8", + "name": "IPED1_START", + "description": "IPED region 1 Start", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0B8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0B8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B8-bits8-31", + "name": "IPED_CTX1_START_ADDR", + "description": "IPED_CTX1_START_ADDR" + } + ] + }, + { + "id": "field0BC", + "name": "IPED1_END", + "description": "IPED region 1 End", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0BC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0BC-bits8-31", + "name": "IPED_CTX1_END_ADDR", + "description": "IPED_CTX1_END_ADDR" + } + ] + }, + { + "id": "field0C0", + "name": "IPED2_START", + "description": "IPED region 2 Start", + "offset_int": "0x00C0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0C0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0C0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C0-bits8-31", + "name": "IPED_CTX2_START_ADDR", + "description": "IPED_CTX2_START_ADDR" + } + ] + }, + { + "id": "field0C4", + "name": "IPED2_END", + "description": "IPED region 2 End", + "offset_int": "0x00C4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0C4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C4-bits8-31", + "name": "IPED_CTX2_END_ADDR", + "description": "IPED_CTX2_END_ADDR" + } + ] + }, + { + "id": "field0C8", + "name": "IPED3_START", + "description": "IPED region 3 Start", + "offset_int": "0x00C8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0C8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0C8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C8-bits8-31", + "name": "IPED_CTX3_START_ADDR", + "description": "IPED_CTX3_START_ADDR" + } + ] + }, + { + "id": "field0CC", + "name": "IPED3_END", + "description": "IPED region 3 End", + "offset_int": "0x00CC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0CC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0CC-bits8-31", + "name": "IPED_CTX3_END_ADDR", + "description": "IPED_CTX3_END_ADDR" + } + ] + }, + { + "id": "field0D0", + "name": "IPED4_START", + "description": "IPED region 4 Start", + "offset_int": "0x00D0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0D0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0D0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D0-bits8-31", + "name": "IPED_CTX4_START_ADDR", + "description": "IPED_CTX4_START_ADDR" + } + ] + }, + { + "id": "field0D4", + "name": "IPED4_END", + "description": "IPED region 4 End", + "offset_int": "0x00D4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0D4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D4-bits8-31", + "name": "IPED_CTX4_END_ADDR", + "description": "IPED_CTX4_END_ADDR" + } + ] + }, + { + "id": "field0D8", + "name": "IPED5_START", + "description": "IPED region 5 Start", + "offset_int": "0x00D8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0D8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0D8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D8-bits8-31", + "name": "IPED_CTX5_START_ADDR", + "description": "IPED_CTX5_START_ADDR" + } + ] + }, + { + "id": "field0DC", + "name": "IPED5_END", + "description": "IPED region 5 End", + "offset_int": "0x00DC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0DC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0DC-bits8-31", + "name": "IPED_CTX5_END_ADDR", + "description": "IPED_CTX5_END_ADDR" + } + ] + }, + { + "id": "field0E0", + "name": "IPED6_START", + "description": "IPED region 6 Start", + "offset_int": "0x00E0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0E0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0E0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E0-bits8-31", + "name": "IPED_CTX6_START_ADDR", + "description": "IPED_CTX6_START_ADDR" + } + ] + }, + { + "id": "field0E4", + "name": "IPED6_END", + "description": "IPED region 6 End", + "offset_int": "0x00E4", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0E4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E4-bits8-31", + "name": "IPED_CTX6_END_ADDR", + "description": "IPED_CTX6_END_ADDR" + } + ] + }, + { + "id": "field0E8", + "name": "IPED7_START", + "description": "IPED region 7 Start", + "offset_int": "0x00E8", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field0E8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable.", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode. " + } + ] + }, + { + "width": 1, + "id": "field0E8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E8-bits8-31", + "name": "IPED_CTX7_START_ADDR", + "description": "IPED_CTX7_START_ADDR" + } + ] + }, + { + "id": "field0EC", + "name": "IPED7_END", + "description": "IPED region 7 End", + "offset_int": "0x00EC", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field0EC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings.", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 3, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0EC-bits8-31", + "name": "IPED_CTX7_END_ADDR", + "description": "IPED_CTX7_END_ADDR" + } + ] + }, + { + "id": "field0F0", + "name": "REC_IMG_EXT0", + "description": "REC_IMG_EXT0: Bitmap mask for recovery image extended sectors (sectors 0 -31)", + "offset_int": "0x00F0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F4", + "name": "REC_IMG_EXT1", + "description": "REC_IMG_EXT1: Bitmap mask for recovery image extended sectors (sectors 32 - 63)", + "offset_int": "0x00F4", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 000F8-0011C", + "description": "Reserved 000F8-0011C" + }, + "registers": [ + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field120", + "name": "QUICK_SET_GPIO_0", + "description": "Quick Set to Drive GPIO 0 port pins high", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "QUICK_CLR_GPIO_0", + "description": "Quick Clear to Drive GPIO 0 port pins low", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "QUICK_SET_GPIO_1", + "description": "Quick Set to Drive GPIO 1 port pins high", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "QUICK_CLR_GPIO_1", + "description": "Quick Clear to Drive GPIO 1 port pins low", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "QUICK_SET_GPIO_2", + "description": "Quick Set to Drive GPIO 2 port pins high", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "QUICK_CLR_GPIO_2", + "description": "Quick Clear to Drive GPIO 2 port pins low", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "QUICK_SET_GPIO_3", + "description": "Quick Set to Drive GPIO 3 port pins high", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "QUICK_CLR_GPIO_3", + "description": "Quick Clear to Drive GPIO 3 port pins low", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "QUICK_SET_GPIO_4", + "description": "Quick Set to Drive GPIO 4 port pins high", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "QUICK_CLR_GPIO_4", + "description": "Quick Clear to Drive GPIO 4 port pins low", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "QUICK_SET_GPIO_5", + "description": "Quick Set to Drive GPIO 5 port pins high", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "QUICK_CLR_GPIO_5", + "description": "Quick Clear to Drive GPIO 5 port pins low", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00150-0015C", + "description": "Reserved 00150-0015C" + }, + "registers": [ + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUST_MK_SK_KEY_BLOB", + "description": "CUST_MK_SK_KEY_BLOB", + "offset_int": "0x0160", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00164-001E8", + "description": "Reserved 00164-001E8" + }, + "registers": [ + { + "id": "Reserved00164", + "name": "Reserved 0x00164", + "description": "This field is reserved for internal use", + "offset_int": "0x0164", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00168", + "name": "Reserved 0x00168", + "description": "This field is reserved for internal use", + "offset_int": "0x0168", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0016C", + "name": "Reserved 0x0016C", + "description": "This field is reserved for internal use", + "offset_int": "0x016C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00170", + "name": "Reserved 0x00170", + "description": "This field is reserved for internal use", + "offset_int": "0x0170", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00174", + "name": "Reserved 0x00174", + "description": "This field is reserved for internal use", + "offset_int": "0x0174", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00178", + "name": "Reserved 0x00178", + "description": "This field is reserved for internal use", + "offset_int": "0x0178", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0017C", + "name": "Reserved 0x0017C", + "description": "This field is reserved for internal use", + "offset_int": "0x017C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00180", + "name": "Reserved 0x00180", + "description": "This field is reserved for internal use", + "offset_int": "0x0180", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00184", + "name": "Reserved 0x00184", + "description": "This field is reserved for internal use", + "offset_int": "0x0184", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00188", + "name": "Reserved 0x00188", + "description": "This field is reserved for internal use", + "offset_int": "0x0188", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0018C", + "name": "Reserved 0x0018C", + "description": "This field is reserved for internal use", + "offset_int": "0x018C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CRC32", + "description": "CRC32 fields" + }, + "registers": [ + { + "id": "field1EC", + "name": "CMPA_CRC32", + "description": "CMPA_CRC32 for address range 0x0200_4000 - 0x0200_41EB", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "CMAC", + "description": "CMAC fields" + }, + "registers": [ + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "CMPA CMAC 0", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMPA CMAC 1", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMPA CMAC 2", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMPA CMAC 3", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a1.json new file mode 100644 index 0000000..45ccfca --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/pfr_cmpa_a1.json @@ -0,0 +1,4693 @@ +{ + "cpu": "mcxn946", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0x59630000", + "bitfields": [ + { + "width": 2, + "id": "field000-bits0-1", + "name": "BOOT_SRC", + "description": "Primary boot source", + "values": [ + { + "name": "INTERNAL_FLASH_0B00", + "value": 0, + "description": "Internal flash" + }, + { + "name": "FLEXSPI_FLASH_XIP", + "value": 1, + "description": "FlexSPI flash XIP image" + }, + { + "name": "SECONDARY_BOOTLOADER", + "value": 2, + "description": "Secondary Boot loader in Bank1 IFR0 (32KB)" + }, + { + "name": "INTERNAL_FLASH_0B11", + "value": 3, + "description": "Internal flash" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "ISP_BOOT_IF", + "description": "ISP boot interface", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 1, + "description": "UART ISP" + }, + { + "name": "SPI_SLAVE", + "value": 2, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_SLAVE", + "value": 3, + "description": "I2C slave ISP" + }, + { + "name": "USB0_HID", + "value": 4, + "description": "USB0 HID" + }, + { + "name": "USB1_HID", + "value": 5, + "description": "USB1 HID" + }, + { + "name": "CAN_ISP", + "value": 6, + "description": "CAN ISP" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field000-bits8-9", + "name": "REC_BOOT_SRC", + "description": "Recovery boot source", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Recovery boot disabled" + }, + { + "name": "XIP_IMAGE", + "value": 1, + "description": "XIP image in Bank1 IFR0 (32KB)" + }, + { + "name": "SB3_IMAGE", + "value": 2, + "description": "SB3 image in 1-bit SPI flash connected to FlexComm. FC7 used for this function by default overlappes with FlexSPI A" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field000-bits12-13", + "name": "BOOT_SPEED", + "description": "Boot speed. Selects the core frequency and voltage to use during ROM execution", + "values": [ + { + "name": "FRO_48_MHZ", + "value": 0, + "description": "48 MHz FRO @ 1.0V" + }, + { + "name": "FRO_72_MHZ", + "value": 1, + "description": "72 MHz FRO @ 1.1V" + }, + { + "name": "FRO_144_MHZ", + "value": 2, + "description": "144 MHz FRO @ 1.2V" + }, + { + "name": "PLL_150_MHZ", + "value": 3, + "description": "150 MHz PLL @ 1.2V" + } + ] + }, + { + "width": 2 + }, + { + "width": 16, + "access": "WRITE_CONST", + "id": "field000-bits16-31", + "name": "HEADER", + "description": "CMPA Header marker should be set to 0x5963. After this header is set, all non-zero values will take effect; leaving all settings at 0xff will cause undefined behavior. It is recommended to set all values to 0x00 before setting the CMPA header value" + } + ] + }, + { + "id": "field004", + "name": "FLASH_CFG", + "description": "Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "FLASH_REMAP_SIZE", + "description": "Flash remap size. FLASH_REMAP_SIZE defines the size of the secondary boot image (the range of flash addresses that will be remapped)in internal flash, where remapped address end = (FLASH_REMAP_SIZE + 1)" + }, + { + "width": 3, + "id": "field004-bits5-7", + "name": "OEM_BANK1_IFR0_PROT", + "description": "Defines flash protection of Bank1_IFR0 area based on usage. Note, if the SBL / Recovery image size is more than IFR0 size of 32KB then sectors from user flash can be associated for extended image size using CMPA.REC_IMG_EXT0/1", + "values": [ + { + "name": "OEM_ROM_RWXL_CODE", + "value": 0, + "description": "Not determined by ROM (MBC fields are modified by OEM code)" + }, + { + "name": "OEM_ROOT_RWXL_1010", + "value": 1, + "description": "Used as OEM Root of Trust image, in other words secondary boot loader (OEM_SBL). MBC protection bits set as RWXL = 1010. Updatable by OEM code later" + }, + { + "name": "OEM_SBL_RWXL_1011", + "value": 2, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 1011" + }, + { + "name": "OEM_SBL_RWXL_0011", + "value": 3, + "description": "Used as OEM_SBL. MBC protection bits set as RWXL = 0011" + }, + { + "name": "OEM_REC_RWXL_1010", + "value": 4, + "description": "Used as OEM recovery boot image with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1010 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_1011", + "value": 5, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 1011 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_0011", + "value": 6, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0011 on ROM exiting to user image" + }, + { + "name": "OEM_REC_RWXL_0001", + "value": 7, + "description": "Used as OEM_RCVRY_IMG with MBC protection RWXL = 1010 on ROM exiting to recovery image. But set to RWXL = 0001 on ROM exiting to user image" + } + ] + }, + { + "width": 2, + "id": "field004-bits8-9", + "name": "ISP_PIN_ENTRY", + "description": "Disable ISP mode entry through pin assertion", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits10-11", + "name": "ISP_DM_ENTRY", + "description": "Disable ISP mode entry through debug mailbox command", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits12-13", + "name": "ISP_API_ENTRY", + "description": "Disable ISP mode entry through ROM API call. ISP mode can be entered through ROM API invocation", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 2, + "id": "field004-bits14-15", + "name": "ISP_FT_ENTRY", + "description": "Disable ISP mode entry through image authentication failure", + "values": [ + { + "name": "ALLOWED_0B00", + "value": 0, + "description": "ISP entry allowed" + }, + { + "name": "DISABLED_0B01", + "value": 1, + "description": "ISP entry disabled" + }, + { + "name": "ALLOWED_0B10", + "value": 2, + "description": "ISP entry allowed" + }, + { + "name": "ALLOWED_0B11", + "value": 3, + "description": "ISP entry allowed" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "field008", + "name": "BOOT_LED_STATUS", + "description": "Boot LED Status", + "offset_int": "0x0008", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field008-bits0-7", + "name": "REC_BOOT_LED", + "description": "Assert on recovery boot. ROM drives the GPIO pin high, identified by this field whenever primary boot fails and fall through to recovery boot source. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits8-15", + "name": "ISP_BOOT_LED", + "description": "Assert on ISP fall through. ROM drives the GPIO pin high identified by this field whenever primary boot fails and execution falls through to ISP mode. [[4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8, + "id": "field008-bits16-23", + "name": "BOOT_FAIL_LED", + "description": "Assert on fatal errors during boot. ROM drives the GPIO pin high identified by this field whenever primary boot fails due to fatal errors before locking-up/reset. [4:0] GPIO Pin number. P0_0 and P0_1 are not supported. [7:5] GPIO port number. Only 0 - 4 ports are allowed. If this feature is not use then set this field to 0x00. If this feature is not use then set this field to 0x00" + }, + { + "width": 8 + } + ] + }, + { + "id": "field00C", + "name": "BOOT_TIMERS", + "description": "Boot Timers", + "offset_int": "0x000C", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field00C-bits0-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Powerdown timeout: ISP mode peripheral detection timeout value in seconds. If a non-zero value is program and peripheral activity is not detected within the number of seconds specified here, then the device will go to power down mode to conserve power" + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "WDOG_TIMEOUT_COUNT", + "description": "WDOG timeout: Upper 16 bits of 24-bit count value in WWDT0_TC register Timeout value in seconds. The lower 8 bits of WWDT0_TC are set to 0. When a non-zero value is programmed in this field ROM configures the watch dog timer to reset the device on timeout before passing execution control to user code" + } + ] + }, + { + "id": "field010", + "name": "FLEXSPI_BOOT_CFG0", + "description": "FlexSPI Boot Configuration 0", + "offset_int": "0x0010", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field010-bit0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "field010-bits1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type. Note, this field is used when FLEXSPI_AUTO_PROBE_EN is set", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MACRONIC_OCTAL_FLASH", + "value": 1, + "description": "Macronix Octal FLASH" + }, + { + "name": "MICRON_OCTAL_FLASH", + "value": 2, + "description": "Micron Octal FLASH" + }, + { + "name": "ADESTO_OCTAL_FLASH", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "field010-bits4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types. This field is always used irrespective of FLEXSPI_AUTO_PROBE_EN value", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "QSPI ADDR 3B" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HYPER 1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HYPER 3V3" + }, + { + "name": "DDR_MXIC", + "value": 4, + "description": "FlexSPI_DDR_MXIC" + }, + { + "name": "DDR_MICRON", + "value": 5, + "description": "FlexSPI_DDR_MICRON" + } + ] + }, + { + "width": 4, + "id": "field010-bits7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command. If a non-zero value is programmed in this field, then the value is used to override the default number of dummy cycles for a fast read command read from the serial flash\u2019s SFDP information. Note: this field is only used if FLEXSPI_AUTO_PROBE_EN is set" + }, + { + "width": 3, + "id": "field010-bits11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Quad/Octal-SPI flash interface frequency. Note, this field is used when FLEXSPI_AUTO_PROBE_EN is set", + "values": [ + { + "name": "MHZ_75", + "value": 0, + "description": "75Mhz" + }, + { + "name": "MHZ_60", + "value": 1, + "description": "60Mhz" + }, + { + "name": "MHZ_50", + "value": 2, + "description": "50Mhz" + }, + { + "name": "MHZ_100", + "value": 3, + "description": "100Mhz" + } + ] + }, + { + "width": 1, + "id": "field010-bit14", + "name": "FLEXSPI_RESET_ENABLE", + "description": "Use O/QSPI_RESET_PIN to reset the flash device", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "NO_RESET(O/QSPI device reset pin is not connected or available" + }, + { + "name": "EN_RESET", + "value": 1, + "description": "EN_RESET(O/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN)" + } + ] + }, + { + "width": 3, + "id": "field010-bits15-17", + "name": "FLEXSPI_RESET_GPIO_PORT", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO port number to use for O/QSPI reset function" + }, + { + "width": 5, + "id": "field010-bits18-22", + "name": "FLEXSPI_RESET_GPIO_PIN", + "description": "When FLEXSPI_RESET_ENABLE = 1, this field determines the GPIO pin number to use for O/QSPI reset function" + }, + { + "width": 2, + "id": "field010-bits23-24", + "name": "FLEXSPI_HOLD_TIME", + "description": "Delay after reset before accessing Quad/Octal-SPI flash devices. Note, for POR in addition to this wait time FLEXSPI_PWR_HOLD_TIME is added", + "values": [ + { + "name": "WAIT_500US", + "value": 0, + "description": "Wait for 500 microseconds" + }, + { + "name": "WAIT_1MS", + "value": 1, + "description": "Wait for 1 milliseconds" + }, + { + "name": "WAIT_3MS", + "value": 2, + "description": "Wait for 3 milliseconds" + }, + { + "name": "WAIT_10MS", + "value": 3, + "description": "Wait for 10 milliseconds" + } + ] + }, + { + "width": 4, + "id": "field010-bits25-28", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by FLEXSPI_HOLD TIME field", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "WAIT_100US", + "value": 1, + "description": "Waits additional 100 microseconds" + }, + { + "name": "WAIT_500US", + "value": 2, + "description": "Waits additional 500 microseconds" + }, + { + "name": "WAIT_1MS", + "value": 3, + "description": "Waits additional 1 milliseconds" + }, + { + "name": "WAIT_10MS", + "value": 4, + "description": "Waits additional 10 milliseconds" + }, + { + "name": "WAIT_20MS", + "value": 5, + "description": "Waits additional 20 milliseconds" + }, + { + "name": "WAIT_40MS", + "value": 6, + "description": "Waits additional 40 milliseconds" + }, + { + "name": "WAIT_60MS", + "value": 7, + "description": "Waits additional 60 milliseconds" + }, + { + "name": "WAIT_80MS", + "value": 8, + "description": "Waits additional 80 milliseconds" + }, + { + "name": "WAIT_100SM", + "value": 9, + "description": "Waits additional 100 milliseconds" + }, + { + "name": "WAIT_120MS", + "value": 10, + "description": "Waits additional 120 milliseconds" + }, + { + "name": "WAIT_140MS", + "value": 11, + "description": "Waits additional 140 milliseconds" + }, + { + "name": "WAIT_160MS", + "value": 12, + "description": "Waits additional 160 milliseconds" + }, + { + "name": "WAIT_180MS", + "value": 13, + "description": "Waits additional 180 milliseconds" + }, + { + "name": "WAIT_200MS", + "value": 14, + "description": "Waits additional 200 milliseconds" + }, + { + "name": "WAIT_220MS", + "value": 15, + "description": "Waits additional 220 milliseconds" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "field010-bit31", + "name": "PORT_SEL", + "description": "Defines which FlexSPI portA/B is used for boot", + "values": [ + { + "name": "PORT_A", + "value": 0, + "description": "Port A" + }, + { + "name": "PORT_B", + "value": 1, + "description": "Port B" + } + ] + } + ] + }, + { + "id": "field014", + "name": "FLEXSPI_BOOT_CFG1", + "description": "FlexSPI Boot Configuration 1", + "offset_int": "0x0014", + "default_value_int": "0", + "bitfields": [ + { + "width": 7, + "id": "field014-bits0-6", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS). The value provided here is loaded into the FLEXSPIn_DLLnCR" + }, + { + "width": 10, + "id": "field014-bits7-16", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FLEXSPI_IMAGE_OFFSET field specifies the offset location of the second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. If this field is left blank boot ROM will not enable FlexSPI remap feature. The physical flash offset is computed as below: physical offset = FLEXSPI_IMAGE_OFFSET" + }, + { + "width": 4, + "id": "field014-bits17-20", + "name": "FLEXSPI_REMAP_IMAGE_SIZE", + "description": "Any offset in memory mapped FlexSPI Flash area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. FLEXSPI_IMAGE_OFFSET field specifies the offset location of second image. FLEXSPI_REMAP_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. NOTE: FlexSPI remap size cannot exceed the start address of boot image 1", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "Remap size = FLEXSPI_IMAGE_OFFSET * 256KByte; '' SIZE_OFFSET ''Size of the remapped area (aka second half) is same as first half. It is determined by FLEXSPI_IMAGE_OFFSET Field" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "Size of remapped area is 1MByte" + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "Size of remapped area is 2MByte" + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "Size of remapped area is 3MByte" + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "Size of remapped area is 4MByte" + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "Size of remapped area is 5MByte" + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "Size of remapped area is 6MByte" + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "Size of remapped area is 7MByte" + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "Size of remapped area is 8MByte" + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "Size of remapped area is 9MByte" + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "Size of remapped area is 10MByte" + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "Size of remapped area is 11MByte" + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "Size of remapped area is 12MByte" + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "Size of remapped area is 256KByte" + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "Size of remapped area is 512KByte" + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "Size of remapped area is 768KByte" + } + ] + }, + { + "width": 11 + } + ] + }, + { + "id": "field018", + "name": "REC_SPI_FLASH_CFG0", + "description": "Recovery SPI Flash Configuration 0", + "offset_int": "0x0018", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field018-bits0-7", + "name": "REC_SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits8-11", + "name": "REC_SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field018-bits12-15", + "name": "REC_SPI_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field018-bits16-23", + "name": "REC_SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field018-bits24-27", + "name": "REC_SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field01C", + "name": "REC_SPI_FLASH_CFG1", + "description": "Recovery SPI Flash Configuration 1", + "offset_int": "0x001C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field01C-bits0-7", + "name": "REC_SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits8-11", + "name": "REC_SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field01C-bits16-23", + "name": "REC_SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field01C-bits24-27", + "name": "REC_SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by REC_SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field01C-bits28-29", + "name": "REC_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2, + "id": "field01C-bits30-31", + "name": "REC_BOOT_PIN_CUST", + "description": "Use customer defined pins for 1-bit SPI recovery boot pins", + "values": [ + { + "name": "DEFAULT_ROM_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUSTOMER_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_ROM_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_ROM_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + }, + { + "id": "field020", + "name": "ISP_UART_CFG", + "description": "ISP UART Configuration", + "offset_int": "0x0020", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field020-bits0-7", + "name": "UART_RX_PIN", + "description": "Override default UART RX ISP pin. Identifies the pin to be used as UART_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits8-11", + "name": "UART_RX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_RX_PIN" + }, + { + "width": 4, + "id": "field020-bits12-15", + "name": "UART_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for UART ISP mode" + }, + { + "width": 8, + "id": "field020-bits16-23", + "name": "UART_TX_PIN", + "description": "Override default UART TX ISP pin. Identifies the pin to be used as UART_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field020-bits24-27", + "name": "UART_TX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by UART_TX_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field024", + "name": "ISP_I2C_CFG", + "description": "ISP I2C Configuration", + "offset_int": "0x0024", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field024-bits0-7", + "name": "I2C_SCL_PIN", + "description": "Override default I2C SCL ISP pin. Identifies the pin to be used as I2C_SCL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits8-11", + "name": "I2C_SCL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SCL_PIN" + }, + { + "width": 4, + "id": "field024-bits12-15", + "name": "I2C_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for I2C ISP mode" + }, + { + "width": 8, + "id": "field024-bits16-23", + "name": "I2C_SDA_PIN", + "description": "Override default I2C SDA ISP pin. Identifies the pin to be used as I2C_SDA pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field024-bits24-27", + "name": "I2C_SDA_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by I2C_SDA_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field028", + "name": "ISP_CAN_CFG", + "description": "ISP CAN Configuration", + "offset_int": "0x0028", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field028-bits0-7", + "name": "CAN_RX_PIN", + "description": "Override default CAN RX ISP pin. Identifies the pin to be used as CAN_RX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits8-11", + "name": "CAN_RX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by CAN_RX_PIN" + }, + { + "width": 4, + "id": "field028-bits12-15", + "name": "CAN_ISP_INST", + "description": "Identifies the instance used for CAN ISP mode", + "values": [ + { + "name": "CAN_0", + "value": 0, + "description": "For CAN0" + }, + { + "name": "CAN_1", + "value": 1, + "description": "For CAN1" + } + ] + }, + { + "width": 8, + "id": "field028-bits16-23", + "name": "CAN_TX_PIN", + "description": "Override default CAN TX ISP pin. Identifies the pin to be used as CAN_TX pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field028-bits24-27", + "name": "CAN_TX_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by CAN_TX_PIN" + }, + { + "width": 4, + "id": "field028-bits28-31", + "name": "CAN_BAUD_RATE", + "description": "CAN baud rate. Baud rate configured during CAN ISP mode", + "values": [ + { + "name": "AUTO_DETECT", + "value": 0, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "KBPS_125", + "value": 1, + "description": "125 kbps" + }, + { + "name": "KBPS_250", + "value": 2, + "description": "250 kbps" + }, + { + "name": "KBPS_500", + "value": 3, + "description": "500 kbps" + }, + { + "name": "KBPS_750", + "value": 4, + "description": "750 kbps" + }, + { + "name": "KBPS_1000", + "value": 5, + "description": "1000 kbps" + }, + { + "name": "AUTO_DETECT_0b0110", + "value": 6, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b0111", + "value": 7, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1000", + "value": 8, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1001", + "value": 9, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1010", + "value": 10, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1011", + "value": 11, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1100", + "value": 12, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1101", + "value": 13, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1110", + "value": 14, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + }, + { + "name": "AUTO_DETECT_0b1111", + "value": 15, + "description": "Auto baud detection (125K, 250K, 500K, 750K, 1M)" + } + ] + } + ] + }, + { + "id": "field02C", + "name": "ISP_SPI_CFG0", + "description": "ISP SPI Configuration 0", + "offset_int": "0x002C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field02C-bits0-7", + "name": "SPI_SCK_PIN", + "description": "Override default SPI_SCK ISP pin. Identifies the pin to be used as SPI_SCK pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits8-11", + "name": "SPI_SCK_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SCK_PIN" + }, + { + "width": 4, + "id": "field02C-bits12-15", + "name": "SPI_ISP_FLEXCOM", + "description": "Identifies the FlexComm used for SPI ISP mode" + }, + { + "width": 8, + "id": "field02C-bits16-23", + "name": "SPI_MOSI_PIN", + "description": "Override default SPI_MOSI ISP pin. Identifies the pin to be used as SPI_MOSI pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field02C-bits24-27", + "name": "SPI_MOSI_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MOSI_PIN" + }, + { + "width": 4 + } + ] + }, + { + "id": "field030", + "name": "ISP_SPI_CFG1", + "description": "ISP SPI Configuration 1", + "offset_int": "0x0030", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field030-bits0-7", + "name": "SPI_MISO_PIN", + "description": "Override default SPI_MISO ISP pin. Identifies the pin to be used as SPI_MISO pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits8-11", + "name": "SPI_MISO_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_MISO_PIN" + }, + { + "width": 4 + }, + { + "width": 8, + "id": "field030-bits16-23", + "name": "SPI_SSEL_PIN", + "description": "Override default SPI_SSEL ISP pin. Identifies the pin to be used as SPI_SSEL pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field030-bits24-27", + "name": "SPI_SSEL_FUNC_SLOT", + "description": "Identifies the ALT pin mux function to use for the pin selected by SPI_SSEL_PIN" + }, + { + "width": 2, + "id": "field030-bits28-29", + "name": "ISP_SPI_SSEL_X", + "description": "SPI chip select number. FlexComm SPI interfaces supports up to four chip selects" + }, + { + "width": 2 + } + ] + }, + { + "id": "field034", + "name": "ISP_USB_ID", + "description": "ISP USB Identification", + "offset_int": "0x0034", + "default_value_int": "0", + "bitfields": [ + { + "width": 16, + "id": "field034-bits0-15", + "name": "USB_Vendor_ID", + "description": "Customer defined USB vendor ID used during USB-ISP mode device enumeration" + }, + { + "width": 16, + "id": "field034-bits16-31", + "name": "USB_Product_ID", + "description": "Customer defined USB product ID used during USB-ISP mode device enumeration" + } + ] + }, + { + "id": "field038", + "name": "ISP_USB_CFG", + "description": "ISP USB Configuration", + "offset_int": "0x0038", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field038-bits0-7", + "name": "USBx_VBUS_PIN", + "deprecated_names": [ + "USB0_VBUS_PIN" + ], + "description": "Override default USBx_VBUS_DETECT ISP pin. Identifies the pin to be used as USBx_VBUS detect pin. [4:0] GPIO Pin number [7:5] GPIO port number" + }, + { + "width": 4, + "id": "field038-bits8-11", + "name": "USBx_VBUS_FUNC_SLOT", + "deprecated_names": [ + "USB0_VBUS_FUNC_SLOT" + ], + "description": "Identifies the ALT pin mux function to use for the pin selected by USBx_VBUS_PIN" + }, + { + "width": 4 + }, + { + "width": 3, + "id": "field038-bits16-18", + "name": "EXT_XTAL_CLK", + "description": "USB PHY input clock frequency. For USB high speed PHY external XTAL input is needed. This field specifies the frequency of XTAL used on board. \u2022 000b - 24MHz input clock (Divide by 20) \u2022 001b - 30MHz input clock (Divide by 16) \u2022 010b - 32MHz input clock (Divide by 15) \u2022 011b - Reserved \u2022 100b - 20MHz input clock (Divide by 24) \u2022 101b - 19.2MHz input clock (Divide by 25) \u2022 110b - 16MHz input clock (Divide by 30) - Default option when CMPA is blank. \u2022 111b - 12MHz input clock (Divide by 40)", + "values": [ + { + "name": "XTAL_24MHZ", + "value": 0, + "description": "24MHz input clock (Divide by 20)" + }, + { + "name": "XTAL_30MHZ", + "value": 1, + "description": "30MHz input clock (Divide by 16)" + }, + { + "name": "XTAL_32MHZ", + "value": 2, + "description": "32MHz input clock (Divide by 15)" + }, + { + "name": "XTAL_20MHZ", + "value": 4, + "description": "20MHz input clock (Divide by 24)" + }, + { + "name": "XTAL_19_2MHZ", + "value": 5, + "description": "19.2MHz input clock (Divide by 25)" + }, + { + "name": "XTAL_16MHZ", + "value": 6, + "description": "16MHz input clock (Divide by 30) - Default option when CMPA is blank" + }, + { + "name": "XTAL_12MHZ", + "value": 7, + "description": "12MHz input clock (Divide by 40)" + } + ] + }, + { + "width": 1, + "id": "field038-bit19", + "name": "PRE_DIV", + "description": "Enable Pre-divider. Needed to support 48MHz and other high speed crystals", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 12 + } + ] + }, + { + "id": "field03C", + "name": "ISP_MISC_CFG", + "description": "ISP Miscellaneous Configuration", + "offset_int": "0x003C", + "default_value_int": "0", + "bitfields": [ + { + "width": 8, + "id": "field03C-bits0-7", + "name": "I2C_SLAVE_ADDR", + "description": "I2C slave address A 7-bit Address used for selecting our device on shared I2C bus system. By default ROM uses 0x10 as slave address. If this address conflicts with another slave on board customer could use this field to override the address" + }, + { + "width": 14 + }, + { + "width": 2, + "id": "field03C-bits22-23", + "name": "ISP_USB_CUST", + "description": "Use customer defined GPIO for USB VBUS detect function during ISP mode", + "values": [ + { + "name": "DEDICATED", + "value": 0, + "description": "Use dedicated VBUS pins" + }, + { + "name": "USB0_VBUS", + "value": 1, + "description": "Customer defined GPIO for USB0_VBUS detect" + }, + { + "name": "USB1_VBUS", + "value": 2, + "description": "Customer defined GPIO for USB1_VBUS detect" + }, + { + "name": "VDD_USB", + "value": 3, + "description": "Use VDD_USB for VBUS presence. On board regulator should generate VDD_USB voltage using 5V input fo VBUS pin on connector" + } + ] + }, + { + "width": 2, + "id": "field03C-bits24-25", + "name": "ISP_CAN_CUST", + "description": "Use customer defined CAN ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits26-27", + "name": "ISP_SPI_CUST", + "description": "Use customer defined SPI ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits28-29", + "name": "ISP_I2C_CUST", + "description": "Use customer defined I2C ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + }, + { + "width": 2, + "id": "field03C-bits30-31", + "name": "ISP_UART_CUST", + "description": "Use customer defined UART ISP pins", + "values": [ + { + "name": "DEFAULT_0b00", + "value": 0, + "description": "Default ROM defined pins" + }, + { + "name": "CUST_DEF_0b01", + "value": 1, + "description": "Customer defined" + }, + { + "name": "DEFAULT_0b10", + "value": 2, + "description": "Default ROM defined pins" + }, + { + "name": "DEFAULT_0b11", + "value": 3, + "description": "Default ROM defined pins" + } + ] + } + ] + }, + { + "id": "field040", + "name": "CC_SOCU_PIN", + "description": "Credential Constraints for SoC specific Use Pinned", + "offset_int": "0x0040", + "deprecated_names": [ + "DCFG_CC_SOCU_PIN" + ], + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field040-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field040-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug enable", + "values": [ + { + "name": "USE_Dap", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit6", + "name": "ISP_CMD_EN", + "description": "ISP boot command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit7", + "name": "FA_CMD_EN", + "description": "FA Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit8", + "name": "ME_CMD_EN", + "description": "Flash Mass Erase Command Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 Non-invasive Debug Enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field040-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Disabled" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 1, + "id": "field040-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Debug certificate can be used with all devices" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Debug certificate per device with matching UUID is needed" + } + ] + }, + { + "width": 16, + "id": "field040-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field044", + "name": "CC_SOCU_DFLT", + "description": "Credential Constraints for SoC specific Use Debug Filter", + "offset_int": "0x0044", + "deprecated_names": [ + "DCFG_CC_SOCU_DFLT" + ], + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field044-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit1", + "name": "DBGEN", + "description": "Non Secure debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field044-bit5", + "name": "DSP_DBGEN", + "description": "DSP debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit6", + "name": "ISP_CMD_EN", + "description": "ISP command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit7", + "name": "FA_CMD_EN", + "description": "Set FA mode command Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit8", + "name": "ME_CMD_EN", + "description": "Mass erase flash command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit9", + "name": "CPU1_NIDEN", + "description": "Second CM33 Non-Invasive Debug Fixed State", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field044-bit10", + "name": "CPU1_DBGEN", + "description": "Second CM33 debug Fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 5 + }, + { + "width": 16, + "id": "field044-bits16-31", + "name": "Inverse_value", + "description": "Inverse Value", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field048", + "name": "VENDOR_USAGE", + "description": "Vendor Usage", + "offset_int": "0x0048", + "default_value_int": "0", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field048-bits16-31", + "name": "VENDOR_USAGE", + "description": "Vendor Usage [31:16]. Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area (CFPA.DBG_REVOKE_VU)" + } + ] + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "field050", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x0050", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field050-bits0-1", + "name": "SEC_BOOT_EN", + "description": "Secure boot enforcement. This field defines the minimum image verification procedure (CRC32, CMAC, ECDSA sign). The Image type field in header indicates the type of verification data (checksum or signature) included in it. Note: Plain < CRC32 < CMAC < ECDSA", + "values": [ + { + "name": "ALL_IMAGES", + "value": 0, + "description": "All Image types are allowed" + }, + { + "name": "CRC32_IMAGES", + "value": 1, + "description": "Only CRC32 or signed (CMAC or ECDSA) images are allowed" + }, + { + "name": "SIGNED_IMAGES", + "value": 2, + "description": "Only Signed (CMAC or ECDSA) images are allowed" + }, + { + "name": "ECDSA_SIGNED", + "value": 3, + "description": "Only ECDSA signed images are allowed" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field050-bits3-4", + "name": "LP_SEC_BOOT", + "description": "Secure boot option for low-power wake from power-down and deep-powerdown. For CFPA/CMPA do CRC check always", + "values": [ + { + "name": "COLD_BOOT", + "value": 0, + "description": "Same as cold boot" + }, + { + "name": "CHECK_CRC32", + "value": 1, + "description": "CRC check for CFPA/CMPA & CRC32 check of active image" + }, + { + "name": "CHECK_JUMP", + "value": 2, + "description": "CRC check for CFPA/CMPA & jump to vector address specified in CFPA" + }, + { + "name": "CMAC_CHECK", + "value": 3, + "description": "CRC check for CFPA/CMPA & CMAC check of active image" + } + ] + }, + { + "width": 3 + }, + { + "width": 2, + "id": "field050-bits8-9", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite approved algorithms for secure boot, secure update and debug authentication. Note, CMAC image authentication is only allowed in 2b'00 setting", + "values": [ + { + "name": "ALL_ALLOWED_0B00", + "value": 0, + "description": "All algorithm allowed" + }, + { + "name": "LIMITED_0B01", + "value": 1, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used" + }, + { + "name": "LIMITED_0B10", + "value": 2, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used" + }, + { + "name": "LIMITED_0B11", + "value": 3, + "description": "Only ECC P-384 keys, SHA384 & AES256 algorithms are used" + } + ] + }, + { + "width": 2, + "id": "field050-bits10-11", + "name": "ENF_TZM_PRESET", + "description": "Enforce TrustZone-M mode", + "values": [ + { + "name": "IGNORE_0B00", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_0B01", + "value": 1, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_0B10", + "value": 2, + "description": "Enforce preset TZM data in image manifest" + }, + { + "name": "ENFORCE_0B11", + "value": 3, + "description": "Enforce preset TZM data in image manifest" + } + ] + }, + { + "width": 2, + "id": "field050-bits12-13", + "name": "ITRC_ZEROIZE", + "description": "RAM zeroize on ITRC event. Zeroize long-term storage RAM (RAMA) on subsequent boot when Intrusion and Tamper control signals an intrusion event (ITRC_OUT3). Note, when ITRC is re-configured in application then ITRC_OUT4 (CHIP_RESET) should be triggered with at least same events as ITRC_OUT3 (RAM_ZEROIZE)", + "values": [ + { + "name": "NO_ACTION", + "value": 0, + "description": "No action" + }, + { + "name": "PKC_RAM_ON_ITRC", + "value": 1, + "description": "Always Zeroize PKC RAM on ITRC event only" + }, + { + "name": "PKC_RAMA_ON_ITRC", + "value": 2, + "description": "Zeroize PKC & RAMA on ITRC event only" + }, + { + "name": "PKC_RAMA_ALL_RESET", + "value": 3, + "description": "Always Zeroize PKC & RAMA on all reset boot" + } + ] + }, + { + "width": 2, + "id": "field050-bits14-15", + "name": "ACTIVE_IMG_PROT", + "description": "Protection of active image. This field defines protection of flash area occupied by the active image. Only applicable to internal flash", + "values": [ + { + "name": "FLASH_ACL_PROTECTION", + "value": 0, + "description": "Protection is defined using the CFPA FLASH_ACL settings" + }, + { + "name": "WITH_STICKY_LOCK", + "value": 1, + "description": "Write protect active image area with sticky lock. GLBAC2 is used. FLASH_ACL settings are ignored" + }, + { + "name": "NO_STICKY_LOCK", + "value": 2, + "description": "Write protect active image area without sticky lock. GLBAC4 is used. FLASH_ACL settings are ignored" + }, + { + "name": "XOM_PROTECTION", + "value": 3, + "description": "XOM protect active image area with sticky lock. GLBAC6 is used. FLASH_ACL settings are ignored" + } + ] + }, + { + "width": 2, + "id": "field050-bits16-17", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits18-19", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits20-21", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits22-23", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits24-25", + "name": "FIPS_CMAC_STEN", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits26-27", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for KDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2, + "id": "field050-bits28-29", + "name": "FIPS_PUF_STEN", + "description": "Enable self-test for PUF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in SYSCON->ELS_AS_BOOT_LOG1[FIPS]", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "FAILURE_BOOT", + "value": 1, + "description": "On failure continue to boot" + }, + { + "name": "FAILURE_ISP", + "value": 2, + "description": "On failure enter ISP mode for recovery" + }, + { + "name": "FAILURE_ENF_POWER", + "value": 3, + "description": "On failure lock the device to enforce power-cycle" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "field054", + "name": "RoTK_USAGE", + "description": "Root of Trust Key Usage", + "offset_int": "0x0054", + "default_value_int": "0", + "bitfields": [ + { + "width": 3, + "id": "field054-bits0-2", + "name": "RoTK0_Usage", + "description": "RoT key 0 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits3-5", + "name": "RoTK1_Usage", + "description": "RoT key 1 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits6-8", + "name": "RoTK2_Usage", + "description": "RoT key 2 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 3, + "id": "field054-bits9-11", + "name": "RoTK3_Usage", + "description": "RoT key 3 usage properties", + "values": [ + { + "name": "USABLE", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key" + }, + { + "name": "DEBUG", + "value": 1, + "description": "Usable as debug CA only" + }, + { + "name": "IMG_BOOT_FW", + "value": 2, + "description": "Usable as image (boot & FW) CA only" + }, + { + "name": "DEBUG_BOOT_FW_IMG", + "value": 3, + "description": "Usable as debug, boot & FW image CA" + }, + { + "name": "IMG_FW_UPDATE_KEY", + "value": 4, + "description": "Usable as image key & FW update key only" + }, + { + "name": "BOOT_IMAGE_KEY", + "value": 5, + "description": "Usable as boot image key only" + }, + { + "name": "FW_UPDATE_IMG_KEY", + "value": 6, + "description": "Usable as FW update image key only" + }, + { + "name": "KEY_SLOT_NOT_USED", + "value": 7, + "description": "Key slot is not used" + } + ] + }, + { + "width": 1, + "id": "field054-bit12", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE_DICE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_DICE", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 1, + "id": "field054-bit13", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area (IFR1) containing specific part configuration data defined during chip manufacturing process in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1, + "id": "field054-bit14", + "name": "DICE_INC_CUST_CFG", + "description": "Include data from CMPA page (512 bytes) in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "included" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "field054-bits16-17", + "name": "REG0_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 0. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check. 0x - ROM API will not perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase heck is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits18-19", + "name": "REG1_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 1. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check. 0x - ROM API will not perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase heck is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits20-21", + "name": "REG2_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 2. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check. 0x - ROM API will not perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase heck is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits22-23", + "name": "REG3_ERASE_CHECK_EN", + "description": "Enable erase check for NPX PRINCE context 3. When erase check is enabled ROM API will enforce a check to guarantee that all sectors selected in the context are erased together. When erase check is enabled only contiguous sectors can be selected in context bitmap. 0x - ROM API will not perform erase check. 1x - ROM API will perform erase check. 0x - ROM API will not perform erase check", + "values": [ + { + "name": "DISABLED_0b00", + "value": 0, + "description": "Erase check is disabled" + }, + { + "name": "DISABLED_0b01", + "value": 1, + "description": "Erase check is disabled" + }, + { + "name": "ENABLED_0b10", + "value": 2, + "description": "Erase heck is enabled" + }, + { + "name": "ENABLED_0b11", + "value": 3, + "description": "Erase check is enabled" + } + ] + }, + { + "width": 2, + "id": "field054-bits24-25", + "name": "NPX_LOCK_CTX0", + "description": "Lock on-chip flash NPX PRINCE context 0 settings. Note: when locking a region recommendation is to also enable erase checking using the REG0_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits26-27", + "name": "NPX_LOCK_CTX1", + "description": "Lock on-chip flash NPX PRINCE context 1 settings. Note: when locking a region recommendation is to also enable erase checking using the REG1_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits28-29", + "name": "NPX_LOCK_CTX2", + "description": "Lock on-chip flash NPX PRINCE context 2 settings. Note: when locking a region recommendation is to also enable erase checking using the REG2_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 2, + "id": "field054-bits30-31", + "name": "NPX_LOCK_CTX3", + "description": "Lock on-chip flash NPX PRINCE context 3 settings. Note: when locking a region recommendation is to also enable erase checking using the REG3_ERASE_CHECK_EN field", + "values": [ + { + "name": "NOT_LOCKED_0B00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0B01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0B11", + "value": 3, + "description": "Region is locked" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00058-0005C", + "description": "Reserved 00058-0005C" + }, + "registers": [ + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH (Root of Trust Key Hash) configuration" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "Root of Trust Key Hash 0", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "Root of Trust Key Hash 1", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "Root of Trust Key Hash 2", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "Root of Trust Key Hash 3", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "Root of Trust Key Hash 4", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "Root of Trust Key Hash 5", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "Root of Trust Key Hash 6", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "Root of Trust Key Hash 7", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field080", + "name": "ROTKH8", + "description": "Root of Trust Key Hash 8", + "offset_int": "0x0080", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field084", + "name": "ROTKH9", + "description": "Root of Trust Key Hash 9", + "offset_int": "0x0084", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field088", + "name": "ROTKH10", + "description": "Root of Trust Key Hash 10", + "offset_int": "0x0088", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field08C", + "name": "ROTKH11", + "description": "Root of Trust Key Hash 11", + "offset_int": "0x008C", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "NPX_CTX", + "description": "Prince region configuration" + }, + "registers": [ + { + "id": "field090", + "name": "NPX_CTX0_WD0", + "description": "Bitmap mask for NPX Prince context 0 (sectors .ROM copies this value to NPX->VMAPCTX0_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key and IV.", + "offset_int": "0x0090", + "default_value_int": "0" + }, + { + "id": "field094", + "name": "NPX_CTX0_WD1", + "description": "Bitmap mask for NPX Prince context 0 (sectors .ROM copies this value to NPX->VMAPCTX0_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX0 key and IV.", + "offset_int": "0x0094", + "default_value_int": "0" + }, + { + "id": "field098", + "name": "NPX_CTX1_WD0", + "description": "Bitmap mask for NPX Prince context 1 (sectors .ROM copies this value to NPX->VMAPCTX1_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key and IV.", + "offset_int": "0x0098", + "default_value_int": "0" + }, + { + "id": "field09C", + "name": "NPX_CTX1_WD1", + "description": "Bitmap mask for NPX Prince context 1 (sectors .ROM copies this value to NPX->VMAPCTX1_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX1 key and IV.", + "offset_int": "0x009C", + "default_value_int": "0" + }, + { + "id": "field0A0", + "name": "NPX_CTX2_WD0", + "description": "Bitmap mask for NPX Prince context 2 (sectors .ROM copies this value to NPX->VMAPCTX2_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key and IV.", + "offset_int": "0x00A0", + "default_value_int": "0" + }, + { + "id": "field0A4", + "name": "NPX_CTX2_WD1", + "description": "Bitmap mask for NPX Prince context 2 (sectors .ROM copies this value to NPX->VMAPCTX2_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX2 key and IV.", + "offset_int": "0x00A4", + "default_value_int": "0" + }, + { + "id": "field0A8", + "name": "NPX_CTX3_WD0", + "description": "Bitmap mask for NPX Prince context 3 (sectors .ROM copies this value to NPX->VMAPCTX3_WD0 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key and IV.", + "offset_int": "0x00A8", + "default_value_int": "0" + }, + { + "id": "field0AC", + "name": "NPX_CTX3_WD1", + "description": "Bitmap mask for NPX Prince context 3 (sectors .ROM copies this value to NPX->VMAPCTX3_WD1 register during flash initialization. This bitmask indicates which 32KB block is encrypted/decrypted using CTX3 key and IV.", + "offset_int": "0x00AC", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "IPED", + "description": "IPED region configuration" + }, + "registers": [ + { + "id": "field0B0", + "name": "IPED0_START", + "description": "IPED region 0 Start", + "offset_int": "0x00B0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0B0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0B0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B0-bits8-31", + "name": "IPED_CTX0_START_ADDR", + "description": "Upper 24-bits of IPED region 0 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0B4", + "name": "IPED0_END", + "description": "IPED region 0 End", + "offset_int": "0x00B4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0B4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B4-bits8-31", + "name": "IPED_CTX0_END_ADDR", + "description": "Upper 24-bits of IPED region 0 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0B8", + "name": "IPED1_START", + "description": "IPED region 1 Start", + "offset_int": "0x00B8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0B8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0B8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0B8-bits8-31", + "name": "IPED_CTX1_START_ADDR", + "description": "Upper 24-bits of IPED region 1 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0BC", + "name": "IPED1_END", + "description": "IPED region 1 End", + "offset_int": "0x00BC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0BC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0BC-bits8-31", + "name": "IPED_CTX1_END_ADDR", + "description": "Upper 24-bits of IPED region 1 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C0", + "name": "IPED2_START", + "description": "IPED region 2 Start", + "offset_int": "0x00C0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0C0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0C0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C0-bits8-31", + "name": "IPED_CTX2_START_ADDR", + "description": "Upper 24-bits of IPED region 2 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C4", + "name": "IPED2_END", + "description": "IPED region 2 End", + "offset_int": "0x00C4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0C4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C4-bits8-31", + "name": "IPED_CTX2_END_ADDR", + "description": "Upper 24-bits of IPED region 2 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0C8", + "name": "IPED3_START", + "description": "IPED region 3 Start", + "offset_int": "0x00C8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0C8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0C8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0C8-bits8-31", + "name": "IPED_CTX3_START_ADDR", + "description": "Upper 24-bits of IPED region 3 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0CC", + "name": "IPED3_END", + "description": "IPED region 3 End", + "offset_int": "0x00CC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0CC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0CC-bits8-31", + "name": "IPED_CTX3_END_ADDR", + "description": "Upper 24-bits of IPED region 3 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D0", + "name": "IPED4_START", + "description": "IPED region 4 Start", + "offset_int": "0x00D0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0D0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0D0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D0-bits8-31", + "name": "IPED_CTX4_START_ADDR", + "description": "Upper 24-bits of IPED region 4 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D4", + "name": "IPED4_END", + "description": "IPED region 4 End", + "offset_int": "0x00D4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0D4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D4-bits8-31", + "name": "IPED_CTX4_END_ADDR", + "description": "Upper 24-bits of IPED region 4 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0D8", + "name": "IPED5_START", + "description": "IPED region 5 Start", + "offset_int": "0x00D8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0D8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0D8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0D8-bits8-31", + "name": "IPED_CTX5_START_ADDR", + "description": "Upper 24-bits of IPED region 5 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0DC", + "name": "IPED5_END", + "description": "IPED region 5 End", + "offset_int": "0x00DC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0DC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0DC-bits8-31", + "name": "IPED_CTX5_END_ADDR", + "description": "Upper 24-bits of IPED region 5 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E0", + "name": "IPED6_START", + "description": "IPED region 6 Start", + "offset_int": "0x00E0", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0E0-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0E0-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E0-bits8-31", + "name": "IPED_CTX6_START_ADDR", + "description": "Upper 24-bits of IPED region 6 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E4", + "name": "IPED6_END", + "description": "IPED region 6 End", + "offset_int": "0x00E4", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0E4-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E4-bits8-31", + "name": "IPED_CTX6_END_ADDR", + "description": "Upper 24-bits of IPED region 6 end address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0E8", + "name": "IPED7_START", + "description": "IPED region 7 Start", + "offset_int": "0x00E8", + "default_value_int": "0", + "bitfields": [ + { + "width": 1, + "id": "field0E8-bit0", + "name": "GCM_MODE", + "description": "GCM mode enable", + "values": [ + { + "name": "ENABLE_CTR_MODE", + "value": 0, + "description": "Region is enabled in CTR mode" + }, + { + "name": "ENABLE_GCM_MODE", + "value": 1, + "description": "Region is enabled in GCM mode" + } + ] + }, + { + "width": 1, + "id": "field0E8-bit1", + "name": "AHBERR_DIS", + "description": "Disable AHB bus error. If GCM authentication fails generates bus error or not", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Bus error enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Bus error disabled" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0E8-bits8-31", + "name": "IPED_CTX7_START_ADDR", + "description": "Upper 24-bits of IPED region 7 start address. Lower 8 address bits are always 0" + } + ] + }, + { + "id": "field0EC", + "name": "IPED7_END", + "description": "IPED region 7 End", + "offset_int": "0x00EC", + "default_value_int": "0", + "bitfields": [ + { + "width": 2, + "id": "field0EC-bits0-1", + "name": "LOCK_EN", + "description": "Lock the external PRINCE context settings", + "values": [ + { + "name": "NOT_LOCKED_0b00", + "value": 0, + "description": "Region is not locked" + }, + { + "name": "LOCKED_0b01", + "value": 1, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b10", + "value": 2, + "description": "Region is locked" + }, + { + "name": "LOCKED_0b11", + "value": 3, + "description": "Region is locked" + } + ] + }, + { + "width": 6 + }, + { + "width": 24, + "id": "field0EC-bits8-31", + "name": "IPED_CTX7_END_ADDR", + "description": "Upper 24-bits of IPED region 7 end address. Lower 8 address bits are always 0" + } + ] + } + ] + }, + { + "group": { + "name": "REC_IMG", + "description": "Recovery image configuration" + }, + "registers": [ + { + "id": "field0F0", + "name": "REC_IMG_EXT0", + "description": "Bitmap mask to indicate sectors included in recovery image (sectors .Recovery image is programmed in BANK1_IFR0. But if the image size is more than 32KB, this field can be used to indicate sectors to include in recovery image.ROM will configure flash protection setting for these sectors the same as BANK1_IFR0 before exiting to user code. The protection settings are managed through CMPA.OEM_BANK1_IFR0_PROT. The lower 8 sectors are excluded from this mask to avoid conflicts with dual image boot feature.", + "offset_int": "0x00F0", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 1, + "id": "field0F0-bit8", + "name": "REC_IMG_EXT0_SEC8", + "description": "REC_IMG_EXT0_SEC set protection for memory in range 0x40000:0x47FFF" + }, + { + "width": 1, + "id": "field0F0-bit9", + "name": "REC_IMG_EXT0_SEC9", + "description": "REC_IMG_EXT0_SEC9 set protection for memory in range 0x48000:0x4FFFF" + }, + { + "width": 1, + "id": "field0F0-bit10", + "name": "REC_IMG_EXT0_SEC10", + "description": "REC_IMG_EXT0_SEC10 set protection for memory in range 0x50000:0x57FFF" + }, + { + "width": 1, + "id": "field0F0-bit11", + "name": "REC_IMG_EXT0_SEC11", + "description": "REC_IMG_EXT0_SEC11 set protection for memory in range 0x58000:0x5FFFF" + }, + { + "width": 1, + "id": "field0F0-bit12", + "name": "REC_IMG_EXT0_SEC12", + "description": "REC_IMG_EXT0_SEC12 set protection for memory in range 0x60000:0x67FFF" + }, + { + "width": 1, + "id": "field0F0-bit13", + "name": "REC_IMG_EXT0_SEC13", + "description": "REC_IMG_EXT0_SEC13 set protection for memory in range 0x68000:0x6FFFF" + }, + { + "width": 1, + "id": "field0F0-bit14", + "name": "REC_IMG_EXT0_SEC14", + "description": "REC_IMG_EXT0_SEC14 set protection for memory in range 0x70000:0x77FFF" + }, + { + "width": 1, + "id": "field0F0-bit15", + "name": "REC_IMG_EXT0_SEC15", + "description": "REC_IMG_EXT0_SEC15 set protection for memory in range 0x78000:0x7FFFF" + }, + { + "width": 1, + "id": "field0F0-bit16", + "name": "REC_IMG_EXT0_SEC16", + "description": "REC_IMG_EXT0_SEC16 set protection for memory in range 0x80000:0x87FFF" + }, + { + "width": 1, + "id": "field0F0-bit17", + "name": "REC_IMG_EXT0_SEC17", + "description": "REC_IMG_EXT0_SEC17 set protection for memory in range 0x88000:0x8FFFF" + }, + { + "width": 1, + "id": "field0F0-bit18", + "name": "REC_IMG_EXT0_SEC18", + "description": "REC_IMG_EXT0_SEC18 set protection for memory in range 0x90000:0x97FFF" + }, + { + "width": 1, + "id": "field0F0-bit19", + "name": "REC_IMG_EXT0_SEC19", + "description": "REC_IMG_EXT0_SEC19 set protection for memory in range 0x98000:0x9FFFF" + }, + { + "width": 1, + "id": "field0F0-bit20", + "name": "REC_IMG_EXT0_SEC20", + "description": "REC_IMG_EXT0_SEC20 set protection for memory in range 0xA0000:0xA7FFF" + }, + { + "width": 1, + "id": "field0F0-bit21", + "name": "REC_IMG_EXT0_SEC21", + "description": "REC_IMG_EXT0_SEC21 set protection for memory in range 0xA8000:0xAFFFF" + }, + { + "width": 1, + "id": "field0F0-bit22", + "name": "REC_IMG_EXT0_SEC22", + "description": "REC_IMG_EXT0_SEC22 set protection for memory in range 0xB0000:0xB7FFF" + }, + { + "width": 1, + "id": "field0F0-bit23", + "name": "REC_IMG_EXT0_SEC23", + "description": "REC_IMG_EXT0_SEC23 set protection for memory in range 0xB8000:0xBFFFF" + }, + { + "width": 1, + "id": "field0F0-bit24", + "name": "REC_IMG_EXT0_SEC24", + "description": "REC_IMG_EXT0_SEC24 set protection for memory in range 0xC0000:0xC7FFF" + }, + { + "width": 1, + "id": "field0F0-bit25", + "name": "REC_IMG_EXT0_SEC25", + "description": "REC_IMG_EXT0_SEC25 set protection for memory in range 0xC8000:0xCFFFF" + }, + { + "width": 1, + "id": "field0F0-bit26", + "name": "REC_IMG_EXT0_SEC26", + "description": "REC_IMG_EXT0_SEC26 set protection for memory in range 0xD0000:0xD7FFF" + }, + { + "width": 1, + "id": "field0F0-bit27", + "name": "REC_IMG_EXT0_SEC27", + "description": "REC_IMG_EXT0_SEC27 set protection for memory in range 0xD8000:0xDFFFF" + }, + { + "width": 1, + "id": "field0F0-bit28", + "name": "REC_IMG_EXT0_SEC28", + "description": "REC_IMG_EXT0_SEC28 set protection for memory in range 0xE0000:0xE7FFF" + }, + { + "width": 1, + "id": "field0F0-bit29", + "name": "REC_IMG_EXT0_SEC29", + "description": "REC_IMG_EXT0_SEC29 set protection for memory in range 0xE8000:0xEFFFF" + }, + { + "width": 1, + "id": "field0F0-bit30", + "name": "REC_IMG_EXT0_SEC30", + "description": "REC_IMG_EXT0_SEC30 set protection for memory in range 0xF0000:0xF7FFF" + }, + { + "width": 1, + "id": "field0F0-bit31", + "name": "REC_IMG_EXT0_SEC31", + "description": "REC_IMG_EXT0_SEC31 set protection for memory in range 0xF8000:0xFFFFF" + } + ] + }, + { + "id": "field0F4", + "name": "REC_IMG_EXT1", + "description": "Bitmap mask to indicate sectors included in recovery image (sectors .Recovery image is programmed in BANK1_IFR0. But if the image size is more than 32KB, this field can be used to indicate sectors to include in recovery image.ROM will configure flash protection setting for these sectors the same as BANK1_IFR0 before exiting to user code. The protection settings are managed through CMPA.OEM_BANK1_IFR0_PROT. The lower 8 sectors are excluded from this mask to avoid conflicts with dual image boot feature.", + "offset_int": "0x00F4", + "default_value_int": "0", + "bitfields": [ + { + "width": 8 + }, + { + "width": 1, + "id": "field0F4-bit8", + "name": "REC_IMG_EXT1_SEC40", + "description": "REC_IMG_EXT1_SEC40 set protection for memory in range 0x140000:0x147FFF" + }, + { + "width": 1, + "id": "field0F4-bit9", + "name": "REC_IMG_EXT1_SEC41", + "description": "REC_IMG_EXT1_SEC41 set protection for memory in range 0x148000:0x14FFFF" + }, + { + "width": 1, + "id": "field0F4-bit10", + "name": "REC_IMG_EXT1_SEC42", + "description": "REC_IMG_EXT1_SEC42 set protection for memory in range 0x150000:0x157FFF" + }, + { + "width": 1, + "id": "field0F4-bit11", + "name": "REC_IMG_EXT1_SEC43", + "description": "REC_IMG_EXT1_SEC43 set protection for memory in range 0x158000:0x15FFFF" + }, + { + "width": 1, + "id": "field0F4-bit12", + "name": "REC_IMG_EXT1_SEC44", + "description": "REC_IMG_EXT1_SEC44 set protection for memory in range 0x160000:0x167FFF" + }, + { + "width": 1, + "id": "field0F4-bit13", + "name": "REC_IMG_EXT1_SEC45", + "description": "REC_IMG_EXT1_SEC45 set protection for memory in range 0x168000:0x16FFFF" + }, + { + "width": 1, + "id": "field0F4-bit14", + "name": "REC_IMG_EXT1_SEC46", + "description": "REC_IMG_EXT1_SEC46 set protection for memory in range 0x170000:0x177FFF" + }, + { + "width": 1, + "id": "field0F4-bit15", + "name": "REC_IMG_EXT1_SEC47", + "description": "REC_IMG_EXT1_SEC47 set protection for memory in range 0x178000:0x17FFFF" + }, + { + "width": 1, + "id": "field0F4-bit16", + "name": "REC_IMG_EXT1_SEC48", + "description": "REC_IMG_EXT1_SEC48 set protection for memory in range 0x180000:0x187FFF" + }, + { + "width": 1, + "id": "field0F4-bit17", + "name": "REC_IMG_EXT1_SEC49", + "description": "REC_IMG_EXT1_SEC49 set protection for memory in range 0x188000:0x18FFFF" + }, + { + "width": 1, + "id": "field0F4-bit18", + "name": "REC_IMG_EXT1_SEC50", + "description": "REC_IMG_EXT1_SEC50 set protection for memory in range 0x190000:0x197FFF" + }, + { + "width": 1, + "id": "field0F4-bit19", + "name": "REC_IMG_EXT1_SEC51", + "description": "REC_IMG_EXT1_SEC51 set protection for memory in range 0x198000:0x19FFFF" + }, + { + "width": 1, + "id": "field0F4-bit20", + "name": "REC_IMG_EXT1_SEC52", + "description": "REC_IMG_EXT1_SEC52 set protection for memory in range 0x1A0000:0x1A7FFF" + }, + { + "width": 1, + "id": "field0F4-bit21", + "name": "REC_IMG_EXT1_SEC53", + "description": "REC_IMG_EXT1_SEC53 set protection for memory in range 0x1A8000:0x1AFFFF" + }, + { + "width": 1, + "id": "field0F4-bit22", + "name": "REC_IMG_EXT1_SEC54", + "description": "REC_IMG_EXT1_SEC54 set protection for memory in range 0x1B0000:0x1B7FFF" + }, + { + "width": 1, + "id": "field0F4-bit23", + "name": "REC_IMG_EXT1_SEC55", + "description": "REC_IMG_EXT1_SEC55 set protection for memory in range 0x1B8000:0x1BFFFF" + }, + { + "width": 1, + "id": "field0F4-bit24", + "name": "REC_IMG_EXT1_SEC56", + "description": "REC_IMG_EXT1_SEC56 set protection for memory in range 0x1C0000:0x1C7FFF" + }, + { + "width": 1, + "id": "field0F4-bit25", + "name": "REC_IMG_EXT1_SEC57", + "description": "REC_IMG_EXT1_SEC57 set protection for memory in range 0x1C8000:0x1CFFFF" + }, + { + "width": 1, + "id": "field0F4-bit26", + "name": "REC_IMG_EXT1_SEC58", + "description": "REC_IMG_EXT0_SEC58 set protection for memory in range 0x1D0000:0x1D7FFF" + }, + { + "width": 1, + "id": "field0F4-bit27", + "name": "REC_IMG_EXT1_SEC59", + "description": "REC_IMG_EXT0_SEC59 set protection for memory in range 0x1D8000:0x1DFFFF" + }, + { + "width": 1, + "id": "field0F4-bit28", + "name": "REC_IMG_EXT1_SEC60", + "description": "REC_IMG_EXT0_SEC60 set protection for memory in range 0x1E0000:0x1E7FFF" + }, + { + "width": 1, + "id": "field0F4-bit29", + "name": "REC_IMG_EXT1_SEC61", + "description": "REC_IMG_EXT0_SEC61 set protection for memory in range 0x1E8000:0x1EFFFF" + }, + { + "width": 1, + "id": "field0F4-bit30", + "name": "REC_IMG_EXT1_SEC62", + "description": "REC_IMG_EXT0_SEC62 set protection for memory in range 0x1F0000:0x1F7FFF" + }, + { + "width": 1, + "id": "field0F4-bit31", + "name": "REC_IMG_EXT1_SEC63", + "description": "REC_IMG_EXT0_SEC63 set protection for memory in range 0x1F8000:0x1FFFFF" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 000F8-0011C", + "description": "Reserved 000F8-0011C" + }, + "registers": [ + { + "id": "Reserved000F8", + "name": "Reserved 0x000F8", + "description": "This field is reserved for internal use", + "offset_int": "0x00F8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved000FC", + "name": "Reserved 0x000FC", + "description": "This field is reserved for internal use", + "offset_int": "0x00FC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00100", + "name": "Reserved 0x00100", + "description": "This field is reserved for internal use", + "offset_int": "0x0100", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00104", + "name": "Reserved 0x00104", + "description": "This field is reserved for internal use", + "offset_int": "0x0104", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00108", + "name": "Reserved 0x00108", + "description": "This field is reserved for internal use", + "offset_int": "0x0108", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0010C", + "name": "Reserved 0x0010C", + "description": "This field is reserved for internal use", + "offset_int": "0x010C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00110", + "name": "Reserved 0x00110", + "description": "This field is reserved for internal use", + "offset_int": "0x0110", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00114", + "name": "Reserved 0x00114", + "description": "This field is reserved for internal use", + "offset_int": "0x0114", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00118", + "name": "Reserved 0x00118", + "description": "This field is reserved for internal use", + "offset_int": "0x0118", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0011C", + "name": "Reserved 0x0011C", + "description": "This field is reserved for internal use", + "offset_int": "0x011C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Quick GPIO Configuration", + "description": "Quick GPIO Configuration" + }, + "registers": [ + { + "id": "field120", + "name": "QUICK_SET_GPIO_0", + "description": "Drive GPIO 0 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_0 and QUICK_CLR_GPIO_0 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0120", + "default_value_int": "0" + }, + { + "id": "field124", + "name": "QUICK_CLR_GPIO_0", + "description": "Drive GPIO 0 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_0 and QUICK_CLR_GPIO_0 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0124", + "default_value_int": "0" + }, + { + "id": "field128", + "name": "QUICK_SET_GPIO_1", + "description": "Drive GPIO 1 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_1 and QUICK_CLR_GPIO_1 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0128", + "default_value_int": "0" + }, + { + "id": "field12C", + "name": "QUICK_CLR_GPIO_1", + "description": "Drive GPIO 1 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_1 and QUICK_CLR_GPIO_1 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x012C", + "default_value_int": "0" + }, + { + "id": "field130", + "name": "QUICK_SET_GPIO_2", + "description": "Drive GPIO 2 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_2 and QUICK_CLR_GPIO_2 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0130", + "default_value_int": "0" + }, + { + "id": "field134", + "name": "QUICK_CLR_GPIO_2", + "description": "Drive GPIO 2 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_2 and QUICK_CLR_GPIO_2 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0134", + "default_value_int": "0" + }, + { + "id": "field138", + "name": "QUICK_SET_GPIO_3", + "description": "Drive GPIO 3 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_3 and QUICK_CLR_GPIO_3 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0138", + "default_value_int": "0" + }, + { + "id": "field13C", + "name": "QUICK_CLR_GPIO_3", + "description": "Drive GPIO 3 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_3 and QUICK_CLR_GPIO_3 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x013C", + "default_value_int": "0" + }, + { + "id": "field140", + "name": "QUICK_SET_GPIO_4", + "description": "Drive GPIO 4 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_4 and QUICK_CLR_GPIO_4 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0140", + "default_value_int": "0" + }, + { + "id": "field144", + "name": "QUICK_CLR_GPIO_4", + "description": "Drive GPIO 4 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_4 and QUICK_CLR_GPIO_4 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0144", + "default_value_int": "0" + }, + { + "id": "field148", + "name": "QUICK_SET_GPIO_5", + "description": "Drive GPIO 5 port [31:0] pins high after reset. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_5 and QUICK_CLR_GPIO_5 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x0148", + "default_value_int": "0" + }, + { + "id": "field14C", + "name": "QUICK_CLR_GPIO_5", + "description": "Drive GPIO 5 port [31:0] pins low. Each bit corresponds to the pin in GPIO port 0. When set ROM drives the corresponding pin high as soon as possible. By default most pins come-up as tri-stated inputs. This feature allows customer to specify active drive pins soon after reset instead of waiting till complete boot. Note, if a pin is selected in both QUICK_SET_GPIO_5 and QUICK_CLR_GPIO_5 fields then pin will be set to high-level with quick transition to low.", + "offset_int": "0x014C", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00150-0015C", + "description": "Reserved 00150-0015C" + }, + "registers": [ + { + "id": "Reserved00150", + "name": "Reserved 0x00150", + "description": "This field is reserved for internal use", + "offset_int": "0x0150", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00154", + "name": "Reserved 0x00154", + "description": "This field is reserved for internal use", + "offset_int": "0x0154", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00158", + "name": "Reserved 0x00158", + "description": "This field is reserved for internal use", + "offset_int": "0x0158", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0015C", + "name": "Reserved 0x0015C", + "description": "This field is reserved for internal use", + "offset_int": "0x015C", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CUST_MK_SK", + "description": "CUST_MK_SK key blob" + }, + "registers": [ + { + "id": "field160", + "name": "CUST_MK_SK_KEY_BLOB0", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0160", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field164", + "name": "CUST_MK_SK_KEY_BLOB1", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0164", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field168", + "name": "CUST_MK_SK_KEY_BLOB2", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0168", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field16C", + "name": "CUST_MK_SK_KEY_BLOB3", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x016C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field170", + "name": "CUST_MK_SK_KEY_BLOB4", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0170", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field174", + "name": "CUST_MK_SK_KEY_BLOB5", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0174", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field178", + "name": "CUST_MK_SK_KEY_BLOB6", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0178", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field17C", + "name": "CUST_MK_SK_KEY_BLOB7", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x017C", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field180", + "name": "CUST_MK_SK_KEY_BLOB8", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0180", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field184", + "name": "CUST_MK_SK_KEY_BLOB9", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0184", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field188", + "name": "CUST_MK_SK_KEY_BLOB10", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x0188", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field18C", + "name": "CUST_MK_SK_KEY_BLOB11", + "description": "CUST_MK_SK is stored in form of RFC3394 blob and it is used by bootloader to decrypt SB3.1 encryption key during processing of SB file by bootloader. CUST_MK_SK is generated during device provisioning process by HSM_KEY_GEN (random key) or by HSM_STORE_KEY (user defined key) commands. To store this key into CMPA, SB_STORE_KEY command should be used.", + "offset_int": "0x018C", + "access": "RO", + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "Reserved 00190-001E8", + "description": "Reserved 00190-001E8" + }, + "registers": [ + { + "id": "Reserved00190", + "name": "Reserved 0x00190", + "description": "This field is reserved for internal use", + "offset_int": "0x0190", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00194", + "name": "Reserved 0x00194", + "description": "This field is reserved for internal use", + "offset_int": "0x0194", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved00198", + "name": "Reserved 0x00198", + "description": "This field is reserved for internal use", + "offset_int": "0x0198", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved0019C", + "name": "Reserved 0x0019C", + "description": "This field is reserved for internal use", + "offset_int": "0x019C", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A0", + "name": "Reserved 0x001A0", + "description": "This field is reserved for internal use", + "offset_int": "0x01A0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A4", + "name": "Reserved 0x001A4", + "description": "This field is reserved for internal use", + "offset_int": "0x01A4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001A8", + "name": "Reserved 0x001A8", + "description": "This field is reserved for internal use", + "offset_int": "0x01A8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001AC", + "name": "Reserved 0x001AC", + "description": "This field is reserved for internal use", + "offset_int": "0x01AC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B0", + "name": "Reserved 0x001B0", + "description": "This field is reserved for internal use", + "offset_int": "0x01B0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B4", + "name": "Reserved 0x001B4", + "description": "This field is reserved for internal use", + "offset_int": "0x01B4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001B8", + "name": "Reserved 0x001B8", + "description": "This field is reserved for internal use", + "offset_int": "0x01B8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001BC", + "name": "Reserved 0x001BC", + "description": "This field is reserved for internal use", + "offset_int": "0x01BC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C0", + "name": "Reserved 0x001C0", + "description": "This field is reserved for internal use", + "offset_int": "0x01C0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C4", + "name": "Reserved 0x001C4", + "description": "This field is reserved for internal use", + "offset_int": "0x01C4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001C8", + "name": "Reserved 0x001C8", + "description": "This field is reserved for internal use", + "offset_int": "0x01C8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001CC", + "name": "Reserved 0x001CC", + "description": "This field is reserved for internal use", + "offset_int": "0x01CC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D0", + "name": "Reserved 0x001D0", + "description": "This field is reserved for internal use", + "offset_int": "0x01D0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D4", + "name": "Reserved 0x001D4", + "description": "This field is reserved for internal use", + "offset_int": "0x01D4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001D8", + "name": "Reserved 0x001D8", + "description": "This field is reserved for internal use", + "offset_int": "0x01D8", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001DC", + "name": "Reserved 0x001DC", + "description": "This field is reserved for internal use", + "offset_int": "0x01DC", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E0", + "name": "Reserved 0x001E0", + "description": "This field is reserved for internal use", + "offset_int": "0x01E0", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E4", + "name": "Reserved 0x001E4", + "description": "This field is reserved for internal use", + "offset_int": "0x01E4", + "is_reserved": true, + "default_value_int": "0" + }, + { + "id": "Reserved001E8", + "name": "Reserved 0x001E8", + "description": "This field is reserved for internal use", + "offset_int": "0x01E8", + "is_reserved": true, + "default_value_int": "0" + } + ] + }, + { + "group": { + "name": "CRC - CMAC", + "description": "CRC32 and CMAC CMPA securing" + }, + "registers": [ + { + "id": "field1EC", + "name": "CMPA_CRC32", + "description": "CRC32 of CMPA page data from offset . ROM updates this field along with CMPA_CMAC. ROM uses this field based on CMPA.LP_SEC_BOOT field option.", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F0", + "name": "CMPA_CMAC0", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F4", + "name": "CMPA_CMAC1", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1F8", + "name": "CMPA_CMAC2", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0" + }, + { + "id": "field1FC", + "name": "CMPA_CMAC3", + "description": "CMAC[31:0] of CMPA page data from offset . ROM updates this field on subsequent boot after page update.", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0" + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a0.json new file mode 100644 index 0000000..4e54fc7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a0.json @@ -0,0 +1,1525 @@ +{ + "cpu": "mcxn946", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "description": "TrustZone register - Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "description": "TrustZone register - Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 0 (flash01_mem_rule0)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 0 (flash01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 1 (flash01_mem_rule1)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 1 (flash01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 2 (flash01_mem_rule2)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 2 (flash01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 3 (flash01_mem_rule3)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 3 (flash01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "FLASH 02 Memory Rule Register (flash02_mem_rule)", + "description": "TrustZone register - FLASH 02 Memory Rule Register (flash02_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "FLASH 03 Memory Rule Register (flash03_mem_rule)", + "description": "TrustZone register - FLASH 03 Memory Rule Register (flash03_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "description": "TrustZone register - RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "description": "TrustZone register - RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "description": "TrustZone register - RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAMA Memory Rule Register (rama_mem_rule)", + "description": "TrustZone register - RAMA Memory Rule Register (rama_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAMB Memory Rule Register (ramb_mem_rule)", + "description": "TrustZone register - RAMB Memory Rule Register (ramb_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "description": "TrustZone register - RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "description": "TrustZone register - RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "description": "TrustZone register - RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "description": "TrustZone register - RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAME Memory Rule Register 0 (rame_mem_rule0)", + "description": "TrustZone register - RAME Memory Rule Register 0 (rame_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAME Memory Rule Register 1 (rame_mem_rule1)", + "description": "TrustZone register - RAME Memory Rule Register 1 (rame_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAMF Memory Rule Register 0 (ramf_mem_rule0)", + "description": "TrustZone register - RAMF Memory Rule Register 0 (ramf_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAMF Memory Rule Register 1 (ramf_mem_rule1)", + "description": "TrustZone register - RAMF Memory Rule Register 1 (ramf_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAMG Memory Rule Register 0 (ramg_mem_rule0)", + "description": "TrustZone register - RAMG Memory Rule Register 0 (ramg_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAMG Memory Rule Register 1 (ramg_mem_rule1)", + "description": "TrustZone register - RAMG Memory Rule Register 1 (ramg_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAMH Memory Rule Register 0 (ramh_mem_rule0)", + "description": "TrustZone register - RAMH Memory Rule Register 0 (ramh_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "description": "TrustZone register - AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "default_value_int": "0x3333" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 0 (fspi0_reg0_mem_rule0)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 0 (fspi0_reg0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 1 (fspi0_reg0_mem_rule1)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 1 (fspi0_reg0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 2 (fspi0_reg0_mem_rule2)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 2 (fspi0_reg0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 3 (fspi0_reg0_mem_rule3)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 3 (fspi0_reg0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "FLEXSPI0 Region 1 Memory Rule Register (fspi0_reg1_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 1 Memory Rule Register (fspi0_reg1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "FLEXSPI0 Region 2 Memory Rule Register (fspi0_reg2_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 2 Memory Rule Register (fspi0_reg2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "FLEXSPI0 Region 3 Memory Rule Register (fspi0_reg3_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 3 Memory Rule Register (fspi0_reg3_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "FLEXSPI0 Region 4 Memory Rule Register (fspi0_reg4_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 4 Memory Rule Register (fspi0_reg4_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "FLEXSPI0 Region 5 Memory Rule Register (fspi0_reg5_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 5 Memory Rule Register (fspi0_reg5_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "FLEXSPI0 Region 6 Memory Rule Register (fspi0_reg6_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 6 Memory Rule Register (fspi0_reg6_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 0 (fspi0_reg7_mem_rule0)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 0 (fspi0_reg7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 1 (fspi0_reg7_mem_rule1)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 1 (fspi0_reg7_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 2 (fspi0_reg7_mem_rule2)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 2 (fspi0_reg7_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 3 (fspi0_reg7_mem_rule3)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 3 (fspi0_reg7_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "FLEXSPI0 Region 8 Memory Rule Register (fspi0_reg8_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 8 Memory Rule Register (fspi0_reg8_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "FLEXSPI0 Region 9 Memory Rule Register (fspi0_reg9_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 9 Memory Rule Register (fspi0_reg9_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "FLEXSPI0 Region 10 Memory Rule Register (fspi0_reg10_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 10 Memory Rule Register (fspi0_reg10_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "FLEXSPI0 Region 11 Memory Rule Register (fspi0_reg11_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 11 Memory Rule Register (fspi0_reg11_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "FLEXSPI0 Region 12 Memory Rule Register (fspi0_reg12_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 12 Memory Rule Register (fspi0_reg12_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "FLEXSPI0 Region 13 Memory Rule Register (fspi0_reg13_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 13 Memory Rule Register (fspi0_reg13_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "description": "TrustZone register - Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "description": "TrustZone register - Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "Secure GPIO Mask Register 2 (sec_gpio_mask2)", + "description": "TrustZone register - Secure GPIO Mask Register 2 (sec_gpio_mask2)", + "default_value_int": "0xfff" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "Secure GPIO Mask Register 3 (sec_gpio_mask3)", + "description": "TrustZone register - Secure GPIO Mask Register 3 (sec_gpio_mask3)", + "default_value_int": "0xffffff" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "Secure GPIO Mask Register 4 (sec_gpio_mask4)", + "description": "TrustZone register - Secure GPIO Mask Register 4 (sec_gpio_mask4)", + "default_value_int": "0xffffff" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask5)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask5)", + "default_value_int": "0x3ff" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask6)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask6)", + "default_value_int": "0xffffffff" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask7)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask7)", + "default_value_int": "0xffffffff" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask8)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask8)", + "default_value_int": "0xffffffff" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask9)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask9)", + "default_value_int": "0xffffffff" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask10)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask10)", + "default_value_int": "0xfffffff" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "description": "TrustZone register - Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "default_value_int": "0x2aaaaa" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "CM33 Lock Control Register 0 (cm33_lock_reg0)", + "description": "TrustZone register - CM33 Lock Control Register 0 (cm33_lock_reg0)", + "default_value_int": "0x800002aa" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "CM33 Lock Control Register 1 (cm33_lock_reg1)", + "description": "TrustZone register - CM33 Lock Control Register 1 (cm33_lock_reg1)", + "default_value_int": "0x800002aa" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "description": "TrustZone register - MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "default_value_int": "0x6600" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "description": "TrustZone register - MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "default_value_int": "0x5500" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "description": "TrustZone register - MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "default_value_int": "0x1100" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 4 (mbc0_dom0_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC Memory Block Configuration Word 4 (mbc0_dom0_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 5 (mbc0_dom0_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC Memory Block Configuration Word 5 (mbc0_dom0_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 6 (mbc0_dom0_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC Memory Block Configuration Word 6 (mbc0_dom0_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 7 (mbc0_dom0_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC Memory Block Configuration Word 7 (mbc0_dom0_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "ITRC ELS_RESET Trigger source selector register 0 (itrc_els_reset_out1_sel0)", + "description": "TrustZone register - ITRC ELS_RESET Trigger source selector register 0 (itrc_els_reset_out1_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "ITRC ELS_RESET Trigger source selector register 1 (itrc_els_reset_out1_sel1)", + "description": "TrustZone register - ITRC ELS_RESET Trigger source selector register 1 (itrc_els_reset_out1_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "default_value_int": "0xaaaaaaaa" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a1.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a1.json new file mode 100644 index 0000000..77a86f5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn946/tz_a1.json @@ -0,0 +1,1973 @@ +{ + "cpu": "mcxn946", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "description": "TrustZone register - Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "description": "TrustZone register - Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 0 (flash00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 1 (flash00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 2 (flash00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "description": "TrustZone register - FLASH 00 Memory Rule Register 3 (flash00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 0 (flash01_mem_rule0)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 0 (flash01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 1 (flash01_mem_rule1)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 1 (flash01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 2 (flash01_mem_rule2)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 2 (flash01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "FLASH 01 Memory Rule Register 3 (flash01_mem_rule3)", + "description": "TrustZone register - FLASH 01 Memory Rule Register 3 (flash01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "FLASH 02 Memory Rule Register (flash02_mem_rule)", + "description": "TrustZone register - FLASH 02 Memory Rule Register (flash02_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "FLASH 03 Memory Rule Register (flash03_mem_rule)", + "description": "TrustZone register - FLASH 03 Memory Rule Register (flash03_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "description": "TrustZone register - RAMX Memory Rule Register 1 (ramx_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "description": "TrustZone register - RAMX Memory Rule Register 2 (ramx_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "description": "TrustZone register - RAMX Memory Rule Register 3 (ramx_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAMA Memory Rule Register (rama_mem_rule)", + "description": "TrustZone register - RAMA Memory Rule Register (rama_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAMB Memory Rule Register (ramb_mem_rule)", + "description": "TrustZone register - RAMB Memory Rule Register (ramb_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "description": "TrustZone register - RAMC Memory Rule Register 0 (ramc_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "description": "TrustZone register - RAMC Memory Rule Register 1 (ramc_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "description": "TrustZone register - RAMD Memory Rule Register 0 (ramd_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "description": "TrustZone register - RAMD Memory Rule Register 1 (ramd_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAME Memory Rule Register 0 (rame_mem_rule0)", + "description": "TrustZone register - RAME Memory Rule Register 0 (rame_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAME Memory Rule Register 1 (rame_mem_rule1)", + "description": "TrustZone register - RAME Memory Rule Register 1 (rame_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAMF Memory Rule Register 0 (ramf_mem_rule0)", + "description": "TrustZone register - RAMF Memory Rule Register 0 (ramf_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAMF Memory Rule Register 1 (ramf_mem_rule1)", + "description": "TrustZone register - RAMF Memory Rule Register 1 (ramf_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAMG Memory Rule Register 0 (ramg_mem_rule0)", + "description": "TrustZone register - RAMG Memory Rule Register 0 (ramg_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAMG Memory Rule Register 1 (ramg_mem_rule1)", + "description": "TrustZone register - RAMG Memory Rule Register 1 (ramg_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAMH Memory Rule Register 0 (ramh_mem_rule0)", + "description": "TrustZone register - RAMH Memory Rule Register 0 (ramh_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 0 (apb_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 1 (apb_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 2 (apb_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "description": "TrustZone register - APB Bridge 0 Memory Rule Register 3 (apb_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 0 (apb_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 1 (apb_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "description": "TrustZone register - APB Bridge 1 Memory Rule Register 2 (apb_bridge1_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 2 (aips_bridge0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 0 Peripherals Memory Rule Register 3 (aips_bridge0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 0 (ahb_periph0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 1 (ahb_periph0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 0 Memory Rule Register 2 (ahb_periph0_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 1 Peripherals Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 0 (ahb_periph1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 1 (ahb_periph1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "description": "TrustZone register - AHB Peripherals 1 Memory Rule Register 2 (ahb_periph1_mem_rule2)", + "default_value_int": "0x3" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 0 (aips_bridge2_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 2 Peripherals Memory Rule Register 1 (aips_bridge2_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 0 (aips_bridge3_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 1 (aips_bridge3_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 2 (aips_bridge3_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 3 Peripherals Memory Rule Register 3 (aips_bridge3_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 0 (aips_bridge4_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 1 (aips_bridge4_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 2 (aips_bridge4_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "description": "TrustZone register - AIPS BRIDGE 4 Peripherals Memory Rule Register 3 (aips_bridge4_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "description": "TrustZone register - AHB Secure Controller Peripheral Rule Register (ahb_sec_ctrl_periph_rule)", + "default_value_int": "0x3333" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 0 (fspi0_reg0_mem_rule0)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 0 (fspi0_reg0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 1 (fspi0_reg0_mem_rule1)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 1 (fspi0_reg0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 2 (fspi0_reg0_mem_rule2)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 2 (fspi0_reg0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "FLEXSPI0 Region 0 Memory Rule Register 3 (fspi0_reg0_mem_rule3)", + "description": "TrustZone register - FLEXSPI0 Region 0 Memory Rule Register 3 (fspi0_reg0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "FLEXSPI0 Region 1 Memory Rule Register (fspi0_reg1_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 1 Memory Rule Register (fspi0_reg1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "FLEXSPI0 Region 2 Memory Rule Register (fspi0_reg2_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 2 Memory Rule Register (fspi0_reg2_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "FLEXSPI0 Region 3 Memory Rule Register (fspi0_reg3_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 3 Memory Rule Register (fspi0_reg3_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "FLEXSPI0 Region 4 Memory Rule Register (fspi0_reg4_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 4 Memory Rule Register (fspi0_reg4_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "FLEXSPI0 Region 5 Memory Rule Register (fspi0_reg5_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 5 Memory Rule Register (fspi0_reg5_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "FLEXSPI0 Region 6 Memory Rule Register (fspi0_reg6_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 6 Memory Rule Register (fspi0_reg6_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 0 (fspi0_reg7_mem_rule0)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 0 (fspi0_reg7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 1 (fspi0_reg7_mem_rule1)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 1 (fspi0_reg7_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 2 (fspi0_reg7_mem_rule2)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 2 (fspi0_reg7_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "FLEXSPI0 Region 7 Memory Rule Register 3 (fspi0_reg7_mem_rule3)", + "description": "TrustZone register - FLEXSPI0 Region 7 Memory Rule Register 3 (fspi0_reg7_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "FLEXSPI0 Region 8 Memory Rule Register (fspi0_reg8_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 8 Memory Rule Register (fspi0_reg8_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "FLEXSPI0 Region 9 Memory Rule Register (fspi0_reg9_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 9 Memory Rule Register (fspi0_reg9_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "FLEXSPI0 Region 10 Memory Rule Register (fspi0_reg10_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 10 Memory Rule Register (fspi0_reg10_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "FLEXSPI0 Region 11 Memory Rule Register (fspi0_reg11_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 11 Memory Rule Register (fspi0_reg11_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "FLEXSPI0 Region 12 Memory Rule Register (fspi0_reg12_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 12 Memory Rule Register (fspi0_reg12_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "FLEXSPI0 Region 13 Memory Rule Register (fspi0_reg13_mem_rule)", + "description": "TrustZone register - FLEXSPI0 Region 13 Memory Rule Register (fspi0_reg13_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "Secure GPIO PINT Mask Register 0 (sec_gpio_pint_mask0)", + "description": "TrustZone register - Secure GPIO PINT Mask Register 0 (sec_gpio_pint_mask0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "Secure GPIO PINT Mask Register 1 (sec_gpio_pint_mask1)", + "description": "TrustZone register - Secure GPIO PINT Mask Register 1 (sec_gpio_pint_mask1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 0 (sec_int_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 1 (sec_int_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 2 (sec_int_reg2)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 2 (sec_int_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 3 (sec_int_reg3)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 3 (sec_int_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "Secure Interrupt Mask for CPU1 Register 4 (sec_int_reg4)", + "description": "TrustZone register - Secure Interrupt Mask for CPU1 Register 4 (sec_int_reg4)", + "default_value_int": "0xfffffff" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "description": "TrustZone register - Secure GPIO Mask Lock Register 2 (sec_mask_lock)", + "default_value_int": "0x2aaaaa" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "CM33 Lock Control Register 0 (cm33_lock_reg0)", + "description": "TrustZone register - CM33 Lock Control Register 0 (cm33_lock_reg0)", + "default_value_int": "0x800002aa" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "CM33 Lock Control Register 1 (cm33_lock_reg1)", + "description": "TrustZone register - CM33 Lock Control Register 1 (cm33_lock_reg1)", + "default_value_int": "0x800002aa" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x86aa" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "description": "TrustZone register - MBC Global Access Control Register 0 (mbc0_memn_glbac0)", + "default_value_int": "0x7777" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "description": "TrustZone register - MBC Global Access Control Register 4 (mbc0_memn_glbac4)", + "default_value_int": "0x5500" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "description": "TrustZone register - MBC Global Access Control Register 5 (mbc0_memn_glbac5)", + "default_value_int": "0x1100" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "description": "TrustZone register - MBC Memory Block Configuration Word 0 (mbc0_dom0_mem0_blk_cfg_w0)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "description": "TrustZone register - MBC Memory Block Configuration Word 1 (mbc0_dom0_mem0_blk_cfg_w1)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "description": "TrustZone register - MBC Memory Block Configuration Word 2 (mbc0_dom0_mem0_blk_cfg_w2)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "description": "TrustZone register - MBC Memory Block Configuration Word 3 (mbc0_dom0_mem0_blk_cfg_w3)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 4 (mbc0_dom0_mem0_blk_cfg_w4)", + "description": "TrustZone register - MBC Memory Block Configuration Word 4 (mbc0_dom0_mem0_blk_cfg_w4)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 5 (mbc0_dom0_mem0_blk_cfg_w5)", + "description": "TrustZone register - MBC Memory Block Configuration Word 5 (mbc0_dom0_mem0_blk_cfg_w5)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 6 (mbc0_dom0_mem0_blk_cfg_w6)", + "description": "TrustZone register - MBC Memory Block Configuration Word 6 (mbc0_dom0_mem0_blk_cfg_w6)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "MBC Memory Block Configuration Word 7 (mbc0_dom0_mem0_blk_cfg_w7)", + "description": "TrustZone register - MBC Memory Block Configuration Word 7 (mbc0_dom0_mem0_blk_cfg_w7)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "default_value_int": "0xa0002aaa" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "description": "TrustZone register - GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "description": "TrustZone register - GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "GPIO0 Lock Register (gpio0_lock)", + "description": "TrustZone register - GPIO0 Lock Register (gpio0_lock)", + "default_value_int": "0xf" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "description": "TrustZone register - GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "description": "TrustZone register - GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "GPIO1 Lock Register (gpio1_lock)", + "description": "TrustZone register - GPIO1 Lock Register (gpio1_lock)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "description": "TrustZone register - GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "description": "TrustZone register - GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "GPIO2 Lock Register (gpio2_lock)", + "description": "TrustZone register - GPIO2 Lock Register (gpio2_lock)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "description": "TrustZone register - GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Privilege (gpio3_pcnp)", + "description": "TrustZone register - GPIO3 Pin Control Non-Privilege (gpio3_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "GPIO3 Lock Register (gpio3_lock)", + "description": "TrustZone register - GPIO3 Lock Register (gpio3_lock)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "description": "TrustZone register - GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "description": "TrustZone register - GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "GPIO4 Lock Register (gpio4_lock)", + "description": "TrustZone register - GPIO4 Lock Register (gpio4_lock)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "description": "TrustZone register - GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "description": "TrustZone register - GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "GPIO5 Lock Register (gpio5_lock)", + "description": "TrustZone register - GPIO5 Lock Register (gpio5_lock)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn947/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn947/database.yaml new file mode 100644 index 0000000..ba46e47 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxn947/database.yaml @@ -0,0 +1,47 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxn946 + +# General MCU information +info: + spsdk_predecessor_name: mcxn94x + memory_map: # Memory map basic info + internal-flash_ns: + start_int: "0x0" + size_int: "0x200000" + external: false + flexspi_ns: + start_int: "0x80000000" + size_int: "0x8000000" + external: true + flexspi_s: + start_int: "0x90000000" + size_int: "0x8000000" + external: true + mirror_of: flexspi_ns + internal-flash_s: + start_int: "0x10000000" + size_int: "0x200000" + external: false + mirror_of: internal-flash_ns + sram: + start_int: "0x20000000" + size_int: "0x68000" + external: false + non_xip_type: int_ram + sramx: + start_int: "0x4000000" + size_int: "0x18000" + external: false + __comment: Does not work as target `onchip RAM` memory + ifr-bank1_ns: + start_int: "0x1008000" + size_int: "0x8000" + external: false + ifr-bank1_s: + start_int: "0x11008000" + size_int: "0x8000" + external: false + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw235/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw235/database.yaml new file mode 100644 index 0000000..8448faa --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw235/database.yaml @@ -0,0 +1,37 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mcxw236 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Connectivity MCUs + # Web page of MCU representative + web: https://www.nxp.com + memory_map: + # Memory map basic info + internal-flash_ns: + start_int: 0x0 + size_int: 0xFE000 + external: false + internal-flash_s: + start_int: 0x10000000 + size_int: 0xFE000 + external: false + mirror_of: internal-flash_ns + sram: + start_int: 0x20004000 + size_int: 0x1C000 + external: false + sramx: + start_int: 0x4000000 + size_int: 0x4000 + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/database.yaml new file mode 100644 index 0000000..9203956 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/database.yaml @@ -0,0 +1,182 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Connectivity MCUs + # Web page of MCU representative + web: https://www.nxp.com + memory_map: + # Memory map basic info + internal-flash_ns: + start_int: 0x0 + size_int: 0xFE000 + external: false + internal-flash_s: + start_int: 0x10000000 + size_int: 0xFE000 + external: false + mirror_of: internal-flash_ns + sram: + start_int: 0x20004000 + size_int: 0x1C000 + external: false + sramx: + start_int: 0x4000000 + size_int: 0x4000 + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_4000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0xF_E000 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x10_4000 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + computed_fields: + field008: # DCFG_CC_SOCU_PIN + field008-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field00C: # DCFG_CC_SOCU_DFLT + field00C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cfpa.json new file mode 100644 index 0000000..107325f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cfpa.json @@ -0,0 +1,1523 @@ +{ + "cpu": "mcxw236", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "CFPA header field", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "CFPA version number", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Debug vendor usage field", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "DBG_VENDOR_USAGE." + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00030-0007C", + "description": "Reserved 00030-0007C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field080", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0088", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x008C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C0", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C4", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C8", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0CC", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D0", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D4", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D8", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0DC", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00DC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E0", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E4", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E8", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0EC", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00EC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F0", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00F0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F4", + "name": "CUSTOMER_DEFINED29", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00F4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F8", + "name": "CUSTOMER_DEFINED30", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00F8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0FC", + "name": "CUSTOMER_DEFINED31", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00FC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field100", + "name": "CUSTOMER_DEFINED32", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0100", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field104", + "name": "CUSTOMER_DEFINED33", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0104", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field108", + "name": "CUSTOMER_DEFINED34", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0108", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field10C", + "name": "CUSTOMER_DEFINED35", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x010C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field110", + "name": "CUSTOMER_DEFINED36", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0110", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field114", + "name": "CUSTOMER_DEFINED37", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0114", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field118", + "name": "CUSTOMER_DEFINED38", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0118", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field11C", + "name": "CUSTOMER_DEFINED39", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x011C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field120", + "name": "CUSTOMER_DEFINED40", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0120", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field124", + "name": "CUSTOMER_DEFINED41", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0124", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field128", + "name": "CUSTOMER_DEFINED42", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0128", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field12C", + "name": "CUSTOMER_DEFINED43", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x012C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field130", + "name": "CUSTOMER_DEFINED44", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0130", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field134", + "name": "CUSTOMER_DEFINED45", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0134", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field138", + "name": "CUSTOMER_DEFINED46", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0138", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field13C", + "name": "CUSTOMER_DEFINED47", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x013C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field140", + "name": "CUSTOMER_DEFINED48", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0140", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field144", + "name": "CUSTOMER_DEFINED49", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0144", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field148", + "name": "CUSTOMER_DEFINED50", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0148", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field14C", + "name": "CUSTOMER_DEFINED51", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x014C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field150", + "name": "CUSTOMER_DEFINED52", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0150", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field154", + "name": "CUSTOMER_DEFINED53", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0154", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field158", + "name": "CUSTOMER_DEFINED54", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0158", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field15C", + "name": "CUSTOMER_DEFINED55", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x015C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field160", + "name": "CUSTOMER_DEFINED56", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0160", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field164", + "name": "CUSTOMER_DEFINED57", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0164", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field168", + "name": "CUSTOMER_DEFINED58", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0168", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field16C", + "name": "CUSTOMER_DEFINED59", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x016C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field170", + "name": "CUSTOMER_DEFINED60", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0170", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field174", + "name": "CUSTOMER_DEFINED61", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0174", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field178", + "name": "CUSTOMER_DEFINED62", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0178", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field17C", + "name": "CUSTOMER_DEFINED63", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field180", + "name": "CUSTOMER_DEFINED64", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0180", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field184", + "name": "CUSTOMER_DEFINED65", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0184", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field188", + "name": "CUSTOMER_DEFINED66", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0188", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field18C", + "name": "CUSTOMER_DEFINED67", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x018C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field190", + "name": "CUSTOMER_DEFINED68", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field194", + "name": "CUSTOMER_DEFINED69", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0194", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field198", + "name": "CUSTOMER_DEFINED70", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0198", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field19C", + "name": "CUSTOMER_DEFINED71", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x019C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A0", + "name": "CUSTOMER_DEFINED72", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A4", + "name": "CUSTOMER_DEFINED73", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1A8", + "name": "CUSTOMER_DEFINED74", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1AC", + "name": "CUSTOMER_DEFINED75", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B0", + "name": "CUSTOMER_DEFINED76", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B4", + "name": "CUSTOMER_DEFINED77", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1B8", + "name": "CUSTOMER_DEFINED78", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1BC", + "name": "CUSTOMER_DEFINED79", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C0", + "name": "CUSTOMER_DEFINED80", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C4", + "name": "CUSTOMER_DEFINED81", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1C8", + "name": "CUSTOMER_DEFINED82", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1CC", + "name": "CUSTOMER_DEFINED83", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D0", + "name": "CUSTOMER_DEFINED84", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D4", + "name": "CUSTOMER_DEFINED85", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1D8", + "name": "CUSTOMER_DEFINED86", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1DC", + "name": "CUSTOMER_DEFINED87", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x01DC", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "SHA256_DIGEST", + "description": "SHA256_DIGEST" + }, + "registers": [ + { + "id": "field1E0", + "name": "SHA256_DIGEST0", + "description": "SHA256_DIGEST0 for DIGEST[31:0]", + "offset_int": "0x01E0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E4", + "name": "SHA256_DIGEST1", + "description": "SHA256_DIGEST1 for DIGEST[63:32]", + "offset_int": "0x01E4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1E8", + "name": "SHA256_DIGEST2", + "description": "SHA256_DIGEST2 for DIGEST[95:64]", + "offset_int": "0x01E8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1EC", + "name": "SHA256_DIGEST3", + "description": "SHA256_DIGEST3 for DIGEST[127:96]", + "offset_int": "0x01EC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F0", + "name": "SHA256_DIGEST4", + "description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cmpa.json new file mode 100644 index 0000000..6171f13 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/pfr_cmpa.json @@ -0,0 +1,4261 @@ +{ + "cpu": "MCXW236", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_12MHZ", + "value": 1, + "description": "12MHz FRO" + }, + { + "name": "FRO_32MHZ", + "value": 2, + "description": "32MHz FRO" + } + ] + }, + { + "width": 15 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and number of the pin to use for indicating failure reason. \nThe toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field008-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field008-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field008-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field00C", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field00C-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field00C-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field010", + "name": "VENDOR_USAGE", + "description": "Field.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field014", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RSA4K", + "description": "Use RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "Allow RSA2048 and higher" + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "RSA4096 only" + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "RSA4096 only" + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "RSA4096 only" + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field014-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field014-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field014-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits16-17", + "name": "SKIP_BOOT_SEED", + "description": "Skip boot seed computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable BOOT_SEED" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable BOOT_SEED" + } + ] + }, + { + "width": 2, + "id": "field014-bits18-19", + "name": "BOOT_SEED_INC_NXP_CFG", + "description": "Include NXP area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits20-21", + "name": "BOOT_SEED_CUST_CFG", + "description": "Include Customer factory area (including keys) in BOOT SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits22-23", + "name": "BOOT_SEED_INC_SEC_EPOCH", + "description": "Include security EPOCH in BOOT_SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field014-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field01C", + "name": "PRINCE_CFG", + "description": "Prince Configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field01C-bit1", + "name": "GEE", + "description": "Global Encryption Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit5", + "name": "GDE", + "description": "Global Decryption Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit9", + "name": "SLK", + "description": "System Lock Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit13", + "name": "GLK", + "description": "Global Lock Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 18 + } + ] + }, + { + "id": "field020", + "name": "BMAPCTX0", + "description": "Bitmap Control for Memory Context 0", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field024", + "name": "BMAPCTX1", + "description": "Bitmap Control for Memory Context 1", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field028", + "name": "BMAPCTX2", + "description": "Bitmap Control for Memory Context 2", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field02C", + "name": "BMAPCTX3", + "description": "Bitmap Control for Memory Context 3", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field02C-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0004C", + "description": "Reserved 00030-0004C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "BLE", + "description": "BLE unique addressing" + }, + "registers": [ + { + "id": "field050", + "name": "BLE_UNIQUE_ADDRESS0", + "description": "Bits 31 down to 0 of the BLE Unique Address to be used when BLE_UNIQUE_ADDRESS_VALID field is equal to 0xC3A5", + "offset_int": "0x0050", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "BLE_UNIQUE_ADDRESS1", + "description": "BLE_UNIQUE_ADDRESS part 2", + "offset_int": "0x0054", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field054-bits0-15", + "name": "BLE_UNIQUE_ADDRESS_47_32", + "description": "Bits 47 down to 32 of the BLE Unique Address to be used when BLE_UNIQUE_ADDRESS_VALID field is equal to 0xC3A5" + }, + { + "width": 16, + "id": "field054-bits16-31", + "name": "BLE_UNIQUE_ADDRESS_VALID", + "description": "Use 48-bit value from BLE_UNIQUE_ADDRESS field as BLE address when this field is equal to 0xC3A5. If this field is different from 0xC3A5, check BLE_DEFAULT_ADDRESS_VALID field in NMPA to know which address to use." + } + ] + } + ] + }, + { + "group": { + "name": "FLASH_REMAP", + "description": "Flash image address remapping" + }, + "registers": [ + { + "id": "field058", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes.", + "offset_int": "0x0058", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped.", + "offset_int": "0x005C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field080", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0088", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x008C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0BC", + "name": "CUSTOMER_DEFINED15", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00BC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C0", + "name": "CUSTOMER_DEFINED16", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C4", + "name": "CUSTOMER_DEFINED17", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0C8", + "name": "CUSTOMER_DEFINED18", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00C8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0CC", + "name": "CUSTOMER_DEFINED19", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00CC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D0", + "name": "CUSTOMER_DEFINED20", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D4", + "name": "CUSTOMER_DEFINED21", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0D8", + "name": "CUSTOMER_DEFINED22", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00D8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0DC", + "name": "CUSTOMER_DEFINED23", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00DC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E0", + "name": "CUSTOMER_DEFINED24", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E4", + "name": "CUSTOMER_DEFINED25", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0E8", + "name": "CUSTOMER_DEFINED26", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00E8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0EC", + "name": "CUSTOMER_DEFINED27", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00EC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0F0", + "name": "CUSTOMER_DEFINED28", + "description": "Customer Defined (Programmable through ROM API)", + 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b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/tz.json new file mode 100644 index 0000000..4819ae4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw236/tz.json @@ -0,0 +1,861 @@ +{ + "cpu": "mcxw236", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x20000" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register(cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register(cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0xfffffe1" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x20004000" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0xefffffe1" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x1000fe00" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x1000ffe3" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x30" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x32103210" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "default_value_int": "0x3333" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "description": "TrustZone register - RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "SPIFI Slave Rule Register (spifi_slave_rule)", + "description": "TrustZone register - SPIFI Slave Rule Register (spifi_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 0 (spifi_mem_rule0)", + "description": "TrustZone register - SPIFI Memory Rule Register 0 (spifi_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 1 (spifi_mem_rule1)", + "description": "TrustZone register - SPIFI Memory Rule Register 1 (spifi_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 2 (spifi_mem_rule2)", + "description": "TrustZone register - SPIFI Memory Rule Register 2 (spifi_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 3 (spifi_mem_rule3)", + "description": "TrustZone register - SPIFI Memory Rule Register 3 (spifi_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "AHB port 7 Slave Rule Register 0 (ahb_port7_slave_rule0)", + "description": "TrustZone register - AHB port 7 Slave Rule Register 0 (ahb_port7_slave_rule0)", + "default_value_int": "0x3000000" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "AHB port 7 Slave Rule Register 1 (ahb_port7_slave_rule1)", + "description": "TrustZone register - AHB port 7 Slave Rule Register 1 (ahb_port7_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "AHB port 8 Slave Rule Register 0 (ahb_port8_slave_rule0)", + "description": "TrustZone register - AHB port 8 Slave Rule Register 0 (ahb_port8_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "AHB port 8 Slave Rule Register 1 (ahb_port8_slave_rule1)", + "description": "TrustZone register - AHB port 8 Slave Rule Register 1 (ahb_port8_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "AHB port 9 Slave Rule Register 0 (ahb_port9_slave_rule0)", + "description": "TrustZone register - AHB port 9 Slave Rule Register 0 (ahb_port9_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "AHB port 9 Slave Rule Register 1 (ahb_port9_slave_rule1)", + "description": "TrustZone register - AHB port 9 Slave Rule Register 1 (ahb_port9_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "AHB port 10 Slave Rule Register 0 (ahb_port10_slave_rule0)", + "description": "TrustZone register - AHB port 10 Slave Rule Register 0 (ahb_port10_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "AHB Memory Rule Register 0 (ahb_mem_rule0)", + "description": "TrustZone register - AHB Memory Rule Register 0 (ahb_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0x2" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x400002a9" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716a/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716a/database.yaml new file mode 100644 index 0000000..766c80d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716a/database.yaml @@ -0,0 +1,17 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: k32w148 + +# General MCU information +info: + # Web page of MCU representative + spsdk_predecessor_name: mcxw71xx + web: https://www.nxp.com/products/MCX-W71 + +features: + # ======== PFR section ======== + pfr: + romcfg: + reg_spec: ifr_romcfg_a2.json diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716c/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716c/database.yaml new file mode 100644 index 0000000..7400a7f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw716c/database.yaml @@ -0,0 +1,11 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw45b41z8 + +# General MCU information +info: + # Web page of MCU representative + spsdk_predecessor_name: mcxw71xx + web: https://www.nxp.com/products/MCX-W71 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727a/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727a/database.yaml new file mode 100644 index 0000000..767625d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727a/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + # Web page of MCU representative + web: https://www.nxp.com/products/MCX-W72 + use_in_doc: True # Include this MCU in generated documentation + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727c/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727c/database.yaml new file mode 100644 index 0000000..767625d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727c/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + # Web page of MCU representative + web: https://www.nxp.com/products/MCX-W72 + use_in_doc: True # Include this MCU in generated documentation + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727d/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727d/database.yaml new file mode 100644 index 0000000..767625d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mcxw727d/database.yaml @@ -0,0 +1,21 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: kw47b42zb7 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + # Web page of MCU representative + web: https://www.nxp.com/products/MCX-W72 + use_in_doc: True # Include this MCU in generated documentation + memory_map: # Memory map basic info + internal-flash: + start_int: "0x0" + size_int: "0x20_0000" + external: false + sram: + start_int: "0x2000_0000" + size_int: "0x4_2000" + external: false diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx28/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx28/database.yaml new file mode 100644 index 0000000..571152f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx28/database.yaml @@ -0,0 +1,29 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx28 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx28-processors:IMX28_FAMILY + memory_map: {} + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x15a2 + pid: 0x007D + protocol_params: + no_cmd: False + hid_ep1: False + hid_pack_size: 1024 + +features: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8dxl/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8dxl/database.yaml new file mode 100644 index 0000000..c4d9b26 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8dxl/database.yaml @@ -0,0 +1,116 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX8 + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8380_0000 # comm buffer in DDR + size: 0x20000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== AHAB section ======== + ahab: + valid_offset_minimal_alignment: 0x400 + containers_max_cnt: 3 + oem_images_max_cnt: 8 + container_types: [1] # Supported container types + core_ids: + CORTEX_M4: [1, "cortex-m4", "Cortex M4"] + CORTEX_A35: [2, "cortex-a35", "Cortex A35"] + ELE: [0x06, seco, SECO core] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + ele: + ELE: [0x06, seco, SECO Image] + v2x: + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + ddr_alignments: [0x8000, 0x4000, 0x8000, 0] + ddr_fw_alignment: 0x4 + ddr_image_size_alignment: 0x400 + + spl_ddr_load_address: 0x80000000 + spl_ddr_core_id: cortex-a35 + spl_ddr_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x80000000 + atf_core_id: cortex-a35 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80020000 + uboot_core_id: cortex-a35 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x96000000 + tee_core_id: cortex-a35 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + extra_images: ["spl_ddr", "atf", "uboot", "tee"] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8m/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8m/database.yaml new file mode 100644 index 0000000..002b45e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8m/database.yaml @@ -0,0 +1,28 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M + isp: + rom: + protocol: sdp + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x012B + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: {} + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mm/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mm/database.yaml new file mode 100644 index 0000000..0feed86 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mm/database.yaml @@ -0,0 +1,27 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI + isp: + rom: + protocol: sdp + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x0134 + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mn/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mn/database.yaml new file mode 100644 index 0000000..77c02be --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mn/database.yaml @@ -0,0 +1,28 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx8mn + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-nano-family-arm-cortex-a53-cortex-m7:i.MX8MNANO + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x013E + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mp/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mp/database.yaml new file mode 100644 index 0000000..31c17d1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8mp/database.yaml @@ -0,0 +1,28 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx8mp + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x0146 + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qm/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qm/database.yaml new file mode 100644 index 0000000..d4c74ab --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qm/database.yaml @@ -0,0 +1,111 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX8 + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8380_0000 # comm buffer in DDR + size: 0x20000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== AHAB section ======== + ahab: + valid_offset_minimal_alignment: 0x400 + containers_max_cnt: 3 + oem_images_max_cnt: 8 + container_types: [1] # Supported container types + core_ids: + CORTEX_M4_0: [1, "cortex-m4-0", "Cortex M4 Core 0"] + CORTEX_M4_1: [2, "cortex-m4-1", "Cortex M4 Core 1"] + CORTEX_A72: [3, "cortex-a72", "Cortex A72"] + CORTEX_A53: [4, "cortex-a53", "Cortex A53"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + DCD: [0x05, dcd, DCD Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION: [0x08, dek_validation, DEK validation Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + ele: + ELE: [0x06, seco, SECO Image] + + image_types_mapping: + ele: [6] + + # AHAB extra images + ddr_alignments: [0x8000, 0x4000, 0x8000, 0] + ddr_fw_alignment: 0x4 + ddr_image_size_alignment: 0x400 + + spl_ddr_load_address: 0x80000000 + spl_ddr_core_id: cortex-a72 + spl_ddr_meta_data_start_cpu_id: 3 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x80000000 + atf_core_id: cortex-a72 + atf_meta_data_start_cpu_id: 3 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80020000 + uboot_core_id: cortex-a72 + uboot_meta_data_start_cpu_id: 3 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x96000000 + tee_core_id: cortex-a72 + tee_meta_data_start_cpu_id: 3 + tee_image_size_alignment: 0x400 + + extra_images: ["spl_ddr", "atf", "uboot", "tee"] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qxp/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qxp/database.yaml new file mode 100644 index 0000000..37e7f89 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8qxp/database.yaml @@ -0,0 +1,109 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX8 + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8380_0000 # comm buffer in DDR + size: 0x20000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== AHAB section ======== + ahab: + valid_offset_minimal_alignment: 0x400 + containers_max_cnt: 3 + oem_images_max_cnt: 8 + container_types: [1] # Supported container types + core_ids: + CORTEX_M4: [1, "cortex-m4", "Cortex M4"] + CORTEX_A35: [2, "cortex-a35", "Cortex A35"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + DCD: [0x05, dcd, DCD Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION: [0x08, dek_validation, DEK validation Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + ele: + ELE: [0x06, seco, SECO Image] + + image_types_mapping: + ele: [6] + + # AHAB extra images + ddr_alignments: [0x8000, 0x4000, 0x8000, 0] + ddr_fw_alignment: 0x4 + ddr_image_size_alignment: 0x400 + + spl_ddr_load_address: 0x80000000 + spl_ddr_core_id: cortex-a35 + spl_ddr_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x80000000 + atf_core_id: cortex-a35 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80020000 + uboot_core_id: cortex-a35 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x96000000 + tee_core_id: cortex-a35 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + extra_images: ["spl_ddr", "atf", "uboot", "tee"] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8ulp/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8ulp/database.yaml new file mode 100644 index 0000000..2daccf4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8ulp/database.yaml @@ -0,0 +1,296 @@ +# Copyright 2023-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: {} + a2: {} +latest: a2 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx8ulp + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8ulp-applications-processor-family:i.MX8ULP + memory_map: + code-tcm_ns: + start_int: 0x0FFC0000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + code-tcm_s: + start_int: 0x1FFC0000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + system-tcm_ns: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + system-tcm_s: + start_int: 0x30000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram_ns: + start_int: 0x22020000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x32020000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + flexspi0_ns: + start_int: 0x04000000 + size_int: 0x08000000 + external: true + mirror_of: flexspi0_s + flexspi0_s: + start_int: 0x14000000 + size_int: 0x08000000 + external: true + flexspi1_ns: + start_int: 0x40000000 + size_int: 0x10000000 + external: true + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x50000000 + size_int: 0x08000000 + external: true + flexspi2_ns: + start_int: 0x60000000 + size_int: 0x10000000 + external: true + mirror_of: flexspi2_s + flexspi2_s: + start_int: 0x70000000 + size_int: 0x08000000 + external: true + dram1_ns: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram1_s: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_ns: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_s: + start_int: 0xB0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_ns: + start_int: 0xC0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_s: + start_int: 0xD0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x014B + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8000_0000 + size: 0x20000 + device: nxpele + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== DAT section ======== + dat: + socc: 0x4D580008 # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + test_address: 0x22020000 + dmbox_ap_ix: 0 + + # ======== AHAB section ======== + ahab: + containers_max_cnt: 3 + valid_offset_minimal_alignment: 0x400 + container_types: [1] # Supported container types + core_ids: + CORTEX_M33: [1, "cortex-m33", "Cortex M33"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + CORTEX_A53: [4, "cortex-a53", "Cortex A53"] + ELE: [6, "ele", "EdgeLock Enclave"] + HDMI_TX: [7, "hdmi-tx", "HDMI Tx"] + HDMI_RX: [8, "hdmi-rx", "HDMI Rx"] + + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION_FCB_CHK: + [0x08, dek_validation_fcb_chk, DEK validation FCB check Image] + ele: + ELE: [0x06, ele, EdgeLock Enclave Image] + + image_types_mapping: + ele: [6] + + # AHAB extra images + upower_load_address: 0x28300200 + upower_core_id: cortex-a53 + upower_meta_data_start_cpu_id: 0 + upower_image_size_alignment: 0x400 + + spl_load_address: 0x22020000 + spl_core_id: cortex-a55 + spl_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x20040000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 0 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 0 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0xa6000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 0 + tee_image_size_alignment: 0x400 + + mcu_load_address: 0x1ffc2000 + mcu_core_id: cortex-m33 + mcu_meta_data_start_cpu_id: 0 + mcu_image_size_alignment: 0x400 + + kernel_load_address: 0x80400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 0 + kernel_chunk_size: 0x700000 + kernel_revisions_to_split: [a0] + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x83000000 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_entry_point: 0x0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: [upower, spl, atf, uboot, tee, mcu, kernel, dtb] + + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 0 + sb_21_supported: False + has_kek_fuses: False + supports_key_scrambling: True + # TODO add fuses + additional_template: ["otfad_scramble"] + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + note: " + Connected FlexSPI0.\n + - Real time core images only\n + Connected FlexSPI2. \n + - AP image only for dual-boot configuration\n + - RT image and AP image for single-boot configuration + " + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + note: "Connected uSDHC0. \n + - AP image only for dual-boot configuration\n + - RT image and AP image for single-boot configuration" + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc_boot: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + sd: + note: "Connected uSDHC1/uSDHC2. \n + - AP image only for dual-boot configuration\n + - RT image and AP image for single-boot configuration" + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nand: + note: "Connected FlexSPI2.\n + - AP image only for dual-boot configuration\n + - RT image and AP image for single-boot configuration" + segments: + # xmcd: 0x00 TODO: add support for XMCD + primary_image_container_set: 0x400 # That should be Right behind FCB/DBBT + secondary_image_container_set: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI4/5. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_interface: uboot_fastboot + el2go_name: IMX8 + prov_method: oem_app + validation_method: max_count=16;max_total_size=16384 + uuid_fuse_index: "7 0 4" + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8x/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8x/database.yaml new file mode 100644 index 0000000..92315b5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx8x/database.yaml @@ -0,0 +1,29 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: False # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx8x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X + memory_map: {} + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x007D + protocol_params: + no_cmd: True + hid_ep1: False + hid_pack_size: 1024 + +features: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/database.yaml new file mode 100644 index 0000000..be52f9d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/database.yaml @@ -0,0 +1,243 @@ +# Copyright 2024-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx91 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/secure-energy-efficient-i-mx-91-family-brings-essential-linux-capabilities-for-thousands-of-edge-applications:i.MX91 + memory_map: + ocram_ns: + start_int: 0x20480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x30480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + dram1: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram4: + start_int: 0xB0000000 + size_int: 0x44000 + external: true + non_xip_type: ext_ram_ddr + dram5: + start_int: 0xB0044000 + size_int: 0xBC000 + external: true + non_xip_type: ext_ram_ddr + dram6: + start_int: 0xB0100000 + size_int: 0xFF00000 + external: true + non_xip_type: ext_ram_ddr + dram7: + start_int: 0xC0000000 + size_int: 0x40000000 + external: true + non_xip_type: ext_ram_ddr + isp: + rom: + protocol: sdps + interfaces: ["usb"] + usb: + - vid: 0x1FC9 + pid: 0x0159 + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 +features: + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: srkh + name: SRKH + width: 256 + reversed: True + config_as_hexstring: True + description: "SHA256 hash digest of OEM SRK public keys stored in Container" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + ] + + # ======== AHAB section ======== + ahab: + valid_offset_minimal_alignment: 0x400 + containers_max_cnt: 3 + oem_images_max_cnt: 8 + container_types: [1] # Supported container types + core_ids: + RESERVED: [1, "reserved", "Reserved Core ID"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + ELE: [6, "ele", "EdgeLock Enclave"] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + ele: + ELE: [0x06, ele, EdgeLock Enclave Image] + v2x: + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + ddr_alignments: [0x8000, 0x4000, 0x8000, 0] + ddr_fw_alignment: 0x4 + ddr_image_size_alignment: 0x400 + + spl_ddr_load_address: 0x204A0000 + spl_ddr_core_id: cortex-a55 + spl_ddr_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x204C0000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x96000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + kernel_load_address: 0x80400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 2 + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x83000000 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_entry_point: 0x0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: ["spl_ddr", "atf", "uboot", "tee", "kernel", "dtb"] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8380_0000 # comm buffer in DDR + size: 0x20000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== DAT section ======== + dat: + socc: 0x4D58005B # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + test_address: 0x2048_0000 + dmbox_ap_ix: 0 + + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc_boot: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + # flexspi_nand: + # segments: + # xmcd: 0x00 + # primary_image_container_set: 0x400 + # secondary_image_container_set: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI1/2/3/4. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # ======== nxpuuu ========== + nxpuuu: {} + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_interface: uboot_fastboot + el2go_name: IMX9 + prov_method: oem_app + validation_method: max_count=16;max_total_size=16384 + uuid_fuse_index: "6 0 4" + + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/fuses.json new file mode 100644 index 0000000..a7ab0ab --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9131/fuses.json @@ -0,0 +1,10176 @@ +{ + "cpu": "MIMX9131", + "groups": [ + { + "group": { + "name": "General", + "description": "General settings configuration" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG_LOCK", + "description": "Boot Configuration Fuse Lock for Boot_CFG 0-3 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID0 Lock - Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-12-14", + "name": "CRC_HI_LOCK", + "description": "CRC words 4,5,6 and 7 Lock field", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse2-bits-0-2", + "name": "OEM_SW_CFG_LOCK", + "description": "OEM SW Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-3-5", + "name": "ELE_OTFAD1_KEY_LOCK", + "description": "OTFAD Key Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-9-11", + "name": "ELE_JTAG_RESP_LOCK", + "description": "JTAG Response Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse2-bit-15", + "name": "BOOT2_CFG_LOCK_0", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be burned)" + }, + { + "name": "WRITE_PROTECTED", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)", + "deprecated_names": [ + "WP" + ] + } + ] + } + ] + }, + { + "id": "fuse3", + "name": "LOCK_CFG3", + "description": "LOCK_CFG3", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse3-bit-15", + "name": "BOOT2_CFG_LOCK_1", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (Fuse can be over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "OP", + "value": 1, + "description": "(Over-ride Protect, the controlled field shadow registers can not be over-written)" + } + ] + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-6-8", + "name": "ELE_MISC1_LOCK", + "description": "EdgeLock Enclave Misc. NXP Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-12-14", + "name": "ELE_OEM_SRKH_LOCK", + "description": "EdgeLock Enclave OEM SRK Hash Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1, + "id": "fuse4-bit-15", + "name": "BOOT2_CFG_LOCK_2", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read sensed)" + }, + { + "name": "READ_PROTECT", + "value": 1, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)", + "deprecated_names": [ + "RP" + ] + } + ] + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0005", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved6", + "name": "Reserved 0x6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0006", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved7", + "name": "Reserved 0x7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0007", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved8", + "name": "Reserved 0x8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0008", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG9", + "description": "LOCK_CFG9", + "index_int": "0x0009", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse9-bits-3-5", + "name": "GPR2_LOCK", + "description": "General Purpose 2 Fuse Lock ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-6-8", + "name": "GPR3_LOCK", + "description": "General Purpose 3 Fuse Lock ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-9-11", + "name": "GPR4_LOCK", + "description": "General Purpose 4 Fuse Lock ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0xA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000A", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0xB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0xC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000C", + "is_reserved": true + }, + { + "id": "Reserved13", + "name": "Reserved 0xD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000D", + "is_reserved": true + }, + { + "id": "Reserved14", + "name": "Reserved 0xE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000E", + "is_reserved": true + }, + { + "id": "Reserved15", + "name": "Reserved 0xF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000F", + "is_reserved": true + }, + { + "id": "Reserved16", + "name": "Reserved 0x10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0010", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 11 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x11", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0011", + "is_reserved": true, + "reg_width": 16 + }, + { + "id": "Reserved18", + "name": "Reserved 0x12", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 15 + }, + { + "width": 1 + }, + { + "width": 15 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x13", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 2 + }, + { + "width": 6 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x14", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x15", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 23 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x16", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0016", + "is_reserved": true + }, + { + "id": "Reserved23", + "name": "Reserved 0x17", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 25 + } + ] + }, + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "BOOT_CFG0", + "index_int": "0x0018", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse24-bits-0-3", + "name": "Boot_Mode_Fuses", + "description": "Boot Mode Fuses\nBootRom will retrieve boot mode from these fuses instead of Boot_Mode pins if\n(BT_FUSE_SEL=1 && Boot_Mode=Internal Fuses)\nOr\n(Force FORCE_BT_FROM_FUSE=1)\n", + "values": [ + { + "name": "A55_INTERNAL_FUSES", + "value": 0, + "description": "Cortex-A55 boot from internal fuses", + "deprecated_names": [ + "INTERNAL_FUSES_A55" + ] + }, + { + "name": "A55_SERIAL_DOWNLOADER", + "value": 1, + "description": "Cortex-A55 boot via Serial Downloader USB 1", + "deprecated_names": [ + "SERIAL_DOWNLOADER_A55" + ] + }, + { + "name": "A55_USDHC1_EMMC", + "value": 2, + "description": "Cortex-A55 boot from USDHC1 8-bit eMMC 5.1", + "deprecated_names": [ + "EMMC_A55" + ] + }, + { + "name": "A55_USDHC2_SD", + "value": 3, + "description": "Cortex-A55 boot from USDHC2 4-bit SD3.0", + "deprecated_names": [ + "SD_CARD_A55" + ] + }, + { + "name": "A55_FLEXSPI_NOR", + "value": 4, + "description": "Cortex-A55 boot from FlexSPI Serial NOR", + "deprecated_names": [ + "FLEXSPI_NOR_A55" + ] + }, + { + "name": "A55_FLEXSPI_NAND", + "value": 5, + "description": "Cortex-A55 boot from FlexSPI Serial NAND 2K page", + "deprecated_names": [ + "FLEXSPI_NAND_A55" + ] + }, + { + "name": "M33_INTERNAL_FUSES", + "value": 8, + "description": "Cortex-M33 boot from internal fuses", + "deprecated_names": [ + "INTERNAL_FUSES_M33" + ] + }, + { + "name": "M33_SERIAL_DOWNLOADER", + "value": 9, + "description": "Cortex-M33 boot via Serial Downloader USB 1", + "deprecated_names": [ + "SERIAL_DOWNLOADER_M33" + ] + }, + { + "name": "M33_USDHC1_EMMC", + "value": 10, + "description": "Cortex-M33 boot from USDHC1 8-bit eMMC 5.1", + "deprecated_names": [ + "EMMC_M33" + ] + }, + { + "name": "M33_USDHC2_SD", + "value": 11, + "description": "Cortex-M33 boot from USDHC2 4-bit SD3.0", + "deprecated_names": [ + "SD_CARD_M33" + ] + }, + { + "name": "M33_FLEXSPI_NOR", + "value": 12, + "description": "Cortex-M33 boot from FlexSPI Serial NOR", + "deprecated_names": [ + "FLEXSPI_NOR_M33" + ] + }, + { + "name": "M33_FLEXSPI_NAND", + "value": 13, + "description": "Cortex-M33 boot from FlexSPI Serial NAND 2K page", + "deprecated_names": [ + "FLEXSPI_NAND_M33" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-4", + "name": "Override_FlexSPI_NOR_Boot_Selection", + "description": "Override FlexSPI NOR Boot Selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Do not override", + "deprecated_names": [ + "0" + ] + }, + { + "name": "Override", + "value": 1, + "description": "Override" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-5-6", + "name": "FlexSPI_NOR_Boot_Override_Selection", + "description": "FlexSPI NOR Boot Override Selection", + "values": [ + { + "name": "FLEXSPI_HYPERFLASH", + "value": 0, + "description": "Flex SPI (Hyperflash 1.8V)", + "deprecated_names": [ + "00" + ] + }, + { + "name": "FLEXSPI_4B_READ", + "value": 1, + "description": "Flex SPI (Flash with 4B READ(0x13)default supported)", + "deprecated_names": [ + "01" + ] + }, + { + "name": "OCTAL_MODE_MICRON", + "value": 2, + "description": "Default Octal mode\u00a0(Micron, Nice to have)", + "deprecated_names": [ + "10" + ] + }, + { + "name": "OCTAL_MODE_MXIC", + "value": 3, + "description": "Default Octal mode (Mxic, Nice to have )", + "deprecated_names": [ + "11" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-7", + "name": "FlexSPI_NAND_4K_Page_Selection", + "description": "FlexSPI NAND 4K Page Selection", + "values": [ + { + "name": "DEFAULT_2K_PAGE", + "value": 0, + "description": "Not override the default selection (2K page)", + "deprecated_names": [ + "0" + ] + }, + { + "name": "OVERRIDE_4K_PAGE", + "value": 1, + "description": "Override, 4K page is selected.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-8", + "name": "uSDHC_Device_Type", + "description": "uSDHC Device Type", + "values": [ + { + "name": "EMMC", + "value": 0, + "description": "uSDHC_Device_Type: eMMC" + }, + { + "name": "SD", + "value": 1, + "description": "uSDHC_Device_Type: SD" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-9", + "name": "FLEXSPI_NOR_DATA_IOMUX_SION_EN", + "description": "FLEXSPI NOR DATA IOMUX SION EN", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "DISABLED SION is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "ENABLED SION is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-10-11", + "name": "FLEXSPI_NOR_FCB_OFFSET", + "description": "FLEXSPI NOR FCB OFFSET", + "values": [ + { + "name": "OFFSET_400B", + "value": 0, + "description": "Select the offset of FlexSPI NOR FCB at 0x400B", + "deprecated_names": [ + "0x400B" + ] + }, + { + "name": "OFFSET_600B", + "value": 1, + "description": "Select the offset of FlexSPI NOR FCB at 0x600B", + "deprecated_names": [ + "0x600B" + ] + }, + { + "name": "OFFSET_800B", + "value": 2, + "description": "Select the offset of FlexSPI NOR FCB at 0x800B", + "deprecated_names": [ + "0x800B" + ] + }, + { + "name": "OFFSET_A00B", + "value": 3, + "description": "Select the offset of FlexSPI NOR FCB at 0xA00B", + "deprecated_names": [ + "0xA00B" + ] + } + ] + }, + { + "width": 3, + "id": "fuse24-bits-12-14", + "name": "FLEXSPI_AUTOPROBE_FEQ_SEL", + "description": "FLEXSPI AUTOPROBE FEQ SEL", + "values": [ + { + "name": "FREQ_24MHZ", + "value": 0, + "description": "24MHz", + "deprecated_names": [ + "24MHz" + ] + }, + { + "name": "FREQ_133MHZ", + "value": 1, + "description": "133 MHz", + "deprecated_names": [ + "133_MHz" + ] + }, + { + "name": "FREQ_166MHZ", + "value": 2, + "description": "166 MHz", + "deprecated_names": [ + "166_MHz" + ] + }, + { + "name": "FREQ_200MHZ", + "value": 3, + "description": "200 MHz", + "deprecated_names": [ + "200_MHz" + ] + }, + { + "name": "FREQ_80MHZ", + "value": 4, + "description": "80MHz", + "deprecated_names": [ + "80MHz" + ] + }, + { + "name": "FREQ_100MHZ", + "value": 5, + "description": "100MHz", + "deprecated_names": [ + "100MHz" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-15", + "name": "FLEXSPI_FCB_COPY_FLAG", + "description": "FLEXSPI FCB COPY FLAG", + "values": [ + { + "name": "PORT_2", + "value": 0, + "description": "Port 2 (single boot mode)" + }, + { + "name": "PORT_3", + "value": 1, + "description": "Port 3 (single boot mode)" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-16", + "name": "SD_Loopback_Clock_Source_Sel", + "description": "SD Loopback clock Source Sel", + "deprecated_names": [ + "SD_Loopback_Clock_Source_Sel " + ], + "values": [ + { + "name": "THROUGH_PAD", + "value": 0, + "description": "Through SD pad", + "deprecated_names": [ + "0" + ] + }, + { + "name": "DIRECT", + "value": 1, + "description": "Direct" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-17-18", + "name": "SD_Speed_Selection", + "description": "SD Speed Selection", + "values": [ + { + "name": "NORMAL_SDR12", + "value": 0, + "description": "Normal/SDR12 BUS_WIDTH_4BIT 4 bit" + }, + { + "name": "HIGH_SDR25", + "value": 1, + "description": "High/SDR25 BUS_WIDTH_8BIT 8 bit" + }, + { + "name": "SDR50", + "value": 2, + "description": "BUS_WIDTH_4BIT_DDR 4 bit DDR (eMMC 4.4)" + }, + { + "name": "SDR104", + "value": 3, + "description": "BUS_WIDTH_8BIT_DDR bit DDR (eMMC 4.4)" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-19", + "name": "eMMC_Speed_Selection", + "description": "eMMC Speed Selection", + "values": [ + { + "name": "NORMAL_SPEED", + "value": 0, + "description": "Normal Speed" + }, + { + "name": "HIGH_SPEED", + "value": 1, + "description": "High Speed" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-20", + "name": "eMMC_fast_boot", + "description": "eMMC fast boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-21", + "name": "RSVD_BT_CFG0_21", + "description": "BOOT_CFG0" + }, + { + "width": 1, + "id": "fuse24-bit-22", + "name": "eMMC_voltage_selection", + "description": "eMMC Voltage selection", + "values": [ + { + "name": "VOLTAGE_3V3", + "value": 0, + "description": "eMMC_voltage_selection: 3.3v", + "deprecated_names": [ + "3.3v" + ] + }, + { + "name": "VOLTAGE_1V8", + "value": 1, + "description": "eMMC_voltage_selection: 1.8v", + "deprecated_names": [ + "1.8v" + ] + } + ] + }, + { + "width": 5, + "id": "fuse24-bits-23-27", + "name": "FlexSPI_NOR_Reset_Pin_selections", + "description": "FlexDPI NOR Reset Pin selections", + "values": [ + { + "name": "GPIO_PIN_0", + "value": 0, + "description": "GPIO[x].0", + "deprecated_names": [ + "GPIO[x].0" + ] + }, + { + "name": "GPIO_PIN_1", + "value": 1, + "description": "GPIO[x].1" + }, + { + "name": "GPIO_PIN_2", + "value": 2, + "description": "GPIO[x].2" + }, + { + "name": "GPIO_PIN_3", + "value": 3, + "description": "GPIO[x].3" + }, + { + "name": "GPIO_PIN_4", + "value": 4, + "description": "GPIO[x].4" + }, + { + "name": "GPIO_PIN_5", + "value": 5, + "description": "GPIO[x].5" + }, + { + "name": "GPIO_PIN_6", + "value": 6, + "description": "GPIO[x].6" + }, + { + "name": "GPIO_PIN_7", + "value": 7, + "description": "GPIO[x].7" + }, + { + "name": "GPIO_PIN_8", + "value": 8, + "description": "GPIO[x].8" + }, + { + "name": "GPIO_PIN_9", + "value": 9, + "description": "GPIO[x].9" + }, + { + "name": "GPIO_PIN_10", + "value": 10, + "description": "GPIO[x].10" + }, + { + "name": "GPIO_PIN_11", + "value": 11, + "description": "GPIO[x].11" + }, + { + "name": "GPIO_PIN_12", + "value": 12, + "description": "GPIO[x].12" + }, + { + "name": "GPIO_PIN_13", + "value": 13, + "description": "GPIO[x].13" + }, + { + "name": "GPIO_PIN_14", + "value": 14, + "description": "GPIO[x].14" + }, + { + "name": "GPIO_PIN_15", + "value": 15, + "description": "GPIO[x].15" + }, + { + "name": "GPIO_PIN_16", + "value": 16, + "description": "GPIO[x].16" + }, + { + "name": "GPIO_PIN_17", + "value": 17, + "description": "GPIO[x].17" + }, + { + "name": "GPIO_PIN_18", + "value": 18, + "description": "GPIO[x].18" + }, + { + "name": "GPIO_PIN_19", + "value": 19, + "description": "GPIO[x].19" + }, + { + "name": "GPIO_PIN_20", + "value": 20, + "description": "GPIO[x].20" + }, + { + "name": "GPIO_PIN_21", + "value": 21, + "description": "GPIO[x].21" + }, + { + "name": "GPIO_PIN_22", + "value": 22, + "description": "GPIO[x].22" + }, + { + "name": "GPIO_PIN_23", + "value": 23, + "description": "GPIO[x].23" + }, + { + "name": "GPIO_PIN_24", + "value": 24, + "description": "GPIO[x].24" + }, + { + "name": "GPIO_PIN_25", + "value": 25, + "description": "GPIO[x].25" + }, + { + "name": "GPIO_PIN_26", + "value": 26, + "description": "GPIO[x].26" + }, + { + "name": "GPIO_PIN_27", + "value": 27, + "description": "GPIO[x].27" + }, + { + "name": "GPIO_PIN_28", + "value": 28, + "description": "GPIO[x].28" + }, + { + "name": "GPIO_PIN_29", + "value": 29, + "description": "GPIO[x].29" + }, + { + "name": "GPIO_PIN_30", + "value": 30, + "description": "GPIO[x].30" + }, + { + "name": "GPIO_PIN_31", + "value": 31, + "description": "GPIO[x].31", + "deprecated_names": [ + "GPIO[x].31" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-28", + "name": "BT_FREQ_SEL", + "description": "BT FREQ SEL", + "values": [ + { + "name": "NORMAL_FREQ", + "value": 0, + "description": "Normal clock frequency", + "deprecated_names": [ + "0" + ] + }, + { + "name": "LOW_FREQ", + "value": 1, + "description": "Low clock frequency", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-29", + "name": "BT_FUSE_SEL", + "description": "BT FUSE SEL", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot fuses not programmed", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot fuses programmed yet", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-30", + "name": "Force_Boot_from_Fuse", + "description": "Force Boot from Fuse", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override Boot_Mode pins by boot mode fuses", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-31", + "name": "Force_Serial_Download", + "description": "Force Serial Download", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Normal boot mode selection applies" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override all other Boot_Mode & Boot Mode Fuses and enter Serial Download", + "deprecated_names": [ + "1" + ] + } + ] + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "BOOT_CFG1", + "index_int": "0x0019", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse25-bit-0", + "name": "Fast_Boot_Acknowledge_Disable", + "description": "Fast Boot Acknowledge Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot Ack Disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot Ack Enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse25-bit-2", + "name": "uSDHC_Power_On_Polarity", + "description": "uSHDC Power On Polarity", + "values": [ + { + "name": "LOW", + "value": 0, + "description": "uSDHC_Power_On_Polarity: Low" + }, + { + "name": "HIGH", + "value": 1, + "description": "uSDHC_Power_On_Polarity: High" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-3", + "name": "uSDHC_Power_Cycle_Delay", + "description": "uSDHC Power Cycle Delay", + "values": [ + { + "name": "DELAY_5MS", + "value": 0, + "description": "uSDHC_Power_Cycle_Delay: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "DELAY_2_5MS", + "value": 1, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-4-5", + "name": "uSDHC_Power_Cycle_Interval", + "description": "uSDHC Power Cycle Interval", + "values": [ + { + "name": "INTERVAL_20MS", + "value": 0, + "description": "20 ms", + "deprecated_names": [ + "20_ms" + ] + }, + { + "name": "INTERVAL_10MS", + "value": 1, + "description": "10 ms", + "deprecated_names": [ + "10_ms" + ] + }, + { + "name": "INTERVAL_5MS", + "value": 2, + "description": "uSDHC_Power_Cycle_Interval: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "INTERVAL_2_5MS", + "value": 3, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-6-7", + "name": "SD_Calibration_Step", + "description": "SD Calibration Step", + "values": [ + { + "name": "1_delay_cell", + "value": 0, + "description": "1 delay cell" + }, + { + "name": "2_delay_cell", + "value": 1, + "description": "2 delay cell" + }, + { + "name": "3_delay_cell", + "value": 2, + "description": "3 delay cell" + }, + { + "name": "5_delay_cell", + "value": 3, + "description": "5 delay cell" + } + ] + }, + { + "width": 8, + "id": "fuse25-bits-8-15", + "name": "uSDHC_PAD_Settings_Low_bits", + "description": "uSDHC Pad Settings Low bits", + "values": [ + { + "name": "OVERRIDE_MIN", + "value": 0, + "description": "Override value 0 - minimum pad setting", + "deprecated_names": [ + "11111111" + ] + }, + { + "name": "OVERRIDE_001", + "value": 1, + "description": "Override value 1 - very low pad setting" + }, + { + "name": "OVERRIDE_002", + "value": 2, + "description": "Override value 2 - very low pad setting" + }, + { + "name": "OVERRIDE_003", + "value": 3, + "description": "Override value 3 - very low pad setting" + }, + { + "name": "OVERRIDE_004", + "value": 4, + "description": "Override value 4 - very low pad setting" + }, + { + "name": "OVERRIDE_005", + "value": 5, + "description": "Override value 5 - very low pad setting" + }, + { + "name": "OVERRIDE_006", + "value": 6, + "description": "Override value 6 - very low pad setting" + }, + { + "name": "OVERRIDE_007", + "value": 7, + "description": "Override value 7 - very low pad setting" + }, + { + "name": "OVERRIDE_008", + "value": 8, + "description": "Override value 8 - low pad setting" + }, + { + "name": "OVERRIDE_016", + "value": 16, + "description": "Override value 16 - low pad setting" + }, + { + "name": "OVERRIDE_024", + "value": 24, + "description": "Override value 24 - low pad setting" + }, + { + "name": "OVERRIDE_032", + "value": 32, + "description": "Override value 32 - low-medium pad setting" + }, + { + "name": "OVERRIDE_048", + "value": 48, + "description": "Override value 48 - low-medium pad setting" + }, + { + "name": "OVERRIDE_064", + "value": 64, + "description": "Override value 64 - medium pad setting" + }, + { + "name": "OVERRIDE_080", + "value": 80, + "description": "Override value 80 - medium pad setting" + }, + { + "name": "OVERRIDE_096", + "value": 96, + "description": "Override value 96 - medium pad setting" + }, + { + "name": "OVERRIDE_112", + "value": 112, + "description": "Override value 112 - medium-high pad setting" + }, + { + "name": "OVERRIDE_128", + "value": 128, + "description": "Override value 128 - medium-high pad setting" + }, + { + "name": "OVERRIDE_144", + "value": 144, + "description": "Override value 144 - medium-high pad setting" + }, + { + "name": "OVERRIDE_160", + "value": 160, + "description": "Override value 160 - high pad setting" + }, + { + "name": "OVERRIDE_176", + "value": 176, + "description": "Override value 176 - high pad setting" + }, + { + "name": "OVERRIDE_192", + "value": 192, + "description": "Override value 192 - high pad setting" + }, + { + "name": "OVERRIDE_208", + "value": 208, + "description": "Override value 208 - very high pad setting" + }, + { + "name": "OVERRIDE_224", + "value": 224, + "description": "Override value 224 - very high pad setting" + }, + { + "name": "OVERRIDE_240", + "value": 240, + "description": "Override value 240 - very high pad setting" + }, + { + "name": "OVERRIDE_248", + "value": 248, + "description": "Override value 248 - very high pad setting" + }, + { + "name": "OVERRIDE_252", + "value": 252, + "description": "Override value 252 - very high pad setting" + }, + { + "name": "OVERRIDE_254", + "value": 254, + "description": "Override value 254 - very high pad setting" + }, + { + "name": "OVERRIDE_MAX", + "value": 255, + "description": "Override value 255 - maximum pad setting" + } + ] + }, + { + "width": 4, + "id": "fuse25-bits-16-19", + "name": "uSDHC_PAD_Setting_High_bits", + "description": "uSDHC Pad Settings High bits", + "values": [ + { + "name": "OVERRIDE_VAL_0", + "value": 0, + "description": "Override value 0 for uSDHC pad settings (High bits)", + "deprecated_names": [ + "1111" + ] + }, + { + "name": "OVERRIDE_VAL_1", + "value": 1, + "description": "Override value 1 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_2", + "value": 2, + "description": "Override value 2 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_3", + "value": 3, + "description": "Override value 3 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_4", + "value": 4, + "description": "Override value 4 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_5", + "value": 5, + "description": "Override value 5 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_6", + "value": 6, + "description": "Override value 6 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_7", + "value": 7, + "description": "Override value 7 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_8", + "value": 8, + "description": "Override value 8 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_9", + "value": 9, + "description": "Override value 9 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_10", + "value": 10, + "description": "Override value 10 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_11", + "value": 11, + "description": "Override value 11 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_12", + "value": 12, + "description": "Override value 12 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_13", + "value": 13, + "description": "Override value 13 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_14", + "value": 14, + "description": "Override value 14 for uSDHC pad settings (High bits)" + }, + { + "name": "OVERRIDE_VAL_15", + "value": 15, + "description": "Override value 15 for uSDHC pad settings (High bits)" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-20", + "name": "Power_Cycle_Enable", + "description": "Power Cycle Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "No power cycle", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-21", + "name": "uSDHC_Override_Pad_Settings", + "description": "uSDHC Override Pad Settings\n(using PAD_SETTINGS value)" + }, + { + "width": 1, + "id": "fuse25-bit-22", + "name": "uSDHC_DLL_Enable", + "description": "uSDHC DLL EnableEnable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse25-bits-24-30", + "name": "MMC_DLL_DLY", + "description": "MMC DLL DLY", + "values": [ + { + "name": "DLY_TARGET_0", + "value": 0, + "description": "Delay target for uSDHC DLL set to 0", + "deprecated_names": [ + "1111111" + ] + }, + { + "name": "DLY_TARGET_1", + "value": 1, + "description": "Delay target for uSDHC DLL set to 1" + }, + { + "name": "DLY_TARGET_2", + "value": 2, + "description": "Delay target for uSDHC DLL set to 2" + }, + { + "name": "DLY_TARGET_3", + "value": 3, + "description": "Delay target for uSDHC DLL set to 3" + }, + { + "name": "DLY_TARGET_4", + "value": 4, + "description": "Delay target for uSDHC DLL set to 4" + }, + { + "name": "DLY_TARGET_5", + "value": 5, + "description": "Delay target for uSDHC DLL set to 5" + }, + { + "name": "DLY_TARGET_6", + "value": 6, + "description": "Delay target for uSDHC DLL set to 6" + }, + { + "name": "DLY_TARGET_7", + "value": 7, + "description": "Delay target for uSDHC DLL set to 7" + }, + { + "name": "DLY_TARGET_8", + "value": 8, + "description": "Delay target for uSDHC DLL set to 8" + }, + { + "name": "DLY_TARGET_9", + "value": 9, + "description": "Delay target for uSDHC DLL set to 9" + }, + { + "name": "DLY_TARGET_10", + "value": 10, + "description": "Delay target for uSDHC DLL set to 10" + }, + { + "name": "DLY_TARGET_11", + "value": 11, + "description": "Delay target for uSDHC DLL set to 11" + }, + { + "name": "DLY_TARGET_12", + "value": 12, + "description": "Delay target for uSDHC DLL set to 12" + }, + { + "name": "DLY_TARGET_13", + "value": 13, + "description": "Delay target for uSDHC DLL set to 13" + }, + { + "name": "DLY_TARGET_14", + "value": 14, + "description": "Delay target for uSDHC DLL set to 14" + }, + { + "name": "DLY_TARGET_15", + "value": 15, + "description": "Delay target for uSDHC DLL set to 15" + }, + { + "name": "DLY_TARGET_16", + "value": 16, + "description": "Delay target for uSDHC DLL set to 16" + }, + { + "name": "DLY_TARGET_17", + "value": 17, + "description": "Delay target for uSDHC DLL set to 17" + }, + { + "name": "DLY_TARGET_18", + "value": 18, + "description": "Delay target for uSDHC DLL set to 18" + }, + { + "name": "DLY_TARGET_19", + "value": 19, + "description": "Delay target for uSDHC DLL set to 19" + }, + { + "name": "DLY_TARGET_20", + "value": 20, + "description": "Delay target for uSDHC DLL set to 20" + }, + { + "name": "DLY_TARGET_21", + "value": 21, + "description": "Delay target for uSDHC DLL set to 21" + }, + { + "name": "DLY_TARGET_22", + "value": 22, + "description": "Delay target for uSDHC DLL set to 22" + }, + { + "name": "DLY_TARGET_23", + "value": 23, + "description": "Delay target for uSDHC DLL set to 23" + }, + { + "name": "DLY_TARGET_24", + "value": 24, + "description": "Delay target for uSDHC DLL set to 24" + }, + { + "name": "DLY_TARGET_25", + "value": 25, + "description": "Delay target for uSDHC DLL set to 25" + }, + { + "name": "DLY_TARGET_26", + "value": 26, + "description": "Delay target for uSDHC DLL set to 26" + }, + { + "name": "DLY_TARGET_27", + "value": 27, + "description": "Delay target for uSDHC DLL set to 27" + }, + { + "name": "DLY_TARGET_28", + "value": 28, + "description": "Delay target for uSDHC DLL set to 28" + }, + { + "name": "DLY_TARGET_29", + "value": 29, + "description": "Delay target for uSDHC DLL set to 29" + }, + { + "name": "DLY_TARGET_30", + "value": 30, + "description": "Delay target for uSDHC DLL set to 30" + }, + { + "name": "DLY_TARGET_31", + "value": 31, + "description": "Delay target for uSDHC DLL set to 31" + }, + { + "name": "DLY_TARGET_32", + "value": 32, + "description": "Delay target for uSDHC DLL set to 32" + }, + { + "name": "DLY_TARGET_33", + "value": 33, + "description": "Delay target for uSDHC DLL set to 33" + }, + { + "name": "DLY_TARGET_34", + "value": 34, + "description": "Delay target for uSDHC DLL set to 34" + }, + { + "name": "DLY_TARGET_35", + "value": 35, + "description": "Delay target for uSDHC DLL set to 35" + }, + { + "name": "DLY_TARGET_36", + "value": 36, + "description": "Delay target for uSDHC DLL set to 36" + }, + { + "name": "DLY_TARGET_37", + "value": 37, + "description": "Delay target for uSDHC DLL set to 37" + }, + { + "name": "DLY_TARGET_38", + "value": 38, + "description": "Delay target for uSDHC DLL set to 38" + }, + { + "name": "DLY_TARGET_39", + "value": 39, + "description": "Delay target for uSDHC DLL set to 39" + }, + { + "name": "DLY_TARGET_40", + "value": 40, + "description": "Delay target for uSDHC DLL set to 40" + }, + { + "name": "DLY_TARGET_41", + "value": 41, + "description": "Delay target for uSDHC DLL set to 41" + }, + { + "name": "DLY_TARGET_42", + "value": 42, + "description": "Delay target for uSDHC DLL set to 42" + }, + { + "name": "DLY_TARGET_43", + "value": 43, + "description": "Delay target for uSDHC DLL set to 43" + }, + { + "name": "DLY_TARGET_44", + "value": 44, + "description": "Delay target for uSDHC DLL set to 44" + }, + { + "name": "DLY_TARGET_45", + "value": 45, + "description": "Delay target for uSDHC DLL set to 45" + }, + { + "name": "DLY_TARGET_46", + "value": 46, + "description": "Delay target for uSDHC DLL set to 46" + }, + { + "name": "DLY_TARGET_47", + "value": 47, + "description": "Delay target for uSDHC DLL set to 47" + }, + { + "name": "DLY_TARGET_48", + "value": 48, + "description": "Delay target for uSDHC DLL set to 48" + }, + { + "name": "DLY_TARGET_49", + "value": 49, + "description": "Delay target for uSDHC DLL set to 49" + }, + { + "name": "DLY_TARGET_50", + "value": 50, + "description": "Delay target for uSDHC DLL set to 50" + }, + { + "name": "DLY_TARGET_51", + "value": 51, + "description": "Delay target for uSDHC DLL set to 51" + }, + { + "name": "DLY_TARGET_52", + "value": 52, + "description": "Delay target for uSDHC DLL set to 52" + }, + { + "name": "DLY_TARGET_53", + "value": 53, + "description": "Delay target for uSDHC DLL set to 53" + }, + { + "name": "DLY_TARGET_54", + "value": 54, + "description": "Delay target for uSDHC DLL set to 54" + }, + { + "name": "DLY_TARGET_55", + "value": 55, + "description": "Delay target for uSDHC DLL set to 55" + }, + { + "name": "DLY_TARGET_56", + "value": 56, + "description": "Delay target for uSDHC DLL set to 56" + }, + { + "name": "DLY_TARGET_57", + "value": 57, + "description": "Delay target for uSDHC DLL set to 57" + }, + { + "name": "DLY_TARGET_58", + "value": 58, + "description": "Delay target for uSDHC DLL set to 58" + }, + { + "name": "DLY_TARGET_59", + "value": 59, + "description": "Delay target for uSDHC DLL set to 59" + }, + { + "name": "DLY_TARGET_60", + "value": 60, + "description": "Delay target for uSDHC DLL set to 60" + }, + { + "name": "DLY_TARGET_61", + "value": 61, + "description": "Delay target for uSDHC DLL set to 61" + }, + { + "name": "DLY_TARGET_62", + "value": 62, + "description": "Delay target for uSDHC DLL set to 62" + }, + { + "name": "DLY_TARGET_63", + "value": 63, + "description": "Delay target for uSDHC DLL set to 63" + }, + { + "name": "DLY_TARGET_64", + "value": 64, + "description": "Delay target for uSDHC DLL set to 64" + }, + { + "name": "DLY_TARGET_65", + "value": 65, + "description": "Delay target for uSDHC DLL set to 65" + }, + { + "name": "DLY_TARGET_66", + "value": 66, + "description": "Delay target for uSDHC DLL set to 66" + }, + { + "name": "DLY_TARGET_67", + "value": 67, + "description": "Delay target for uSDHC DLL set to 67" + }, + { + "name": "DLY_TARGET_68", + "value": 68, + "description": "Delay target for uSDHC DLL set to 68" + }, + { + "name": "DLY_TARGET_69", + "value": 69, + "description": "Delay target for uSDHC DLL set to 69" + }, + { + "name": "DLY_TARGET_70", + "value": 70, + "description": "Delay target for uSDHC DLL set to 70" + }, + { + "name": "DLY_TARGET_71", + "value": 71, + "description": "Delay target for uSDHC DLL set to 71" + }, + { + "name": "DLY_TARGET_72", + "value": 72, + "description": "Delay target for uSDHC DLL set to 72" + }, + { + "name": "DLY_TARGET_73", + "value": 73, + "description": "Delay target for uSDHC DLL set to 73" + }, + { + "name": "DLY_TARGET_74", + "value": 74, + "description": "Delay target for uSDHC DLL set to 74" + }, + { + "name": "DLY_TARGET_75", + "value": 75, + "description": "Delay target for uSDHC DLL set to 75" + }, + { + "name": "DLY_TARGET_76", + "value": 76, + "description": "Delay target for uSDHC DLL set to 76" + }, + { + "name": "DLY_TARGET_77", + "value": 77, + "description": "Delay target for uSDHC DLL set to 77" + }, + { + "name": "DLY_TARGET_78", + "value": 78, + "description": "Delay target for uSDHC DLL set to 78" + }, + { + "name": "DLY_TARGET_79", + "value": 79, + "description": "Delay target for uSDHC DLL set to 79" + }, + { + "name": "DLY_TARGET_80", + "value": 80, + "description": "Delay target for uSDHC DLL set to 80" + }, + { + "name": "DLY_TARGET_81", + "value": 81, + "description": "Delay target for uSDHC DLL set to 81" + }, + { + "name": "DLY_TARGET_82", + "value": 82, + "description": "Delay target for uSDHC DLL set to 82" + }, + { + "name": "DLY_TARGET_83", + "value": 83, + "description": "Delay target for uSDHC DLL set to 83" + }, + { + "name": "DLY_TARGET_84", + "value": 84, + "description": "Delay target for uSDHC DLL set to 84" + }, + { + "name": "DLY_TARGET_85", + "value": 85, + "description": "Delay target for uSDHC DLL set to 85" + }, + { + "name": "DLY_TARGET_86", + "value": 86, + "description": "Delay target for uSDHC DLL set to 86" + }, + { + "name": "DLY_TARGET_87", + "value": 87, + "description": "Delay target for uSDHC DLL set to 87" + }, + { + "name": "DLY_TARGET_88", + "value": 88, + "description": "Delay target for uSDHC DLL set to 88" + }, + { + "name": "DLY_TARGET_89", + "value": 89, + "description": "Delay target for uSDHC DLL set to 89" + }, + { + "name": "DLY_TARGET_90", + "value": 90, + "description": "Delay target for uSDHC DLL set to 90" + }, + { + "name": "DLY_TARGET_91", + "value": 91, + "description": "Delay target for uSDHC DLL set to 91" + }, + { + "name": "DLY_TARGET_92", + "value": 92, + "description": "Delay target for uSDHC DLL set to 92" + }, + { + "name": "DLY_TARGET_93", + "value": 93, + "description": "Delay target for uSDHC DLL set to 93" + }, + { + "name": "DLY_TARGET_94", + "value": 94, + "description": "Delay target for uSDHC DLL set to 94" + }, + { + "name": "DLY_TARGET_95", + "value": 95, + "description": "Delay target for uSDHC DLL set to 95" + }, + { + "name": "DLY_TARGET_96", + "value": 96, + "description": "Delay target for uSDHC DLL set to 96" + }, + { + "name": "DLY_TARGET_97", + "value": 97, + "description": "Delay target for uSDHC DLL set to 97" + }, + { + "name": "DLY_TARGET_98", + "value": 98, + "description": "Delay target for uSDHC DLL set to 98" + }, + { + "name": "DLY_TARGET_99", + "value": 99, + "description": "Delay target for uSDHC DLL set to 99" + }, + { + "name": "DLY_TARGET_100", + "value": 100, + "description": "Delay target for uSDHC DLL set to 100" + }, + { + "name": "DLY_TARGET_101", + "value": 101, + "description": "Delay target for uSDHC DLL set to 101" + }, + { + "name": "DLY_TARGET_102", + "value": 102, + "description": "Delay target for uSDHC DLL set to 102" + }, + { + "name": "DLY_TARGET_103", + "value": 103, + "description": "Delay target for uSDHC DLL set to 103" + }, + { + "name": "DLY_TARGET_104", + "value": 104, + "description": "Delay target for uSDHC DLL set to 104" + }, + { + "name": "DLY_TARGET_105", + "value": 105, + "description": "Delay target for uSDHC DLL set to 105" + }, + { + "name": "DLY_TARGET_106", + "value": 106, + "description": "Delay target for uSDHC DLL set to 106" + }, + { + "name": "DLY_TARGET_107", + "value": 107, + "description": "Delay target for uSDHC DLL set to 107" + }, + { + "name": "DLY_TARGET_108", + "value": 108, + "description": "Delay target for uSDHC DLL set to 108" + }, + { + "name": "DLY_TARGET_109", + "value": 109, + "description": "Delay target for uSDHC DLL set to 109" + }, + { + "name": "DLY_TARGET_110", + "value": 110, + "description": "Delay target for uSDHC DLL set to 110" + }, + { + "name": "DLY_TARGET_111", + "value": 111, + "description": "Delay target for uSDHC DLL set to 111" + }, + { + "name": "DLY_TARGET_112", + "value": 112, + "description": "Delay target for uSDHC DLL set to 112" + }, + { + "name": "DLY_TARGET_113", + "value": 113, + "description": "Delay target for uSDHC DLL set to 113" + }, + { + "name": "DLY_TARGET_114", + "value": 114, + "description": "Delay target for uSDHC DLL set to 114" + }, + { + "name": "DLY_TARGET_115", + "value": 115, + "description": "Delay target for uSDHC DLL set to 115" + }, + { + "name": "DLY_TARGET_116", + "value": 116, + "description": "Delay target for uSDHC DLL set to 116" + }, + { + "name": "DLY_TARGET_117", + "value": 117, + "description": "Delay target for uSDHC DLL set to 117" + }, + { + "name": "DLY_TARGET_118", + "value": 118, + "description": "Delay target for uSDHC DLL set to 118" + }, + { + "name": "DLY_TARGET_119", + "value": 119, + "description": "Delay target for uSDHC DLL set to 119" + }, + { + "name": "DLY_TARGET_120", + "value": 120, + "description": "Delay target for uSDHC DLL set to 120" + }, + { + "name": "DLY_TARGET_121", + "value": 121, + "description": "Delay target for uSDHC DLL set to 121" + }, + { + "name": "DLY_TARGET_122", + "value": 122, + "description": "Delay target for uSDHC DLL set to 122" + }, + { + "name": "DLY_TARGET_123", + "value": 123, + "description": "Delay target for uSDHC DLL set to 123" + }, + { + "name": "DLY_TARGET_124", + "value": 124, + "description": "Delay target for uSDHC DLL set to 124" + }, + { + "name": "DLY_TARGET_125", + "value": 125, + "description": "Delay target for uSDHC DLL set to 125" + }, + { + "name": "DLY_TARGET_126", + "value": 126, + "description": "Delay target for uSDHC DLL set to 126" + }, + { + "name": "DLY_TARGET_127", + "value": 127, + "description": "Delay target for uSDHC DLL set to 127" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-31", + "name": "uSDHC_DLL_Select", + "description": "uSDHC DLL Select", + "values": [ + { + "name": "DLL_SLAVE", + "value": 0, + "description": "DLL Slave Mode for" + }, + { + "name": "DLL_OVERRIDE", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "BOOT_CFG2", + "index_int": "0x001A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse26-bits-0-1", + "name": "FlexSPI_NAND_Column_Address_Width", + "description": "FlexSPI NAND Column Address Width", + "values": [ + { + "name": "WIDTH_12_BITS", + "value": 0, + "description": "12-bit column address width", + "deprecated_names": [ + "ADDR_WIDTH_12" + ] + }, + { + "name": "WIDTH_13_BITS", + "value": 1, + "description": "13-bit column address width", + "deprecated_names": [ + "ADDR_WIDTH_13" + ] + }, + { + "name": "WIDTH_14_BITS", + "value": 2, + "description": "14-bit column address width", + "deprecated_names": [ + "ADDR_WIDTH_14" + ] + }, + { + "name": "WIDTH_15_BITS", + "value": 3, + "description": "15-bit column address width", + "deprecated_names": [ + "ADDR_WIDTH_15" + ] + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-2-3", + "name": "FlexSPI_NAND_CS_Interval", + "description": "FlexSPI NAND CS Interval", + "values": [ + { + "name": "INTERVAL_100NS", + "value": 0, + "description": "100 ns" + }, + { + "name": "INTERVAL_200NS", + "value": 1, + "description": "200 ns" + }, + { + "name": "INTERVAL_400NS", + "value": 2, + "description": "400 ns" + }, + { + "name": "INTERVAL_50NS", + "value": 3, + "description": "50 ns" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-4-5", + "name": "FlexSPI_NAND_Search_Count", + "description": "FlexSPI NAND Search Count", + "values": [ + { + "name": "SEARCH_COUNT_2", + "value": 0, + "description": "FlexSPI_NAND_Search_Count: 2", + "deprecated_names": [ + "2" + ] + }, + { + "name": "01", + "value": 1, + "description": "2 Redudant value" + }, + { + "name": "SEARCH_COUNT_4", + "value": 2, + "description": "FlexSPI_NAND_Search_Count: 4", + "deprecated_names": [ + "4" + ] + }, + { + "name": "SEARCH_COUNT_8", + "value": 3, + "description": "FlexSPI_NAND_Search_Count: 8", + "deprecated_names": [ + "8" + ] + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-6-7", + "name": "FlexSPI_NAND_Search_Stride", + "description": "FlexSPI NAND Search Stride", + "values": [ + { + "name": "64_pages", + "value": 0, + "description": "64 pages" + }, + { + "name": "128_pages", + "value": 1, + "description": "128 pages" + }, + { + "name": "256_pages", + "value": 2, + "description": "256 pages" + }, + { + "name": "32_pages", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 8, + "id": "fuse26-bits-8-15", + "name": "FlexSPI_DLL_Value", + "description": "FlexSPI DLL Value", + "values": [ + { + "name": "DLL_DELAY_MIN", + "value": 0, + "description": "The delay line value only for HyperFlash - minimum delay (0)", + "deprecated_names": [ + "11111111" + ] + }, + { + "name": "DLL_DELAY_1", + "value": 1, + "description": "The delay line value only for HyperFlash - delay value 1" + }, + { + "name": "DLL_DELAY_2", + "value": 2, + "description": "The delay line value only for HyperFlash - delay value 2" + }, + { + "name": "DLL_DELAY_3", + "value": 3, + "description": "The delay line value only for HyperFlash - delay value 3" + }, + { + "name": "DLL_DELAY_4", + "value": 4, + "description": "The delay line value only for HyperFlash - delay value 4" + }, + { + "name": "DLL_DELAY_5", + "value": 5, + "description": "The delay line value only for HyperFlash - delay value 5" + }, + { + "name": "DLL_DELAY_6", + "value": 6, + "description": "The delay line value only for HyperFlash - delay value 6" + }, + { + "name": "DLL_DELAY_7", + "value": 7, + "description": "The delay line value only for HyperFlash - delay value 7" + }, + { + "name": "DLL_DELAY_8", + "value": 8, + "description": "The delay line value only for HyperFlash - delay value 8" + }, + { + "name": "DLL_DELAY_9", + "value": 9, + "description": "The delay line value only for HyperFlash - delay value 9" + }, + { + "name": "DLL_DELAY_10", + "value": 10, + "description": "The delay line value only for HyperFlash - delay value 10" + }, + { + "name": "DLL_DELAY_11", + "value": 11, + "description": "The delay line value only for HyperFlash - delay value 11" + }, + { + "name": "DLL_DELAY_12", + "value": 12, + "description": "The delay line value only for HyperFlash - delay value 12" + }, + { + "name": "DLL_DELAY_13", + "value": 13, + "description": "The delay line value only for HyperFlash - delay value 13" + }, + { + "name": "DLL_DELAY_14", + "value": 14, + "description": "The delay line value only for HyperFlash - delay value 14" + }, + { + "name": "DLL_DELAY_15", + "value": 15, + "description": "The delay line value only for HyperFlash - delay value 15" + }, + { + "name": "DLL_DELAY_16", + "value": 16, + "description": "The delay line value only for HyperFlash - delay value 16" + }, + { + "name": "DLL_DELAY_17", + "value": 17, + "description": "The delay line value only for HyperFlash - delay value 17" + }, + { + "name": "DLL_DELAY_18", + "value": 18, + "description": "The delay line value only for HyperFlash - delay value 18" + }, + { + "name": "DLL_DELAY_19", + "value": 19, + "description": "The delay line value only for HyperFlash - delay value 19" + }, + { + "name": "DLL_DELAY_20", + "value": 20, + "description": "The delay line value only for HyperFlash - delay value 20" + }, + { + "name": "DLL_DELAY_21", + "value": 21, + "description": "The delay line value only for HyperFlash - delay value 21" + }, + { + "name": "DLL_DELAY_22", + "value": 22, + "description": "The delay line value only for HyperFlash - delay value 22" + }, + { + "name": "DLL_DELAY_23", + "value": 23, + "description": "The delay line value only for HyperFlash - delay value 23" + }, + { + "name": "DLL_DELAY_24", + "value": 24, + "description": "The delay line value only for HyperFlash - delay value 24" + }, + { + "name": "DLL_DELAY_25", + "value": 25, + "description": "The delay line value only for HyperFlash - delay value 25" + }, + { + "name": "DLL_DELAY_26", + "value": 26, + "description": "The delay line value only for HyperFlash - delay value 26" + }, + { + "name": "DLL_DELAY_27", + "value": 27, + "description": "The delay line value only for HyperFlash - delay value 27" + }, + { + "name": "DLL_DELAY_28", + "value": 28, + "description": "The delay line value only for HyperFlash - delay value 28" + }, + { + "name": "DLL_DELAY_29", + "value": 29, + "description": "The delay line value only for HyperFlash - delay value 29" + }, + { + "name": "DLL_DELAY_30", + "value": 30, + "description": "The delay line value only for HyperFlash - delay value 30" + }, + { + "name": "DLL_DELAY_31", + "value": 31, + "description": "The delay line value only for HyperFlash - delay value 31" + }, + { + "name": "DLL_DELAY_32", + "value": 32, + "description": "The delay line value only for HyperFlash - delay value 32" + }, + { + "name": "DLL_DELAY_33", + "value": 33, + "description": "The delay line value only for HyperFlash - delay value 33" + }, + { + "name": "DLL_DELAY_34", + "value": 34, + "description": "The delay line value only for HyperFlash - delay value 34" + }, + { + "name": "DLL_DELAY_35", + "value": 35, + "description": "The delay line value only for HyperFlash - delay value 35" + }, + { + "name": "DLL_DELAY_36", + "value": 36, + "description": "The delay line value only for HyperFlash - delay value 36" + }, + { + "name": "DLL_DELAY_37", + "value": 37, + "description": "The delay line value only for HyperFlash - delay value 37" + }, + { + "name": "DLL_DELAY_38", + "value": 38, + "description": "The delay line value only for HyperFlash - delay value 38" + }, + { + "name": "DLL_DELAY_39", + "value": 39, + "description": "The delay line value only for HyperFlash - delay value 39" + }, + { + "name": "DLL_DELAY_40", + "value": 40, + "description": "The delay line value only for HyperFlash - delay value 40" + }, + { + "name": "DLL_DELAY_41", + "value": 41, + "description": "The delay line value only for HyperFlash - delay value 41" + }, + { + "name": "DLL_DELAY_42", + "value": 42, + "description": "The delay line value only for HyperFlash - delay value 42" + }, + { + "name": "DLL_DELAY_43", + "value": 43, + "description": "The delay line value only for HyperFlash - delay value 43" + }, + { + "name": "DLL_DELAY_44", + "value": 44, + "description": "The delay line value only for HyperFlash - delay value 44" + }, + { + "name": "DLL_DELAY_45", + "value": 45, + "description": "The delay line value only for HyperFlash - delay value 45" + }, + { + "name": "DLL_DELAY_46", + "value": 46, + "description": "The delay line value only for HyperFlash - delay value 46" + }, + { + "name": "DLL_DELAY_47", + "value": 47, + "description": "The delay line value only for HyperFlash - delay value 47" + }, + { + "name": "DLL_DELAY_48", + "value": 48, + "description": "The delay line value only for HyperFlash - delay value 48" + }, + { + "name": "DLL_DELAY_49", + "value": 49, + "description": "The delay line value only for HyperFlash - delay value 49" + }, + { + "name": "DLL_DELAY_50", + "value": 50, + "description": "The delay line value only for HyperFlash - delay value 50" + }, + { + "name": "DLL_DELAY_51", + "value": 51, + "description": "The delay line value only for HyperFlash - delay value 51" + }, + { + "name": "DLL_DELAY_52", + "value": 52, + "description": "The delay line value only for HyperFlash - delay value 52" + }, + { + "name": "DLL_DELAY_53", + "value": 53, + "description": "The delay line value only for HyperFlash - delay value 53" + }, + { + "name": "DLL_DELAY_54", + "value": 54, + "description": "The delay line value only for HyperFlash - delay value 54" + }, + { + "name": "DLL_DELAY_55", + "value": 55, + "description": "The delay line value only for HyperFlash - delay value 55" + }, + { + "name": "DLL_DELAY_56", + "value": 56, + "description": "The delay line value only for HyperFlash - delay value 56" + }, + { + "name": "DLL_DELAY_57", + "value": 57, + "description": "The delay line value only for HyperFlash - delay value 57" + }, + { + "name": "DLL_DELAY_58", + "value": 58, + "description": "The delay line value only for HyperFlash - delay value 58" + }, + { + "name": "DLL_DELAY_59", + "value": 59, + "description": "The delay line value only for HyperFlash - delay value 59" + }, + { + "name": "DLL_DELAY_60", + "value": 60, + "description": "The delay line value only for HyperFlash - delay value 60" + }, + { + "name": "DLL_DELAY_61", + "value": 61, + "description": "The delay line value only for HyperFlash - delay value 61" + }, + { + "name": "DLL_DELAY_62", + "value": 62, + "description": "The delay line value only for HyperFlash - delay value 62" + }, + { + "name": "DLL_DELAY_63", + "value": 63, + "description": "The delay line value only for HyperFlash - delay value 63" + }, + { + "name": "DLL_DELAY_64", + "value": 64, + "description": "The delay line value only for HyperFlash - delay value 64" + }, + { + "name": "DLL_DELAY_65", + "value": 65, + "description": "The delay line value only for HyperFlash - delay value 65" + }, + { + "name": "DLL_DELAY_66", + "value": 66, + "description": "The delay line value only for HyperFlash - delay value 66" + }, + { + "name": "DLL_DELAY_67", + "value": 67, + "description": "The delay line value only for HyperFlash - delay value 67" + }, + { + "name": "DLL_DELAY_68", + "value": 68, + "description": "The delay line value only for HyperFlash - delay value 68" + }, + { + "name": "DLL_DELAY_69", + "value": 69, + "description": "The delay line value only for HyperFlash - delay value 69" + }, + { + "name": "DLL_DELAY_70", + "value": 70, + "description": "The delay line value only for HyperFlash - delay value 70" + }, + { + "name": "DLL_DELAY_71", + "value": 71, + "description": "The delay line value only for HyperFlash - delay value 71" + }, + { + "name": "DLL_DELAY_72", + "value": 72, + "description": "The delay line value only for HyperFlash - delay value 72" + }, + { + "name": "DLL_DELAY_73", + "value": 73, + "description": "The delay line value only for HyperFlash - delay value 73" + }, + { + "name": "DLL_DELAY_74", + "value": 74, + "description": "The delay line value only for HyperFlash - delay value 74" + }, + { + "name": "DLL_DELAY_75", + "value": 75, + "description": "The delay line value only for HyperFlash - delay value 75" + }, + { + "name": "DLL_DELAY_76", + "value": 76, + "description": "The delay line value only for HyperFlash - delay value 76" + }, + { + "name": "DLL_DELAY_77", + "value": 77, + "description": "The delay line value only for HyperFlash - delay value 77" + }, + { + "name": "DLL_DELAY_78", + "value": 78, + "description": "The delay line value only for HyperFlash - delay value 78" + }, + { + "name": "DLL_DELAY_79", + "value": 79, + "description": "The delay line value only for HyperFlash - delay value 79" + }, + { + "name": "DLL_DELAY_80", + "value": 80, + "description": "The delay line value only for HyperFlash - delay value 80" + }, + { + "name": "DLL_DELAY_81", + "value": 81, + "description": "The delay line value only for HyperFlash - delay value 81" + }, + { + "name": "DLL_DELAY_82", + "value": 82, + "description": "The delay line value only for HyperFlash - delay value 82" + }, + { + "name": "DLL_DELAY_83", + "value": 83, + "description": "The delay line value only for HyperFlash - delay value 83" + }, + { + "name": "DLL_DELAY_84", + "value": 84, + "description": "The delay line value only for HyperFlash - delay value 84" + }, + { + "name": "DLL_DELAY_85", + "value": 85, + "description": "The delay line value only for HyperFlash - delay value 85" + }, + { + "name": "DLL_DELAY_86", + "value": 86, + "description": "The delay line value only for HyperFlash - delay value 86" + }, + { + "name": "DLL_DELAY_87", + "value": 87, + "description": "The delay line value only for HyperFlash - delay value 87" + }, + { + "name": "DLL_DELAY_88", + "value": 88, + "description": "The delay line value only for HyperFlash - delay value 88" + }, + { + "name": "DLL_DELAY_89", + "value": 89, + "description": "The delay line value only for HyperFlash - delay value 89" + }, + { + "name": "DLL_DELAY_90", + "value": 90, + "description": "The delay line value only for HyperFlash - delay value 90" + }, + { + "name": "DLL_DELAY_91", + "value": 91, + "description": "The delay line value only for HyperFlash - delay value 91" + }, + { + "name": "DLL_DELAY_92", + "value": 92, + "description": "The delay line value only for HyperFlash - delay value 92" + }, + { + "name": "DLL_DELAY_93", + "value": 93, + "description": "The delay line value only for HyperFlash - delay value 93" + }, + { + "name": "DLL_DELAY_94", + "value": 94, + "description": "The delay line value only for HyperFlash - delay value 94" + }, + { + "name": "DLL_DELAY_95", + "value": 95, + "description": "The delay line value only for HyperFlash - delay value 95" + }, + { + "name": "DLL_DELAY_96", + "value": 96, + "description": "The delay line value only for HyperFlash - delay value 96" + }, + { + "name": "DLL_DELAY_97", + "value": 97, + "description": "The delay line value only for HyperFlash - delay value 97" + }, + { + "name": "DLL_DELAY_98", + "value": 98, + "description": "The delay line value only for HyperFlash - delay value 98" + }, + { + "name": "DLL_DELAY_99", + "value": 99, + "description": "The delay line value only for HyperFlash - delay value 99" + }, + { + "name": "DLL_DELAY_100", + "value": 100, + "description": "The delay line value only for HyperFlash - delay value 100" + }, + { + "name": "DLL_DELAY_101", + "value": 101, + "description": "The delay line value only for HyperFlash - delay value 101" + }, + { + "name": "DLL_DELAY_102", + "value": 102, + "description": "The delay line value only for HyperFlash - delay value 102" + }, + { + "name": "DLL_DELAY_103", + "value": 103, + "description": "The delay line value only for HyperFlash - delay value 103" + }, + { + "name": "DLL_DELAY_104", + "value": 104, + "description": "The delay line value only for HyperFlash - delay value 104" + }, + { + "name": "DLL_DELAY_105", + "value": 105, + "description": "The delay line value only for HyperFlash - delay value 105" + }, + { + "name": "DLL_DELAY_106", + "value": 106, + "description": "The delay line value only for HyperFlash - delay value 106" + }, + { + "name": "DLL_DELAY_107", + "value": 107, + "description": "The delay line value only for HyperFlash - delay value 107" + }, + { + "name": "DLL_DELAY_108", + "value": 108, + "description": "The delay line value only for HyperFlash - delay value 108" + }, + { + "name": "DLL_DELAY_109", + "value": 109, + "description": "The delay line value only for HyperFlash - delay value 109" + }, + { + "name": "DLL_DELAY_110", + "value": 110, + "description": "The delay line value only for HyperFlash - delay value 110" + }, + { + "name": "DLL_DELAY_111", + "value": 111, + "description": "The delay line value only for HyperFlash - delay value 111" + }, + { + "name": "DLL_DELAY_112", + "value": 112, + "description": "The delay line value only for HyperFlash - delay value 112" + }, + { + "name": "DLL_DELAY_113", + "value": 113, + "description": "The delay line value only for HyperFlash - delay value 113" + }, + { + "name": "DLL_DELAY_114", + "value": 114, + "description": "The delay line value only for HyperFlash - delay value 114" + }, + { + "name": "DLL_DELAY_115", + "value": 115, + "description": "The delay line value only for HyperFlash - delay value 115" + }, + { + "name": "DLL_DELAY_116", + "value": 116, + "description": "The delay line value only for HyperFlash - delay value 116" + }, + { + "name": "DLL_DELAY_117", + "value": 117, + "description": "The delay line value only for HyperFlash - delay value 117" + }, + { + "name": "DLL_DELAY_118", + "value": 118, + "description": "The delay line value only for HyperFlash - delay value 118" + }, + { + "name": "DLL_DELAY_119", + "value": 119, + "description": "The delay line value only for HyperFlash - delay value 119" + }, + { + "name": "DLL_DELAY_120", + "value": 120, + "description": "The delay line value only for HyperFlash - delay value 120" + }, + { + "name": "DLL_DELAY_121", + "value": 121, + "description": "The delay line value only for HyperFlash - delay value 121" + }, + { + "name": "DLL_DELAY_122", + "value": 122, + "description": "The delay line value only for HyperFlash - delay value 122" + }, + { + "name": "DLL_DELAY_123", + "value": 123, + "description": "The delay line value only for HyperFlash - delay value 123" + }, + { + "name": "DLL_DELAY_124", + "value": 124, + "description": "The delay line value only for HyperFlash - delay value 124" + }, + { + "name": "DLL_DELAY_125", + "value": 125, + "description": "The delay line value only for HyperFlash - delay value 125" + }, + { + "name": "DLL_DELAY_126", + "value": 126, + "description": "The delay line value only for HyperFlash - delay value 126" + }, + { + "name": "DLL_DELAY_127", + "value": 127, + "description": "The delay line value only for HyperFlash - delay value 127" + }, + { + "name": "DLL_DELAY_128", + "value": 128, + "description": "The delay line value only for HyperFlash - delay value 128" + }, + { + "name": "DLL_DELAY_129", + "value": 129, + "description": "The delay line value only for HyperFlash - delay value 129" + }, + { + "name": "DLL_DELAY_130", + "value": 130, + "description": "The delay line value only for HyperFlash - delay value 130" + }, + { + "name": "DLL_DELAY_131", + "value": 131, + "description": "The delay line value only for HyperFlash - delay value 131" + }, + { + "name": "DLL_DELAY_132", + "value": 132, + "description": "The delay line value only for HyperFlash - delay value 132" + }, + { + "name": "DLL_DELAY_133", + "value": 133, + "description": "The delay line value only for HyperFlash - delay value 133" + }, + { + "name": "DLL_DELAY_134", + "value": 134, + "description": "The delay line value only for HyperFlash - delay value 134" + }, + { + "name": "DLL_DELAY_135", + "value": 135, + "description": "The delay line value only for HyperFlash - delay value 135" + }, + { + "name": "DLL_DELAY_136", + "value": 136, + "description": "The delay line value only for HyperFlash - delay value 136" + }, + { + "name": "DLL_DELAY_137", + "value": 137, + "description": "The delay line value only for HyperFlash - delay value 137" + }, + { + "name": "DLL_DELAY_138", + "value": 138, + "description": "The delay line value only for HyperFlash - delay value 138" + }, + { + "name": "DLL_DELAY_139", + "value": 139, + "description": "The delay line value only for HyperFlash - delay value 139" + }, + { + "name": "DLL_DELAY_140", + "value": 140, + "description": "The delay line value only for HyperFlash - delay value 140" + }, + { + "name": "DLL_DELAY_141", + "value": 141, + "description": "The delay line value only for HyperFlash - delay value 141" + }, + { + "name": "DLL_DELAY_142", + "value": 142, + "description": "The delay line value only for HyperFlash - delay value 142" + }, + { + "name": "DLL_DELAY_143", + "value": 143, + "description": "The delay line value only for HyperFlash - delay value 143" + }, + { + "name": "DLL_DELAY_144", + "value": 144, + "description": "The delay line value only for HyperFlash - delay value 144" + }, + { + "name": "DLL_DELAY_145", + "value": 145, + "description": "The delay line value only for HyperFlash - delay value 145" + }, + { + "name": "DLL_DELAY_146", + "value": 146, + "description": "The delay line value only for HyperFlash - delay value 146" + }, + { + "name": "DLL_DELAY_147", + "value": 147, + "description": "The delay line value only for HyperFlash - delay value 147" + }, + { + "name": "DLL_DELAY_148", + "value": 148, + "description": "The delay line value only for HyperFlash - delay value 148" + }, + { + "name": "DLL_DELAY_149", + "value": 149, + "description": "The delay line value only for HyperFlash - delay value 149" + }, + { + "name": "DLL_DELAY_150", + "value": 150, + "description": "The delay line value only for HyperFlash - delay value 150" + }, + { + "name": "DLL_DELAY_151", + "value": 151, + "description": "The delay line value only for HyperFlash - delay value 151" + }, + { + "name": "DLL_DELAY_152", + "value": 152, + "description": "The delay line value only for HyperFlash - delay value 152" + }, + { + "name": "DLL_DELAY_153", + "value": 153, + "description": "The delay line value only for HyperFlash - delay value 153" + }, + { + "name": "DLL_DELAY_154", + "value": 154, + "description": "The delay line value only for HyperFlash - delay value 154" + }, + { + "name": "DLL_DELAY_155", + "value": 155, + "description": "The delay line value only for HyperFlash - delay value 155" + }, + { + "name": "DLL_DELAY_156", + "value": 156, + "description": "The delay line value only for HyperFlash - delay value 156" + }, + { + "name": "DLL_DELAY_157", + "value": 157, + "description": "The delay line value only for HyperFlash - delay value 157" + }, + { + "name": "DLL_DELAY_158", + "value": 158, + "description": "The delay line value only for HyperFlash - delay value 158" + }, + { + "name": "DLL_DELAY_159", + "value": 159, + "description": "The delay line value only for HyperFlash - delay value 159" + }, + { + "name": "DLL_DELAY_160", + "value": 160, + "description": "The delay line value only for HyperFlash - delay value 160" + }, + { + "name": "DLL_DELAY_161", + "value": 161, + "description": "The delay line value only for HyperFlash - delay value 161" + }, + { + "name": "DLL_DELAY_162", + "value": 162, + "description": "The delay line value only for HyperFlash - delay value 162" + }, + { + "name": "DLL_DELAY_163", + "value": 163, + "description": "The delay line value only for HyperFlash - delay value 163" + }, + { + "name": "DLL_DELAY_164", + "value": 164, + "description": "The delay line value only for HyperFlash - delay value 164" + }, + { + "name": "DLL_DELAY_165", + "value": 165, + "description": "The delay line value only for HyperFlash - delay value 165" + }, + { + "name": "DLL_DELAY_166", + "value": 166, + "description": "The delay line value only for H" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-16", + "name": "SPI_Clock_Data_Phase_Control", + "description": "SPI Clock Data Phase Control ", + "values": [ + { + "name": "TX_FALL_RX_RISE", + "value": 0, + "description": "Tx on falling, Rx on rising", + "deprecated_names": [ + "0" + ] + }, + { + "name": "TX_RISE_RX_FALL", + "value": 1, + "description": "Tx on rising, Rx on falling", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-17", + "name": "SPI_SCLK_Active", + "description": "SPI SCLK Active", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high" + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-18", + "name": "SPI_SS_Active", + "description": "SPI SS Active", + "values": [ + { + "name": "ACTIVE_LOW", + "value": 0, + "description": "Active low" + }, + { + "name": "ACTIVE_HIGH", + "value": 1, + "description": "Active high" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-19", + "name": "Recovery_SPI_Addressing", + "description": "Recovery SPI Addressing", + "values": [ + { + "name": "ADDRESSING_3BYTE", + "value": 0, + "description": "3-bytes (24-bit)", + "deprecated_names": [ + "3-bytes" + ] + }, + { + "name": "ADDRESSING_2BYTE", + "value": 1, + "description": "2-bytes (16-bit)", + "deprecated_names": [ + "2-bytes" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-20", + "name": "FLEXSPI_NOR_AUTO_PROBE_EN", + "description": "FlexSPI NOR auto probe enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Auto probe is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Auto probe is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 3, + "id": "fuse26-bits-21-23", + "name": "FlexSPI_NAND_Busy_Bit_Offset_Override", + "description": "FlexSPI NAND Busy Bit Offset Override ", + "values": [ + { + "name": "BIT_OFFSET_0", + "value": 0, + "description": "Busy bit at offset 0 in 8-bit register" + }, + { + "name": "BIT_OFFSET_1", + "value": 1, + "description": "Busy bit at offset 1 in 8-bit register" + }, + { + "name": "BIT_OFFSET_2", + "value": 2, + "description": "Busy bit at offset 2 in 8-bit register" + }, + { + "name": "BIT_OFFSET_3", + "value": 3, + "description": "Busy bit at offset 3 in 8-bit register" + }, + { + "name": "BIT_OFFSET_4", + "value": 4, + "description": "Busy bit at offset 4 in 8-bit register" + }, + { + "name": "BIT_OFFSET_5", + "value": 5, + "description": "Busy bit at offset 5 in 8-bit register" + }, + { + "name": "BIT_OFFSET_6", + "value": 6, + "description": "Busy bit at offset 6 in 8-bit register" + }, + { + "name": "BIT_OFFSET_7", + "value": 7, + "description": "Busy bit at offset 7 in 8-bit register" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-24", + "name": "Recovery_CS_Select", + "description": "Recovery CS Select", + "values": [ + { + "name": "CS0", + "value": 0, + "description": "Recovery_CS_Select: CS0" + }, + { + "name": "CS1", + "value": 1, + "description": "Recovery_CS_Select: CS1" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-25", + "name": "RSVD_BT_CFG2_25", + "description": "BOOT_CFG2" + }, + { + "width": 2, + "id": "fuse26-bits-26-27", + "name": "Recovery_Port_Select", + "description": "Recovery Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 4, + "id": "fuse26-bits-28-31", + "name": "FLEXSPI_DUMMY_CYCLE_SEL", + "description": "FlexSPI Dummy Cycle Select", + "values": [ + { + "name": "0_cycle", + "value": 0, + "description": "0 cycle" + }, + { + "name": "CYCLES_1", + "value": 1, + "description": "1 cycle" + }, + { + "name": "CYCLES_2", + "value": 2, + "description": "2 cycles" + }, + { + "name": "CYCLES_3", + "value": 3, + "description": "3 cycles" + }, + { + "name": "CYCLES_4", + "value": 4, + "description": "4 cycles" + }, + { + "name": "CYCLES_5", + "value": 5, + "description": "5 cycles" + }, + { + "name": "CYCLES_6", + "value": 6, + "description": "6 cycles" + }, + { + "name": "CYCLES_7", + "value": 7, + "description": "7 cycles" + }, + { + "name": "CYCLES_8", + "value": 8, + "description": "8 cycles" + }, + { + "name": "CYCLES_9", + "value": 9, + "description": "9 cycles" + }, + { + "name": "CYCLES_10", + "value": 10, + "description": "10 cycles" + }, + { + "name": "CYCLES_11", + "value": 11, + "description": "11 cycles" + }, + { + "name": "CYCLES_12", + "value": 12, + "description": "12 cycles" + }, + { + "name": "CYCLES_13", + "value": 13, + "description": "13 cycles" + }, + { + "name": "CYCLES_14", + "value": 14, + "description": "14 cycles" + }, + { + "name": "15_cycles", + "value": 15, + "description": "15 cycles" + } + ] + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_CFG3", + "description": "BOOT_CFG3", + "index_int": "0x001B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse27-bits-0-2", + "name": "FlexSPI_NOR_Reset_Pin_selection", + "description": "FlexSPI NOR Reset Pin Selection", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "Not reset boot device", + "deprecated_names": [ + "000" + ] + }, + { + "name": "GPIO_PORT1", + "value": 1, + "description": "GPIO port1", + "deprecated_names": [ + "GPIO1" + ] + }, + { + "name": "GPIO_PORT2", + "value": 2, + "description": "GPIO port2", + "deprecated_names": [ + "GPIO2" + ] + }, + { + "name": "GPIO_PORT3", + "value": 3, + "description": "GPIO port3", + "deprecated_names": [ + "GPIO3" + ] + }, + { + "name": "GPIO_PORT4", + "value": 4, + "description": "GPIO port4", + "deprecated_names": [ + "GPIO4" + ] + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-3-4", + "name": "FLEXSPI_NOR_AUTO_PROBE type", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MXIC_OCTAL", + "value": 1, + "description": "MxicOctal" + }, + { + "name": "MICRON_OCTAL", + "value": 2, + "description": "MicronOctal" + }, + { + "name": "ADESTO_OCTAL", + "value": 3, + "description": "AdestoOctal" + } + ] + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved28", + "name": "Reserved 0x1C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001C", + "is_reserved": true + }, + { + "id": "Reserved29", + "name": "Reserved 0x1D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001D", + "is_reserved": true + }, + { + "id": "Reserved30", + "name": "Reserved 0x1E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001E", + "is_reserved": true + }, + { + "id": "Reserved31", + "name": "Reserved 0x1F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001F", + "is_reserved": true + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0020", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "fuse32-bits-8-15", + "name": "Secondary_boot_offset", + "description": "Secondary boot offset", + "values": [ + { + "name": "OFFSET_4MB", + "value": 0, + "description": "Secondary_boot_offset: 4 MB", + "deprecated_names": [ + "4_MB" + ] + }, + { + "name": "OFFSET_2MB", + "value": 1, + "description": "Secondary_boot_offset: 2 MB", + "deprecated_names": [ + "2_MB" + ] + }, + { + "name": "OFFSET_1MB", + "value": 2, + "description": "Secondary_boot_offset: 1 MB", + "deprecated_names": [ + "1_MB" + ] + }, + { + "name": "OFFSET_8MB", + "value": 3, + "description": "Secondary_boot_offset: 8 MB", + "deprecated_names": [ + "8_MB" + ] + }, + { + "name": "OFFSET_16MB", + "value": 4, + "description": "Secondary_boot_offset: 8MB,", + "deprecated_names": [ + "8MB," + ] + }, + { + "name": "OFFSET_32MB", + "value": 5, + "description": "Secondary_boot_offset: 32MB", + "deprecated_names": [ + "32MB" + ] + }, + { + "name": "OFFSET_64MB", + "value": 6, + "description": "Offset = 64 MB" + }, + { + "name": "OFFSET_128MB", + "value": 7, + "description": "Offset = 128 MB" + }, + { + "name": "OFFSET_256MB", + "value": 8, + "description": "Offset = 256 MB" + }, + { + "name": "OFFSET_512MB", + "value": 9, + "description": "Offset = 512 MB", + "deprecated_names": [ + "512_MB" + ] + }, + { + "name": "EMMC_LAST_128MB", + "value": 254, + "description": "EMMC last 128 MB" + }, + { + "name": "EMMC_LAST_24KB", + "value": 255, + "description": "EMMC last 24 KB", + "deprecated_names": [ + "last_24K" + ] + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-16", + "name": "A55_D_Cache_Disable", + "description": "A55 D Cache Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-18", + "name": "USB2_SDP_Disable", + "description": "USB2 SDP Disable", + "values": [ + { + "name": "Not_disable", + "value": 0, + "description": "Not disable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-19", + "name": "Disable_A55_SPI_Recovery", + "description": "Disable A55 SPI Recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-21", + "name": "USB1_SDP_Disable", + "description": "USB1 SDP Disable", + "values": [ + { + "name": "Not_disable", + "value": 0, + "description": "Not disable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-22", + "name": "AHAB_Reauth", + "description": "AHAB Reauth", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Re-authenticate the whole boot code after standby exit is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Re-authenticate the whole boot code after standby exit is enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-24", + "name": "A55_I_Cache_Dis", + "description": "A55 I Cache Dis", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable A55 I-Cache during ROM Boot" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable A55 I-Cache during ROM Boot" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse32-bits-26-27", + "name": "WDOG_Timeout_Select", + "description": "WDOG Timeout Select", + "values": [ + { + "name": "TIMEOUT_32S", + "value": 0, + "description": "WDOG_Timeout_Select: 32 s", + "deprecated_names": [ + "32_s" + ] + }, + { + "name": "TIMEOUT_16S", + "value": 1, + "description": "WDOG_Timeout_Select: 16 s", + "deprecated_names": [ + "16_s" + ] + }, + { + "name": "TIMEOUT_8S", + "value": 2, + "description": "WDOG_Timeout_Select: 8 s", + "deprecated_names": [ + "8_s" + ] + }, + { + "name": "TIMEOUT_4S", + "value": 3, + "description": "WDOG_Timeout_Select: 4 s", + "deprecated_names": [ + "4_s" + ] + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-28", + "name": "A55_WDOG_Enable", + "description": "A55 WDOG Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-29", + "name": "USB_HID_EP1_Out_Disable", + "description": "USB HID EP1 Out Disable", + "values": [ + { + "name": "USB_EP1", + "value": 0, + "description": "USB EP1 Transfer(EP1 Out enable)" + }, + { + "name": "USB_EP0", + "value": 1, + "description": "USB EP0 Transfer(EP1 Out disable)" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-30", + "name": "PLL_LATE_EN", + "description": "PLL LATE EN", + "values": [ + { + "name": "BEFORE_ROM_PATCH", + "value": 0, + "description": "Configure PLLs before installing ROM patch", + "deprecated_names": [ + "0" + ] + }, + { + "name": "AFTER_ROM_PATCH", + "value": 1, + "description": "Configure PLLs after install ROM patch", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse33", + "name": "BOOT_CFG9", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0021", + "bitfields": [ + { + "width": 4 + }, + { + "width": 1, + "id": "fuse33-bit-4", + "name": "A55_Secure_WDOG_Enable (non-ROM)", + "description": "A55 Secure WDOG Enable (non-ROM)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-9", + "name": "CA55_RST_Release_ACK (non-ROM)", + "description": "CA55 RST Release ACK (non-ROM)", + "values": [ + { + "name": "NO_ACK", + "value": 0, + "description": "No Ack from EdgeLock Enclave to release M33 Reset", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ACK_RECEIVED", + "value": 1, + "description": "Ack from EdgeLock Enclave to release M33 Reset", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 14 + }, + { + "width": 1, + "id": "fuse33-bit-24", + "name": "ELE_SRAM_REN_PWRDN (non-ROM)", + "description": "EdgeLock Enclave SRAM REN PWRDN (non-ROM)", + "values": [ + { + "name": "RETAINED", + "value": 0, + "description": "64K retained", + "deprecated_names": [ + "64K" + ] + }, + { + "name": "NOT_RETAINED", + "value": 1, + "description": "I/D-MEM not retained", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse34", + "name": "BOOT_CFG10", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0022", + "bitfields": [ + { + "width": 2, + "id": "fuse34-bits-0-1", + "name": "DAP_ACCESS_IRQ_STKYBIT_DISABLE", + "description": "Disable DAP Access IRQ sticky-bit qualification", + "values": [ + { + "name": "DIRECT_ACCESS", + "value": 0, + "description": "Disable DAP Access qualified by IRQ and sticky-bit logic. Direct DAP Access." + }, + { + "name": "DIRECT_ACCESS_ALT", + "value": 1, + "description": "Disable DAP Access qualified by IRQ and sticky-bit logic. Direct DAP Access." + }, + { + "name": "QUALIFIED_ENABLED", + "value": 2, + "description": "= Enable DAP Access qualified by IRQ and sticky-bit logic.", + "deprecated_names": [ + "10" + ] + }, + { + "name": "DIRECT_ACCESS_DIS", + "value": 3, + "description": "= Disable DAP Access qualified by IRQ and sticky-bit logic. Direct DAP Access.", + "deprecated_names": [ + "11" + ] + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-2", + "name": "SDP_DISABLE", + "description": "SDP Disable ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved35", + "name": "Reserved 0x23", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0023", + "is_reserved": true + }, + { + "id": "Reserved36", + "name": "Reserved 0x24", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0024", + "is_reserved": true + }, + { + "id": "Reserved37", + "name": "Reserved 0x25", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0025", + "is_reserved": true + }, + { + "id": "Reserved38", + "name": "Reserved 0x26", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0026", + "is_reserved": true + }, + { + "id": "Reserved39", + "name": "Reserved 0x27", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0027", + "is_reserved": true + }, + { + "id": "Reserved40", + "name": "Reserved 0x28", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0028", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved41", + "name": "Reserved 0x29", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0029", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved42", + "name": "Reserved 0x2A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002A", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 2 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved43", + "name": "Reserved 0x2B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002B", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 12 + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved44", + "name": "Reserved 0x2C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002C", + "is_reserved": true, + "bitfields": [ + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 9 + } + ] + }, + { + "id": "Reserved45", + "name": "Reserved 0x2D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002D", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 4 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved46", + "name": "Reserved 0x2E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002E", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 19 + } + ] + }, + { + "id": "Reserved47", + "name": "Reserved 0x2F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002F", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved48", + "name": "Reserved 0x30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0030", + "is_reserved": true + }, + { + "id": "Reserved49", + "name": "Reserved 0x31", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0031", + "is_reserved": true + }, + { + "id": "Reserved50", + "name": "Reserved 0x32", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0032", + "is_reserved": true + }, + { + "id": "Reserved51", + "name": "Reserved 0x33", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0033", + "is_reserved": true + }, + { + "id": "Reserved52", + "name": "Reserved 0x34", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0034", + "is_reserved": true + }, + { + "id": "Reserved53", + "name": "Reserved 0x35", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0035", + "is_reserved": true + }, + { + "id": "Reserved54", + "name": "Reserved 0x36", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0036", + "is_reserved": true + }, + { + "id": "Reserved55", + "name": "Reserved 0x37", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0037", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "fuse56", + "name": "ELE_MISC_CTRL0", + "description": "OEM controlled Fuse.", + "index_int": "0x0038", + "bitfields": [ + { + "width": 4, + "id": "fuse56-bits-0-3", + "name": "SOC_SCOPE_PRIMARY_DBG_DISABLE", + "description": "Debug Disable for CM33 ", + "values": [ + { + "name": "ALL_DEBUG_ENABLED", + "value": 0, + "description": "All debug features enabled - spiden, sniden, dbgen, niden all enabled" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug in non-secure state disabled, other debug features enabled" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Invasive debug in non-secure state disabled, other debug features enabled" + }, + { + "name": "NONSECURE_DBG_DISABLED", + "value": 3, + "description": "Non-secure debug disabled - dbgen and niden disabled, secure debug enabled" + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled, other debug features enabled" + }, + { + "name": "SNIDEN_NIDEN_DISABLED", + "value": 5, + "description": "Secure non-invasive and non-secure invasive debug disabled (spiden=0,sniden=1,dbgen=0,niden=1)" + }, + { + "name": "SNIDEN_DBGEN_DISABLED", + "value": 6, + "description": "Secure non-invasive and non-secure invasive debug disabled (spiden=0,sniden=1,dbgen=1,niden=0)" + }, + { + "name": "INVASIVE_DBG_ENABLED", + "value": 7, + "description": "Secure non-invasive and non-secure invasive debug disabled (spiden=0,sniden=1,dbgen=1,niden=1)" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure privileged invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=0)" + }, + { + "name": "SPIDEN_NIDEN_DISABLED", + "value": 9, + "description": "Secure privileged invasive and non-secure invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=1)", + "deprecated_names": [ + "SECURE_INVASIVE_DISABLED" + ] + }, + { + "name": "SPIDEN_DBGEN_DISABLED", + "value": 10, + "description": "Secure privileged invasive and non-secure invasive debug disabled (spiden=1,sniden=0,dbgen=1,niden=0)", + "deprecated_names": [ + "INVASIVE_DBG_DISABLED" + ] + }, + { + "name": "SPIDEN_ONLY_ENABLED", + "value": 11, + "description": "Secure and non-secure invasive debug disabled (spiden=1,sniden=0,dbgen=1,niden=1)" + }, + { + "name": "SECURE_DBG_DISABLED", + "value": 12, + "description": "Secure debug disabled - spiden and sniden disabled, non-secure debug enabled" + }, + { + "name": "NONINVASIVE_ENABLED", + "value": 13, + "description": "Secure invasive and non-secure invasive debug disabled (spiden=1,sniden=1,dbgen=0,niden=1)" + }, + { + "name": "NIDEN_ONLY_ENABLED", + "value": 14, + "description": "Secure invasive and non-secure invasive debug disabled (spiden=1,sniden=1,dbgen=1,niden=0)" + }, + { + "name": "ALL_DEBUG_DISABLED", + "value": 15, + "description": "All debug features disabled - spiden, sniden, dbgen, niden all disabled" + } + ] + }, + { + "width": 4, + "id": "fuse56-bits-4-7", + "name": "SOC_SCOPE1_DBG_DISABLE", + "description": "SOC SCOPE1 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_DISABLED", + "value": 0, + "description": "All debug features disabled - spiden, sniden, dbgen, niden all disabled" + }, + { + "name": "NIDEN_ENABLED", + "value": 1, + "description": "Non-invasive debug enabled, invasive debug disabled" + }, + { + "name": "DBGEN_ENABLED", + "value": 2, + "description": "AXI non-secure trace buffer dump enabled, others disabled" + }, + { + "name": "DBGEN_NIDEN_ENABLED", + "value": 3, + "description": "AXI non-secure trace and non-invasive debug enabled" + }, + { + "name": "SNIDEN_ENABLED", + "value": 4, + "description": "Secure non-invasive debug enabled, others disabled" + }, + { + "name": "SNIDEN_NIDEN_ENABLED", + "value": 5, + "description": "Secure and non-secure non-invasive debug enabled" + }, + { + "name": "SNIDEN_DBGEN_ENABLED", + "value": 6, + "description": "Secure non-invasive and AXI non-secure trace enabled" + }, + { + "name": "SNIDEN_DBGEN_NIDEN", + "value": 7, + "description": "Secure non-invasive, AXI non-secure trace, non-invasive debug enabled" + }, + { + "name": "SPIDEN_ENABLED", + "value": 8, + "description": "AXI secure trace buffer dump enabled, others disabled" + }, + { + "name": "SPIDEN_NIDEN_ENABLED", + "value": 9, + "description": "AXI secure trace and non-invasive debug enabled" + }, + { + "name": "SPIDEN_DBGEN_ENABLED", + "value": 10, + "description": "AXI secure and non-secure trace buffer dump enabled" + }, + { + "name": "SPIDEN_DBGEN_NIDEN", + "value": 11, + "description": "AXI secure/non-secure trace and non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_ENABLED", + "value": 12, + "description": "AXI secure trace and secure non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_NIDEN", + "value": 13, + "description": "AXI secure trace, secure and non-secure non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_DBGEN", + "value": 14, + "description": "AXI secure/non-secure trace and secure non-invasive debug enabled" + }, + { + "name": "ALL_ENABLED", + "value": 15, + "description": "All debug features enabled - spiden, sniden, dbgen, niden all enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse56-bits-12-15", + "name": "SOC_SCOPE3_DBG_DISABLE", + "description": "SOC SCOPE3 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_DEBUG_ENABLED", + "value": 0, + "description": "All debug features enabled (spiden, sniden, dbgen, niden all active)" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug disabled (spiden=0,sniden=0,dbgen=0,niden=1)" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Debug disabled (spiden=0,sniden=0,dbgen=1,niden=0)" + }, + { + "name": "NIDEN_DBGEN_DISABLED", + "value": 3, + "description": "Invasive debug disabled (spiden=0,sniden=0,dbgen=1,niden=1)", + "deprecated_names": [ + "INVASIVE_DBG_DISABLED" + ] + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled (spiden=0,sniden=1,dbgen=0,niden=0)" + }, + { + "name": "SECURE_NIDEN_DISABLED", + "value": 5, + "description": "Secure and non-invasive debug disabled (spiden=0,sniden=1,dbgen=0,niden=1)" + }, + { + "name": "SECURE_INVASIVE_OFF", + "value": 6, + "description": "Secure non-invasive and invasive debug disabled (spiden=0,sniden=1,dbgen=1,niden=0)" + }, + { + "name": "NON_SECURE_DBG_OFF", + "value": 7, + "description": "Secure non-invasive, non-invasive, and invasive debug disabled" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure privileged invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=0)" + }, + { + "name": "SPIDEN_NIDEN_DISABLED", + "value": 9, + "description": "Secure privileged invasive and non-invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=1)", + "deprecated_names": [ + "SECURE_INVASIVE_OFF2" + ] + }, + { + "name": "SPIDEN_DBGEN_DISABLED", + "value": 10, + "description": "Secure privileged and invasive debug disabled (spiden=1,sniden=0,dbgen=1,niden=0)", + "deprecated_names": [ + "ALL_INVASIVE_OFF" + ] + }, + { + "name": "SPIDEN_NIDEN_DBG_DIS", + "value": 11, + "description": "Secure privileged and all invasive debug disabled (spiden=1,sniden=0,dbgen=1,niden=1)", + "deprecated_names": [ + "INVASIVE_NIDEN_OFF" + ] + }, + { + "name": "SPIDEN_SNIDEN_DISABLED", + "value": 12, + "description": "All secure debug disabled (spiden=1,sniden=1,dbgen=0,niden=0)", + "deprecated_names": [ + "SECURE_DEBUG_OFF" + ] + }, + { + "name": "SPIDEN_SNIDEN_NID_DIS", + "value": 13, + "description": "Secure invasive, secure non-invasive, and non-invasive debug disabled", + "deprecated_names": [ + "MOST_DEBUG_OFF" + ] + }, + { + "name": "SPIDEN_SNIDEN_DBG_DIS", + "value": 14, + "description": "Secure invasive, secure non-invasive, and invasive debug disabled", + "deprecated_names": [ + "INVASIVE_ONLY" + ] + }, + { + "name": "ALL_DEBUG_DISABLED", + "value": 15, + "description": "All debug features disabled (spiden, sniden, dbgen, niden all disabled)" + } + ] + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse57", + "name": "ELE_MISC_CTRL1", + "description": "OEM controlled Fuse.", + "index_int": "0x0039", + "bitfields": [ + { + "width": 4, + "id": "fuse57-bits-0-3", + "name": "SOC_SCOPE4_DBG_DISABLE", + "description": "SOC SCOPE4 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_DEBUG_ENABLED", + "value": 0, + "description": "All debug features enabled (spiden=0,sniden=0,dbgen=0,niden=0)" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug disabled (spiden=0,sniden=0,dbgen=0,niden=1)" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Debug disabled, non-invasive and secure debug enabled" + }, + { + "name": "NIDEN_DBGEN_DISABLED", + "value": 3, + "description": "Debug and non-invasive debug disabled (spiden=0,sniden=0,dbgen=1,niden=1)" + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled (spiden=0,sniden=1,dbgen=0,niden=0)" + }, + { + "name": "SNIDEN_NIDEN_DISABLED", + "value": 5, + "description": "Secure and non-invasive debug disabled (spiden=0,sniden=1,dbgen=0,niden=1)" + }, + { + "name": "SNIDEN_DBGEN_DISABLED", + "value": 6, + "description": "Secure non-invasive and debug disabled (spiden=0,sniden=1,dbgen=1,niden=0)" + }, + { + "name": "NS_DEBUG_DISABLED", + "value": 7, + "description": "Only invasive debug enabled (spiden=0,sniden=1,dbgen=1,niden=1)" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure privileged invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=0)" + }, + { + "name": "SPIDEN_NIDEN_DISABLED", + "value": 9, + "description": "Secure privileged invasive and non-invasive debug disabled (spiden=1,sniden=0,dbgen=0,niden=1)" + }, + { + "name": "SPIDEN_DBGEN_DISABLED", + "value": 10, + "description": "Secure privileged invasive and debug disabled (spiden=1,sniden=0,dbgen=1,niden=0)" + }, + { + "name": "SNIDEN_ENABLED_ONLY", + "value": 11, + "description": "Only secure non-invasive debug enabled (spiden=1,sniden=0,dbgen=1,niden=1)", + "deprecated_names": [ + "INVASIVE_NIDEN_DISABLED" + ] + }, + { + "name": "SPIDEN_SNIDEN_DISABLED", + "value": 12, + "description": "All secure debug disabled (spiden=1,sniden=1,dbgen=0,niden=0)", + "deprecated_names": [ + "SECURE_DEBUG_DISABLED" + ] + }, + { + "name": "NONSECURE_NIDEN_ENABLED", + "value": 13, + "description": "Secure and non-invasive debug disabled (spiden=1,sniden=1,dbgen=0,niden=1)", + "deprecated_names": [ + "SECURE_NIDEN_DISABLED" + ] + }, + { + "name": "NONSECURE_DBGEN_ENABLED", + "value": 14, + "description": "Secure privileged invasive, secure non-invasive, and debug disabled", + "deprecated_names": [ + "SECURE_DBGEN_DISABLED" + ] + }, + { + "name": "ALL_DEBUG_DISABLED", + "value": 15, + "description": "All debug features disabled (spiden=1,sniden=1,dbgen=1,niden=1)" + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse57-bit-8", + "name": "SJC_DISABLE", + "description": "Hardware disablement of SJC. Disables JTAG debugger, including ability for boundary scan.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "SJC is enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "SJC is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 7 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse58", + "name": "ELE_MISC_CTRL2", + "description": "OEM controlled Fuse.", + "index_int": "0x003A", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse58-bits-6-7", + "name": "OEM_GDET_DISABLE", + "description": "OEM GDET DISABLE", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Disable ELE Glitch detector. This bit should only be set if security is not of concern. This bit can only be set in OEM OPEN" + }, + { + "name": "DISABLED", + "value": 1, + "description": "ELE Glitch detector is enabled (default secure state)" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-8", + "name": "SOC_GLBL_DBG_DISABLE", + "description": "SOC GLBL DBG DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Global JTAG disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Global JTAG enable" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-9", + "name": "NORMAL_CH_RESP_DISABLE", + "description": "NORMAL CH RESP DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Password match mechanism for debug enable is active" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Password match mechanism for debug enable is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-10", + "name": "TZ_GLBL_DBG_DISABLE", + "description": "TZ GLBL DBG DISABLE" + }, + { + "width": 1, + "id": "fuse58-bit-11", + "name": "TZ_CH_RESP_DISABLE", + "description": "TZ CH RESP DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Password match mechanism for trust zone debug enable is active" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Password match mechanism for trust zone debug enable is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-12", + "name": "OEM_FDET_DISABLE", + "description": "OEM FDET DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "ELE Frequency detectors are enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Disable ELE Frequency detectors. This bit can only be set in OEM OPEN" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "fuse59", + "name": "ELE_MISC_CTRL3", + "description": "NXP controlled.", + "index_int": "0x003B", + "bitfields": [ + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse59-bits-3-4", + "name": "FASTBOOT_ENABLE", + "description": "FastBoot Enablement", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "= Disable FastBoot", + "deprecated_names": [ + "00" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "= Enable FastBoot", + "deprecated_names": [ + "01" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse60", + "name": "ELE_MISC_CTRL4", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003C", + "reg_width": 16, + "bitfields": [ + { + "width": 12, + "id": "fuse60-bits-0-11", + "name": "EXPORT_CONTROL", + "description": "Each fuse disables the following : \n[11] : Reserved for NXP\n[10] : Reserved for NXP\n[9] : Reserved\n[8] : Reserved for ELE\n[7] : A55 Crypto extension\n[6] : M7 MMCAU\n[5] : M33 MMCAU\n[4] : OTFADs\n[3:0] : Reserved" + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse61", + "name": "ELE_MISC_CTRL5", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003D", + "bitfields": [ + { + "width": 1, + "id": "fuse61-bit-0", + "name": "DFT_DISABLE", + "description": "DFT DISABLE", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved62", + "name": "Reserved 0x3E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003E", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved63", + "name": "Reserved 0x3F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved64", + "name": "Reserved 0x40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0040", + "is_reserved": true + }, + { + "id": "Reserved65", + "name": "Reserved 0x41", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0041", + "is_reserved": true + }, + { + "id": "Reserved66", + "name": "Reserved 0x42", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0042", + "is_reserved": true + }, + { + "id": "Reserved67", + "name": "Reserved 0x43", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0043", + "is_reserved": true + }, + { + "id": "Reserved68", + "name": "Reserved 0x44", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0044", + "is_reserved": true + }, + { + "id": "Reserved69", + "name": "Reserved 0x45", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0045", + "is_reserved": true + }, + { + "id": "Reserved70", + "name": "Reserved 0x46", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0046", + "is_reserved": true + }, + { + "id": "Reserved71", + "name": "Reserved 0x47", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0047", + "is_reserved": true + }, + { + "id": "Reserved72", + "name": "Reserved 0x48", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0048", + "is_reserved": true + }, + { + "id": "Reserved73", + "name": "Reserved 0x49", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0049", + "is_reserved": true + }, + { + "id": "Reserved74", + "name": "Reserved 0x4A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004A", + "is_reserved": true + }, + { + "id": "Reserved75", + "name": "Reserved 0x4B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004B", + "is_reserved": true + }, + { + "id": "Reserved76", + "name": "Reserved 0x4C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004C", + "is_reserved": true + }, + { + "id": "Reserved77", + "name": "Reserved 0x4D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004D", + "is_reserved": true + }, + { + "id": "Reserved78", + "name": "Reserved 0x4E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004E", + "is_reserved": true + }, + { + "id": "Reserved79", + "name": "Reserved 0x4F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004F", + "is_reserved": true + }, + { + "id": "Reserved80", + "name": "Reserved 0x50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0050", + "is_reserved": true + }, + { + "id": "Reserved81", + "name": "Reserved 0x51", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0051", + "is_reserved": true + }, + { + "id": "Reserved82", + "name": "Reserved 0x52", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0052", + "is_reserved": true + }, + { + "id": "Reserved83", + "name": "Reserved 0x53", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0053", + "is_reserved": true + }, + { + "id": "Reserved84", + "name": "Reserved 0x54", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0054", + "is_reserved": true + }, + { + "id": "Reserved85", + "name": "Reserved 0x55", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0055", + "is_reserved": true + }, + { + "id": "Reserved86", + "name": "Reserved 0x56", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0056", + "is_reserved": true + }, + { + "id": "Reserved87", + "name": "Reserved 0x57", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0057", + "is_reserved": true + }, + { + "id": "fuse88", + "name": "JTAG_RESP7", + "description": "Part of 128 bit key to enable SoC domain debug", + "index_int": "0x0058", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse89", + "name": "JTAG_RESP6", + "description": "Part of 128 bit key to enable SoC domain debug", + "index_int": "0x0059", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse90", + "name": "JTAG_RESP5", + "description": "Part of 128 bit key to enable SoC domain debug", + "index_int": "0x005A", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse91", + "name": "JTAG_RESP4", + "description": "Part of 128 bit key to enable SoC domain debug", + "index_int": "0x005B", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse92", + "name": "JTAG_RESP3", + "description": "Part of 128 bit key to TZ SoC domain debug", + "index_int": "0x005C", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse93", + "name": "JTAG_RESP2", + "description": "Part of 128 bit key to TZ SoC domain debug", + "index_int": "0x005D", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse94", + "name": "JTAG_RESP1", + "description": "Part of 128 bit key to TZ SoC domain debug", + "index_int": "0x005E", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse95", + "name": "JTAG_RESP0", + "description": "Part of 128 bit key to TZ SoC domain debug", + "index_int": "0x005F", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "Reserved96", + "name": "Reserved 0x60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0060", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved97", + "name": "Reserved 0x61", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0061", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved98", + "name": "Reserved 0x62", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0062", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved99", + "name": "Reserved 0x63", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0063", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved100", + "name": "Reserved 0x64", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0064", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved101", + "name": "Reserved 0x65", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0065", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved102", + "name": "Reserved 0x66", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0066", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved103", + "name": "Reserved 0x67", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0067", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved104", + "name": "Reserved 0x68", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0068", + "is_reserved": true + }, + { + "id": "Reserved105", + "name": "Reserved 0x69", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0069", + "is_reserved": true + }, + { + "id": "Reserved106", + "name": "Reserved 0x6A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006A", + "is_reserved": true + }, + { + "id": "Reserved107", + "name": "Reserved 0x6B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006B", + "is_reserved": true + }, + { + "id": "Reserved108", + "name": "Reserved 0x6C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006C", + "is_reserved": true + }, + { + "id": "Reserved109", + "name": "Reserved 0x6D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006D", + "is_reserved": true + }, + { + "id": "Reserved110", + "name": "Reserved 0x6E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006E", + "is_reserved": true + }, + { + "id": "Reserved111", + "name": "Reserved 0x6F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006F", + "is_reserved": true + }, + { + "id": "Reserved112", + "name": "Reserved 0x70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0070", + "is_reserved": true + }, + { + "id": "Reserved113", + "name": "Reserved 0x71", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0071", + "is_reserved": true + }, + { + "id": "Reserved114", + "name": "Reserved 0x72", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0072", + "is_reserved": true + }, + { + "id": "Reserved115", + "name": "Reserved 0x73", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0073", + "is_reserved": true + }, + { + "id": "Reserved116", + "name": "Reserved 0x74", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0074", + "is_reserved": true + }, + { + "id": "Reserved117", + "name": "Reserved 0x75", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0075", + "is_reserved": true + }, + { + "id": "Reserved118", + "name": "Reserved 0x76", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0076", + "is_reserved": true + }, + { + "id": "Reserved119", + "name": "Reserved 0x77", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0077", + "is_reserved": true + }, + { + "id": "Reserved120", + "name": "Reserved 0x78", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0078", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved121", + "name": "Reserved 0x79", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0079", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved122", + "name": "Reserved 0x7A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007A", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved123", + "name": "Reserved 0x7B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved124", + "name": "Reserved 0x7C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007C", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved125", + "name": "Reserved 0x7D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved126", + "name": "Reserved 0x7E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved127", + "name": "Reserved 0x7F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "fuse128", + "name": "OEM_SRKH0", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0080", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse129", + "name": "OEM_SRKH1", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0081", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse130", + "name": "OEM_SRKH2", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0082", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse131", + "name": "OEM_SRKH3", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0083", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse132", + "name": "OEM_SRKH4", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0084", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse133", + "name": "OEM_SRKH5", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0085", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse134", + "name": "OEM_SRKH6", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0086", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse135", + "name": "OEM_SRKH7", + "description": "Hash of OEM SRK public keys stored in Container", + "index_int": "0x0087", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "Reserved136", + "name": "Reserved 0x88", + "description": "Reserved for future use. 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Software should not rely on the value.", + "index_int": "0x00AB", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved172", + "name": "Reserved 0xAC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AC", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved173", + "name": "Reserved 0xAD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AD", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved174", + "name": "Reserved 0xAE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AE", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved175", + "name": "Reserved 0xAF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AF", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved176", + "name": "Reserved 0xB0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B0", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 7 + }, + { + "width": 9 + } + ] + }, + { + "id": "Reserved177", + "name": "Reserved 0xB1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C9", + "is_reserved": true + }, + { + "id": "Reserved202", + "name": "Reserved 0xCA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CA", + "is_reserved": true + }, + { + "id": "Reserved203", + "name": "Reserved 0xCB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CB", + "is_reserved": true + }, + { + "id": "Reserved204", + "name": "Reserved 0xCC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CC", + "is_reserved": true + }, + { + "id": "Reserved205", + "name": "Reserved 0xCD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CD", + "is_reserved": true + }, + { + "id": "Reserved206", + "name": "Reserved 0xCE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CE", + "is_reserved": true + }, + { + "id": "Reserved207", + "name": "Reserved 0xCF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CF", + "is_reserved": true + }, + { + "id": "Reserved208", + "name": "Reserved 0xD0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D0", + "is_reserved": true + }, + { + "id": "Reserved209", + "name": "Reserved 0xD1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D1", + "is_reserved": true + }, + { + "id": "Reserved210", + "name": "Reserved 0xD2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D2", + "is_reserved": true + }, + { + "id": "Reserved211", + "name": "Reserved 0xD3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D3", + "is_reserved": true + }, + { + "id": "Reserved212", + "name": "Reserved 0xD4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D4", + "is_reserved": true + }, + { + "id": "Reserved213", + "name": "Reserved 0xD5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D5", + "is_reserved": true + }, + { + "id": "Reserved214", + "name": "Reserved 0xD6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D6", + "is_reserved": true + }, + { + "id": "Reserved215", + "name": "Reserved 0xD7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D7", + "is_reserved": true + }, + { + "id": "Reserved216", + "name": "Reserved 0xD8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D8", + "is_reserved": true + }, + { + "id": "Reserved217", + "name": "Reserved 0xD9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D9", + "is_reserved": true + }, + { + "id": "Reserved218", + "name": "Reserved 0xDA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DA", + "is_reserved": true + }, + { + "id": "Reserved219", + "name": "Reserved 0xDB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DB", + "is_reserved": true + }, + { + "id": "Reserved220", + "name": "Reserved 0xDC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DC", + "is_reserved": true + }, + { + "id": "Reserved221", + "name": "Reserved 0xDD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DD", + "is_reserved": true + }, + { + "id": "Reserved222", + "name": "Reserved 0xDE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DE", + "is_reserved": true + }, + { + "id": "Reserved223", + "name": "Reserved 0xDF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DF", + "is_reserved": true + }, + { + "id": "Reserved224", + "name": "Reserved 0xE0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E0", + "is_reserved": true + }, + { + "id": "Reserved225", + "name": "Reserved 0xE1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E1", + "is_reserved": true + }, + { + "id": "Reserved226", + "name": "Reserved 0xE2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E2", + "is_reserved": true + }, + { + "id": "Reserved227", + "name": "Reserved 0xE3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E3", + "is_reserved": true + }, + { + "id": "Reserved228", + "name": "Reserved 0xE4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E4", + "is_reserved": true + }, + { + "id": "Reserved229", + "name": "Reserved 0xE5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E5", + "is_reserved": true + }, + { + "id": "Reserved230", + "name": "Reserved 0xE6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E6", + "is_reserved": true + }, + { + "id": "Reserved231", + "name": "Reserved 0xE7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E7", + "is_reserved": true + }, + { + "id": "Reserved232", + "name": "Reserved 0xE8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E8", + "is_reserved": true + }, + { + "id": "Reserved233", + "name": "Reserved 0xE9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E9", + "is_reserved": true + }, + { + "id": "Reserved234", + "name": "Reserved 0xEA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EA", + "is_reserved": true + }, + { + "id": "Reserved235", + "name": "Reserved 0xEB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EB", + "is_reserved": true + }, + { + "id": "Reserved236", + "name": "Reserved 0xEC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EC", + "is_reserved": true + }, + { + "id": "Reserved237", + "name": "Reserved 0xED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00ED", + "is_reserved": true + }, + { + "id": "Reserved238", + "name": "Reserved 0xEE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EE", + "is_reserved": true + }, + { + "id": "Reserved239", + "name": "Reserved 0xEF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EF", + "is_reserved": true + }, + { + "id": "Reserved240", + "name": "Reserved 0xF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F0", + "is_reserved": true + }, + { + "id": "Reserved241", + "name": "Reserved 0xF1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F1", + "is_reserved": true + }, + { + "id": "Reserved242", + "name": "Reserved 0xF2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F2", + "is_reserved": true + }, + { + "id": "Reserved243", + "name": "Reserved 0xF3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F3", + "is_reserved": true + }, + { + "id": "Reserved244", + "name": "Reserved 0xF4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F4", + "is_reserved": true + }, + { + "id": "Reserved245", + "name": "Reserved 0xF5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F5", + "is_reserved": true + }, + { + "id": "Reserved246", + "name": "Reserved 0xF6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F6", + "is_reserved": true + }, + { + "id": "Reserved247", + "name": "Reserved 0xF7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F7", + "is_reserved": true + }, + { + "id": "Reserved248", + "name": "Reserved 0xF8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F8", + "is_reserved": true + }, + { + "id": "Reserved249", + "name": "Reserved 0xF9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F9", + "is_reserved": true + }, + { + "id": "Reserved250", + "name": "Reserved 0xFA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FA", + "is_reserved": true + }, + { + "id": "Reserved251", + "name": "Reserved 0xFB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FB", + "is_reserved": true + }, + { + "id": "Reserved252", + "name": "Reserved 0xFC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FC", + "is_reserved": true + }, + { + "id": "Reserved253", + "name": "Reserved 0xFD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FD", + "is_reserved": true + }, + { + "id": "Reserved254", + "name": "Reserved 0xFE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FE", + "is_reserved": true + }, + { + "id": "Reserved255", + "name": "Reserved 0xFF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FF", + "is_reserved": true + }, + { + "id": "Reserved256", + "name": "Reserved 0x100", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0100", + "is_reserved": true + }, + { + "id": "Reserved257", + "name": "Reserved 0x101", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0101", + "is_reserved": true + }, + { + "id": "Reserved258", + "name": "Reserved 0x102", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0102", + "is_reserved": true + }, + { + "id": "Reserved259", + "name": "Reserved 0x103", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0103", + "is_reserved": true + }, + { + "id": "Reserved260", + "name": "Reserved 0x104", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0104", + "is_reserved": true + }, + { + "id": "Reserved261", + "name": "Reserved 0x105", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0105", + "is_reserved": true + }, + { + "id": "Reserved262", + "name": "Reserved 0x106", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0106", + "is_reserved": true + }, + { + "id": "Reserved263", + "name": "Reserved 0x107", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0107", + "is_reserved": true + }, + { + "id": "Reserved264", + "name": "Reserved 0x108", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0108", + "is_reserved": true + }, + { + "id": "Reserved265", + "name": "Reserved 0x109", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0109", + "is_reserved": true + }, + { + "id": "Reserved266", + "name": "Reserved 0x10A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010A", + "is_reserved": true + }, + { + "id": "Reserved267", + "name": "Reserved 0x10B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010B", + "is_reserved": true + }, + { + "id": "Reserved268", + "name": "Reserved 0x10C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010C", + "is_reserved": true + }, + { + "id": "Reserved269", + "name": "Reserved 0x10D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010D", + "is_reserved": true + }, + { + "id": "Reserved270", + "name": "Reserved 0x10E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010E", + "is_reserved": true + }, + { + "id": "Reserved271", + "name": "Reserved 0x10F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010F", + "is_reserved": true + }, + { + "id": "Reserved272", + "name": "Reserved 0x110", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0110", + "is_reserved": true + }, + { + "id": "Reserved273", + "name": "Reserved 0x111", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0111", + "is_reserved": true + }, + { + "id": "Reserved274", + "name": "Reserved 0x112", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0112", + "is_reserved": true + }, + { + "id": "Reserved275", + "name": "Reserved 0x113", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0113", + "is_reserved": true + }, + { + "id": "Reserved276", + "name": "Reserved 0x114", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0114", + "is_reserved": true + }, + { + "id": "Reserved277", + "name": "Reserved 0x115", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0115", + "is_reserved": true + }, + { + "id": "Reserved278", + "name": "Reserved 0x116", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0116", + "is_reserved": true + }, + { + "id": "Reserved279", + "name": "Reserved 0x117", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0117", + "is_reserved": true + }, + { + "id": "Reserved280", + "name": "Reserved 0x118", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0118", + "is_reserved": true + }, + { + "id": "Reserved281", + "name": "Reserved 0x119", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0119", + "is_reserved": true + }, + { + "id": "Reserved282", + "name": "Reserved 0x11A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011A", + "is_reserved": true + }, + { + "id": "Reserved283", + "name": "Reserved 0x11B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011B", + "is_reserved": true + }, + { + "id": "Reserved284", + "name": "Reserved 0x11C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011C", + "is_reserved": true + }, + { + "id": "Reserved285", + "name": "Reserved 0x11D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011D", + "is_reserved": true + }, + { + "id": "Reserved286", + "name": "Reserved 0x11E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011E", + "is_reserved": true + }, + { + "id": "Reserved287", + "name": "Reserved 0x11F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011F", + "is_reserved": true + }, + { + "id": "Reserved288", + "name": "Reserved 0x120", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0120", + "is_reserved": true + }, + { + "id": "Reserved289", + "name": "Reserved 0x121", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0121", + "is_reserved": true + }, + { + "id": "Reserved290", + "name": "Reserved 0x122", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0122", + "is_reserved": true + }, + { + "id": "Reserved291", + "name": "Reserved 0x123", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0123", + "is_reserved": true + }, + { + "id": "Reserved292", + "name": "Reserved 0x124", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0124", + "is_reserved": true + }, + { + "id": "Reserved293", + "name": "Reserved 0x125", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0125", + "is_reserved": true + }, + { + "id": "Reserved294", + "name": "Reserved 0x126", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0126", + "is_reserved": true + }, + { + "id": "Reserved295", + "name": "Reserved 0x127", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0127", + "is_reserved": true + }, + { + "id": "Reserved296", + "name": "Reserved 0x128", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0128", + "is_reserved": true + }, + { + "id": "Reserved297", + "name": "Reserved 0x129", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0129", + "is_reserved": true + }, + { + "id": "Reserved298", + "name": "Reserved 0x12A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012A", + "is_reserved": true + }, + { + "id": "Reserved299", + "name": "Reserved 0x12B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012B", + "is_reserved": true + }, + { + "id": "Reserved300", + "name": "Reserved 0x12C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012C", + "is_reserved": true + }, + { + "id": "Reserved301", + "name": "Reserved 0x12D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012D", + "is_reserved": true + }, + { + "id": "Reserved302", + "name": "Reserved 0x12E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012E", + "is_reserved": true + }, + { + "id": "Reserved303", + "name": "Reserved 0x12F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012F", + "is_reserved": true + }, + { + "id": "Reserved304", + "name": "Reserved 0x130", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0130", + "is_reserved": true + }, + { + "id": "Reserved305", + "name": "Reserved 0x131", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0131", + "is_reserved": true + }, + { + "id": "Reserved306", + "name": "Reserved 0x132", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0132", + "is_reserved": true + }, + { + "id": "Reserved307", + "name": "Reserved 0x133", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0133", + "is_reserved": true + }, + { + "id": "Reserved308", + "name": "Reserved 0x134", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0134", + "is_reserved": true + }, + { + "id": "Reserved309", + "name": "Reserved 0x135", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0135", + "is_reserved": true + }, + { + "id": "Reserved310", + "name": "Reserved 0x136", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0136", + "is_reserved": true + }, + { + "id": "Reserved311", + "name": "Reserved 0x137", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0137", + "is_reserved": true + }, + { + "id": "fuse312", + "name": "COM_DEVICE_ID_CFG0", + "description": "COM_DEVICE_ID_CFG0", + "index_int": "0x0138", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse312-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse312-bits-16-31", + "name": "USB1_PID", + "description": "USB1 Product ID" + } + ] + }, + { + "id": "fuse313", + "name": "COM_DEVICE_ID_CFG1", + "description": "COM_DEVICE_ID_CFG1", + "index_int": "0x0139", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse313-bits-0-15", + "name": "USB2_PID", + "description": "USB2 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved314", + "name": "Reserved 0x13A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013A", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse315", + "name": "COM_DEVICE_ID_CFG3", + "description": "COM_DEVICE_ID_CFG3", + "index_int": "0x013B", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse315-bits-0-31", + "name": "MAC1_ADDR_31_0", + "description": "MAC_1 Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse316", + "name": "COM_DEVICE_ID_CFG4", + "description": "COM_DEVICE_ID_CFG4", + "index_int": "0x013C", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse316-bits-0-15", + "name": "MAC1_ADDR_47_32", + "description": "MAC_1 Address. Reserved for customer SW" + }, + { + "width": 16, + "id": "fuse316-bits-16-31", + "name": "MAC2_ADDR_15_0", + "description": "MAC_2 Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse317", + "name": "COM_DEVICE_ID_CFG5", + "description": "COM_DEVICE_ID_CFG5", + "index_int": "0x013D", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse317-bits-0-31", + "name": "MAC2_ADDR_47_16", + "description": "MAC_2 Address. Reserved for customer SW" + } + ] + }, + { + "id": "Reserved318", + "name": "Reserved 0x13E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved319", + "name": "Reserved 0x13F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013F", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved320", + "name": "Reserved 0x140", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0140", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved321", + "name": "Reserved 0x141", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0141", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved322", + "name": "Reserved 0x142", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0142", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved323", + "name": "Reserved 0x143", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0143", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved324", + "name": "Reserved 0x144", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0144", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved325", + "name": "Reserved 0x145", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0145", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved326", + "name": "Reserved 0x146", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0146", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse327", + "name": "OEM_SW_CFG", + "description": "OEM Software Configuration", + "index_int": "0x0147", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16 + }, + { + "id": "Reserved328", + "name": "Reserved 0x148", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0148", + "is_reserved": true + }, + { + "id": "Reserved329", + "name": "Reserved 0x149", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0149", + "is_reserved": true + }, + { + "id": "Reserved330", + "name": "Reserved 0x14A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014A", + "is_reserved": true + }, + { + "id": "Reserved331", + "name": "Reserved 0x14B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014B", + "is_reserved": true + }, + { + "id": "Reserved332", + "name": "Reserved 0x14C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014C", + "is_reserved": true + }, + { + "id": "Reserved333", + "name": "Reserved 0x14D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014D", + "is_reserved": true + }, + { + "id": "Reserved334", + "name": "Reserved 0x14E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014E", + "is_reserved": true + }, + { + "id": "Reserved335", + "name": "Reserved 0x14F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014F", + "is_reserved": true + }, + { + "id": "Reserved336", + "name": "Reserved 0x150", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0150", + "is_reserved": true + }, + { + "id": "Reserved337", + "name": "Reserved 0x151", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0151", + "is_reserved": true + }, + { + "id": "Reserved338", + "name": "Reserved 0x152", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0152", + "is_reserved": true + }, + { + "id": "Reserved339", + "name": "Reserved 0x153", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0153", + "is_reserved": true + }, + { + "id": "Reserved340", + "name": "Reserved 0x154", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0154", + "is_reserved": true + }, + { + "id": "Reserved341", + "name": "Reserved 0x155", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0155", + "is_reserved": true + }, + { + "id": "Reserved342", + "name": "Reserved 0x156", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0156", + "is_reserved": true + }, + { + "id": "Reserved343", + "name": "Reserved 0x157", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0157", + "is_reserved": true + }, + { + "id": "Reserved344", + "name": "Reserved 0x158", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0158", + "is_reserved": true + }, + { + "id": "Reserved345", + "name": "Reserved 0x159", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0159", + "is_reserved": true + }, + { + "id": "Reserved346", + "name": "Reserved 0x15A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015A", + "is_reserved": true + }, + { + "id": "Reserved347", + "name": "Reserved 0x15B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015B", + "is_reserved": true + }, + { + "id": "Reserved348", + "name": "Reserved 0x15C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015C", + "is_reserved": true + }, + { + "id": "Reserved349", + "name": "Reserved 0x15D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015D", + "is_reserved": true + }, + { + "id": "Reserved350", + "name": "Reserved 0x15E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015E", + "is_reserved": true + }, + { + "id": "Reserved351", + "name": "Reserved 0x15F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015F", + "is_reserved": true + }, + { + "id": "Reserved352", + "name": "Reserved 0x160", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0160", + "is_reserved": true + }, + { + "id": "Reserved353", + "name": "Reserved 0x161", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0161", + "is_reserved": true + }, + { + "id": "Reserved354", + "name": "Reserved 0x162", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0162", + "is_reserved": true + }, + { + "id": "Reserved355", + "name": "Reserved 0x163", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0163", + "is_reserved": true + }, + { + "id": "Reserved356", + "name": "Reserved 0x164", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0164", + "is_reserved": true + }, + { + "id": "Reserved357", + "name": "Reserved 0x165", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0165", + "is_reserved": true + }, + { + "id": "Reserved358", + "name": "Reserved 0x166", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0166", + "is_reserved": true + }, + { + "id": "Reserved359", + "name": "Reserved 0x167", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0167", + "is_reserved": true + }, + { + "id": "Reserved360", + "name": "Reserved 0x168", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0168", + "is_reserved": true + }, + { + "id": "Reserved361", + "name": "Reserved 0x169", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0169", + "is_reserved": true + }, + { + "id": "Reserved362", + "name": "Reserved 0x16A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016A", + "is_reserved": true + }, + { + "id": "Reserved363", + "name": "Reserved 0x16B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016B", + "is_reserved": true + }, + { + "id": "Reserved364", + "name": "Reserved 0x16C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016C", + "is_reserved": true + }, + { + "id": "Reserved365", + "name": "Reserved 0x16D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016D", + "is_reserved": true + }, + { + "id": "Reserved366", + "name": "Reserved 0x16E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016E", + "is_reserved": true + }, + { + "id": "Reserved367", + "name": "Reserved 0x16F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016F", + "is_reserved": true + }, + { + "id": "Reserved368", + "name": "Reserved 0x170", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0170", + "is_reserved": true + }, + { + "id": "Reserved369", + "name": "Reserved 0x171", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0171", + "is_reserved": true + }, + { + "id": "Reserved370", + "name": "Reserved 0x172", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0172", + "is_reserved": true + }, + { + "id": "Reserved371", + "name": "Reserved 0x173", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0173", + "is_reserved": true + }, + { + "id": "Reserved372", + "name": "Reserved 0x174", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0174", + "is_reserved": true + }, + { + "id": "Reserved373", + "name": "Reserved 0x175", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0175", + "is_reserved": true + }, + { + "id": "Reserved374", + "name": "Reserved 0x176", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0176", + "is_reserved": true + }, + { + "id": "Reserved375", + "name": "Reserved 0x177", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0177", + "is_reserved": true + }, + { + "id": "fuse376", + "name": "GPR2_CFG0", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x0178" + }, + { + "id": "fuse377", + "name": "GPR2_CFG1", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x0179", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse378", + "name": "GPR2_CFG2", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse379", + "name": "GPR2_CFG3", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse380", + "name": "GPR2_CFG4", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse381", + "name": "GPR2_CFG5", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse382", + "name": "GPR2_CFG6", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse383", + "name": "GPR2_CFG7", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017F", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse384", + "name": "GPR3_CFG0", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0180", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse385", + "name": "GPR3_CFG1", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0181", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse386", + "name": "GPR3_CFG2", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0182", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse387", + "name": "GPR3_CFG3", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0183", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse388", + "name": "GPR3_CFG4", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0184", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse389", + "name": "GPR3_CFG5", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0185", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse390", + "name": "GPR3_CFG6", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0186", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse391", + "name": "GPR3_CFG7", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0187", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse392", + "name": "GPR4_CFG0", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x0188" + }, + { + "id": "fuse393", + "name": "GPR4_CFG1", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x0189" + }, + { + "id": "fuse394", + "name": "GPR4_CFG2", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018A" + }, + { + "id": "fuse395", + "name": "GPR4_CFG3", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018B" + }, + { + "id": "fuse396", + "name": "GPR4_CFG4", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse397", + "name": "GPR4_CFG5", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018D", + "reg_width": 16 + }, + { + "id": "fuse398", + "name": "GPR4_CFG6", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018E", + "reg_width": 16 + }, + { + "id": "fuse399", + "name": "GPR4_CFG7", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018F", + "reg_width": 16 + }, + { + "id": "Reserved400", + "name": "Reserved 0x190", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0190", + "is_reserved": true + }, + { + "id": "Reserved401", + "name": "Reserved 0x191", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0191", + "is_reserved": true + }, + { + "id": "Reserved402", + "name": "Reserved 0x192", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0192", + "is_reserved": true + }, + { + "id": "Reserved403", + "name": "Reserved 0x193", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0193", + "is_reserved": true + }, + { + "id": "Reserved404", + "name": "Reserved 0x194", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019C", + "is_reserved": true + }, + { + "id": "Reserved413", + "name": "Reserved 0x19D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019D", + "is_reserved": true + }, + { + "id": "Reserved414", + "name": "Reserved 0x19E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019E", + "is_reserved": true + }, + { + "id": "Reserved415", + "name": "Reserved 0x19F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019F", + "is_reserved": true + }, + { + "id": "Reserved416", + "name": "Reserved 0x1A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A0", + "is_reserved": true + }, + { + "id": "Reserved417", + "name": "Reserved 0x1A1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A1", + "is_reserved": true + }, + { + "id": "Reserved418", + "name": "Reserved 0x1A2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A2", + "is_reserved": true + }, + { + "id": "Reserved419", + "name": "Reserved 0x1A3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A3", + "is_reserved": true + }, + { + "id": "Reserved420", + "name": "Reserved 0x1A4", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A8", + "is_reserved": true + }, + { + "id": "Reserved425", + "name": "Reserved 0x1A9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A9", + "is_reserved": true + }, + { + "id": "Reserved426", + "name": "Reserved 0x1AA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AA", + "is_reserved": true + }, + { + "id": "Reserved427", + "name": "Reserved 0x1AB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AB", + "is_reserved": true + }, + { + "id": "Reserved428", + "name": "Reserved 0x1AC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AC", + "is_reserved": true + }, + { + "id": "Reserved429", + "name": "Reserved 0x1AD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AD", + "is_reserved": true + }, + { + "id": "Reserved430", + "name": "Reserved 0x1AE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AE", + "is_reserved": true + }, + { + "id": "Reserved431", + "name": "Reserved 0x1AF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AF", + "is_reserved": true + }, + { + "id": "Reserved432", + "name": "Reserved 0x1B0", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B8", + "is_reserved": true + }, + { + "id": "Reserved441", + "name": "Reserved 0x1B9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B9", + "is_reserved": true + }, + { + "id": "Reserved442", + "name": "Reserved 0x1BA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BA", + "is_reserved": true + }, + { + "id": "Reserved443", + "name": "Reserved 0x1BB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BB", + "is_reserved": true + }, + { + "id": "Reserved444", + "name": "Reserved 0x1BC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BC", + "is_reserved": true + }, + { + "id": "Reserved445", + "name": "Reserved 0x1BD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BD", + "is_reserved": true + }, + { + "id": "Reserved446", + "name": "Reserved 0x1BE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BE", + "is_reserved": true + }, + { + "id": "Reserved447", + "name": "Reserved 0x1BF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BF", + "is_reserved": true + }, + { + "id": "Reserved448", + "name": "Reserved 0x1C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C0", + "is_reserved": true + }, + { + "id": "Reserved449", + "name": "Reserved 0x1C1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C1", + "is_reserved": true + }, + { + "id": "Reserved450", + "name": "Reserved 0x1C2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C2", + "is_reserved": true + }, + { + "id": "Reserved451", + "name": "Reserved 0x1C3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C3", + "is_reserved": true + }, + { + "id": "Reserved452", + "name": "Reserved 0x1C4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C4", + "is_reserved": true + }, + { + "id": "Reserved453", + "name": "Reserved 0x1C5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C5", + "is_reserved": true + }, + { + "id": "Reserved454", + "name": "Reserved 0x1C6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C6", + "is_reserved": true + }, + { + "id": "Reserved455", + "name": "Reserved 0x1C7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C7", + "is_reserved": true + }, + { + "id": "Reserved456", + "name": "Reserved 0x1C8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C8", + "is_reserved": true + }, + { + "id": "Reserved457", + "name": "Reserved 0x1C9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C9", + "is_reserved": true + }, + { + "id": "Reserved458", + "name": "Reserved 0x1CA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CA", + "is_reserved": true + }, + { + "id": "Reserved459", + "name": "Reserved 0x1CB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CB", + "is_reserved": true + }, + { + "id": "Reserved460", + "name": "Reserved 0x1CC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CC", + "is_reserved": true + }, + { + "id": "Reserved461", + "name": "Reserved 0x1CD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CD", + "is_reserved": true + }, + { + "id": "Reserved462", + "name": "Reserved 0x1CE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CE", + "is_reserved": true + }, + { + "id": "Reserved463", + "name": "Reserved 0x1CF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CF", + "is_reserved": true + }, + { + "id": "Reserved464", + "name": "Reserved 0x1D0", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D4", + "is_reserved": true + }, + { + "id": "Reserved469", + "name": "Reserved 0x1D5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D5", + "is_reserved": true + }, + { + "id": "Reserved470", + "name": "Reserved 0x1D6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D6", + "is_reserved": true + }, + { + "id": "Reserved471", + "name": "Reserved 0x1D7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D7", + "is_reserved": true + }, + { + "id": "Reserved472", + "name": "Reserved 0x1D8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D8", + "is_reserved": true + }, + { + "id": "Reserved473", + "name": "Reserved 0x1D9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D9", + "is_reserved": true + }, + { + "id": "Reserved474", + "name": "Reserved 0x1DA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DA", + "is_reserved": true + }, + { + "id": "Reserved475", + "name": "Reserved 0x1DB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DB", + "is_reserved": true + }, + { + "id": "Reserved476", + "name": "Reserved 0x1DC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DC", + "is_reserved": true + }, + { + "id": "Reserved477", + "name": "Reserved 0x1DD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DD", + "is_reserved": true + }, + { + "id": "Reserved478", + "name": "Reserved 0x1DE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DE", + "is_reserved": true + }, + { + "id": "Reserved479", + "name": "Reserved 0x1DF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DF", + "is_reserved": true + }, + { + "id": "Reserved480", + "name": "Reserved 0x1E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E0", + "is_reserved": true + }, + { + "id": "Reserved481", + "name": "Reserved 0x1E1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E1", + "is_reserved": true + }, + { + "id": "Reserved482", + "name": "Reserved 0x1E2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E2", + "is_reserved": true + }, + { + "id": "Reserved483", + "name": "Reserved 0x1E3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E3", + "is_reserved": true + }, + { + "id": "Reserved484", + "name": "Reserved 0x1E4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E4", + "is_reserved": true + }, + { + "id": "Reserved485", + "name": "Reserved 0x1E5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E5", + "is_reserved": true + }, + { + "id": "Reserved486", + "name": "Reserved 0x1E6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E6", + "is_reserved": true + }, + { + "id": "Reserved487", + "name": "Reserved 0x1E7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E7", + "is_reserved": true + }, + { + "id": "Reserved488", + "name": "Reserved 0x1E8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E8", + "is_reserved": true + }, + { + "id": "Reserved489", + "name": "Reserved 0x1E9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E9", + "is_reserved": true + }, + { + "id": "Reserved490", + "name": "Reserved 0x1EA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EA", + "is_reserved": true + }, + { + "id": "Reserved491", + "name": "Reserved 0x1EB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EB", + "is_reserved": true + }, + { + "id": "fuse492", + "name": "CRC_HI4", + "description": "CRC 5", + "index_int": "0x01EC", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse493", + "name": "CRC_HI5", + "description": "CRC 6", + "index_int": "0x01ED", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse494", + "name": "CRC_HI6", + "description": "CRC 7", + "index_int": "0x01EE", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse495", + "name": "CRC_HI7", + "description": "CRC 8", + "index_int": "0x01EF", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "Reserved496", + "name": "Reserved 0x1F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F0", + "is_reserved": true + }, + { + "id": "Reserved497", + "name": "Reserved 0x1F1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F1", + "is_reserved": true + }, + { + "id": "Reserved498", + "name": "Reserved 0x1F2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F2", + "is_reserved": true + }, + { + "id": "Reserved499", + "name": "Reserved 0x1F3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F3", + "is_reserved": true + }, + { + "id": "Reserved500", + "name": "Reserved 0x1F4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F4", + "is_reserved": true + }, + { + "id": "Reserved501", + "name": "Reserved 0x1F5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F5", + "is_reserved": true + }, + { + "id": "Reserved502", + "name": "Reserved 0x1F6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F6", + "is_reserved": true + }, + { + "id": "Reserved503", + "name": "Reserved 0x1F7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F7", + "is_reserved": true + }, + { + "id": "Reserved504", + "name": "Reserved 0x1F8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F8", + "is_reserved": true + }, + { + "id": "Reserved505", + "name": "Reserved 0x1F9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F9", + "is_reserved": true + }, + { + "id": "Reserved506", + "name": "Reserved 0x1FA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FA", + "is_reserved": true + }, + { + "id": "Reserved507", + "name": "Reserved 0x1FB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FB", + "is_reserved": true + }, + { + "id": "Reserved508", + "name": "Reserved 0x1FC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FC", + "is_reserved": true + }, + { + "id": "Reserved509", + "name": "Reserved 0x1FD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FD", + "is_reserved": true + }, + { + "id": "Reserved510", + "name": "Reserved 0x1FE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FE", + "is_reserved": true + }, + { + "id": "Reserved511", + "name": "Reserved 0x1FF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FF", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/database.yaml new file mode 100644 index 0000000..0bcecc0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/database.yaml @@ -0,0 +1,358 @@ +# Copyright 2023-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: {} +latest: a1 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx93 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93 + memory_map: + ocram_ns: + start_int: 0x20480000 + size_int: 0xA0000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x30480000 + size_int: 0xA0000 + external: false + non_xip_type: int_ram + dram1: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram4: + start_int: 0xB0000000 + size_int: 0x44000 + external: true + non_xip_type: ext_ram_ddr + dram5: + start_int: 0xB0044000 + size_int: 0xBC000 + external: true + non_xip_type: ext_ram_ddr + dram6: + start_int: 0xB0100000 + size_int: 0xFF00000 + external: true + non_xip_type: ext_ram_ddr + dram7: + start_int: 0xC0000000 + size_int: 0x40000000 + external: true + non_xip_type: ext_ram_ddr + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + flexspi2_ns: + start_int: 0x04000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi2_s + evk_default: true + flexspi2_s: + start_int: 0x14000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + isp: + interfaces: [usb] + rom: + protocol: sdps + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + usb: + - vid: 0x1FC9 + pid: 0x014E + +features: + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: otfad1_key + name: OTFAD1_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD1 Key known as KEK. + sub_regs: [fuse184, fuse185, fuse186, fuse187] + - uid: otfad2_key + name: OTFAD2_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD2 Key known as KEK. + sub_regs: [fuse178, fuse179, fuse180, fuse181] + - uid: srkh + name: SRKH + width: 256 + reversed: True + config_as_hexstring: True + description: "SHA256 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + ] + # ======== Communication buffer section ======== + comm_buffer: + address: 0x8380_0000 # comm buffer in DDR + size: 0x20000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== DAT section ======== + dat: + socc: 0x4D58005D # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + dmbox_ap_ix: 0 + test_address: 0x2048_0000 + + # ======== AHAB section ======== + ahab: + valid_offset_minimal_alignment: 0x400 + containers_max_cnt: 3 + oem_images_max_cnt: 8 + container_types: [1] # Supported container types + core_ids: + CORTEX_M33: [1, "cortex-m33", "Cortex M33"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + ELE: [6, "ele", "EdgeLock Enclave"] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + ele: + ELE: [0x06, ele, EdgeLock Enclave Image] + v2x: + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + ddr_alignments: [0x8000, 0x4000, 0x8000, 0] + ddr_fw_alignment: 0x4 + ddr_image_size_alignment: 0x400 + + spl_ddr_load_address: 0x2049A000 + spl_ddr_core_id: cortex-a55 + spl_ddr_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x204E0000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x80200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x96000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + kernel_load_address: 0x80400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 2 + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x83000000 + dtb_entry_point: 0x0 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: ["spl_ddr", "atf", "uboot", "tee", "kernel", "dtb"] + + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 8 + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + + fuses_1: # Fuses for OTFAD1 + _name: Configuration of fuses for OTFAD1 + _no_verify: True + fuse188: # OTFAD CFG Fuse + fuse188-bit-3: 1 # OTFAD Enable + fuse188-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse188-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse189: __key_scramble_mask # OTFAD Scramble Key + otfad1_key: __kek # OTFAD Key + + fuses_2: # Fuses for OTFAD2 + _name: Configuration of fuses for OTFAD2 + _no_verify: True + fuse182: # OTFAD CFG Fuse + fuse182-bit-3: 1 # OTFAD Enable + fuse182-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse182-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse183: __key_scramble_mask # OTFAD Scramble Key + otfad2_key: __kek # OTFAD Key + + additional_template: ["otfad_scramble"] + additional_template_text: | + Is important to use physical addresses (non-secure) in settings of OTFAD to proper run the decryption on device. + For example: + In case of using FlexSPI2 the secure base address address is 0x1400_0000. But in setting of the OTFAD use 0x0400_0000 as a base address. + The code must be still linked on secure base address 0x1400_0000 to proper run of OTFAD hardware. + + Same is for FlexSPI1, but instead of 0x3800_0000 base address, the 0x2800_0000 must be used in OTFAD configuration. + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc_boot: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + # flexspi_nand: + # segments: + # xmcd: 0x00 + # primary_image_container_set: 0x400 + # secondary_image_container_set: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI1/2/3/4. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # Template definitions for bootable image generation + templates: + imx_boot_flash_singleboot: + description: "Complete imx-bootloader image" + mem_type: serial_downloader + configs: + - name: spl + type: spl + containers: + - name: nxp_containers + path: "mx93a1-ahab-container.img" + - name: spl_container + images: [spl_ddr] + - name: uboot + type: uboot + containers: + - name: uboot_container + images: [atf, uboot, tee] + boards: + imx93-11x11-lpddr4x-evk: + lpddr_imem_1d: lpddr4_imem_1d_v202201.bin + lpddr_dmem_1d: lpddr4_dmem_1d_v202201.bin + lpddr_imem_2d: lpddr4_imem_2d_v202201.bin + lpddr_dmem_2d: lpddr4_dmem_2d_v202201.bin + spl_ddr: u-boot-spl.bin-imx93-11x11-lpddr4x-evk-sd + atf: bl31-imx93.bin + uboot: u-boot-imx93-11x11-lpddr4x-evk.bin-sd + tee: tee.bin + imx93-9x9-lpddr4-qsb: + lpddr_imem_1d: lpddr4_imem_1d_v202201.bin + lpddr_dmem_1d: lpddr4_dmem_1d_v202201.bin + lpddr_imem_2d: lpddr4_imem_2d_v202201.bin + lpddr_dmem_2d: lpddr4_dmem_2d_v202201.bin + spl_ddr: u-boot-spl.bin-imx93-9x9-lpddr4-qsb-sd + atf: bl31-imx93.bin + uboot: u-boot-imx93-9x9-lpddr4-qsb.bin-sd + tee: tee.bin + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x8280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_interface: uboot_fastboot + el2go_name: IMX9 + prov_method: oem_app + validation_method: max_count=16;max_total_size=16384 + uuid_fuse_index: "6 0 4" + + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fcb_flexspi_nor.json new file mode 100644 index 0000000..99dcd17 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fcb_flexspi_nor.json @@ -0,0 +1,1621 @@ +{ + "cpu": "MIMX9352", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010000", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "bugfix", + "access": "RW", + "description": "[07:00] Bugfix - 0" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "minor", + "access": "RW", + "description": "[15:08] Minor" + }, + { + "id": "field004-bits16-23", + "width": 8, + "name": "major", + "access": "RW", + "description": "[23:16] Major - 1" + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type: 0 - Generic, 1 - Quad Enable, 2 - SPI-to-xSPI, 3 - xSPI-to-SPI", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration. effective only when deviceModeCfgEnable = 1", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "Reserved01D", + "offset_int": "0x1d", + "reg_width": 24, + "name": "reserved1", + "description": " [0x01d-0x019] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved3", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 64, + "name": "reserved4", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 8, + "name": "csPadSettingOverrideEn", + "description": " [0x060-0x060] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field061", + "offset_int": "0x61", + "reg_width": 8, + "name": "csPadSettingOverride", + "description": " [0x061-0x061] Overriding pad setting of CS", + "default_value_int": "0x0" + }, + { + "id": "Reserved062", + "offset_int": "0x62", + "reg_width": 16, + "name": "reserved5", + "description": " [0x062-0x063] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 8, + "name": "sclkPadSettingOverrideEn", + "description": " [0x064-0x064] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field065", + "offset_int": "0x65", + "reg_width": 8, + "name": "sclkPadSettingOverride", + "description": " [0x065-0x065] Overriding pad setting of SCLK", + "default_value_int": "0x0" + }, + { + "id": "Reserved066", + "offset_int": "0x66", + "reg_width": 16, + "name": "reserved6", + "description": " [0x066-0x067] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 8, + "name": "dataPadSettingOverrideEn", + "description": " [0x068-0x068] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field069", + "offset_int": "0x69", + "reg_width": 8, + "name": "dataPadSettingOverride", + "description": " [0x069-0x069] Overriding pad setting of data signals", + "default_value_int": "0x0" + }, + { + "id": "Reserved06A", + "offset_int": "0x6a", + "reg_width": 16, + "name": "reserved7", + "description": " [0x06a-0x06b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 8, + "name": "dqsPadSettingOverrideEn", + "description": " [0x06c-0x06c] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field06D", + "offset_int": "0x6d", + "reg_width": 8, + "name": "dqsPadSettingOverride", + "description": " [0x06d-0x06d] Overriding pad setting of DQS", + "default_value_int": "0x0" + }, + { + "id": "Reserved06E", + "offset_int": "0x6e", + "reg_width": 16, + "name": "reserved8", + "description": " [0x06e-0x06f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "dataValidTime", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-15", + "width": 16, + "name": "dllAValidTime", + "access": "RW", + "description": " Data valid time for DLLA in terms of 0.1 ns" + }, + { + "id": "field078-bits16-31", + "width": 16, + "name": "dllBValidTime", + "access": "RW", + "description": " Data valid time for DLLB in terms of 0.1 ns" + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "lookupTable_0", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "lookupTable_1", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "lookupTable_2", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "lookupTable_3", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "lookupTable_4", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "lookupTable_5", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "lookupTable_6", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "lookupTable_7", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "lookupTable_8", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "lookupTable_9", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "lookupTable_10", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "lookupTable_11", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "lookupTable_12", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "lookupTable_13", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "lookupTable_14", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "lookupTable_15", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "lookupTable_16", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "lookupTable_17", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "lookupTable_18", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "lookupTable_19", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "lookupTable_20", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "lookupTable_21", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "lookupTable_22", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "lookupTable_23", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "lookupTable_24", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "lookupTable_25", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "lookupTable_26", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "lookupTable_27", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "lookupTable_28", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "lookupTable_29", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "lookupTable_30", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "lookupTable_31", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "lookupTable_32", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "lookupTable_33", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "lookupTable_34", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "lookupTable_35", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "lookupTable_36", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "lookupTable_37", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "lookupTable_38", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "lookupTable_39", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "lookupTable_40", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "lookupTable_41", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "lookupTable_42", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "lookupTable_43", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "lookupTable_44", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "lookupTable_45", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "lookupTable_46", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "lookupTable_47", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "lookupTable_48", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "lookupTable_49", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "lookupTable_50", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "lookupTable_51", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "lookupTable_52", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "lookupTable_53", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "lookupTable_54", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "lookupTable_55", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "lookupTable_56", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "lookupTable_57", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "lookupTable_58", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "lookupTable_59", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "lookupTable_60", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "lookupTable_61", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "lookupTable_62", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "lookupTable_63", + "description": " [0x080-0x17f] Lookup table holds Flash command sequences", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved9_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved9_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved9_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved9_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " The data order is swapped in OPI DDR mode", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved10_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "reserved10_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "reserved10_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "reserved10_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "reserved10_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context after being configured", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D4-bits0-7", + "width": 8, + "name": "flashPorMode", + "access": "RW", + "description": " Flash POR Mode" + }, + { + "id": "field1D4-bits8-15", + "width": 8, + "name": "flashCurrentMode", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "width": 8 + }, + { + "id": "field1D4-bits24-31", + "width": 8, + "name": "flashRestoringSequence", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + } + ] + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserved11_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserved11_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserved11_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserved11_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserved11_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserved11_5", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserved11_6", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserved11_7", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserved11_8", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserved11_9", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fuses.json new file mode 100644 index 0000000..054e34a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9352/fuses.json @@ -0,0 +1,9828 @@ +{ + "cpu": "mimx9352", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG_LOCK", + "description": "Boot Configuration Fuse Lock for Boot_CFG 0-3 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect, the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect, the controlled field can be sensed only, can not be burned and can't be read from shadow registers", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect, the controlled field can be sensed only, can't be read from shadow registers and can not be over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-3-5", + "name": "HSW_CFG_LOCK", + "description": "Hardware and Software Configuration Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "Write Protect, the controlled field can not be burned" + }, + { + "name": "OP", + "value": 2, + "description": "Over-ride Protect, the controlled field shadow registers can not be over-written" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Over-ride + Write Protect, the controlled field can not be overridden nor burned" + }, + { + "name": "RP", + "value": 4, + "description": "Read Protect, the controlled field can be sensed only, but can't be read from shadow registers" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned" + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register" + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID0 Lock - Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect, the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect, the controlled field can be sensed only, can't be read from shadow registers and can not be burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect, the controlled field can be sensed only, can't be read from shadow registers and can not be over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks - Read, Write and Over-ride Protect, the controlled field can be sensed only, can't be read, burned or over-written", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse2-bits-0-2", + "name": "OEM_SW_CFG_LOCK", + "description": "OEM SW Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-3-5", + "name": "ELE_OTFAD1_KEY_LOCK", + "description": "OTFAD Key Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse2-bit-15", + "name": "BOOT2_CFG_LOCK_0", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be burned)" + }, + { + "name": "WP", + "value": 1, + "description": "Write Protect, the controlled field can not be burned" + } + ] + } + ] + }, + { + "id": "fuse3", + "name": "LOCK_CFG3", + "description": "LOCK_CFG3", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse3-bit-15", + "name": "BOOT2_CFG_LOCK_1", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (Fuse can be over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "OP", + "value": 1, + "description": "Over-ride Protect, the controlled field shadow registers can not be over-written" + } + ] + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-6-8", + "name": "ELE_MISC1_LOCK", + "description": "ELE-AP Misc. NXP Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read nor burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read nor over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-12-14", + "name": "ELE_OEM_SRKH_LOCK", + "description": "ELE-AP OEM SRK Hash Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1, + "id": "fuse4-bit-15", + "name": "BOOT2_CFG_LOCK_2", + "description": "Boot Configuration Fuse Lock for Boot_CFG 8-11 fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read sensed)" + }, + { + "name": "READ_PROTECT", + "value": 1, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + } + ] + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0005", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved6", + "name": "Reserved 0x6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0006", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved7", + "name": "Reserved 0x7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0007", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved8", + "name": "Reserved 0x8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0008", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG9", + "description": "LOCK_CFG9", + "index_int": "0x0009", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse9-bits-3-5", + "name": "GPR2_LOCK", + "description": "GPR2_CFG lock bits ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-6-8", + "name": "GPR3_LOCK", + "description": "GPR3_CFG lock bits ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-9-11", + "name": "GPR4_LOCK", + "description": "GPR4_CFG lock bits ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0xA-0xB", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved10", + "name": "Reserved 0xA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000A", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0xB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "ECID", + "description": "Device Unique ID" + }, + "registers": [ + { + "id": "fuse12", + "name": "ECID3", + "description": "Device Unique ID", + "index_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse13", + "name": "ECID2", + "description": "Device Unique ID", + "index_int": "0x000D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse14", + "name": "ECID1", + "description": "Device Unique ID", + "index_int": "0x000E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse15", + "name": "ECID0", + "description": "Device Unique ID", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + } + ] + }, + { + "group": { + "name": "Reserved 0x10-0x12", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0010", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 11 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x11", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0011", + "is_reserved": true, + "reg_width": 16 + }, + { + "id": "Reserved18", + "name": "Reserved 0x12", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 15 + }, + { + "width": 1 + }, + { + "width": 15 + } + ] + } + ] + }, + { + "group": { + "name": "HW_CFG", + "description": "Hardware configuration" + }, + "registers": [ + { + "id": "fuse19", + "name": "HW_CFG1", + "description": "HW_CFG1", + "index_int": "0x0013", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse19-bits-0-3", + "name": "SI_REV", + "description": "Silicon Revision number. Lower 2 bits represent the minor number and upper 2 bits represent the TO letter. So, A0 would be represented with 0000, A1 with 0001 and B1 with 0101. " + }, + { + "width": 2, + "id": "fuse19-bits-4-5", + "name": "MARKET_SEGMENT", + "description": "Indicate Auto/Industrial/Commercial Market", + "values": [ + { + "name": "CONSUMER", + "value": 0, + "description": "Consumer 0C to 95C (P/N Char 5D, 8D)", + "deprecated_names": [ + "00" + ] + }, + { + "name": "EXT_CONSUMER", + "value": 1, + "description": "Ext. Consumer -20C to 105C (P/N Char 5E, 8E)", + "deprecated_names": [ + "01" + ] + }, + { + "name": "INDUSTRIAL", + "value": 2, + "description": "Industrial -40C to 105C (P/N Char 7C)" + }, + { + "name": "AUTOMOTIVE", + "value": 3, + "description": "Automotive -40C to 125C (P/N Char 4A,6A, 1A)" + } + ] + }, + { + "width": 6, + "id": "fuse19-bits-6-11", + "name": "SPEED_GRADING", + "description": "Burned by tester program, for indicating IC core speed. (Hot burn may not be used).", + "values": [ + { + "name": "SPEED_2300MHZ", + "value": 0, + "description": "2300 MHz, P/N Code 23" + }, + { + "name": "SPEED_2200MHZ", + "value": 1, + "description": "2200 MHz, P/N Code 22" + }, + { + "name": "SPEED_2100MHZ", + "value": 2, + "description": "2100 MHz, P/N Code 21" + }, + { + "name": "SPEED_2000MHZ", + "value": 3, + "description": "2000 MHz, P/N Code 20" + }, + { + "name": "SPEED_1900MHZ", + "value": 4, + "description": "1900 MHz, P/N Code 19" + }, + { + "name": "SPEED_1800MHZ", + "value": 5, + "description": "1800 MHz, P/N Code 18" + }, + { + "name": "SPEED_1700MHZ", + "value": 6, + "description": "1700 MHz, P/N Code 17" + }, + { + "name": "SPEED_1600MHZ", + "value": 7, + "description": "1600 MHz, P/N Code 16" + }, + { + "name": "SPEED_1500MHZ", + "value": 8, + "description": "1500 MHz, P/N Code 15" + }, + { + "name": "SPEED_1400MHZ", + "value": 9, + "description": "1400 MHz, P/N Code 14" + }, + { + "name": "SPEED_1300MHZ", + "value": 10, + "description": "1300 MHz, P/N Code 13" + }, + { + "name": "SPEED_1200MHZ", + "value": 11, + "description": "1200 MHz, P/N Code 12" + }, + { + "name": "SPEED_1100MHZ", + "value": 12, + "description": "1100 MHz, P/N Code 11" + }, + { + "name": "SPEED_1000MHZ", + "value": 13, + "description": "1000 MHz, P/N Code 10" + }, + { + "name": "SPEED_900MHZ", + "value": 14, + "description": "900 MHz, P/N Code 09" + }, + { + "name": "SPEED_800MHZ", + "value": 15, + "description": "800 MHz, P/N Code 08" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x14-0x17", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved20", + "name": "Reserved 0x14", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x15", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 23 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x16", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0016", + "is_reserved": true + }, + { + "id": "Reserved23", + "name": "Reserved 0x17", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 25 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "BOOT_CFG0", + "index_int": "0x0018", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse24-bits-0-3", + "name": "Boot_Mode_Fuses", + "description": "Boot Mode Fuses\nBootRom will retrieve boot mode from these fuses instead of Boot_Mode pins if\n(BT_FUSE_SEL=1 && Boot_Mode=Internal Fuses)\nOr\n(Force FORCE_BT_FROM_FUSE=1)\n", + "values": [ + { + "name": "A55_INTERNAL_FUSES", + "value": 0, + "description": "Cortex-A55 boot from internal fuses" + }, + { + "name": "A55_SERIAL_DOWNLOADER", + "value": 1, + "description": "Cortex-A55 boot via Serial Downloader USB 1" + }, + { + "name": "A55_USDHC1_EMMC", + "value": 2, + "description": "Cortex-A55 boot from USDHC1 8-bit eMMC 5.1" + }, + { + "name": "A55_USDHC2_SD", + "value": 3, + "description": "Cortex-A55 boot from USDHC2 4-bit SD3.0" + }, + { + "name": "A55_FLEXSPI_NOR", + "value": 4, + "description": "Cortex-A55 boot from FlexSPI Serial NOR" + }, + { + "name": "A55_FLEXSPI_NAND", + "value": 5, + "description": "Cortex-A55 boot from FlexSPI Serial NAND 2K page" + }, + { + "name": "M33_INTERNAL_FUSES", + "value": 8, + "description": "Cortex-M33 boot from internal fuses" + }, + { + "name": "M33_SERIAL_DOWNLOADER", + "value": 9, + "description": "Cortex-M33 boot via Serial Downloader USB 1" + }, + { + "name": "M33_USDHC1_EMMC", + "value": 10, + "description": "Cortex-M33 boot from USDHC1 8-bit eMMC 5.1" + }, + { + "name": "M33_USDHC2_SD", + "value": 11, + "description": "Cortex-M33 boot from USDHC2 4-bit SD3.0" + }, + { + "name": "M33_FLEXSPI_NOR", + "value": 12, + "description": "Cortex-M33 boot from FlexSPI Serial NOR" + }, + { + "name": "M33_FLEXSPI_NAND", + "value": 13, + "description": "Cortex-M33 boot from FlexSPI Serial NAND 2K page" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-4", + "name": "Override_FlexSPI_NOR_Boot_Selection", + "description": "Override FlexSPI NOR Boot Selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Do not override" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-5-6", + "name": "FlexSPI_NOR_Boot_Override_Selection", + "description": "FlexSPI NOR Boot Override Selection", + "values": [ + { + "name": "FLEXSPI_HYPERFLASH", + "value": 0, + "description": "Flex SPI (Hyperflash 1.8V)" + }, + { + "name": "FLEXSPI_4B_READ", + "value": 1, + "description": "Flex SPI (Flash with 4B READ(0x13)default supported)" + }, + { + "name": "OCTAL_MICRON", + "value": 2, + "description": "Default Octal mode (Micron, Nice to have)" + }, + { + "name": "OCTAL_MXIC", + "value": 3, + "description": "Default Octal mode (Mxic, Nice to have)" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-7", + "name": "FlexSPI_NAND_4K_Page_Selection", + "description": "FlexSPI NAND 4K Page Selection", + "values": [ + { + "name": "DEFAULT_2K_PAGE", + "value": 0, + "description": "Not override the default selection (2K page)" + }, + { + "name": "OVERRIDE_4K_PAGE", + "value": 1, + "description": "Override, 4K page is selected" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-8", + "name": "uSDHC_Device_Type", + "description": "uSDHC Device Type", + "values": [ + { + "name": "EMMC", + "value": 0, + "description": "uSDHC_Device_Type: eMMC" + }, + { + "name": "SD", + "value": 1, + "description": "uSDHC_Device_Type: SD" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-9", + "name": "FLEXSPI_NOR_DATA_IOMUX_SION_EN", + "description": "FLEXSPI NOR DATA IOMUX SION EN", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "SION is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "SION is enabled" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-10-11", + "name": "FLEXSPI_NOR_FCB_OFFSET", + "description": "FLEXSPI NOR FCB OFFSET", + "values": [ + { + "name": "OFFSET_400B", + "value": 0, + "description": "Select the offset of FlexSPI NOR FCB at 0x400B" + }, + { + "name": "OFFSET_600B", + "value": 1, + "description": "Select the offset of FlexSPI NOR FCB at 0x600B" + }, + { + "name": "OFFSET_800B", + "value": 2, + "description": "Select the offset of FlexSPI NOR FCB at 0x800B" + }, + { + "name": "OFFSET_A00B", + "value": 3, + "description": "Select the offset of FlexSPI NOR FCB at 0xA00B" + } + ] + }, + { + "width": 3, + "id": "fuse24-bits-12-14", + "name": "FLEXSPI_AUTOPROBE_FEQ_SEL", + "description": "FLEXSPI AUTOPROBE FEQ SEL", + "values": [ + { + "name": "FREQ_24MHZ", + "value": 0, + "description": "24MHz" + }, + { + "name": "FREQ_133MHZ", + "value": 1, + "description": "133 MHz" + }, + { + "name": "FREQ_166MHZ", + "value": 2, + "description": "166 MHz" + }, + { + "name": "FREQ_200MHZ", + "value": 3, + "description": "200 MHz" + }, + { + "name": "FREQ_80MHZ", + "value": 4, + "description": "80MHz" + }, + { + "name": "FREQ_100MHZ", + "value": 5, + "description": "100MHz" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-15", + "name": "FLEXSPI_FCB_COPY_FLAG", + "description": "FLEXSPI FCB COPY FLAG", + "values": [ + { + "name": "PORT_2", + "value": 0, + "description": "Port 2 (single boot mode)" + }, + { + "name": "PORT_3", + "value": 1, + "description": "Port 3 (single boot mode)" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-16", + "name": "SD_Loopback_Clock_Source_Sel", + "description": "SD Loopback clock Source Sel", + "deprecated_names": [ + "SD_Loopback_Clock_Source_Sel " + ], + "values": [ + { + "name": "THROUGH_SD_PAD", + "value": 0, + "description": "Through SD pad" + }, + { + "name": "DIRECT", + "value": 1, + "description": "Direct" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-17-18", + "name": "SD_Speed_Selection", + "description": "SD Speed Selection", + "values": [ + { + "name": "NORMAL_SDR12", + "value": 0, + "description": "Normal/SDR12" + }, + { + "name": "HIGH_SDR25", + "value": 1, + "description": "High/SDR25" + }, + { + "name": "SDR50", + "value": 2, + "description": "SDR50" + }, + { + "name": "SDR104", + "value": 3, + "description": "SDR104" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-19", + "name": "eMMC_Speed_Selection", + "description": "eMMC Speed Selection", + "values": [ + { + "name": "NORMAL_SPEED", + "value": 0, + "description": "Normal Speed" + }, + { + "name": "HIGH_SPEED", + "value": 1, + "description": "High Speed" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-20", + "name": "eMMC_fast_boot", + "description": "eMMC fast boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-21", + "name": "RSVD_BOOT_CFG0_21", + "description": "BOOT_CFG0" + }, + { + "width": 1, + "id": "fuse24-bit-22", + "name": "eMMC_voltage_selection", + "description": "eMMC Voltage selection", + "values": [ + { + "name": "VOLTAGE_3V3", + "value": 0, + "description": "eMMC_voltage_selection: 3.3v" + }, + { + "name": "VOLTAGE_1V8", + "value": 1, + "description": "eMMC_voltage_selection: 1.8v" + } + ] + }, + { + "width": 5, + "id": "fuse24-bits-23-27", + "name": "FlexSPI NOR Reset Pin selections", + "description": "FlexDPI NOR Reset Pin selections", + "values": [ + { + "name": "GPIO_PIN_0", + "value": 0, + "description": "GPIO[x].0" + }, + { + "name": "GPIO_PIN_1", + "value": 1, + "description": "GPIO[x].1" + }, + { + "name": "GPIO_PIN_2", + "value": 2, + "description": "GPIO[x].2" + }, + { + "name": "GPIO_PIN_3", + "value": 3, + "description": "GPIO[x].3" + }, + { + "name": "GPIO_PIN_4", + "value": 4, + "description": "GPIO[x].4" + }, + { + "name": "GPIO_PIN_5", + "value": 5, + "description": "GPIO[x].5" + }, + { + "name": "GPIO_PIN_6", + "value": 6, + "description": "GPIO[x].6" + }, + { + "name": "GPIO_PIN_7", + "value": 7, + "description": "GPIO[x].7" + }, + { + "name": "GPIO_PIN_8", + "value": 8, + "description": "GPIO[x].8" + }, + { + "name": "GPIO_PIN_9", + "value": 9, + "description": "GPIO[x].9" + }, + { + "name": "GPIO_PIN_10", + "value": 10, + "description": "GPIO[x].10" + }, + { + "name": "GPIO_PIN_11", + "value": 11, + "description": "GPIO[x].11" + }, + { + "name": "GPIO_PIN_12", + "value": 12, + "description": "GPIO[x].12" + }, + { + "name": "GPIO_PIN_13", + "value": 13, + "description": "GPIO[x].13" + }, + { + "name": "GPIO_PIN_14", + "value": 14, + "description": "GPIO[x].14" + }, + { + "name": "GPIO_PIN_15", + "value": 15, + "description": "GPIO[x].15" + }, + { + "name": "GPIO_PIN_16", + "value": 16, + "description": "GPIO[x].16" + }, + { + "name": "GPIO_PIN_17", + "value": 17, + "description": "GPIO[x].17" + }, + { + "name": "GPIO_PIN_18", + "value": 18, + "description": "GPIO[x].18" + }, + { + "name": "GPIO_PIN_19", + "value": 19, + "description": "GPIO[x].19" + }, + { + "name": "GPIO_PIN_20", + "value": 20, + "description": "GPIO[x].20" + }, + { + "name": "GPIO_PIN_21", + "value": 21, + "description": "GPIO[x].21" + }, + { + "name": "GPIO_PIN_22", + "value": 22, + "description": "GPIO[x].22" + }, + { + "name": "GPIO_PIN_23", + "value": 23, + "description": "GPIO[x].23" + }, + { + "name": "GPIO_PIN_24", + "value": 24, + "description": "GPIO[x].24" + }, + { + "name": "GPIO_PIN_25", + "value": 25, + "description": "GPIO[x].25" + }, + { + "name": "GPIO_PIN_26", + "value": 26, + "description": "GPIO[x].26" + }, + { + "name": "GPIO_PIN_27", + "value": 27, + "description": "GPIO[x].27" + }, + { + "name": "GPIO_PIN_28", + "value": 28, + "description": "GPIO[x].28" + }, + { + "name": "GPIO_PIN_29", + "value": 29, + "description": "GPIO[x].29" + }, + { + "name": "GPIO_PIN_30", + "value": 30, + "description": "GPIO[x].30" + }, + { + "name": "GPIO_PIN_31", + "value": 31, + "description": "GPIO[x].31" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-28", + "name": "BT_FREQ_SEL", + "description": "BT FREQ SEL", + "values": [ + { + "name": "NORMAL_FREQ", + "value": 0, + "description": "Normal clock frequency" + }, + { + "name": "LOW_FREQ", + "value": 1, + "description": "Low clock frequency" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-29", + "name": "BT_FUSE_SEL", + "description": "BT FUSE SEL", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot fuses not programmed" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot fuses programmed yet" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-30", + "name": "Force_Boot_from_Fuse", + "description": "Force Boot from Fuse", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override Boot_Mode pins by boot mode fuses" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-31", + "name": "Force_Serial_Download", + "description": "Force Serial Download", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Normal boot mode selection applies" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override all other Boot_Mode & Boot Mode Fuses and enter Serial Download" + } + ] + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "BOOT_CFG1", + "index_int": "0x0019", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse25-bit-0", + "name": "Fast_Boot_Acknowledge_Disable", + "description": "Fast Boot Acknowledge Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot Ack Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot Ack Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse25-bit-2", + "name": "uSDHC_Power_On_Polarity", + "description": "uSHDC Power On Polarity", + "values": [ + { + "name": "LOW", + "value": 0, + "description": "uSDHC_Power_On_Polarity: Low" + }, + { + "name": "HIGH", + "value": 1, + "description": "uSDHC_Power_On_Polarity: High" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-3", + "name": "uSDHC_Power_Cycle_Delay", + "description": "uSDHC Power Cycle Delay", + "values": [ + { + "name": "DELAY_5MS", + "value": 0, + "description": "uSDHC_Power_Cycle_Delay: 5 ms" + }, + { + "name": "DELAY_2_5MS", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-4-5", + "name": "uSDHC_Power_Cycle_Interval", + "description": "uSDHC Power Cycle Interval", + "values": [ + { + "name": "INTERVAL_20MS", + "value": 0, + "description": "20 ms" + }, + { + "name": "INTERVAL_10MS", + "value": 1, + "description": "10 ms" + }, + { + "name": "INTERVAL_5MS", + "value": 2, + "description": "uSDHC_Power_Cycle_Interval: 5 ms" + }, + { + "name": "INTERVAL_2_5MS", + "value": 3, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-6-7", + "name": "SD_Calibration_Step", + "description": "SD Calibration Step", + "values": [ + { + "name": "DELAY_CELL_1", + "value": 0, + "description": "1 delay cell" + }, + { + "name": "DELAY_CELL_2", + "value": 1, + "description": "2 delay cell" + }, + { + "name": "DELAY_CELL_3", + "value": 2, + "description": "3 delay cell" + }, + { + "name": "DELAY_CELL_5", + "value": 3, + "description": "5 delay cell" + } + ] + }, + { + "width": 8, + "id": "fuse25-bits-8-15", + "name": "uSDHC_PAD_Settings_Low_bits", + "description": "uSDHC Pad Settings Low bits" + }, + { + "width": 4, + "id": "fuse25-bits-16-19", + "name": "uSDHC_PAD_Setting_High_bits", + "description": "uSDHC Pad Settings High bits", + "values": [ + { + "name": "SETTING_0", + "value": 0, + "description": "Override value 0 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_1", + "value": 1, + "description": "Override value 1 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_2", + "value": 2, + "description": "Override value 2 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_3", + "value": 3, + "description": "Override value 3 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_4", + "value": 4, + "description": "Override value 4 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_5", + "value": 5, + "description": "Override value 5 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_6", + "value": 6, + "description": "Override value 6 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_7", + "value": 7, + "description": "Override value 7 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_8", + "value": 8, + "description": "Override value 8 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_9", + "value": 9, + "description": "Override value 9 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_10", + "value": 10, + "description": "Override value 10 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_11", + "value": 11, + "description": "Override value 11 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_12", + "value": 12, + "description": "Override value 12 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_13", + "value": 13, + "description": "Override value 13 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_14", + "value": 14, + "description": "Override value 14 for uSDHC pad settings (High bits)" + }, + { + "name": "SETTING_15", + "value": 15, + "description": "Override value 15 for uSDHC pad settings (High bits)" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-20", + "name": "Power_Cycle_Enable", + "description": "Power Cycle Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "No power cycle" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-21", + "name": "uSDHC_Override_Pad_Settings", + "description": "uSDHC Override Pad Settings\n(using PAD_SETTINGS value)" + }, + { + "width": 1, + "id": "fuse25-bit-22", + "name": "uSDHC_DLL_Enable", + "description": "uSDHC DLL EnableEnable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse25-bits-24-30", + "name": "MMC_DLL_DLY", + "description": "MMC DLL DLY", + "values": [ + { + "name": "DLY_TICKS_0", + "value": 0, + "description": "Delay target for uSDHC DLL - 0 delay ticks" + }, + { + "name": "DLY_TICKS_1", + "value": 1, + "description": "Delay target for uSDHC DLL - 1 delay tick" + }, + { + "name": "DLY_TICKS_2", + "value": 2, + "description": "Delay target for uSDHC DLL - 2 delay ticks" + }, + { + "name": "DLY_TICKS_3", + "value": 3, + "description": "Delay target for uSDHC DLL - 3 delay ticks" + }, + { + "name": "DLY_TICKS_4", + "value": 4, + "description": "Delay target for uSDHC DLL - 4 delay ticks" + }, + { + "name": "DLY_TICKS_5", + "value": 5, + "description": "Delay target for uSDHC DLL - 5 delay ticks" + }, + { + "name": "DLY_TICKS_6", + "value": 6, + "description": "Delay target for uSDHC DLL - 6 delay ticks" + }, + { + "name": "DLY_TICKS_7", + "value": 7, + "description": "Delay target for uSDHC DLL - 7 delay ticks" + }, + { + "name": "DLY_TICKS_8", + "value": 8, + "description": "Delay target for uSDHC DLL - 8 delay ticks" + }, + { + "name": "DLY_TICKS_9", + "value": 9, + "description": "Delay target for uSDHC DLL - 9 delay ticks" + }, + { + "name": "DLY_TICKS_10", + "value": 10, + "description": "Delay target for uSDHC DLL - 10 delay ticks" + }, + { + "name": "DLY_TICKS_11", + "value": 11, + "description": "Delay target for uSDHC DLL - 11 delay ticks" + }, + { + "name": "DLY_TICKS_12", + "value": 12, + "description": "Delay target for uSDHC DLL - 12 delay ticks" + }, + { + "name": "DLY_TICKS_13", + "value": 13, + "description": "Delay target for uSDHC DLL - 13 delay ticks" + }, + { + "name": "DLY_TICKS_14", + "value": 14, + "description": "Delay target for uSDHC DLL - 14 delay ticks" + }, + { + "name": "DLY_TICKS_15", + "value": 15, + "description": "Delay target for uSDHC DLL - 15 delay ticks" + }, + { + "name": "DLY_TICKS_16", + "value": 16, + "description": "Delay target for uSDHC DLL - 16 delay ticks" + }, + { + "name": "DLY_TICKS_17", + "value": 17, + "description": "Delay target for uSDHC DLL - 17 delay ticks" + }, + { + "name": "DLY_TICKS_18", + "value": 18, + "description": "Delay target for uSDHC DLL - 18 delay ticks" + }, + { + "name": "DLY_TICKS_19", + "value": 19, + "description": "Delay target for uSDHC DLL - 19 delay ticks" + }, + { + "name": "DLY_TICKS_20", + "value": 20, + "description": "Delay target for uSDHC DLL - 20 delay ticks" + }, + { + "name": "DLY_TICKS_21", + "value": 21, + "description": "Delay target for uSDHC DLL - 21 delay ticks" + }, + { + "name": "DLY_TICKS_22", + "value": 22, + "description": "Delay target for uSDHC DLL - 22 delay ticks" + }, + { + "name": "DLY_TICKS_23", + "value": 23, + "description": "Delay target for uSDHC DLL - 23 delay ticks" + }, + { + "name": "DLY_TICKS_24", + "value": 24, + "description": "Delay target for uSDHC DLL - 24 delay ticks" + }, + { + "name": "DLY_TICKS_25", + "value": 25, + "description": "Delay target for uSDHC DLL - 25 delay ticks" + }, + { + "name": "DLY_TICKS_26", + "value": 26, + "description": "Delay target for uSDHC DLL - 26 delay ticks" + }, + { + "name": "DLY_TICKS_27", + "value": 27, + "description": "Delay target for uSDHC DLL - 27 delay ticks" + }, + { + "name": "DLY_TICKS_28", + "value": 28, + "description": "Delay target for uSDHC DLL - 28 delay ticks" + }, + { + "name": "DLY_TICKS_29", + "value": 29, + "description": "Delay target for uSDHC DLL - 29 delay ticks" + }, + { + "name": "DLY_TICKS_30", + "value": 30, + "description": "Delay target for uSDHC DLL - 30 delay ticks" + }, + { + "name": "DLY_TICKS_31", + "value": 31, + "description": "Delay target for uSDHC DLL - 31 delay ticks" + }, + { + "name": "DLY_TICKS_32", + "value": 32, + "description": "Delay target for uSDHC DLL - 32 delay ticks" + }, + { + "name": "DLY_TICKS_33", + "value": 33, + "description": "Delay target for uSDHC DLL - 33 delay ticks" + }, + { + "name": "DLY_TICKS_34", + "value": 34, + "description": "Delay target for uSDHC DLL - 34 delay ticks" + }, + { + "name": "DLY_TICKS_35", + "value": 35, + "description": "Delay target for uSDHC DLL - 35 delay ticks" + }, + { + "name": "DLY_TICKS_36", + "value": 36, + "description": "Delay target for uSDHC DLL - 36 delay ticks" + }, + { + "name": "DLY_TICKS_37", + "value": 37, + "description": "Delay target for uSDHC DLL - 37 delay ticks" + }, + { + "name": "DLY_TICKS_38", + "value": 38, + "description": "Delay target for uSDHC DLL - 38 delay ticks" + }, + { + "name": "DLY_TICKS_39", + "value": 39, + "description": "Delay target for uSDHC DLL - 39 delay ticks" + }, + { + "name": "DLY_TICKS_40", + "value": 40, + "description": "Delay target for uSDHC DLL - 40 delay ticks" + }, + { + "name": "DLY_TICKS_41", + "value": 41, + "description": "Delay target for uSDHC DLL - 41 delay ticks" + }, + { + "name": "DLY_TICKS_42", + "value": 42, + "description": "Delay target for uSDHC DLL - 42 delay ticks" + }, + { + "name": "DLY_TICKS_43", + "value": 43, + "description": "Delay target for uSDHC DLL - 43 delay ticks" + }, + { + "name": "DLY_TICKS_44", + "value": 44, + "description": "Delay target for uSDHC DLL - 44 delay ticks" + }, + { + "name": "DLY_TICKS_45", + "value": 45, + "description": "Delay target for uSDHC DLL - 45 delay ticks" + }, + { + "name": "DLY_TICKS_46", + "value": 46, + "description": "Delay target for uSDHC DLL - 46 delay ticks" + }, + { + "name": "DLY_TICKS_47", + "value": 47, + "description": "Delay target for uSDHC DLL - 47 delay ticks" + }, + { + "name": "DLY_TICKS_48", + "value": 48, + "description": "Delay target for uSDHC DLL - 48 delay ticks" + }, + { + "name": "DLY_TICKS_49", + "value": 49, + "description": "Delay target for uSDHC DLL - 49 delay ticks" + }, + { + "name": "DLY_TICKS_50", + "value": 50, + "description": "Delay target for uSDHC DLL - 50 delay ticks" + }, + { + "name": "DLY_TICKS_51", + "value": 51, + "description": "Delay target for uSDHC DLL - 51 delay ticks" + }, + { + "name": "DLY_TICKS_52", + "value": 52, + "description": "Delay target for uSDHC DLL - 52 delay ticks" + }, + { + "name": "DLY_TICKS_53", + "value": 53, + "description": "Delay target for uSDHC DLL - 53 delay ticks" + }, + { + "name": "DLY_TICKS_54", + "value": 54, + "description": "Delay target for uSDHC DLL - 54 delay ticks" + }, + { + "name": "DLY_TICKS_55", + "value": 55, + "description": "Delay target for uSDHC DLL - 55 delay ticks" + }, + { + "name": "DLY_TICKS_56", + "value": 56, + "description": "Delay target for uSDHC DLL - 56 delay ticks" + }, + { + "name": "DLY_TICKS_57", + "value": 57, + "description": "Delay target for uSDHC DLL - 57 delay ticks" + }, + { + "name": "DLY_TICKS_58", + "value": 58, + "description": "Delay target for uSDHC DLL - 58 delay ticks" + }, + { + "name": "DLY_TICKS_59", + "value": 59, + "description": "Delay target for uSDHC DLL - 59 delay ticks" + }, + { + "name": "DLY_TICKS_60", + "value": 60, + "description": "Delay target for uSDHC DLL - 60 delay ticks" + }, + { + "name": "DLY_TICKS_61", + "value": 61, + "description": "Delay target for uSDHC DLL - 61 delay ticks" + }, + { + "name": "DLY_TICKS_62", + "value": 62, + "description": "Delay target for uSDHC DLL - 62 delay ticks" + }, + { + "name": "DLY_TICKS_63", + "value": 63, + "description": "Delay target for uSDHC DLL - 63 delay ticks" + }, + { + "name": "DLY_TICKS_64", + "value": 64, + "description": "Delay target for uSDHC DLL - 64 delay ticks" + }, + { + "name": "DLY_TICKS_65", + "value": 65, + "description": "Delay target for uSDHC DLL - 65 delay ticks" + }, + { + "name": "DLY_TICKS_66", + "value": 66, + "description": "Delay target for uSDHC DLL - 66 delay ticks" + }, + { + "name": "DLY_TICKS_67", + "value": 67, + "description": "Delay target for uSDHC DLL - 67 delay ticks" + }, + { + "name": "DLY_TICKS_68", + "value": 68, + "description": "Delay target for uSDHC DLL - 68 delay ticks" + }, + { + "name": "DLY_TICKS_69", + "value": 69, + "description": "Delay target for uSDHC DLL - 69 delay ticks" + }, + { + "name": "DLY_TICKS_70", + "value": 70, + "description": "Delay target for uSDHC DLL - 70 delay ticks" + }, + { + "name": "DLY_TICKS_71", + "value": 71, + "description": "Delay target for uSDHC DLL - 71 delay ticks" + }, + { + "name": "DLY_TICKS_72", + "value": 72, + "description": "Delay target for uSDHC DLL - 72 delay ticks" + }, + { + "name": "DLY_TICKS_73", + "value": 73, + "description": "Delay target for uSDHC DLL - 73 delay ticks" + }, + { + "name": "DLY_TICKS_74", + "value": 74, + "description": "Delay target for uSDHC DLL - 74 delay ticks" + }, + { + "name": "DLY_TICKS_75", + "value": 75, + "description": "Delay target for uSDHC DLL - 75 delay ticks" + }, + { + "name": "DLY_TICKS_76", + "value": 76, + "description": "Delay target for uSDHC DLL - 76 delay ticks" + }, + { + "name": "DLY_TICKS_77", + "value": 77, + "description": "Delay target for uSDHC DLL - 77 delay ticks" + }, + { + "name": "DLY_TICKS_78", + "value": 78, + "description": "Delay target for uSDHC DLL - 78 delay ticks" + }, + { + "name": "DLY_TICKS_79", + "value": 79, + "description": "Delay target for uSDHC DLL - 79 delay ticks" + }, + { + "name": "DLY_TICKS_80", + "value": 80, + "description": "Delay target for uSDHC DLL - 80 delay ticks" + }, + { + "name": "DLY_TICKS_81", + "value": 81, + "description": "Delay target for uSDHC DLL - 81 delay ticks" + }, + { + "name": "DLY_TICKS_82", + "value": 82, + "description": "Delay target for uSDHC DLL - 82 delay ticks" + }, + { + "name": "DLY_TICKS_83", + "value": 83, + "description": "Delay target for uSDHC DLL - 83 delay ticks" + }, + { + "name": "DLY_TICKS_84", + "value": 84, + "description": "Delay target for uSDHC DLL - 84 delay ticks" + }, + { + "name": "DLY_TICKS_85", + "value": 85, + "description": "Delay target for uSDHC DLL - 85 delay ticks" + }, + { + "name": "DLY_TICKS_86", + "value": 86, + "description": "Delay target for uSDHC DLL - 86 delay ticks" + }, + { + "name": "DLY_TICKS_87", + "value": 87, + "description": "Delay target for uSDHC DLL - 87 delay ticks" + }, + { + "name": "DLY_TICKS_88", + "value": 88, + "description": "Delay target for uSDHC DLL - 88 delay ticks" + }, + { + "name": "DLY_TICKS_89", + "value": 89, + "description": "Delay target for uSDHC DLL - 89 delay ticks" + }, + { + "name": "DLY_TICKS_90", + "value": 90, + "description": "Delay target for uSDHC DLL - 90 delay ticks" + }, + { + "name": "DLY_TICKS_91", + "value": 91, + "description": "Delay target for uSDHC DLL - 91 delay ticks" + }, + { + "name": "DLY_TICKS_92", + "value": 92, + "description": "Delay target for uSDHC DLL - 92 delay ticks" + }, + { + "name": "DLY_TICKS_93", + "value": 93, + "description": "Delay target for uSDHC DLL - 93 delay ticks" + }, + { + "name": "DLY_TICKS_94", + "value": 94, + "description": "Delay target for uSDHC DLL - 94 delay ticks" + }, + { + "name": "DLY_TICKS_95", + "value": 95, + "description": "Delay target for uSDHC DLL - 95 delay ticks" + }, + { + "name": "DLY_TICKS_96", + "value": 96, + "description": "Delay target for uSDHC DLL - 96 delay ticks" + }, + { + "name": "DLY_TICKS_97", + "value": 97, + "description": "Delay target for uSDHC DLL - 97 delay ticks" + }, + { + "name": "DLY_TICKS_98", + "value": 98, + "description": "Delay target for uSDHC DLL - 98 delay ticks" + }, + { + "name": "DLY_TICKS_99", + "value": 99, + "description": "Delay target for uSDHC DLL - 99 delay ticks" + }, + { + "name": "DLY_TICKS_100", + "value": 100, + "description": "Delay target for uSDHC DLL - 100 delay ticks" + }, + { + "name": "DLY_TICKS_101", + "value": 101, + "description": "Delay target for uSDHC DLL - 101 delay ticks" + }, + { + "name": "DLY_TICKS_102", + "value": 102, + "description": "Delay target for uSDHC DLL - 102 delay ticks" + }, + { + "name": "DLY_TICKS_103", + "value": 103, + "description": "Delay target for uSDHC DLL - 103 delay ticks" + }, + { + "name": "DLY_TICKS_104", + "value": 104, + "description": "Delay target for uSDHC DLL - 104 delay ticks" + }, + { + "name": "DLY_TICKS_105", + "value": 105, + "description": "Delay target for uSDHC DLL - 105 delay ticks" + }, + { + "name": "DLY_TICKS_106", + "value": 106, + "description": "Delay target for uSDHC DLL - 106 delay ticks" + }, + { + "name": "DLY_TICKS_107", + "value": 107, + "description": "Delay target for uSDHC DLL - 107 delay ticks" + }, + { + "name": "DLY_TICKS_108", + "value": 108, + "description": "Delay target for uSDHC DLL - 108 delay ticks" + }, + { + "name": "DLY_TICKS_109", + "value": 109, + "description": "Delay target for uSDHC DLL - 109 delay ticks" + }, + { + "name": "DLY_TICKS_110", + "value": 110, + "description": "Delay target for uSDHC DLL - 110 delay ticks" + }, + { + "name": "DLY_TICKS_111", + "value": 111, + "description": "Delay target for uSDHC DLL - 111 delay ticks" + }, + { + "name": "DLY_TICKS_112", + "value": 112, + "description": "Delay target for uSDHC DLL - 112 delay ticks" + }, + { + "name": "DLY_TICKS_113", + "value": 113, + "description": "Delay target for uSDHC DLL - 113 delay ticks" + }, + { + "name": "DLY_TICKS_114", + "value": 114, + "description": "Delay target for uSDHC DLL - 114 delay ticks" + }, + { + "name": "DLY_TICKS_115", + "value": 115, + "description": "Delay target for uSDHC DLL - 115 delay ticks" + }, + { + "name": "DLY_TICKS_116", + "value": 116, + "description": "Delay target for uSDHC DLL - 116 delay ticks" + }, + { + "name": "DLY_TICKS_117", + "value": 117, + "description": "Delay target for uSDHC DLL - 117 delay ticks" + }, + { + "name": "DLY_TICKS_118", + "value": 118, + "description": "Delay target for uSDHC DLL - 118 delay ticks" + }, + { + "name": "DLY_TICKS_119", + "value": 119, + "description": "Delay target for uSDHC DLL - 119 delay ticks" + }, + { + "name": "DLY_TICKS_120", + "value": 120, + "description": "Delay target for uSDHC DLL - 120 delay ticks" + }, + { + "name": "DLY_TICKS_121", + "value": 121, + "description": "Delay target for uSDHC DLL - 121 delay ticks" + }, + { + "name": "DLY_TICKS_122", + "value": 122, + "description": "Delay target for uSDHC DLL - 122 delay ticks" + }, + { + "name": "DLY_TICKS_123", + "value": 123, + "description": "Delay target for uSDHC DLL - 123 delay ticks" + }, + { + "name": "DLY_TICKS_124", + "value": 124, + "description": "Delay target for uSDHC DLL - 124 delay ticks" + }, + { + "name": "DLY_TICKS_125", + "value": 125, + "description": "Delay target for uSDHC DLL - 125 delay ticks" + }, + { + "name": "DLY_TICKS_126", + "value": 126, + "description": "Delay target for uSDHC DLL - 126 delay ticks" + }, + { + "name": "DLY_TICKS_127", + "value": 127, + "description": "Delay target for uSDHC DLL - 127 delay ticks" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-31", + "name": "uSDHC_DLL_Select", + "description": "uSDHC DLL Select", + "values": [ + { + "name": "SLAVE_MODE", + "value": 0, + "description": "DLL Slave Mode" + }, + { + "name": "OVERRIDE_MODE", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "BOOT_CFG2", + "index_int": "0x001A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse26-bits-0-1", + "name": "FlexSPI_NAND_Column_Address_Width", + "description": "FlexSPI NAND Column Address Width", + "values": [ + { + "name": "WIDTH_12_BITS", + "value": 0, + "description": "12 bit column address width" + }, + { + "name": "WIDTH_13_BITS", + "value": 1, + "description": "13 bit column address width" + }, + { + "name": "WIDTH_14_BITS", + "value": 2, + "description": "14 bit column address width" + }, + { + "name": "WIDTH_15_BITS", + "value": 3, + "description": "15 bit column address width" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-2-3", + "name": "FlexSPI_NAND_CS_Interval", + "description": "FlexSPI NAND CS Interval", + "values": [ + { + "name": "INTERVAL_100NS", + "value": 0, + "description": "100 ns" + }, + { + "name": "INTERVAL_200NS", + "value": 1, + "description": "200 ns" + }, + { + "name": "INTERVAL_400NS", + "value": 2, + "description": "400 ns" + }, + { + "name": "INTERVAL_50NS", + "value": 3, + "description": "50 ns" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-4-5", + "name": "FlexSPI_NAND_Search_Count", + "description": "FlexSPI NAND Search Count", + "values": [ + { + "name": "COUNT_2", + "value": 0, + "description": "FlexSPI_NAND_Search_Count: 2" + }, + { + "name": "COUNT_4", + "value": 2, + "description": "FlexSPI_NAND_Search_Count: 4" + }, + { + "name": "COUNT_8", + "value": 3, + "description": "FlexSPI_NAND_Search_Count: 8" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-6-7", + "name": "FlexSPI_NAND_Search_Stride", + "description": "FlexSPI NAND Search Stride", + "values": [ + { + "name": "PAGES_64", + "value": 0, + "description": "64 pages" + }, + { + "name": "PAGES_128", + "value": 1, + "description": "128 pages" + }, + { + "name": "PAGES_256", + "value": 2, + "description": "256 pages" + }, + { + "name": "PAGES_32", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 8, + "id": "fuse26-bits-8-15", + "name": "FlexSPI_DLL_Value", + "description": "FlexSPI DLL Value", + "values": [ + { + "name": "DLL_DELAY_MIN", + "value": 0, + "description": "The delay line value only for HyperFlash - minimum delay (0)" + }, + { + "name": "DLL_DELAY_1", + "value": 1, + "description": "The delay line value only for HyperFlash - delay value 1" + }, + { + "name": "DLL_DELAY_2", + "value": 2, + "description": "The delay line value only for HyperFlash - delay value 2" + }, + { + "name": "DLL_DELAY_3", + "value": 3, + "description": "The delay line value only for HyperFlash - delay value 3" + }, + { + "name": "DLL_DELAY_4", + "value": 4, + "description": "The delay line value only for HyperFlash - delay value 4" + }, + { + "name": "DLL_DELAY_5", + "value": 5, + "description": "The delay line value only for HyperFlash - delay value 5" + }, + { + "name": "DLL_DELAY_6", + "value": 6, + "description": "The delay line value only for HyperFlash - delay value 6" + }, + { + "name": "DLL_DELAY_7", + "value": 7, + "description": "The delay line value only for HyperFlash - delay value 7" + }, + { + "name": "DLL_DELAY_8", + "value": 8, + "description": "The delay line value only for HyperFlash - delay value 8" + }, + { + "name": "DLL_DELAY_9", + "value": 9, + "description": "The delay line value only for HyperFlash - delay value 9" + }, + { + "name": "DLL_DELAY_10", + "value": 10, + "description": "The delay line value only for HyperFlash - delay value 10" + }, + { + "name": "DLL_DELAY_11", + "value": 11, + "description": "The delay line value only for HyperFlash - delay value 11" + }, + { + "name": "DLL_DELAY_12", + "value": 12, + "description": "The delay line value only for HyperFlash - delay value 12" + }, + { + "name": "DLL_DELAY_13", + "value": 13, + "description": "The delay line value only for HyperFlash - delay value 13" + }, + { + "name": "DLL_DELAY_14", + "value": 14, + "description": "The delay line value only for HyperFlash - delay value 14" + }, + { + "name": "DLL_DELAY_15", + "value": 15, + "description": "The delay line value only for HyperFlash - delay value 15" + }, + { + "name": "DLL_DELAY_16", + "value": 16, + "description": "The delay line value only for HyperFlash - delay value 16" + }, + { + "name": "DLL_DELAY_17", + "value": 17, + "description": "The delay line value only for HyperFlash - delay value 17" + }, + { + "name": "DLL_DELAY_18", + "value": 18, + "description": "The delay line value only for HyperFlash - delay value 18" + }, + { + "name": "DLL_DELAY_19", + "value": 19, + "description": "The delay line value only for HyperFlash - delay value 19" + }, + { + "name": "DLL_DELAY_20", + "value": 20, + "description": "The delay line value only for HyperFlash - delay value 20" + }, + { + "name": "DLL_DELAY_21", + "value": 21, + "description": "The delay line value only for HyperFlash - delay value 21" + }, + { + "name": "DLL_DELAY_22", + "value": 22, + "description": "The delay line value only for HyperFlash - delay value 22" + }, + { + "name": "DLL_DELAY_23", + "value": 23, + "description": "The delay line value only for HyperFlash - delay value 23" + }, + { + "name": "DLL_DELAY_24", + "value": 24, + "description": "The delay line value only for HyperFlash - delay value 24" + }, + { + "name": "DLL_DELAY_25", + "value": 25, + "description": "The delay line value only for HyperFlash - delay value 25" + }, + { + "name": "DLL_DELAY_26", + "value": 26, + "description": "The delay line value only for HyperFlash - delay value 26" + }, + { + "name": "DLL_DELAY_27", + "value": 27, + "description": "The delay line value only for HyperFlash - delay value 27" + }, + { + "name": "DLL_DELAY_28", + "value": 28, + "description": "The delay line value only for HyperFlash - delay value 28" + }, + { + "name": "DLL_DELAY_29", + "value": 29, + "description": "The delay line value only for HyperFlash - delay value 29" + }, + { + "name": "DLL_DELAY_30", + "value": 30, + "description": "The delay line value only for HyperFlash - delay value 30" + }, + { + "name": "DLL_DELAY_31", + "value": 31, + "description": "The delay line value only for HyperFlash - delay value 31" + }, + { + "name": "DLL_DELAY_32", + "value": 32, + "description": "The delay line value only for HyperFlash - delay value 32" + }, + { + "name": "DLL_DELAY_33", + "value": 33, + "description": "The delay line value only for HyperFlash - delay value 33" + }, + { + "name": "DLL_DELAY_34", + "value": 34, + "description": "The delay line value only for HyperFlash - delay value 34" + }, + { + "name": "DLL_DELAY_35", + "value": 35, + "description": "The delay line value only for HyperFlash - delay value 35" + }, + { + "name": "DLL_DELAY_36", + "value": 36, + "description": "The delay line value only for HyperFlash - delay value 36" + }, + { + "name": "DLL_DELAY_37", + "value": 37, + "description": "The delay line value only for HyperFlash - delay value 37" + }, + { + "name": "DLL_DELAY_38", + "value": 38, + "description": "The delay line value only for HyperFlash - delay value 38" + }, + { + "name": "DLL_DELAY_39", + "value": 39, + "description": "The delay line value only for HyperFlash - delay value 39" + }, + { + "name": "DLL_DELAY_40", + "value": 40, + "description": "The delay line value only for HyperFlash - delay value 40" + }, + { + "name": "DLL_DELAY_41", + "value": 41, + "description": "The delay line value only for HyperFlash - delay value 41" + }, + { + "name": "DLL_DELAY_42", + "value": 42, + "description": "The delay line value only for HyperFlash - delay value 42" + }, + { + "name": "DLL_DELAY_43", + "value": 43, + "description": "The delay line value only for HyperFlash - delay value 43" + }, + { + "name": "DLL_DELAY_44", + "value": 44, + "description": "The delay line value only for HyperFlash - delay value 44" + }, + { + "name": "DLL_DELAY_45", + "value": 45, + "description": "The delay line value only for HyperFlash - delay value 45" + }, + { + "name": "DLL_DELAY_46", + "value": 46, + "description": "The delay line value only for HyperFlash - delay value 46" + }, + { + "name": "DLL_DELAY_47", + "value": 47, + "description": "The delay line value only for HyperFlash - delay value 47" + }, + { + "name": "DLL_DELAY_48", + "value": 48, + "description": "The delay line value only for HyperFlash - delay value 48" + }, + { + "name": "DLL_DELAY_49", + "value": 49, + "description": "The delay line value only for HyperFlash - delay value 49" + }, + { + "name": "DLL_DELAY_50", + "value": 50, + "description": "The delay line value only for HyperFlash - delay value 50" + }, + { + "name": "DLL_DELAY_51", + "value": 51, + "description": "The delay line value only for HyperFlash - delay value 51" + }, + { + "name": "DLL_DELAY_52", + "value": 52, + "description": "The delay line value only for HyperFlash - delay value 52" + }, + { + "name": "DLL_DELAY_53", + "value": 53, + "description": "The delay line value only for HyperFlash - delay value 53" + }, + { + "name": "DLL_DELAY_54", + "value": 54, + "description": "The delay line value only for HyperFlash - delay value 54" + }, + { + "name": "DLL_DELAY_55", + "value": 55, + "description": "The delay line value only for HyperFlash - delay value 55" + }, + { + "name": "DLL_DELAY_56", + "value": 56, + "description": "The delay line value only for HyperFlash - delay value 56" + }, + { + "name": "DLL_DELAY_57", + "value": 57, + "description": "The delay line value only for HyperFlash - delay value 57" + }, + { + "name": "DLL_DELAY_58", + "value": 58, + "description": "The delay line value only for HyperFlash - delay value 58" + }, + { + "name": "DLL_DELAY_59", + "value": 59, + "description": "The delay line value only for HyperFlash - delay value 59" + }, + { + "name": "DLL_DELAY_60", + "value": 60, + "description": "The delay line value only for HyperFlash - delay value 60" + }, + { + "name": "DLL_DELAY_61", + "value": 61, + "description": "The delay line value only for HyperFlash - delay value 61" + }, + { + "name": "DLL_DELAY_62", + "value": 62, + "description": "The delay line value only for HyperFlash - delay value 62" + }, + { + "name": "DLL_DELAY_63", + "value": 63, + "description": "The delay line value only for HyperFlash - delay value 63" + }, + { + "name": "DLL_DELAY_64", + "value": 64, + "description": "The delay line value only for HyperFlash - delay value 64" + }, + { + "name": "DLL_DELAY_65", + "value": 65, + "description": "The delay line value only for HyperFlash - delay value 65" + }, + { + "name": "DLL_DELAY_66", + "value": 66, + "description": "The delay line value only for HyperFlash - delay value 66" + }, + { + "name": "DLL_DELAY_67", + "value": 67, + "description": "The delay line value only for HyperFlash - delay value 67" + }, + { + "name": "DLL_DELAY_68", + "value": 68, + "description": "The delay line value only for HyperFlash - delay value 68" + }, + { + "name": "DLL_DELAY_69", + "value": 69, + "description": "The delay line value only for HyperFlash - delay value 69" + }, + { + "name": "DLL_DELAY_70", + "value": 70, + "description": "The delay line value only for HyperFlash - delay value 70" + }, + { + "name": "DLL_DELAY_71", + "value": 71, + "description": "The delay line value only for HyperFlash - delay value 71" + }, + { + "name": "DLL_DELAY_72", + "value": 72, + "description": "The delay line value only for HyperFlash - delay value 72" + }, + { + "name": "DLL_DELAY_73", + "value": 73, + "description": "The delay line value only for HyperFlash - delay value 73" + }, + { + "name": "DLL_DELAY_74", + "value": 74, + "description": "The delay line value only for HyperFlash - delay value 74" + }, + { + "name": "DLL_DELAY_75", + "value": 75, + "description": "The delay line value only for HyperFlash - delay value 75" + }, + { + "name": "DLL_DELAY_76", + "value": 76, + "description": "The delay line value only for HyperFlash - delay value 76" + }, + { + "name": "DLL_DELAY_77", + "value": 77, + "description": "The delay line value only for HyperFlash - delay value 77" + }, + { + "name": "DLL_DELAY_78", + "value": 78, + "description": "The delay line value only for HyperFlash - delay value 78" + }, + { + "name": "DLL_DELAY_79", + "value": 79, + "description": "The delay line value only for HyperFlash - delay value 79" + }, + { + "name": "DLL_DELAY_80", + "value": 80, + "description": "The delay line value only for HyperFlash - delay value 80" + }, + { + "name": "DLL_DELAY_81", + "value": 81, + "description": "The delay line value only for HyperFlash - delay value 81" + }, + { + "name": "DLL_DELAY_82", + "value": 82, + "description": "The delay line value only for HyperFlash - delay value 82" + }, + { + "name": "DLL_DELAY_83", + "value": 83, + "description": "The delay line value only for HyperFlash - delay value 83" + }, + { + "name": "DLL_DELAY_84", + "value": 84, + "description": "The delay line value only for HyperFlash - delay value 84" + }, + { + "name": "DLL_DELAY_85", + "value": 85, + "description": "The delay line value only for HyperFlash - delay value 85" + }, + { + "name": "DLL_DELAY_86", + "value": 86, + "description": "The delay line value only for HyperFlash - delay value 86" + }, + { + "name": "DLL_DELAY_87", + "value": 87, + "description": "The delay line value only for HyperFlash - delay value 87" + }, + { + "name": "DLL_DELAY_88", + "value": 88, + "description": "The delay line value only for HyperFlash - delay value 88" + }, + { + "name": "DLL_DELAY_89", + "value": 89, + "description": "The delay line value only for HyperFlash - delay value 89" + }, + { + "name": "DLL_DELAY_90", + "value": 90, + "description": "The delay line value only for HyperFlash - delay value 90" + }, + { + "name": "DLL_DELAY_91", + "value": 91, + "description": "The delay line value only for HyperFlash - delay value 91" + }, + { + "name": "DLL_DELAY_92", + "value": 92, + "description": "The delay line value only for HyperFlash - delay value 92" + }, + { + "name": "DLL_DELAY_93", + "value": 93, + "description": "The delay line value only for HyperFlash - delay value 93" + }, + { + "name": "DLL_DELAY_94", + "value": 94, + "description": "The delay line value only for HyperFlash - delay value 94" + }, + { + "name": "DLL_DELAY_95", + "value": 95, + "description": "The delay line value only for HyperFlash - delay value 95" + }, + { + "name": "DLL_DELAY_96", + "value": 96, + "description": "The delay line value only for HyperFlash - delay value 96" + }, + { + "name": "DLL_DELAY_97", + "value": 97, + "description": "The delay line value only for HyperFlash - delay value 97" + }, + { + "name": "DLL_DELAY_98", + "value": 98, + "description": "The delay line value only for HyperFlash - delay value 98" + }, + { + "name": "DLL_DELAY_99", + "value": 99, + "description": "The delay line value only for HyperFlash - delay value 99" + }, + { + "name": "DLL_DELAY_100", + "value": 100, + "description": "The delay line value only for HyperFlash - delay value 100" + }, + { + "name": "DLL_DELAY_101", + "value": 101, + "description": "The delay line value only for HyperFlash - delay value 101" + }, + { + "name": "DLL_DELAY_102", + "value": 102, + "description": "The delay line value only for HyperFlash - delay value 102" + }, + { + "name": "DLL_DELAY_103", + "value": 103, + "description": "The delay line value only for HyperFlash - delay value 103" + }, + { + "name": "DLL_DELAY_104", + "value": 104, + "description": "The delay line value only for HyperFlash - delay value 104" + }, + { + "name": "DLL_DELAY_105", + "value": 105, + "description": "The delay line value only for HyperFlash - delay value 105" + }, + { + "name": "DLL_DELAY_106", + "value": 106, + "description": "The delay line value only for HyperFlash - delay value 106" + }, + { + "name": "DLL_DELAY_107", + "value": 107, + "description": "The delay line value only for HyperFlash - delay value 107" + }, + { + "name": "DLL_DELAY_108", + "value": 108, + "description": "The delay line value only for HyperFlash - delay value 108" + }, + { + "name": "DLL_DELAY_109", + "value": 109, + "description": "The delay line value only for HyperFlash - delay value 109" + }, + { + "name": "DLL_DELAY_110", + "value": 110, + "description": "The delay line value only for HyperFlash - delay value 110" + }, + { + "name": "DLL_DELAY_111", + "value": 111, + "description": "The delay line value only for HyperFlash - delay value 111" + }, + { + "name": "DLL_DELAY_112", + "value": 112, + "description": "The delay line value only for HyperFlash - delay value 112" + }, + { + "name": "DLL_DELAY_113", + "value": 113, + "description": "The delay line value only for HyperFlash - delay value 113" + }, + { + "name": "DLL_DELAY_114", + "value": 114, + "description": "The delay line value only for HyperFlash - delay value 114" + }, + { + "name": "DLL_DELAY_115", + "value": 115, + "description": "The delay line value only for HyperFlash - delay value 115" + }, + { + "name": "DLL_DELAY_116", + "value": 116, + "description": "The delay line value only for HyperFlash - delay value 116" + }, + { + "name": "DLL_DELAY_117", + "value": 117, + "description": "The delay line value only for HyperFlash - delay value 117" + }, + { + "name": "DLL_DELAY_118", + "value": 118, + "description": "The delay line value only for HyperFlash - delay value 118" + }, + { + "name": "DLL_DELAY_119", + "value": 119, + "description": "The delay line value only for HyperFlash - delay value 119" + }, + { + "name": "DLL_DELAY_120", + "value": 120, + "description": "The delay line value only for HyperFlash - delay value 120" + }, + { + "name": "DLL_DELAY_121", + "value": 121, + "description": "The delay line value only for HyperFlash - delay value 121" + }, + { + "name": "DLL_DELAY_122", + "value": 122, + "description": "The delay line value only for HyperFlash - delay value 122" + }, + { + "name": "DLL_DELAY_123", + "value": 123, + "description": "The delay line value only for HyperFlash - delay value 123" + }, + { + "name": "DLL_DELAY_124", + "value": 124, + "description": "The delay line value only for HyperFlash - delay value 124" + }, + { + "name": "DLL_DELAY_125", + "value": 125, + "description": "The delay line value only for HyperFlash - delay value 125" + }, + { + "name": "DLL_DELAY_126", + "value": 126, + "description": "The delay line value only for HyperFlash - delay value 126" + }, + { + "name": "DLL_DELAY_127", + "value": 127, + "description": "The delay line value only for HyperFlash - delay value 127" + }, + { + "name": "DLL_DELAY_128", + "value": 128, + "description": "The delay line value only for HyperFlash - delay value 128" + }, + { + "name": "DLL_DELAY_129", + "value": 129, + "description": "The delay line value only for HyperFlash - delay value 129" + }, + { + "name": "DLL_DELAY_130", + "value": 130, + "description": "The delay line value only for HyperFlash - delay value 130" + }, + { + "name": "DLL_DELAY_131", + "value": 131, + "description": "The delay line value only for HyperFlash - delay value 131" + }, + { + "name": "DLL_DELAY_132", + "value": 132, + "description": "The delay line value only for HyperFlash - delay value 132" + }, + { + "name": "DLL_DELAY_133", + "value": 133, + "description": "The delay line value only for HyperFlash - delay value 133" + }, + { + "name": "DLL_DELAY_134", + "value": 134, + "description": "The delay line value only for HyperFlash - delay value 134" + }, + { + "name": "DLL_DELAY_135", + "value": 135, + "description": "The delay line value only for HyperFlash - delay value 135" + }, + { + "name": "DLL_DELAY_136", + "value": 136, + "description": "The delay line value only for HyperFlash - delay value 136" + }, + { + "name": "DLL_DELAY_137", + "value": 137, + "description": "The delay line value only for HyperFlash - delay value 137" + }, + { + "name": "DLL_DELAY_138", + "value": 138, + "description": "The delay line value only for HyperFlash - delay value 138" + }, + { + "name": "DLL_DELAY_139", + "value": 139, + "description": "The delay line value only for HyperFlash - delay value 139" + }, + { + "name": "DLL_DELAY_140", + "value": 140, + "description": "The delay line value only for HyperFlash - delay value 140" + }, + { + "name": "DLL_DELAY_141", + "value": 141, + "description": "The delay line value only for HyperFlash - delay value 141" + }, + { + "name": "DLL_DELAY_142", + "value": 142, + "description": "The delay line value only for HyperFlash - delay value 142" + }, + { + "name": "DLL_DELAY_143", + "value": 143, + "description": "The delay line value only for HyperFlash - delay value 143" + }, + { + "name": "DLL_DELAY_144", + "value": 144, + "description": "The delay line value only for HyperFlash - delay value 144" + }, + { + "name": "DLL_DELAY_145", + "value": 145, + "description": "The delay line value only for HyperFlash - delay value 145" + }, + { + "name": "DLL_DELAY_146", + "value": 146, + "description": "The delay line value only for HyperFlash - delay value 146" + }, + { + "name": "DLL_DELAY_147", + "value": 147, + "description": "The delay line value only for HyperFlash - delay value 147" + }, + { + "name": "DLL_DELAY_148", + "value": 148, + "description": "Delay line value 148 for HyperFlash" + }, + { + "name": "DLL_DELAY_149", + "value": 149, + "description": "Delay line value 149 for HyperFlash" + }, + { + "name": "DLL_DELAY_150", + "value": 150, + "description": "Delay line value 150 for HyperFlash" + }, + { + "name": "DLL_DELAY_151", + "value": 151, + "description": "Delay line value 151 for HyperFlash" + }, + { + "name": "DLL_DELAY_152", + "value": 152, + "description": "Delay line value 152 for HyperFlash" + }, + { + "name": "DLL_DELAY_153", + "value": 153, + "description": "Delay line value 153 for HyperFlash" + }, + { + "name": "DLL_DELAY_154", + "value": 154, + "description": "Delay line value 154 for HyperFlash" + }, + { + "name": "DLL_DELAY_155", + "value": 155, + "description": "Delay line value 155 for HyperFlash" + }, + { + "name": "DLL_DELAY_156", + "value": 156, + "description": "Delay line value 156 for HyperFlash" + }, + { + "name": "DLL_DELAY_157", + "value": 157, + "description": "Delay line value 157 for HyperFlash" + }, + { + "name": "DLL_DELAY_158", + "value": 158, + "description": "Delay line value 158 for HyperFlash" + }, + { + "name": "DLL_DELAY_159", + "value": 159, + "description": "Delay line value 159 for HyperFlash" + }, + { + "name": "DLL_DELAY_160", + "value": 160, + "description": "Delay line value 160 for HyperFlash" + }, + { + "name": "DLL_DELAY_161", + "value": 161, + "description": "Delay line value 161 for HyperFlash" + }, + { + "name": "DLL_DELAY_162", + "value": 162, + "description": "Delay line value 162 for HyperFlash" + }, + { + "name": "DLL_DELAY_163", + "value": 163, + "description": "Delay line value 163 for HyperFlash" + }, + { + "name": "DLL_DELAY_164", + "value": 164, + "description": "Delay line value 164 for HyperFlash" + }, + { + "name": "DLL_DELAY_165", + "value": 165, + "description": "Delay line value 165 for HyperFlash" + }, + { + "name": "DLL_DELAY_166", + "value": 166, + "description": "Delay line value 166" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-16", + "name": "SPI_Clock_Data_Phase_Control", + "description": "SPI Clock Data Phase Control ", + "values": [ + { + "name": "TX_FALL_RX_RISE", + "value": 0, + "description": "Tx on falling, Rx on rising" + }, + { + "name": "TX_RISE_RX_FALL", + "value": 1, + "description": "Tx on rising, Rx on falling" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-17", + "name": "SPI_SCLK_Active", + "description": "SPI SCLK Active", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high" + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-18", + "name": "SPI_SS_Active", + "description": "SPI SS Active", + "values": [ + { + "name": "ACTIVE_LOW", + "value": 0, + "description": "Active low" + }, + { + "name": "ACTIVE_HIGH", + "value": 1, + "description": "Active high" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-19", + "name": "Recovery_SPI_Addressing", + "description": "Recovery SPI Addressing", + "values": [ + { + "name": "ADDRESSING_3BYTE", + "value": 0, + "description": "3-bytes (24-bit)" + }, + { + "name": "ADDRESSING_2BYTE", + "value": 1, + "description": "2-bytes (16-bit)" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-20", + "name": "FLEXSPI_NOR_AUTO_PROBE_EN", + "description": "FlexSPI NOR auto probe enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Auto probe is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Auto probe is enabled" + } + ] + }, + { + "width": 3, + "id": "fuse26-bits-21-23", + "name": "FlexSPI_NAND_Busy_Bit_Offset_Override", + "description": "FlexSPI NAND Busy Bit Offset Override ", + "values": [ + { + "name": "BIT_OFFSET_0", + "value": 0, + "description": "Busy bit at offset 0 in 8-bit register" + }, + { + "name": "BIT_OFFSET_1", + "value": 1, + "description": "Busy bit at offset 1 in 8-bit register" + }, + { + "name": "BIT_OFFSET_2", + "value": 2, + "description": "Busy bit at offset 2 in 8-bit register" + }, + { + "name": "BIT_OFFSET_3", + "value": 3, + "description": "Busy bit at offset 3 in 8-bit register" + }, + { + "name": "BIT_OFFSET_4", + "value": 4, + "description": "Busy bit at offset 4 in 8-bit register" + }, + { + "name": "BIT_OFFSET_5", + "value": 5, + "description": "Busy bit at offset 5 in 8-bit register" + }, + { + "name": "BIT_OFFSET_6", + "value": 6, + "description": "Busy bit at offset 6 in 8-bit register" + }, + { + "name": "BIT_OFFSET_7", + "value": 7, + "description": "Busy bit at offset 7 in 8-bit register" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-24", + "name": "Recovery_CS_Select", + "description": "Recovery CS Select", + "values": [ + { + "name": "CS0", + "value": 0, + "description": "Recovery_CS_Select: CS0" + }, + { + "name": "CS1", + "value": 1, + "description": "Recovery_CS_Select: CS1" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-25", + "name": "RSVD_BOOT_CFG2_25", + "description": "BOOT_CFG2" + }, + { + "width": 2, + "id": "fuse26-bits-26-27", + "name": "Recovery_Port_Select", + "description": "Recovery Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 4, + "id": "fuse26-bits-28-31", + "name": "FLEXSPI_DUMMY_CYCLE_SEL", + "description": "FlexSPI Dummy Cycle Select", + "values": [ + { + "name": "CYCLES_0", + "value": 0, + "description": "0 cycle" + }, + { + "name": "CYCLES_1", + "value": 1, + "description": "1 cycle" + }, + { + "name": "CYCLES_2", + "value": 2, + "description": "2 cycles" + }, + { + "name": "CYCLES_3", + "value": 3, + "description": "3 cycles" + }, + { + "name": "CYCLES_4", + "value": 4, + "description": "4 cycles" + }, + { + "name": "CYCLES_5", + "value": 5, + "description": "5 cycles" + }, + { + "name": "CYCLES_6", + "value": 6, + "description": "6 cycles" + }, + { + "name": "CYCLES_7", + "value": 7, + "description": "7 cycles" + }, + { + "name": "CYCLES_8", + "value": 8, + "description": "8 cycles" + }, + { + "name": "CYCLES_9", + "value": 9, + "description": "9 cycles" + }, + { + "name": "CYCLES_10", + "value": 10, + "description": "10 cycles" + }, + { + "name": "CYCLES_11", + "value": 11, + "description": "11 cycles" + }, + { + "name": "CYCLES_12", + "value": 12, + "description": "12 cycles" + }, + { + "name": "CYCLES_13", + "value": 13, + "description": "13 cycles" + }, + { + "name": "CYCLES_14", + "value": 14, + "description": "14 cycles" + }, + { + "name": "CYCLES_15", + "value": 15, + "description": "15 cycles" + } + ] + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_CFG3", + "description": "BOOT_CFG3", + "index_int": "0x001B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse27-bits-0-2", + "name": "FlexSPI_NOR_Reset_Pin_selection", + "description": "FlexSPI NOR Reset Pin Selection", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "Not reset boot device" + }, + { + "name": "GPIO_PORT1", + "value": 1, + "description": "GPIO port1" + }, + { + "name": "GPIO_PORT2", + "value": 2, + "description": "GPIO port2" + }, + { + "name": "GPIO_PORT3", + "value": 3, + "description": "GPIO port3" + }, + { + "name": "GPIO_PORT4", + "value": 4, + "description": "GPIO port4" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-3-4", + "name": "FLEXSPI_NOR_AUTO_PROBE type", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MXIC_OCTAL", + "value": 1, + "description": "MxicOctal" + }, + { + "name": "MICRON_OCTAL", + "value": 2, + "description": "MicronOctal" + }, + { + "name": "ADESTO_OCTAL", + "value": 3, + "description": "AdestoOctal" + } + ] + }, + { + "width": 27 + } + ] + }, + { + "id": "Reserved28", + "name": "Reserved 0x1C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001C", + "is_reserved": true + }, + { + "id": "Reserved29", + "name": "Reserved 0x1D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001D", + "is_reserved": true + }, + { + "id": "Reserved30", + "name": "Reserved 0x1E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001E", + "is_reserved": true + }, + { + "id": "Reserved31", + "name": "Reserved 0x1F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001F", + "is_reserved": true + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0020", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "fuse32-bits-8-15", + "name": "Secondary_boot_offset", + "description": "Secondary boot offset", + "values": [ + { + "name": "OFFSET_4MB", + "value": 0, + "description": "Offset = 4 MB" + }, + { + "name": "OFFSET_2MB", + "value": 1, + "description": "Offset = 2 MB" + }, + { + "name": "OFFSET_1MB", + "value": 2, + "description": "Offset = 1 MB" + }, + { + "name": "OFFSET_8MB", + "value": 3, + "description": "Offset = 8 MB" + }, + { + "name": "OFFSET_16MB", + "value": 4, + "description": "Offset = 16 MB" + }, + { + "name": "OFFSET_32MB", + "value": 5, + "description": "Offset = 32 MB" + }, + { + "name": "OFFSET_64MB", + "value": 6, + "description": "Offset = 64 MB" + }, + { + "name": "OFFSET_128MB", + "value": 7, + "description": "Offset = 128 MB" + }, + { + "name": "OFFSET_256MB", + "value": 8, + "description": "Offset = 256 MB" + }, + { + "name": "OFFSET_512MB", + "value": 9, + "description": "Offset = 512 MB" + }, + { + "name": "EMMC_LAST_128MB", + "value": 254, + "description": "EMMC last 128 MB" + }, + { + "name": "EMMC_LAST_24KB", + "value": 255, + "description": "EMMC last 24KB" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-16", + "name": "A55_D_Cache_Disable", + "description": "CA55 D Cache Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-17", + "name": "M33_D_Cache_Disable", + "description": "CM33 D Cache Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-18", + "name": "USB2_SDP_Disable", + "description": "USB2 SDP Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Not disable" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-19", + "name": "Disable_A55_SPI_Recovery", + "description": "Disable CA55 SPI Recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-20", + "name": "Disable_M33_SPI_Recovery", + "description": "Disable CM33 SPI Recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-21", + "name": "USB1_SDP_Disable", + "description": "USB1 SDP Disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Not disable" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-23", + "name": "M33_WDOG_Enable", + "description": "CM33 WDOG Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-24", + "name": "A55_I_Cache_Dis", + "description": "CA55 I Cache Dis", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enable CA55 I-Cache during ROM Boot" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disable CA55 I-Cache during ROM Boot" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-25", + "name": "M33_I_Cache_Dis", + "description": "CM33 I Cache Dis", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enable CM33 I-Cache during ROM Boot" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disable CM33 I-Cache during ROM Boot" + } + ] + }, + { + "width": 2, + "id": "fuse32-bits-26-27", + "name": "WDOG_Timeout_Select", + "description": "WDOG Timeout Select", + "values": [ + { + "name": "TIMEOUT_32S", + "value": 0, + "description": "WDOG_Timeout_Select: 32 s" + }, + { + "name": "TIMEOUT_16S", + "value": 1, + "description": "WDOG_Timeout_Select: 16 s" + }, + { + "name": "TIMEOUT_8S", + "value": 2, + "description": "WDOG_Timeout_Select: 8 s" + }, + { + "name": "TIMEOUT_4S", + "value": 3, + "description": "WDOG_Timeout_Select: 4 s" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-28", + "name": "A55_WDOG_Enable", + "description": "CA55 WDOG Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-29", + "name": "USB_HID_EP1_Out_Disable", + "description": "USB HID EP1 Out Disable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "USB EP1 Transfer(EP1 Out enable)" + }, + { + "name": "DISABLED", + "value": 1, + "description": "USB EP0 Transfer(EP1 Out disable)" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-30", + "name": "PLL_LATE_EN", + "description": "PLL LATE EN", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Configure PLLs before installing ROM patch" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Configure PLLs after install ROM patch" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse33", + "name": "BOOT_CFG9", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0021", + "bitfields": [ + { + "width": 4 + }, + { + "width": 1, + "id": "fuse33-bit-4", + "name": "A55 Secure WDOG Enable(non-ROM)", + "description": "CA55 Secure WDOG Enable (non-ROM)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-6", + "name": "M33 TZ WDOG Enable(non-ROM)", + "description": "CM33 TZ WDOG Enable (non-ROM)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-8", + "name": "CM33 RST Release ACK(non-ROM)", + "description": "CM33 RST Release ACK (non-ROM)", + "values": [ + { + "name": "NO_ACK", + "value": 0, + "description": "No Ack from ELE-AP to release CM33 Reset" + }, + { + "name": "ACK_RELEASE", + "value": 1, + "description": "Ack from ELE-AP to release CM33 Reset" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-9", + "name": "CA55 RST Release ACK(non-ROM)", + "description": "CA55 RST Release ACK (non-ROM)", + "values": [ + { + "name": "NO_ACK", + "value": 0, + "description": "No Ack from ELE-AP to release CM33 Reset" + }, + { + "name": "ACK_RELEASE", + "value": 1, + "description": "Ack from ELE-AP to release CM33 Reset" + } + ] + }, + { + "width": 14 + }, + { + "width": 1, + "id": "fuse33-bit-24", + "name": "ELE SRAM REN PWRDN(non-ROM)", + "description": "ELE-AP SRAM REN PWRDN (non-ROM)", + "values": [ + { + "name": "RETAINED_64K", + "value": 0, + "description": "64K retained" + }, + { + "name": "NOT_RETAINED", + "value": 1, + "description": "I/D-MEM not retained" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse34", + "name": "BOOT_CFG10", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0022", + "reg_width": 16, + "bitfields": [ + { + "width": 2, + "id": "fuse34-bits-0-1", + "name": "DAP_ACCESS_IRQ_STKYBIT_DISABLE", + "description": "Disable DAP Access IRQ sticky-bit qualification", + "values": [ + { + "name": "DIRECT_ACCESS", + "value": 0, + "description": "Disable DAP Access qualified by IRQ and sticky-bit logic. Direct DAP Access." + }, + { + "name": "QUALIFIED_ACCESS", + "value": 2, + "description": "Enable DAP Access qualified by IRQ and sticky-bit logic." + } + ] + }, + { + "width": 1, + "id": "fuse34-bit-2", + "name": "SDP_Disable", + "description": "SDP Disable ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 11 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x23-0x37", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved35", + "name": "Reserved 0x23", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0023", + "is_reserved": true + }, + { + "id": "Reserved36", + "name": "Reserved 0x24", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0024", + "is_reserved": true + }, + { + "id": "Reserved37", + "name": "Reserved 0x25", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0025", + "is_reserved": true + }, + { + "id": "Reserved38", + "name": "Reserved 0x26", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0026", + "is_reserved": true + }, + { + "id": "Reserved39", + "name": "Reserved 0x27", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0027", + "is_reserved": true + }, + { + "id": "Reserved40", + "name": "Reserved 0x28", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0028", + "is_reserved": true, + "bitfields": [ + { + "width": 24 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved41", + "name": "Reserved 0x29", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0029", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 12 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved42", + "name": "Reserved 0x2A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002A", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 2 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved43", + "name": "Reserved 0x2B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002B", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 12 + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved44", + "name": "Reserved 0x2C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002C", + "is_reserved": true, + "bitfields": [ + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 9 + } + ] + }, + { + "id": "Reserved45", + "name": "Reserved 0x2D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002D", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 4 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved46", + "name": "Reserved 0x2E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002E", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 19 + } + ] + }, + { + "id": "Reserved47", + "name": "Reserved 0x2F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002F", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved48", + "name": "Reserved 0x30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0030", + "is_reserved": true + }, + { + "id": "Reserved49", + "name": "Reserved 0x31", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0031", + "is_reserved": true + }, + { + "id": "Reserved50", + "name": "Reserved 0x32", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0032", + "is_reserved": true + }, + { + "id": "Reserved51", + "name": "Reserved 0x33", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0033", + "is_reserved": true + }, + { + "id": "Reserved52", + "name": "Reserved 0x34", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0034", + "is_reserved": true + }, + { + "id": "Reserved53", + "name": "Reserved 0x35", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0035", + "is_reserved": true + }, + { + "id": "Reserved54", + "name": "Reserved 0x36", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0036", + "is_reserved": true + }, + { + "id": "Reserved55", + "name": "Reserved 0x37", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0037", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "ELE_MISC_CTRL", + "description": "ELE miscellaneous configuration" + }, + "registers": [ + { + "id": "fuse56", + "name": "ELE_MISC_CTRL0", + "description": "OEM controlled Fuse.", + "index_int": "0x0038", + "bitfields": [ + { + "width": 4, + "id": "fuse56-bits-0-3", + "name": "SOC_SCOPE_PRIMARY_DBG_DISABLE", + "description": "Debug Disable for CM33 ", + "values": [ + { + "name": "ALL_DEBUG_ENABLED", + "value": 0, + "description": "All debug features enabled (spiden, sniden, dbgen, niden all enabled)" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug in non-secure state disabled" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Invasive debug in non-secure state disabled" + }, + { + "name": "NIDEN_DBGEN_DISABLED", + "value": 3, + "description": "Non-invasive and invasive debug in non-secure state disabled" + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled" + }, + { + "name": "SNIDEN_NIDEN_DISABLED", + "value": 5, + "description": "Secure non-invasive debug and non-secure non-invasive debug disabled" + }, + { + "name": "SNIDEN_DBGEN_DISABLED", + "value": 6, + "description": "Secure non-invasive debug and non-secure invasive debug disabled" + }, + { + "name": "SNIDEN_NIDEN_DBGEN_DIS", + "value": 7, + "description": "Secure non-invasive debug and all non-secure debug disabled" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure invasive debug disabled" + }, + { + "name": "SPIDEN_NIDEN_DISABLED", + "value": 9, + "description": "Secure invasive debug and non-secure non-invasive debug disabled" + }, + { + "name": "SPIDEN_DBGEN_DISABLED", + "value": 10, + "description": "Secure invasive debug and non-secure invasive debug disabled" + }, + { + "name": "SPIDEN_NIDEN_DBGEN_DIS", + "value": 11, + "description": "Secure invasive debug and all non-secure debug disabled" + }, + { + "name": "SECURE_DEBUG_DISABLED", + "value": 12, + "description": "All secure debug features disabled" + }, + { + "name": "SEC_SPIDEN_NS_NIDEN_DIS", + "value": 13, + "description": "Secure invasive debug and non-secure non-invasive debug disabled" + }, + { + "name": "SEC_SPIDEN_NS_DBGEN_DIS", + "value": 14, + "description": "Secure invasive debug and non-secure invasive debug disabled" + }, + { + "name": "ALL_DEBUG_DISABLED", + "value": 15, + "description": "All debug features disabled (spiden, sniden, dbgen, niden all disabled)" + } + ] + }, + { + "width": 4, + "id": "fuse56-bits-4-7", + "name": "SOC_SCOPE1_DBG_DISABLE", + "description": "SOC SCOPE1 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_DISABLED", + "value": 0, + "description": "All debug features disabled - spiden, sniden, dbgen, niden all disabled" + }, + { + "name": "NIDEN_ENABLED", + "value": 1, + "description": "Non-invasive debug enabled, invasive debug disabled" + }, + { + "name": "DBGEN_ENABLED", + "value": 2, + "description": "AXI non-secure trace buffer dump enabled, others disabled" + }, + { + "name": "DBGEN_NIDEN_ENABLED", + "value": 3, + "description": "AXI non-secure trace and non-invasive debug enabled" + }, + { + "name": "SNIDEN_ENABLED", + "value": 4, + "description": "Secure non-invasive debug enabled, others disabled" + }, + { + "name": "SNIDEN_NIDEN_ENABLED", + "value": 5, + "description": "Secure and non-secure non-invasive debug enabled" + }, + { + "name": "SNIDEN_DBGEN_ENABLED", + "value": 6, + "description": "Secure non-invasive and AXI non-secure trace enabled" + }, + { + "name": "SNIDEN_DBGEN_NIDEN", + "value": 7, + "description": "Secure non-invasive, AXI non-secure trace, non-invasive debug enabled" + }, + { + "name": "SPIDEN_ENABLED", + "value": 8, + "description": "AXI secure trace buffer dump enabled, others disabled" + }, + { + "name": "SPIDEN_NIDEN_ENABLED", + "value": 9, + "description": "AXI secure trace and non-invasive debug enabled" + }, + { + "name": "SPIDEN_DBGEN_ENABLED", + "value": 10, + "description": "AXI secure and non-secure trace buffer dump enabled" + }, + { + "name": "SPIDEN_DBGEN_NIDEN", + "value": 11, + "description": "AXI secure/non-secure trace and non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_ENABLED", + "value": 12, + "description": "AXI secure trace and secure non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_NIDEN", + "value": 13, + "description": "AXI secure trace, secure and non-secure non-invasive debug enabled" + }, + { + "name": "SPIDEN_SNIDEN_DBGEN", + "value": 14, + "description": "AXI secure/non-secure trace and secure non-invasive debug enabled" + }, + { + "name": "ALL_ENABLED", + "value": 15, + "description": "All debug features enabled - spiden, sniden, dbgen, niden all enabled" + } + ] + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse56-bits-12-15", + "name": "SOC_SCOPE3_DBG_DISABLE", + "description": "SOC SCOPE3 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_ENABLED", + "value": 0, + "description": "All debug features enabled (spiden, sniden, dbgen, niden all enabled)" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug disabled, others enabled" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Invasive debug disabled, others enabled" + }, + { + "name": "DBG_NIDEN_DISABLED", + "value": 3, + "description": "Both invasive and non-invasive debug disabled" + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled, others enabled" + }, + { + "name": "SEC_NIDEN_DISABLED", + "value": 5, + "description": "Secure and non-invasive debug disabled" + }, + { + "name": "SEC_DBG_DISABLED", + "value": 6, + "description": "Secure invasive and invasive debug disabled" + }, + { + "name": "SEC_ALL_DISABLED", + "value": 7, + "description": "All secure and non-secure invasive debug disabled" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure invasive debug disabled, others enabled" + }, + { + "name": "SEC_NINV_DISABLED", + "value": 9, + "description": "Secure invasive and non-invasive debug disabled" + }, + { + "name": "SEC_INV_DISABLED", + "value": 10, + "description": "Secure and invasive debug disabled" + }, + { + "name": "INV_DEBUG_DISABLED", + "value": 11, + "description": "All invasive debug disabled" + }, + { + "name": "SECURE_DBG_DISABLED", + "value": 12, + "description": "All secure debug disabled" + }, + { + "name": "SECURE_NINV_DISABLED", + "value": 13, + "description": "Secure debug and non-invasive debug disabled" + }, + { + "name": "SECURE_INV_DISABLED", + "value": 14, + "description": "Secure debug and invasive debug disabled" + }, + { + "name": "ALL_DISABLED", + "value": 15, + "description": "All debug features disabled (spiden, sniden, dbgen, niden all disabled)" + } + ] + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse57", + "name": "ELE_MISC_CTRL1", + "description": "OEM controlled Fuse.", + "index_int": "0x0039", + "bitfields": [ + { + "width": 4, + "id": "fuse57-bits-0-3", + "name": "SOC_SCOPE4_DBG_DISABLE", + "description": "SOC SCOPE4 DBG DISABLE[3:0]", + "values": [ + { + "name": "ALL_ENABLED", + "value": 0, + "description": "All debug features enabled (spiden, sniden, dbgen, niden all enabled)" + }, + { + "name": "NIDEN_DISABLED", + "value": 1, + "description": "Non-invasive debug in non-secure state disabled" + }, + { + "name": "DBGEN_DISABLED", + "value": 2, + "description": "Invasive debug in non-secure state disabled" + }, + { + "name": "NIDEN_DBGEN_DISABLED", + "value": 3, + "description": "Non-invasive and invasive debug in non-secure state disabled" + }, + { + "name": "SNIDEN_DISABLED", + "value": 4, + "description": "Secure non-invasive debug disabled, others enabled" + }, + { + "name": "SNIDEN_NIDEN_DISABLED", + "value": 5, + "description": "Secure non-invasive debug and non-secure non-invasive debug disabled" + }, + { + "name": "SNIDEN_DBGEN_DISABLED", + "value": 6, + "description": "Secure non-invasive debug and non-secure invasive debug disabled" + }, + { + "name": "SNIDEN_NIDEN_DBG_DIS", + "value": 7, + "description": "Secure non-invasive, non-invasive, and invasive debug disabled" + }, + { + "name": "SPIDEN_DISABLED", + "value": 8, + "description": "Secure invasive debug disabled, others enabled" + }, + { + "name": "SPIDEN_NIDEN_DISABLED", + "value": 9, + "description": "Secure invasive debug and non-secure non-invasive debug disabled" + }, + { + "name": "SPIDEN_DBGEN_DISABLED", + "value": 10, + "description": "Secure invasive debug and non-secure invasive debug disabled" + }, + { + "name": "SPIDEN_NIDEN_DBG_DIS", + "value": 11, + "description": "Secure invasive, non-invasive, and invasive debug disabled" + }, + { + "name": "SPIDEN_SNIDEN_DISABLED", + "value": 12, + "description": "Secure invasive and secure non-invasive debug disabled" + }, + { + "name": "SECURE_DBG_NIDEN_DIS", + "value": 13, + "description": "All secure debug and non-secure non-invasive debug disabled" + }, + { + "name": "SECURE_DBG_DBGEN_DIS", + "value": 14, + "description": "All secure debug and non-secure invasive debug disabled" + }, + { + "name": "ALL_DEBUG_DISABLED", + "value": 15, + "description": "All debug features disabled (spiden, sniden, dbgen, niden all disabled)" + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse57-bit-8", + "name": "SJC_DISABLE", + "description": "Hardware disablement of SJC. Disables JTAG debugger, including ability for boundary scan.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "SJC is enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "SJC is disabled" + } + ] + }, + { + "width": 7 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse58", + "name": "ELE_MISC_CTRL2", + "description": "OEM controlled Fuse.", + "index_int": "0x003A", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse58-bits-6-7", + "name": "OEM_GDET_DISABLE", + "description": "OEM GDET DISABLE", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Disable ELE-AP Glitch detector. This bit should only be set if security is not of concern. This bit can only be set in OEM OPEN" + }, + { + "name": "DISABLED", + "value": 1, + "description": "ELE-AP Glitch detector is enabled (default secure state)" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-8", + "name": "SOC_GLBL_DBG_DISABLE", + "description": "SOC GLBL DBG DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Global JTAG disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Global JTAG enable" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-10", + "name": "TZ_GLBL_DBG_DISABLE", + "description": "TZ GLBL DBG DISABLE" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-12", + "name": "OEM_FDET_DISABLE", + "description": "OEM FDET DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "ELE-AP Frequency detectors are enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Disable ELE-AP Frequency detectors. This bit can only be set in OEM OPEN" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "Reserved59", + "name": "Reserved 0x3B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003B", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse60", + "name": "ELE_MISC_CTRL4", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003C", + "reg_width": 16, + "bitfields": [ + { + "width": 12, + "id": "fuse60-bits-0-11", + "name": "EXPORT_CONTROL", + "description": "Each fuse disables the following : \n[11] : Reserved for NXP\n[10] : Reserved for NXP\n[9] : Reserved\n[8] : Reserved for ELE-AP\n[7] : CA55 Crypto extension\n[6] : Reserved\n[5] : Reserved\n[4] : OTFADs\n[3:0] : Reserved" + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse61", + "name": "ELE_MISC_CTRL5", + "description": "OEM and NXP controlled.", + "index_int": "0x003D", + "bitfields": [ + { + "width": 1, + "id": "fuse61-bit-0", + "name": "DFT_DISABLE", + "description": "DFT DISABLE", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x3E-0x3F", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved62", + "name": "Reserved 0x3E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003E", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved63", + "name": "Reserved 0x3F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "ELE_SRKH", + "description": "ELE SRK Hash" + }, + "registers": [ + { + "id": "fuse64", + "name": "ELE_SRKH0", + "description": "ELE_SRKH0", + "index_int": "0x0040" + }, + { + "id": "fuse65", + "name": "ELE_SRKH1", + "description": "ELE_SRKH1", + "index_int": "0x0041" + }, + { + "id": "fuse66", + "name": "ELE_SRKH2", + "description": "ELE_SRKH2", + "index_int": "0x0042" + }, + { + "id": "fuse67", + "name": "ELE_SRKH3", + "description": "ELE_SRKH3", + "index_int": "0x0043" + }, + { + "id": "fuse68", + "name": "ELE_SRKH4", + "description": "ELE_SRKH4", + "index_int": "0x0044" + }, + { + "id": "fuse69", + "name": "ELE_SRKH5", + "description": "ELE_SRKH5", + "index_int": "0x0045" + }, + { + "id": "fuse70", + "name": "ELE_SRKH6", + "description": "ELE_SRKH6", + "index_int": "0x0046" + }, + { + "id": "fuse71", + "name": "ELE_SRKH7", + "description": "ELE_SRKH7", + "index_int": "0x0047" + } + ] + }, + { + "group": { + "name": "Reserved 0x48-0x7F", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved72", + "name": "Reserved 0x48", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0048", + "is_reserved": true + }, + { + "id": "Reserved73", + "name": "Reserved 0x49", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0049", + "is_reserved": true + }, + { + "id": "Reserved74", + "name": "Reserved 0x4A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004A", + "is_reserved": true + }, + { + "id": "Reserved75", + "name": "Reserved 0x4B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004B", + "is_reserved": true + }, + { + "id": "Reserved76", + "name": "Reserved 0x4C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004C", + "is_reserved": true + }, + { + "id": "Reserved77", + "name": "Reserved 0x4D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004D", + "is_reserved": true + }, + { + "id": "Reserved78", + "name": "Reserved 0x4E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004E", + "is_reserved": true + }, + { + "id": "Reserved79", + "name": "Reserved 0x4F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004F", + "is_reserved": true + }, + { + "id": "Reserved80", + "name": "Reserved 0x50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0050", + "is_reserved": true + }, + { + "id": "Reserved81", + "name": "Reserved 0x51", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0051", + "is_reserved": true + }, + { + "id": "Reserved82", + "name": "Reserved 0x52", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0052", + "is_reserved": true + }, + { + "id": "Reserved83", + "name": "Reserved 0x53", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0053", + "is_reserved": true + }, + { + "id": "Reserved84", + "name": "Reserved 0x54", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0054", + "is_reserved": true + }, + { + "id": "Reserved85", + "name": "Reserved 0x55", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0055", + "is_reserved": true + }, + { + "id": "Reserved86", + "name": "Reserved 0x56", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0056", + "is_reserved": true + }, + { + "id": "Reserved87", + "name": "Reserved 0x57", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0057", + "is_reserved": true + }, + { + "id": "Reserved88", + "name": "Reserved 0x58", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0058", + "is_reserved": true + }, + { + "id": "Reserved89", + "name": "Reserved 0x59", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0059", + "is_reserved": true + }, + { + "id": "Reserved90", + "name": "Reserved 0x5A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005A", + "is_reserved": true + }, + { + "id": "Reserved91", + "name": "Reserved 0x5B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005B", + "is_reserved": true + }, + { + "id": "Reserved92", + "name": "Reserved 0x5C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005C", + "is_reserved": true + }, + { + "id": "Reserved93", + "name": "Reserved 0x5D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005D", + "is_reserved": true + }, + { + "id": "Reserved94", + "name": "Reserved 0x5E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005E", + "is_reserved": true + }, + { + "id": "Reserved95", + "name": "Reserved 0x5F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005F", + "is_reserved": true + }, + { + "id": "Reserved96", + "name": "Reserved 0x60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0060", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved97", + "name": "Reserved 0x61", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0061", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved98", + "name": "Reserved 0x62", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0062", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved99", + "name": "Reserved 0x63", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. 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Software should not rely on the value.", + "index_int": "0x00B1", + "is_reserved": true + }, + { + "id": "Reserved178", + "name": "Reserved 0xB2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B2", + "is_reserved": true + }, + { + "id": "Reserved179", + "name": "Reserved 0xB3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B3", + "is_reserved": true + }, + { + "id": "Reserved180", + "name": "Reserved 0xB4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B4", + "is_reserved": true + }, + { + "id": "Reserved181", + "name": "Reserved 0xB5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B5", + "is_reserved": true + }, + { + "id": "Reserved182", + "name": "Reserved 0xB6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B6", + "is_reserved": true, + "bitfields": [ + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 15 + } + ] + }, + { + "id": "Reserved183", + "name": "Reserved 0xB7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B7", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "OTFAD1", + "description": "OTFAD configuration" + }, + "registers": [ + { + "id": "fuse184", + "name": "OTFAD1_KEY3", + "description": "On the Fly Decryption module Key bits 127 - 96", + "index_int": "0x00B8", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse185", + "name": "OTFAD1_KEY2", + "description": "On the Fly Decryption module Key bits 95 - 64", + "index_int": "0x00B9", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse186", + "name": "OTFAD1_KEY1", + "description": "On the Fly Decryption module Key bits 63 - 32", + "index_int": "0x00BA", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse187", + "name": "OTFAD1_KEY0", + "description": "On the Fly Decryption module Key bits 31 - 0", + "index_int": "0x00BB", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse188", + "name": "OTFAD1_CFG4", + "description": "On the Fly Decryption module control bits.", + "index_int": "0x00BC", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 3 + }, + { + "width": 1, + "id": "fuse188-bit-3", + "name": "OTFAD1_ENABLE", + "description": "ENABLE OTFAD. ", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse188-bit-4", + "name": "OTFAD1_DISABLE_OVERRIDE", + "description": "OTFAD1 DISABLE OVERRIDE" + }, + { + "width": 1, + "id": "fuse188-bit-5", + "name": "OTFAD1_KEY_BLOB_EN", + "description": "OTFAD1 KEY BLOB EN" + }, + { + "width": 1, + "id": "fuse188-bit-6", + "name": "OTFAD1_KEY_SCRAMBLE_CRC_EN", + "description": "OTFAD1 KEY SCRAMBLE CRC EN" + }, + { + "width": 1, + "id": "fuse188-bit-7", + "name": "OTFAD1_KEY_SCRAMBLE_EN", + "description": "Enable OTFAD Key Scramble ", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 8, + "id": "fuse188-bits-8-15", + "name": "OTFAD1_KEY_SCRAMBLE_ALIGN", + "description": "OTFAD1 KEY SCRAMBLE ALIGN[7:0]" + }, + { + "width": 1, + "id": "fuse188-bit-16", + "name": "OTFAD1_RESTRICT_OTFAD_IPS", + "description": "OTFAD1 RESTRICT OTFAD IPS" + }, + { + "width": 15 + } + ] + }, + { + "id": "fuse189", + "name": "OTFAD1_KEY_SCRAMBLE", + "description": "OTFAD Key Scramble value", + "index_int": "0x00BD", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + } + ] + }, + { + "group": { + "name": "Reserved 0xBE-0x137", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved190", + "name": "Reserved 0xBE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BE", + "is_reserved": true, + "bitfields": [ + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 12 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved191", + "name": "Reserved 0xBF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BF", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved192", + "name": "Reserved 0xC0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C0", + "is_reserved": true + }, + { + "id": "Reserved193", + "name": "Reserved 0xC1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C1", + "is_reserved": true + }, + { + "id": "Reserved194", + "name": "Reserved 0xC2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C2", + "is_reserved": true + }, + { + "id": "Reserved195", + "name": "Reserved 0xC3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C3", + "is_reserved": true + }, + { + "id": "Reserved196", + "name": "Reserved 0xC4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C4", + "is_reserved": true + }, + { + "id": "Reserved197", + "name": "Reserved 0xC5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C5", + "is_reserved": true + }, + { + "id": "Reserved198", + "name": "Reserved 0xC6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C6", + "is_reserved": true + }, + { + "id": "Reserved199", + "name": "Reserved 0xC7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C7", + "is_reserved": true + }, + { + "id": "Reserved200", + "name": "Reserved 0xC8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C8", + "is_reserved": true + }, + { + "id": "Reserved201", + "name": "Reserved 0xC9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C9", + "is_reserved": true + }, + { + "id": "Reserved202", + "name": "Reserved 0xCA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CA", + "is_reserved": true + }, + { + "id": "Reserved203", + "name": "Reserved 0xCB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CB", + "is_reserved": true + }, + { + "id": "Reserved204", + "name": "Reserved 0xCC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CC", + "is_reserved": true + }, + { + "id": "Reserved205", + "name": "Reserved 0xCD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CD", + "is_reserved": true + }, + { + "id": "Reserved206", + "name": "Reserved 0xCE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CE", + "is_reserved": true + }, + { + "id": "Reserved207", + "name": "Reserved 0xCF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CF", + "is_reserved": true + }, + { + "id": "Reserved208", + "name": "Reserved 0xD0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D0", + "is_reserved": true + }, + { + "id": "Reserved209", + "name": "Reserved 0xD1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D1", + "is_reserved": true + }, + { + "id": "Reserved210", + "name": "Reserved 0xD2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D2", + "is_reserved": true + }, + { + "id": "Reserved211", + "name": "Reserved 0xD3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D3", + "is_reserved": true + }, + { + "id": "Reserved212", + "name": "Reserved 0xD4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D4", + "is_reserved": true + }, + { + "id": "Reserved213", + "name": "Reserved 0xD5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D5", + "is_reserved": true + }, + { + "id": "Reserved214", + "name": "Reserved 0xD6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D6", + "is_reserved": true + }, + { + "id": "Reserved215", + "name": "Reserved 0xD7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D7", + "is_reserved": true + }, + { + "id": "Reserved216", + "name": "Reserved 0xD8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D8", + "is_reserved": true + }, + { + "id": "Reserved217", + "name": "Reserved 0xD9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D9", + "is_reserved": true + }, + { + "id": "Reserved218", + "name": "Reserved 0xDA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DA", + "is_reserved": true + }, + { + "id": "Reserved219", + "name": "Reserved 0xDB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DB", + "is_reserved": true + }, + { + "id": "Reserved220", + "name": "Reserved 0xDC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DC", + "is_reserved": true + }, + { + "id": "Reserved221", + "name": "Reserved 0xDD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DD", + "is_reserved": true + }, + { + "id": "Reserved222", + "name": "Reserved 0xDE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DE", + "is_reserved": true + }, + { + "id": "Reserved223", + "name": "Reserved 0xDF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DF", + "is_reserved": true + }, + { + "id": "Reserved224", + "name": "Reserved 0xE0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E0", + "is_reserved": true + }, + { + "id": "Reserved225", + "name": "Reserved 0xE1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E1", + "is_reserved": true + }, + { + "id": "Reserved226", + "name": "Reserved 0xE2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E2", + "is_reserved": true + }, + { + "id": "Reserved227", + "name": "Reserved 0xE3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E3", + "is_reserved": true + }, + { + "id": "Reserved228", + "name": "Reserved 0xE4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E4", + "is_reserved": true + }, + { + "id": "Reserved229", + "name": "Reserved 0xE5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E5", + "is_reserved": true + }, + { + "id": "Reserved230", + "name": "Reserved 0xE6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E6", + "is_reserved": true + }, + { + "id": "Reserved231", + "name": "Reserved 0xE7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E7", + "is_reserved": true + }, + { + "id": "Reserved232", + "name": "Reserved 0xE8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E8", + "is_reserved": true + }, + { + "id": "Reserved233", + "name": "Reserved 0xE9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E9", + "is_reserved": true + }, + { + "id": "Reserved234", + "name": "Reserved 0xEA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EA", + "is_reserved": true + }, + { + "id": "Reserved235", + "name": "Reserved 0xEB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EB", + "is_reserved": true + }, + { + "id": "Reserved236", + "name": "Reserved 0xEC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EC", + "is_reserved": true + }, + { + "id": "Reserved237", + "name": "Reserved 0xED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00ED", + "is_reserved": true + }, + { + "id": "Reserved238", + "name": "Reserved 0xEE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EE", + "is_reserved": true + }, + { + "id": "Reserved239", + "name": "Reserved 0xEF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EF", + "is_reserved": true + }, + { + "id": "Reserved240", + "name": "Reserved 0xF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F0", + "is_reserved": true + }, + { + "id": "Reserved241", + "name": "Reserved 0xF1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F1", + "is_reserved": true + }, + { + "id": "Reserved242", + "name": "Reserved 0xF2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F2", + "is_reserved": true + }, + { + "id": "Reserved243", + "name": "Reserved 0xF3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F3", + "is_reserved": true + }, + { + "id": "Reserved244", + "name": "Reserved 0xF4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F4", + "is_reserved": true + }, + { + "id": "Reserved245", + "name": "Reserved 0xF5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F5", + "is_reserved": true + }, + { + "id": "Reserved246", + "name": "Reserved 0xF6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F6", + "is_reserved": true + }, + { + "id": "Reserved247", + "name": "Reserved 0xF7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F7", + "is_reserved": true + }, + { + "id": "Reserved248", + "name": "Reserved 0xF8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F8", + "is_reserved": true + }, + { + "id": "Reserved249", + "name": "Reserved 0xF9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F9", + "is_reserved": true + }, + { + "id": "Reserved250", + "name": "Reserved 0xFA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FA", + "is_reserved": true + }, + { + "id": "Reserved251", + "name": "Reserved 0xFB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FB", + "is_reserved": true + }, + { + "id": "Reserved252", + "name": "Reserved 0xFC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FC", + "is_reserved": true + }, + { + "id": "Reserved253", + "name": "Reserved 0xFD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FD", + "is_reserved": true + }, + { + "id": "Reserved254", + "name": "Reserved 0xFE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FE", + "is_reserved": true + }, + { + "id": "Reserved255", + "name": "Reserved 0xFF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FF", + "is_reserved": true + }, + { + "id": "Reserved256", + "name": "Reserved 0x100", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0100", + "is_reserved": true + }, + { + "id": "Reserved257", + "name": "Reserved 0x101", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0101", + "is_reserved": true + }, + { + "id": "Reserved258", + "name": "Reserved 0x102", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0102", + "is_reserved": true + }, + { + "id": "Reserved259", + "name": "Reserved 0x103", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0103", + "is_reserved": true + }, + { + "id": "Reserved260", + "name": "Reserved 0x104", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0104", + "is_reserved": true + }, + { + "id": "Reserved261", + "name": "Reserved 0x105", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0105", + "is_reserved": true + }, + { + "id": "Reserved262", + "name": "Reserved 0x106", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0106", + "is_reserved": true + }, + { + "id": "Reserved263", + "name": "Reserved 0x107", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0107", + "is_reserved": true + }, + { + "id": "Reserved264", + "name": "Reserved 0x108", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0108", + "is_reserved": true + }, + { + "id": "Reserved265", + "name": "Reserved 0x109", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0109", + "is_reserved": true + }, + { + "id": "Reserved266", + "name": "Reserved 0x10A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010A", + "is_reserved": true + }, + { + "id": "Reserved267", + "name": "Reserved 0x10B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010B", + "is_reserved": true + }, + { + "id": "Reserved268", + "name": "Reserved 0x10C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010C", + "is_reserved": true + }, + { + "id": "Reserved269", + "name": "Reserved 0x10D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010D", + "is_reserved": true + }, + { + "id": "Reserved270", + "name": "Reserved 0x10E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010E", + "is_reserved": true + }, + { + "id": "Reserved271", + "name": "Reserved 0x10F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010F", + "is_reserved": true + }, + { + "id": "Reserved272", + "name": "Reserved 0x110", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0110", + "is_reserved": true + }, + { + "id": "Reserved273", + "name": "Reserved 0x111", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0111", + "is_reserved": true + }, + { + "id": "Reserved274", + "name": "Reserved 0x112", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0112", + "is_reserved": true + }, + { + "id": "Reserved275", + "name": "Reserved 0x113", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0113", + "is_reserved": true + }, + { + "id": "Reserved276", + "name": "Reserved 0x114", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0114", + "is_reserved": true + }, + { + "id": "Reserved277", + "name": "Reserved 0x115", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0115", + "is_reserved": true + }, + { + "id": "Reserved278", + "name": "Reserved 0x116", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0116", + "is_reserved": true + }, + { + "id": "Reserved279", + "name": "Reserved 0x117", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0117", + "is_reserved": true + }, + { + "id": "Reserved280", + "name": "Reserved 0x118", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0118", + "is_reserved": true + }, + { + "id": "Reserved281", + "name": "Reserved 0x119", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0119", + "is_reserved": true + }, + { + "id": "Reserved282", + "name": "Reserved 0x11A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011A", + "is_reserved": true + }, + { + "id": "Reserved283", + "name": "Reserved 0x11B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011B", + "is_reserved": true + }, + { + "id": "Reserved284", + "name": "Reserved 0x11C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011C", + "is_reserved": true + }, + { + "id": "Reserved285", + "name": "Reserved 0x11D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011D", + "is_reserved": true + }, + { + "id": "Reserved286", + "name": "Reserved 0x11E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011E", + "is_reserved": true + }, + { + "id": "Reserved287", + "name": "Reserved 0x11F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011F", + "is_reserved": true + }, + { + "id": "Reserved288", + "name": "Reserved 0x120", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0120", + "is_reserved": true + }, + { + "id": "Reserved289", + "name": "Reserved 0x121", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0121", + "is_reserved": true + }, + { + "id": "Reserved290", + "name": "Reserved 0x122", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0122", + "is_reserved": true + }, + { + "id": "Reserved291", + "name": "Reserved 0x123", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0123", + "is_reserved": true + }, + { + "id": "Reserved292", + "name": "Reserved 0x124", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0124", + "is_reserved": true + }, + { + "id": "Reserved293", + "name": "Reserved 0x125", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0125", + "is_reserved": true + }, + { + "id": "Reserved294", + "name": "Reserved 0x126", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0126", + "is_reserved": true + }, + { + "id": "Reserved295", + "name": "Reserved 0x127", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0127", + "is_reserved": true + }, + { + "id": "Reserved296", + "name": "Reserved 0x128", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0128", + "is_reserved": true + }, + { + "id": "Reserved297", + "name": "Reserved 0x129", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0129", + "is_reserved": true + }, + { + "id": "Reserved298", + "name": "Reserved 0x12A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012A", + "is_reserved": true + }, + { + "id": "Reserved299", + "name": "Reserved 0x12B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012B", + "is_reserved": true + }, + { + "id": "Reserved300", + "name": "Reserved 0x12C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012C", + "is_reserved": true + }, + { + "id": "Reserved301", + "name": "Reserved 0x12D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012D", + "is_reserved": true + }, + { + "id": "Reserved302", + "name": "Reserved 0x12E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012E", + "is_reserved": true + }, + { + "id": "Reserved303", + "name": "Reserved 0x12F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012F", + "is_reserved": true + }, + { + "id": "Reserved304", + "name": "Reserved 0x130", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0130", + "is_reserved": true + }, + { + "id": "Reserved305", + "name": "Reserved 0x131", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0131", + "is_reserved": true + }, + { + "id": "Reserved306", + "name": "Reserved 0x132", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0132", + "is_reserved": true + }, + { + "id": "Reserved307", + "name": "Reserved 0x133", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0133", + "is_reserved": true + }, + { + "id": "Reserved308", + "name": "Reserved 0x134", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0134", + "is_reserved": true + }, + { + "id": "Reserved309", + "name": "Reserved 0x135", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0135", + "is_reserved": true + }, + { + "id": "Reserved310", + "name": "Reserved 0x136", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0136", + "is_reserved": true + }, + { + "id": "Reserved311", + "name": "Reserved 0x137", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0137", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "COM_DEVICE_ID_CFG", + "description": "Device communication config" + }, + "registers": [ + { + "id": "fuse312", + "name": "COM_DEVICE_ID_CFG0", + "description": "COM_DEVICE_ID_CFG0", + "index_int": "0x0138", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse312-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse312-bits-16-31", + "name": "USB1_PID", + "description": "USB1 Product ID" + } + ] + }, + { + "id": "fuse313", + "name": "COM_DEVICE_ID_CFG1", + "description": "COM_DEVICE_ID_CFG1", + "index_int": "0x0139", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse313-bits-0-15", + "name": "USB2_PID", + "description": "USB2 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved314", + "name": "Reserved 0x13A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013A", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse315", + "name": "COM_DEVICE_ID_CFG3", + "description": "COM_DEVICE_ID_CFG3", + "index_int": "0x013B", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse315-bits-0-31", + "name": "MAC1_ADDR_31_0", + "description": "MAC_1 Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse316", + "name": "COM_DEVICE_ID_CFG4", + "description": "COM_DEVICE_ID_CFG4", + "index_int": "0x013C", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse316-bits-0-15", + "name": "MAC1_ADDR_47_32", + "description": "MAC_1 Address. Reserved for customer SW" + }, + { + "width": 16, + "id": "fuse316-bits-16-31", + "name": "MAC2_ADDR_15_0", + "description": "MAC_2 Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse317", + "name": "COM_DEVICE_ID_CFG5", + "description": "COM_DEVICE_ID_CFG5", + "index_int": "0x013D", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse317-bits-0-31", + "name": "MAC2_ADDR_47_16", + "description": "MAC_2 Address. Reserved for customer SW" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x13E-0x146", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved318", + "name": "Reserved 0x13E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved319", + "name": "Reserved 0x13F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013F", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved320", + "name": "Reserved 0x140", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0140", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved321", + "name": "Reserved 0x141", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0141", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved322", + "name": "Reserved 0x142", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0142", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved323", + "name": "Reserved 0x143", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0143", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved324", + "name": "Reserved 0x144", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0144", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved325", + "name": "Reserved 0x145", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0145", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved326", + "name": "Reserved 0x146", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0146", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "OEM_SW_CFG", + "description": "OEM software configuration" + }, + "registers": [ + { + "id": "fuse327", + "name": "OEM_SW_CFG", + "description": "OEM Software Configuration", + "index_int": "0x0147", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Reserved 0x148-0x177", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved328", + "name": "Reserved 0x148", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0148", + "is_reserved": true + }, + { + "id": "Reserved329", + "name": "Reserved 0x149", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0149", + "is_reserved": true + }, + { + "id": "Reserved330", + "name": "Reserved 0x14A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014A", + "is_reserved": true + }, + { + "id": "Reserved331", + "name": "Reserved 0x14B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014B", + "is_reserved": true + }, + { + "id": "Reserved332", + "name": "Reserved 0x14C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014C", + "is_reserved": true + }, + { + "id": "Reserved333", + "name": "Reserved 0x14D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014D", + "is_reserved": true + }, + { + "id": "Reserved334", + "name": "Reserved 0x14E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014E", + "is_reserved": true + }, + { + "id": "Reserved335", + "name": "Reserved 0x14F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014F", + "is_reserved": true + }, + { + "id": "Reserved336", + "name": "Reserved 0x150", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0150", + "is_reserved": true + }, + { + "id": "Reserved337", + "name": "Reserved 0x151", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0151", + "is_reserved": true + }, + { + "id": "Reserved338", + "name": "Reserved 0x152", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0152", + "is_reserved": true + }, + { + "id": "Reserved339", + "name": "Reserved 0x153", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0153", + "is_reserved": true + }, + { + "id": "Reserved340", + "name": "Reserved 0x154", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0154", + "is_reserved": true + }, + { + "id": "Reserved341", + "name": "Reserved 0x155", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0155", + "is_reserved": true + }, + { + "id": "Reserved342", + "name": "Reserved 0x156", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0156", + "is_reserved": true + }, + { + "id": "Reserved343", + "name": "Reserved 0x157", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0157", + "is_reserved": true + }, + { + "id": "Reserved344", + "name": "Reserved 0x158", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0158", + "is_reserved": true + }, + { + "id": "Reserved345", + "name": "Reserved 0x159", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0159", + "is_reserved": true + }, + { + "id": "Reserved346", + "name": "Reserved 0x15A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015A", + "is_reserved": true + }, + { + "id": "Reserved347", + "name": "Reserved 0x15B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015B", + "is_reserved": true + }, + { + "id": "Reserved348", + "name": "Reserved 0x15C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015C", + "is_reserved": true + }, + { + "id": "Reserved349", + "name": "Reserved 0x15D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015D", + "is_reserved": true + }, + { + "id": "Reserved350", + "name": "Reserved 0x15E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015E", + "is_reserved": true + }, + { + "id": "Reserved351", + "name": "Reserved 0x15F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015F", + "is_reserved": true + }, + { + "id": "Reserved352", + "name": "Reserved 0x160", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0160", + "is_reserved": true + }, + { + "id": "Reserved353", + "name": "Reserved 0x161", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0161", + "is_reserved": true + }, + { + "id": "Reserved354", + "name": "Reserved 0x162", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0162", + "is_reserved": true + }, + { + "id": "Reserved355", + "name": "Reserved 0x163", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0163", + "is_reserved": true + }, + { + "id": "Reserved356", + "name": "Reserved 0x164", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0164", + "is_reserved": true + }, + { + "id": "Reserved357", + "name": "Reserved 0x165", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0165", + "is_reserved": true + }, + { + "id": "Reserved358", + "name": "Reserved 0x166", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0166", + "is_reserved": true + }, + { + "id": "Reserved359", + "name": "Reserved 0x167", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0167", + "is_reserved": true + }, + { + "id": "Reserved360", + "name": "Reserved 0x168", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0168", + "is_reserved": true + }, + { + "id": "Reserved361", + "name": "Reserved 0x169", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0169", + "is_reserved": true + }, + { + "id": "Reserved362", + "name": "Reserved 0x16A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016A", + "is_reserved": true + }, + { + "id": "Reserved363", + "name": "Reserved 0x16B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016B", + "is_reserved": true + }, + { + "id": "Reserved364", + "name": "Reserved 0x16C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016C", + "is_reserved": true + }, + { + "id": "Reserved365", + "name": "Reserved 0x16D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016D", + "is_reserved": true + }, + { + "id": "Reserved366", + "name": "Reserved 0x16E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016E", + "is_reserved": true + }, + { + "id": "Reserved367", + "name": "Reserved 0x16F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016F", + "is_reserved": true + }, + { + "id": "Reserved368", + "name": "Reserved 0x170", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0170", + "is_reserved": true + }, + { + "id": "Reserved369", + "name": "Reserved 0x171", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0171", + "is_reserved": true + }, + { + "id": "Reserved370", + "name": "Reserved 0x172", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0172", + "is_reserved": true + }, + { + "id": "Reserved371", + "name": "Reserved 0x173", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0173", + "is_reserved": true + }, + { + "id": "Reserved372", + "name": "Reserved 0x174", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0174", + "is_reserved": true + }, + { + "id": "Reserved373", + "name": "Reserved 0x175", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0175", + "is_reserved": true + }, + { + "id": "Reserved374", + "name": "Reserved 0x176", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0176", + "is_reserved": true + }, + { + "id": "Reserved375", + "name": "Reserved 0x177", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0177", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "GPR2_CFG", + "description": "General purpose fuse 2" + }, + "registers": [ + { + "id": "fuse376", + "name": "GPR2_CFG0", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x0178" + }, + { + "id": "fuse377", + "name": "GPR2_CFG1", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x0179", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse378", + "name": "GPR2_CFG2", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse379", + "name": "GPR2_CFG3", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017B" + }, + { + "id": "fuse380", + "name": "GPR2_CFG4", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse381", + "name": "GPR2_CFG5", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017D" + }, + { + "id": "fuse382", + "name": "GPR2_CFG6", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017E" + }, + { + "id": "fuse383", + "name": "GPR2_CFG7", + "description": "OEM Reserved - General Purpose Fuse 2", + "index_int": "0x017F" + } + ] + }, + { + "group": { + "name": "GPR3_CFG", + "description": "General purpose fuse 3" + }, + "registers": [ + { + "id": "fuse384", + "name": "GPR3_CFG0", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0180" + }, + { + "id": "fuse385", + "name": "GPR3_CFG1", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0181", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse386", + "name": "GPR3_CFG2", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0182" + }, + { + "id": "fuse387", + "name": "GPR3_CFG3", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0183" + }, + { + "id": "fuse388", + "name": "GPR3_CFG4", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0184" + }, + { + "id": "fuse389", + "name": "GPR3_CFG5", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0185" + }, + { + "id": "fuse390", + "name": "GPR3_CFG6", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0186" + }, + { + "id": "fuse391", + "name": "GPR3_CFG7", + "description": "OEM Reserved - General Purpose Fuse 3", + "index_int": "0x0187" + } + ] + }, + { + "group": { + "name": "GPR4_CFG", + "description": "General purpose fuse 4" + }, + "registers": [ + { + "id": "fuse392", + "name": "GPR4_CFG0", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x0188" + }, + { + "id": "fuse393", + "name": "GPR4_CFG1", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x0189" + }, + { + "id": "fuse394", + "name": "GPR4_CFG2", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018A" + }, + { + "id": "fuse395", + "name": "GPR4_CFG3", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018B" + }, + { + "id": "fuse396", + "name": "GPR4_CFG4", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse397", + "name": "GPR4_CFG5", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018D" + }, + { + "id": "fuse398", + "name": "GPR4_CFG6", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018E" + }, + { + "id": "fuse399", + "name": "GPR4_CFG7", + "description": "OEM Reserved - General Purpose Fuse 4", + "index_int": "0x018F" + } + ] + }, + { + "group": { + "name": "Reserved 0x190-0x1FF", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved400", + "name": "Reserved 0x190", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0190", + "is_reserved": true + }, + { + "id": "Reserved401", + "name": "Reserved 0x191", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0191", + "is_reserved": true + }, + { + "id": "Reserved402", + "name": "Reserved 0x192", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0192", + "is_reserved": true + }, + { + "id": "Reserved403", + "name": "Reserved 0x193", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0193", + "is_reserved": true + }, + { + "id": "Reserved404", + "name": "Reserved 0x194", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0194", + "is_reserved": true + }, + { + "id": "Reserved405", + "name": "Reserved 0x195", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0195", + "is_reserved": true + }, + { + "id": "Reserved406", + "name": "Reserved 0x196", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0196", + "is_reserved": true + }, + { + "id": "Reserved407", + "name": "Reserved 0x197", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0197", + "is_reserved": true + }, + { + "id": "Reserved408", + "name": "Reserved 0x198", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0198", + "is_reserved": true + }, + { + "id": "Reserved409", + "name": "Reserved 0x199", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0199", + "is_reserved": true + }, + { + "id": "Reserved410", + "name": "Reserved 0x19A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019A", + "is_reserved": true + }, + { + "id": "Reserved411", + "name": "Reserved 0x19B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019B", + "is_reserved": true + }, + { + "id": "Reserved412", + "name": "Reserved 0x19C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019C", + "is_reserved": true + }, + { + "id": "Reserved413", + "name": "Reserved 0x19D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019D", + "is_reserved": true + }, + { + "id": "Reserved414", + "name": "Reserved 0x19E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019E", + "is_reserved": true + }, + { + "id": "Reserved415", + "name": "Reserved 0x19F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x019F", + "is_reserved": true + }, + { + "id": "Reserved416", + "name": "Reserved 0x1A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A0", + "is_reserved": true + }, + { + "id": "Reserved417", + "name": "Reserved 0x1A1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A1", + "is_reserved": true + }, + { + "id": "Reserved418", + "name": "Reserved 0x1A2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A2", + "is_reserved": true + }, + { + "id": "Reserved419", + "name": "Reserved 0x1A3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A3", + "is_reserved": true + }, + { + "id": "Reserved420", + "name": "Reserved 0x1A4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A4", + "is_reserved": true + }, + { + "id": "Reserved421", + "name": "Reserved 0x1A5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A5", + "is_reserved": true + }, + { + "id": "Reserved422", + "name": "Reserved 0x1A6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A6", + "is_reserved": true + }, + { + "id": "Reserved423", + "name": "Reserved 0x1A7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A7", + "is_reserved": true + }, + { + "id": "Reserved424", + "name": "Reserved 0x1A8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A8", + "is_reserved": true + }, + { + "id": "Reserved425", + "name": "Reserved 0x1A9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A9", + "is_reserved": true + }, + { + "id": "Reserved426", + "name": "Reserved 0x1AA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AA", + "is_reserved": true + }, + { + "id": "Reserved427", + "name": "Reserved 0x1AB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AB", + "is_reserved": true + }, + { + "id": "Reserved428", + "name": "Reserved 0x1AC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AC", + "is_reserved": true + }, + { + "id": "Reserved429", + "name": "Reserved 0x1AD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AD", + "is_reserved": true + }, + { + "id": "Reserved430", + "name": "Reserved 0x1AE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AE", + "is_reserved": true + }, + { + "id": "Reserved431", + "name": "Reserved 0x1AF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AF", + "is_reserved": true + }, + { + "id": "Reserved432", + "name": "Reserved 0x1B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B0", + "is_reserved": true + }, + { + "id": "Reserved433", + "name": "Reserved 0x1B1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B1", + "is_reserved": true + }, + { + "id": "Reserved434", + "name": "Reserved 0x1B2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B2", + "is_reserved": true + }, + { + "id": "Reserved435", + "name": "Reserved 0x1B3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B3", + "is_reserved": true + }, + { + "id": "Reserved436", + "name": "Reserved 0x1B4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B4", + "is_reserved": true + }, + { + "id": "Reserved437", + "name": "Reserved 0x1B5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B5", + "is_reserved": true + }, + { + "id": "Reserved438", + "name": "Reserved 0x1B6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B6", + "is_reserved": true + }, + { + "id": "Reserved439", + "name": "Reserved 0x1B7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B7", + "is_reserved": true + }, + { + "id": "Reserved440", + "name": "Reserved 0x1B8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B8", + "is_reserved": true + }, + { + "id": "Reserved441", + "name": "Reserved 0x1B9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B9", + "is_reserved": true + }, + { + "id": "Reserved442", + "name": "Reserved 0x1BA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BA", + "is_reserved": true + }, + { + "id": "Reserved443", + "name": "Reserved 0x1BB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BB", + "is_reserved": true + }, + { + "id": "Reserved444", + "name": "Reserved 0x1BC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BC", + "is_reserved": true + }, + { + "id": "Reserved445", + "name": "Reserved 0x1BD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BD", + "is_reserved": true + }, + { + "id": "Reserved446", + "name": "Reserved 0x1BE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BE", + "is_reserved": true + }, + { + "id": "Reserved447", + "name": "Reserved 0x1BF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BF", + "is_reserved": true + }, + { + "id": "Reserved448", + "name": "Reserved 0x1C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C0", + "is_reserved": true + }, + { + "id": "Reserved449", + "name": "Reserved 0x1C1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C1", + "is_reserved": true + }, + { + "id": "Reserved450", + "name": "Reserved 0x1C2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C2", + "is_reserved": true + }, + { + "id": "Reserved451", + "name": "Reserved 0x1C3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C3", + "is_reserved": true + }, + { + "id": "Reserved452", + "name": "Reserved 0x1C4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C4", + "is_reserved": true + }, + { + "id": "Reserved453", + "name": "Reserved 0x1C5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C5", + "is_reserved": true + }, + { + "id": "Reserved454", + "name": "Reserved 0x1C6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C6", + "is_reserved": true + }, + { + "id": "Reserved455", + "name": "Reserved 0x1C7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C7", + "is_reserved": true + }, + { + "id": "Reserved456", + "name": "Reserved 0x1C8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C8", + "is_reserved": true + }, + { + "id": "Reserved457", + "name": "Reserved 0x1C9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01C9", + "is_reserved": true + }, + { + "id": "Reserved458", + "name": "Reserved 0x1CA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CA", + "is_reserved": true + }, + { + "id": "Reserved459", + "name": "Reserved 0x1CB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CB", + "is_reserved": true + }, + { + "id": "Reserved460", + "name": "Reserved 0x1CC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CC", + "is_reserved": true + }, + { + "id": "Reserved461", + "name": "Reserved 0x1CD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CD", + "is_reserved": true + }, + { + "id": "Reserved462", + "name": "Reserved 0x1CE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CE", + "is_reserved": true + }, + { + "id": "Reserved463", + "name": "Reserved 0x1CF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01CF", + "is_reserved": true + }, + { + "id": "Reserved464", + "name": "Reserved 0x1D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D0", + "is_reserved": true + }, + { + "id": "Reserved465", + "name": "Reserved 0x1D1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D1", + "is_reserved": true + }, + { + "id": "Reserved466", + "name": "Reserved 0x1D2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D2", + "is_reserved": true + }, + { + "id": "Reserved467", + "name": "Reserved 0x1D3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D3", + "is_reserved": true + }, + { + "id": "Reserved468", + "name": "Reserved 0x1D4", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FB", + "is_reserved": true + }, + { + "id": "Reserved508", + "name": "Reserved 0x1FC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FC", + "is_reserved": true + }, + { + "id": "Reserved509", + "name": "Reserved 0x1FD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FD", + "is_reserved": true + }, + { + "id": "Reserved510", + "name": "Reserved 0x1FE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FE", + "is_reserved": true + }, + { + "id": "Reserved511", + "name": "Reserved 0x1FF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FF", + "is_reserved": true + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/database.yaml new file mode 100644 index 0000000..8788f70 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/database.yaml @@ -0,0 +1,408 @@ +# Copyright 2024-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx943 + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX94 + memory_map: + code-tcm_ns: + start_int: 0x0FF80000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + code-tcm_s: + start_int: 0x1FF80000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + system-tcm_ns: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + system-tcm_s: + start_int: 0x30000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_itcm_ns: + start_int: 0x20380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_itcm_s: + start_int: 0x30380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_ns: + start_int: 0x20400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_s: + start_int: 0x30400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram_ns: + start_int: 0x20480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x30480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + neutron_sram_ns: + start_int: 0x4AA00000 + size_int: 0x00100000 + external: false + mirror_of: neutron_sram_s + non_xip_type: int_ram + neutron_sram_s: + start_int: 0x5AA00000 + size_int: 0x00100000 + external: false + non_xip_type: int_ram + dram1_ns: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram1_s: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_ns: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_s: + start_int: 0xB0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_ns: + start_int: 0xC0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_s: + start_int: 0xD0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + isp: + rom: + protocol: sdps + interfaces: [usb] + usb: + - vid: 0x1FC9 + pid: 0x0027 + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: srkh + name: SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse608", + "fuse609", + "fuse610", + "fuse611", + "fuse612", + "fuse613", + "fuse614", + "fuse615", + "fuse616", + "fuse617", + "fuse618", + "fuse619", + "fuse620", + "fuse621", + "fuse622", + "fuse623", + ] + - uid: pqc_srkh + name: PQC_SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse624", + "fuse625", + "fuse626", + "fuse627", + "fuse628", + "fuse629", + "fuse630", + "fuse631", + "fuse632", + "fuse633", + "fuse634", + "fuse635", + "fuse636", + "fuse637", + "fuse638", + "fuse639", + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x9380_0000 + size: 0x30000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab_v2" + + # ======== DAT section ======== + dat: + socc: 0x4D5803AF # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + ele_cnt_version: 2 # DAT container is based on New AHAB container version 2 + dac_version_is_swapped: True + auth_beacon_length: 4 # The length in bytes of authentication beacon + sub_features: ["ele_pqc"] + test_address: 0x2048_0000 + dmbox_ap_ix: 0 + dac_rot_type: not_available # The Dac packet doesn't contains the ROT hash + + # ======== FCB section ======== + # fcb: + # mem_types: {} + + # ======== AHAB section ======== + ahab: + sub_features: [ahab_image, certificate_supported] + fuses_0: + _name: "AHAB SRKH" + srkh: "__srk_hash0" # SRK hash fuse + fuses_1: + _name: "AHAB SRKH PQC" + pqc_srkh: "__srk_hash1" # SRK PQC hash fuse + containers_max_cnt: 3 + valid_offset_minimal_alignment: 0x400 + container_types: [2] # Supported container types + core_ids: + DUMMY_CORE: [0, "dummy", "Virtual dummy core (used for data)"] + CORTEX_M33: [1, "cortex-m33", "Cortex M33 - Boot core"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + ELE: [6, "ele", "EdgeLock Enclave"] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + CORTEX_M7_1: [11, "cortex-m7-1", "Cortex M7 Core ID 1"] + CORTEX_M7_2: [12, "cortex-m7-2", "Functional Safety Cortex M7"] + CORTEX_M33_2: [13, "cortex-m33-2", "Functional Safety Cortex M33"] + DDR: [14, "ddr", "DDR Core"] + + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + OEI: [0x05, oei, OEI Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION_FCB_CHK: + [0x08, dek_validation_fcb_chk, DEK validation FCB check Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + EXECUTABLE_FAST_BOOT_IMAGE: + [0x0A, executable_fast_boot_image, Executable fast boot Image] + OEI_DDR: [0x0D, oei_ddr, Executable boot Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + ele: + ELE_AS_IMAGE: [0x05, ele_as_image, EdgeLock Enclave Image in OEM Image] + ELE: [0x06, ele, EdgeLock Enclave Image] + v2x: + V2X_AS_IMAGE: [0x0A, v2x_as_image, V2X image as OEM Image] + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + oei_ddr_load_address: 0x1ffc0000 + oei_ddr_entry_point: 0x1ffc0001 + oei_ddr_core_id: cortex-m33 + oei_ddr_image_type: oei + oei_ddr_image_size_alignment: 0x400 + oei_ddr_qb_data_mandatory: True + # oei_ddr_gap_after_image: 0x10000 + + oei_tcm_load_address: 0x1ffc0000 + oei_tcm_entry_point: 0x1ffc0001 + oei_tcm_core_id: cortex-m33 + oei_tcm_image_type: oei + oei_tcm_image_size_alignment: 0x400 + + system_manager_load_address: 0x1ffc0000 + system_manager_entry_point: 0x1ffc0000 + system_manager_core_id: cortex-m33 + system_manager_image_size_alignment: 0x400 + + cortex_m7_app_load_address: 0x303c0000 + cortex_m7_app_entry_point: 0 + cortex_m7_app_core_id: cortex-m7-1 + cortex_m7_app_meta_data_start_cpu_id: 1 + cortex_m7_app_image_size_alignment: 0x400 + + cortex_m7_2_app_load_address: 0x302C0000 + cortex_m7_2_app_entry_point: 0 + cortex_m7_2_app_core_id: cortex-m7-2 + cortex_m7_2_app_meta_data_start_cpu_id: 7 + cortex_m7_2_app_image_size_alignment: 0x400 + + cortex_m33_2_app_load_address: 0x309c0000 + cortex_m33_2_app_entry_point: 0x1ffc0000 + cortex_m33_2_app_core_id: cortex-m33-2 + cortex_m33_2_app_meta_data_start_cpu_id: 8 + cortex_m33_2_app_image_size_alignment: 0x400 + + spl_load_address: 0x20480000 + spl_core_id: cortex-a55 + spl_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + atf_load_address: 0x8a200000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x90200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x8c000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + kernel_load_address: 0x90400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 2 + kernel_chunk_size: 0x700000 + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x93000000 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_entry_point: 0x0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: + [ + double_authentication, + oei_ddr, + oei_tcm, + system_manager, + cortex_m7_app, + cortex_m7_2_app, + cortex_m33_2_app, + spl, + atf, + uboot, + tee, + kernel, + dtb, + ] + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc_boot: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + # flexspi_nand: + # segments: + # xmcd: 0x00 + # primary_image_container_set: 0x400 + # secondary_image_container_set_ahab: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI1/2for Low power boot and LPSPI/3/4 for Single boot. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # # ======== OTFAD section ======== + # otfad: + + # # ======== Device Hardware Security Module (HSM) section ======== + # devhsm: EdgeLock 2 Go + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x9280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} + + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/fuses.json new file mode 100644 index 0000000..7bcfddc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx943/fuses.json @@ -0,0 +1,12918 @@ +{ + "cpu": "MIMX943", + "groups": [ + { + "group": { + "name": "General", + "description": "General settings configuration" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-6-8", + "name": "HSW_CFG_LOCK", + "description": "Hardware and Software Configuration Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "Write Protect, the controlled field can not be burned" + }, + { + "name": "OP", + "value": 2, + "description": "Over-ride Protect, the controlled field shadow registers can not be over-written" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written" + }, + { + "name": "RP", + "value": 4, + "description": "Read Protect, the controlled field can be sensed only, but can't be read from shadow registers" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned" + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks - the controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "ELE_MISC1_LOCK", + "description": "Misc. Config lock 1 - Used to lock OEM owned configuration fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-6-8", + "name": "ELE_IPED1_KEY_LOCK", + "description": "IPED1 config lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved3", + "name": "Reserved 0x3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0003", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-12-14", + "name": "ELE_OEM_SRKH_LOCK", + "description": "OEM SRK Hash Lock ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0005", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse6", + "name": "LOCK_CFG6", + "description": "LOCK_CFG6", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse6-bits-0-2", + "name": "ELE_OEM_KEY_PROP_LOCK", + "description": "OEM Key Prop Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse6-bits-3-5", + "name": "ELE_UNIQ_ID_LOCK", + "description": "EdgeLock Enclave Unique ID Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "Write Protect, the controlled field can not be burned" + }, + { + "name": "OP", + "value": 2, + "description": "Over-ride Protect, the controlled field shadow registers can not be over-written" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Over-ride + Write Protect, the controlled field can not be overridden nor burned" + }, + { + "name": "RP", + "value": 4, + "description": "Read Protect, the controlled field can be sensed only, but can't be read from shadow registers" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned" + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register" + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse7", + "name": "LOCK_CFG7", + "description": "LOCK_CFG7", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse7-bits-6-8", + "name": "BOOT_CFG_LOCK", + "description": "Boot config lock - first set (BOOT_CFG0-7)", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read nor burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read nor over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-9-11", + "name": "BOOT2_CFG_LOCK", + "description": "Boot config lock - second set (BOOT_CFG8-11)", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-12-14", + "name": "GPR0_LOCK", + "description": "GPR 0 lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse8", + "name": "LOCK_CFG8", + "description": "LOCK_CFG8", + "index_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse8-bits-9-11", + "name": "ELE_OEM_PQC_SRKH_LOCK", + "description": "OEM post-quantum crypto SRKH Lock ", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse8-bits-12-14", + "name": "ELE_IPED0_KEY_LOCK", + "description": "IPED0 config lock bits " + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG9", + "description": "LOCK_CFG9", + "index_int": "0x0009", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse9-bits-9-11", + "name": "V2X_SHE_MC_LOCK", + "description": "V2X SHE monotonic counter lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-12-14", + "name": "V2X_SHE_KEY_LOCK", + "description": "V2X SHE key lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse10", + "name": "LOCK_CFG10", + "description": "LOCK_CFG10", + "index_int": "0x000A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse10-bits-0-2", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID0 Lock - Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse10-bits-3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse10-bits-9-11", + "name": "BBSM_MC_LOCK", + "description": "Battery Backed Module Secure monotonic counter lock bits.", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse11", + "name": "LOCK_CFG11", + "description": "LOCK_CFG11", + "index_int": "0x000B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse11-bits-0-2", + "name": "GPR1_4_LOCK", + "description": "General Purpose groups 1-4 fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-3-5", + "name": "GPR5_8_LOCK", + "description": "General Purpose groups 5-8 fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-6-8", + "name": "GPR9_12_LOCK", + "description": "General Purpose groups 9-12 fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-9-11", + "name": "GPR13_16_LOCK", + "description": "General Purpose groups 13-16 fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-12-14", + "name": "GPR17_19_LOCK", + "description": "General Purpose groups 17-19 fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse12", + "name": "ECID3", + "description": "Device Unique ID", + "index_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse13", + "name": "ECID2", + "description": "Device Unique ID", + "index_int": "0x000D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse14", + "name": "ECID1", + "description": "Device Unique ID", + "index_int": "0x000E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse15", + "name": "ECID0", + "description": "Device Unique ID", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "Reserved16", + "name": "Reserved 0x10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 22 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x11", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 2 + }, + { + "width": 6 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x12", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x13", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x14", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 19 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x15", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0015", + "is_reserved": true + }, + { + "id": "Reserved22", + "name": "Reserved 0x16", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0016", + "is_reserved": true + }, + { + "id": "Reserved23", + "name": "Reserved 0x17", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0017", + "is_reserved": true + }, + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0018", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse24-bits-0-3", + "name": "Boot_Mode_Fuses", + "description": "Boot_Mode_Fuses", + "values": [ + { + "name": "BOOT_INTERNAL_FUSES", + "value": 8, + "description": "Cortex-M33 From internal fuses" + }, + { + "name": "BOOT_SERIAL_DOWNLOADER", + "value": 9, + "description": "Cortex-M33 Serial Downloader USB 1" + }, + { + "name": "BOOT_EMMC", + "value": 10, + "description": "Cortex-M33 USDHC1 8-bit eMMC 5.1" + }, + { + "name": "BOOT_SD_CARD", + "value": 11, + "description": "Cortex-M33 USDHC2 4-bit SD3.0" + }, + { + "name": "BOOT_SERIAL_NOR", + "value": 12, + "description": "Cortex-M33 xSPI Serial NOR" + }, + { + "name": "BOOT_SERIAL_NAND", + "value": 13, + "description": "Cortex-M33 xSPI Serial NAND 2K page" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-4", + "name": "Override_xSPI_NOR_Boot_Selection", + "description": "Override xSPI NOR Boot Selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Do not override", + "deprecated_names": [ + "0" + ] + }, + { + "name": "Override", + "value": 1, + "description": "Override" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-5-6", + "name": "xSPI_NOR_Boot_Override_Selection", + "description": "xSPI NOR Boot Override Selection", + "values": [ + { + "name": "FLEXSPI_4B_READ", + "value": 1, + "description": "Flex SPI (Flash with 4B READ(0x13)default supported)", + "deprecated_names": [ + "01" + ] + }, + { + "name": "OCTAL_MICRON", + "value": 2, + "description": "Default Octal mode\u00a0(Micron, Nice to have)", + "deprecated_names": [ + "10" + ] + }, + { + "name": "OCTAL_MXIC", + "value": 3, + "description": "Default Octal mode (Mxic, Nice to have )", + "deprecated_names": [ + "11" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-7", + "name": "xSPI_NAND_4K_Page_Selection", + "description": "xSPI NAND 4K Page Selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Not override the default selection (2K page)", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override, 4K page is selected.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-8", + "name": "uSDHC_Device_Type", + "description": "uSDHC_Device_Type", + "values": [ + { + "name": "EMMC", + "value": 0, + "description": "uSDHC_Device_Type: eMMC" + }, + { + "name": "SD", + "value": 1, + "description": "uSDHC_Device_Type: SD" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-9", + "name": "XSPI_NOR_DATA_IOMUX_SION_EN", + "description": "xSPI NOR data IOMUX SION EN", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "SION is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "SION is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-10-11", + "name": "XSPI_NOR_FCB_OFFSET", + "description": "xSPI NOR FCB offset", + "values": [ + { + "name": "OFFSET_0X400", + "value": 0, + "description": "0x400", + "deprecated_names": [ + "0x400" + ] + }, + { + "name": "OFFSET_0X700", + "value": 1, + "description": "0x700", + "deprecated_names": [ + "0x700" + ] + }, + { + "name": "OFFSET_0XA00", + "value": 2, + "description": "0xa00", + "deprecated_names": [ + "0xa00" + ] + }, + { + "name": "OFFSET_0XD00", + "value": 3, + "description": "0xd00", + "deprecated_names": [ + "0xd00" + ] + } + ] + }, + { + "width": 3, + "id": "fuse24-bits-12-14", + "name": "XSPI_NOR_AUTO_PROBE_FEQ_SEL", + "description": "xSPI autoprobe freq sel", + "values": [ + { + "name": "FREQUENCY_100MHZ", + "value": 0, + "description": "100 MHz" + }, + { + "name": "FREQUENCY_133MHZ", + "value": 1, + "description": "133 MHz", + "deprecated_names": [ + "133_MHz" + ] + }, + { + "name": "FREQUENCY_166MHZ", + "value": 2, + "description": "166 MHz", + "deprecated_names": [ + "166_MHz" + ] + }, + { + "name": "FREQUENCY_200MHZ", + "value": 3, + "description": "200 MHz", + "deprecated_names": [ + "200_MHz" + ] + }, + { + "name": "FREQUENCY_80MHZ", + "value": 4, + "description": "80MHz", + "deprecated_names": [ + "80MHz" + ] + }, + { + "name": "FREQUENCY_60MHZ", + "value": 5, + "description": "60MHz", + "deprecated_names": [ + "60MHz" + ] + }, + { + "name": "FREQUENCY_33MHZ", + "value": 6, + "description": "33 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-15", + "name": "XSPI_NOR_FCB_CHECK", + "description": "xSPI FCB check flag", + "values": [ + { + "name": "IMPLEMENTED", + "value": 0, + "description": "FCB check is implemented" + }, + { + "name": "IGNORED", + "value": 1, + "description": "FCB check is ignored" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-16", + "name": "SD_Loopback_Clock_Source_Sel", + "description": "SD loopback clock source sel", + "values": [ + { + "name": "BIT_4_MODE", + "value": 0, + "description": "4 bit mode selection", + "deprecated_names": [ + "4_bit" + ] + }, + { + "name": "BIT_8_MODE", + "value": 1, + "description": "8 bit mode selection", + "deprecated_names": [ + "8_bit" + ] + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-17-18", + "name": "SD_Speed_Selection", + "description": "SD speed selection ", + "values": [ + { + "name": "NORMAL_SPEED", + "value": 0, + "description": "Normal Speed" + }, + { + "name": "HIGH_SPEED", + "value": 1, + "description": "High Speed" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-19", + "name": "eMMC_Speed_Selection", + "description": "eMMC speed selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-20", + "name": "eMMC_fast_boot", + "description": "eMMC fast boot", + "values": [ + { + "name": "BT_FREQ_SEL", + "value": 0, + "description": "See BT_FREQ_SEL BOOT_CFG0[28]", + "deprecated_names": [ + "0" + ] + }, + { + "name": "OVERDRIVE_FREQ", + "value": 1, + "description": "Overdrive Frequency Select.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-21", + "name": "BT_FREQ_SEL_1", + "description": "Boot frequency / voltage select[0]", + "values": [ + { + "name": "BT_FREQ_SEL_MODE", + "value": 0, + "description": "See BT_FREQ_SEL for boot mode frequency and voltage.", + "deprecated_names": [ + "0" + ] + }, + { + "name": "OVERDRIVE_BOOT_MODE", + "value": 1, + "description": "Overdrive boot mode voltage and frequency.", + "deprecated_names": [ + "1", + "OVERDRIVE_MODE" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-22", + "name": "eMMC_voltage_selection", + "description": "eMMC voltage select", + "values": [ + { + "name": "VOLTAGE_3V3", + "value": 0, + "description": "eMMC_voltage_selection: 3.3v", + "deprecated_names": [ + "3.3v" + ] + }, + { + "name": "VOLTAGE_1V8", + "value": 1, + "description": "eMMC_voltage_selection: 1.8v", + "deprecated_names": [ + "1.8v" + ] + } + ] + }, + { + "width": 5, + "id": "fuse24-bits-23-27", + "name": "xSPI_NOR_Reset_Pin_selections", + "description": "xSPI NOR reset pin selections", + "values": [ + { + "name": "GPIO_PIN_0", + "value": 0, + "description": "GPIO[x].0", + "deprecated_names": [ + "GPIO[x].0" + ] + }, + { + "name": "GPIO_PIN_1", + "value": 1, + "description": "GPIO[x].1" + }, + { + "name": "GPIO_PIN_2", + "value": 2, + "description": "GPIO[x].2" + }, + { + "name": "GPIO_PIN_3", + "value": 3, + "description": "GPIO[x].3" + }, + { + "name": "GPIO_PIN_4", + "value": 4, + "description": "GPIO[x].4" + }, + { + "name": "GPIO_PIN_5", + "value": 5, + "description": "GPIO[x].5" + }, + { + "name": "GPIO_PIN_6", + "value": 6, + "description": "GPIO[x].6" + }, + { + "name": "GPIO_PIN_7", + "value": 7, + "description": "GPIO[x].7" + }, + { + "name": "GPIO_PIN_8", + "value": 8, + "description": "GPIO[x].8" + }, + { + "name": "GPIO_PIN_9", + "value": 9, + "description": "GPIO[x].9" + }, + { + "name": "GPIO_PIN_10", + "value": 10, + "description": "GPIO[x].10" + }, + { + "name": "GPIO_PIN_11", + "value": 11, + "description": "GPIO[x].11" + }, + { + "name": "GPIO_PIN_12", + "value": 12, + "description": "GPIO[x].12" + }, + { + "name": "GPIO_PIN_13", + "value": 13, + "description": "GPIO[x].13" + }, + { + "name": "GPIO_PIN_14", + "value": 14, + "description": "GPIO[x].14" + }, + { + "name": "GPIO_PIN_15", + "value": 15, + "description": "GPIO[x].15" + }, + { + "name": "GPIO_PIN_16", + "value": 16, + "description": "GPIO[x].16" + }, + { + "name": "GPIO_PIN_17", + "value": 17, + "description": "GPIO[x].17" + }, + { + "name": "GPIO_PIN_18", + "value": 18, + "description": "GPIO[x].18" + }, + { + "name": "GPIO_PIN_19", + "value": 19, + "description": "GPIO[x].19" + }, + { + "name": "GPIO_PIN_20", + "value": 20, + "description": "GPIO[x].20" + }, + { + "name": "GPIO_PIN_21", + "value": 21, + "description": "GPIO[x].21" + }, + { + "name": "GPIO_PIN_22", + "value": 22, + "description": "GPIO[x].22" + }, + { + "name": "GPIO_PIN_23", + "value": 23, + "description": "GPIO[x].23" + }, + { + "name": "GPIO_PIN_24", + "value": 24, + "description": "GPIO[x].24" + }, + { + "name": "GPIO_PIN_25", + "value": 25, + "description": "GPIO[x].25" + }, + { + "name": "GPIO_PIN_26", + "value": 26, + "description": "GPIO[x].26" + }, + { + "name": "GPIO_PIN_27", + "value": 27, + "description": "GPIO[x].27" + }, + { + "name": "GPIO_PIN_28", + "value": 28, + "description": "GPIO[x].28" + }, + { + "name": "GPIO_PIN_29", + "value": 29, + "description": "GPIO[x].29" + }, + { + "name": "GPIO_PIN_30", + "value": 30, + "description": "GPIO[x].30" + }, + { + "name": "GPIO_PIN_31", + "value": 31, + "description": "GPIO[x].31", + "deprecated_names": [ + "GPIO[x].31" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-28", + "name": "BT_FREQ_SEL", + "description": "Boot frequency / voltage select [0]", + "values": [ + { + "name": "NOMINAL", + "value": 0, + "description": "BT_FREQ_SEL_1 = 0 and BT_FREQ_SEL = 0, Nominal voltage and frequency." + }, + { + "name": "UNDERDRIVE", + "value": 1, + "description": "BT_FREQ_SEL_1 = 0 and BT_FREQ_SEL = 1, Underdrive voltage and frequency." + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-29", + "name": "BT_FUSE_SEL", + "description": "Boot Fuse indication", + "values": [ + { + "name": "NOT_PROGRAMMED", + "value": 0, + "description": "Boot fuses not programmed", + "deprecated_names": [ + "0", + "DISABLED" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot fuses programmed yet", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-30", + "name": "Force_Boot_from_Fuse", + "description": "Force boot from fuse", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disable", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override Boot_Mode pins by boot mode fuses", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-31", + "name": "Force_Serial_Download", + "description": "Force serial download", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Normal boot mode selection based on Boot_Mode and Boot Mode Fuses" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override all other Boot_Mode and Boot Mode Fuses and enter Serial Download" + } + ] + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0019", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse25-bit-0", + "name": "Fast_Boot_Acknowledge_Disable", + "description": "Fast boot acknowledge disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot Ack Disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot Ack Enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-1", + "name": "uSDHC2_Device_Type", + "description": "uSDHC 2 Device Type", + "values": [ + { + "name": "SD_DEVICE", + "value": 0, + "description": "uSDHC2_Device_Type: SD", + "deprecated_names": [ + "SD" + ] + }, + { + "name": "EMMC_DEVICE", + "value": 1, + "description": "uSDHC2_Device_Type: eMMC", + "deprecated_names": [ + "eMMC" + ] + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-2", + "name": "uSDHC_Power_On_Polarity", + "description": "uSDHC power on polarity", + "values": [ + { + "name": "LOW", + "value": 0, + "description": "uSDHC_Power_On_Polarity: Low" + }, + { + "name": "HIGH", + "value": 1, + "description": "uSDHC_Power_On_Polarity: High" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-3", + "name": "uSDHC_Power_CycleDelay", + "description": "uSDHC power cycle delay", + "values": [ + { + "name": "DELAY_5MS", + "value": 0, + "description": "uSDHC_Power_CycleDelay: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "DELAY_2_5MS", + "value": 1, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-4-5", + "name": "uSDHC_Power_Cycle_Interval", + "description": "uSDHC power cycle interval", + "values": [ + { + "name": "INTERVAL_20MS", + "value": 0, + "description": "20 ms", + "deprecated_names": [ + "20_ms" + ] + }, + { + "name": "INTERVAL_10MS", + "value": 1, + "description": "10 ms", + "deprecated_names": [ + "10_ms" + ] + }, + { + "name": "INTERVAL_5MS", + "value": 2, + "description": "uSDHC_Power_Cycle_Interval: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "INTERVAL_2_5MS", + "value": 3, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-6-7", + "name": "SD_Calibration_Step", + "description": "SD calibration step ", + "values": [ + { + "name": "1_DELAY_CELL", + "value": 0, + "description": "1 delay cell" + }, + { + "name": "2_DELAY_CELL", + "value": 1, + "description": "2 delay cell" + }, + { + "name": "3_DELAY_CELL", + "value": 2, + "description": "3 delay cell" + }, + { + "name": "5_DELAY_CELL", + "value": 3, + "description": "5 delay cell" + } + ] + }, + { + "width": 8, + "id": "fuse25-bits-8-15", + "name": "uSDHC_PAD_Settings_Low_bits", + "description": "uSDHC pad settings low bits. The override value for uSDHC pad settings ", + "values": [ + { + "name": "MIN_DRIVE_SLOW", + "value": 0, + "description": "Minimum drive strength with slow slew rate", + "deprecated_names": [ + "11111111" + ] + }, + { + "name": "MIN_DRIVE_MEDIUM", + "value": 1, + "description": "Minimum drive strength with medium slew rate" + }, + { + "name": "MIN_DRIVE_FAST", + "value": 2, + "description": "Minimum drive strength with fast slew rate" + }, + { + "name": "LOW_DRIVE_NO_PULL", + "value": 3, + "description": "Low drive strength with no pull resistor" + }, + { + "name": "LOW_DRIVE_PULL_DOWN", + "value": 4, + "description": "Low drive strength with pull-down enabled" + }, + { + "name": "LOW_DRIVE_PULL_UP", + "value": 5, + "description": "Low drive strength with pull-up enabled" + }, + { + "name": "MED_DRIVE_NO_PULL", + "value": 6, + "description": "Medium drive strength with no pull resistor" + }, + { + "name": "MED_DRIVE_PULL_DOWN", + "value": 7, + "description": "Medium drive strength with pull-down enabled" + }, + { + "name": "MED_DRIVE_PULL_UP", + "value": 8, + "description": "Medium drive strength with pull-up enabled" + }, + { + "name": "HIGH_DRIVE_NO_PULL", + "value": 9, + "description": "High drive strength with no pull resistor" + }, + { + "name": "HIGH_DRIVE_PULL_DOWN", + "value": 10, + "description": "High drive strength with pull-down enabled" + }, + { + "name": "HIGH_DRIVE_PULL_UP", + "value": 11, + "description": "High drive strength with pull-up enabled" + }, + { + "name": "MAX_DRIVE_NO_PULL", + "value": 12, + "description": "Maximum drive strength with no pull resistor" + }, + { + "name": "MAX_DRIVE_PULL_DOWN", + "value": 13, + "description": "Maximum drive strength with pull-down enabled" + }, + { + "name": "MAX_DRIVE_PULL_UP", + "value": 14, + "description": "Maximum drive strength with pull-up enabled" + }, + { + "name": "LOWER_NIBBLE_SET", + "value": 15, + "description": "Lower 4 bits set (00001111)", + "deprecated_names": [ + "CUSTOM_CONFIG_1" + ] + }, + { + "name": "LOW_DRIVE_SLOW", + "value": 16, + "description": "Low drive strength with slow slew rate" + }, + { + "name": "LOW_DRIVE_MEDIUM", + "value": 17, + "description": "Low drive strength with medium slew rate" + }, + { + "name": "LOW_DRIVE_FAST", + "value": 18, + "description": "Low drive strength with fast slew rate" + }, + { + "name": "MED_DRIVE_SLOW", + "value": 32, + "description": "Medium drive strength with slow slew rate" + }, + { + "name": "MED_DRIVE_MEDIUM", + "value": 33, + "description": "Medium drive strength with medium slew rate" + }, + { + "name": "MED_DRIVE_FAST", + "value": 34, + "description": "Medium drive strength with fast slew rate" + }, + { + "name": "HIGH_DRIVE_SLOW", + "value": 48, + "description": "High drive strength with slow slew rate" + }, + { + "name": "HIGH_DRIVE_MEDIUM", + "value": 49, + "description": "High drive strength with medium slew rate" + }, + { + "name": "HIGH_DRIVE_FAST", + "value": 50, + "description": "High drive strength with fast slew rate" + }, + { + "name": "BIT_6_SET", + "value": 64, + "description": "Pad configuration option 64 (01000000)" + }, + { + "name": "BIT_7_SET", + "value": 128, + "description": "Pad configuration option 128 (10000000)" + }, + { + "name": "MAX_DRIVE_SLOW", + "value": 240, + "description": "Maximum drive strength with slow slew rate" + }, + { + "name": "MAX_DRIVE_MEDIUM", + "value": 241, + "description": "Maximum drive strength with medium slew rate" + }, + { + "name": "MAX_DRIVE_FAST", + "value": 242, + "description": "Maximum drive strength with fast slew rate" + }, + { + "name": "ALL_BITS_SET", + "value": 255, + "description": "Maximum drive strength with all features enabled", + "deprecated_names": [ + "MAX_ALL_SETTINGS" + ] + } + ] + }, + { + "width": 4, + "id": "fuse25-bits-16-19", + "name": "uSDHC_PAD_Setting_High_bits", + "description": "uSDHC pad settings high bits. The override value for uSDHC pad settings", + "values": [ + { + "name": "SETTING_0", + "value": 0, + "description": "uSDHC_PAD_Setting_High_bits: 1111", + "deprecated_names": [ + "1111" + ] + }, + { + "name": "SETTING_1", + "value": 1, + "description": "Pad setting level 1" + }, + { + "name": "SETTING_2", + "value": 2, + "description": "Pad setting level 2" + }, + { + "name": "SETTING_3", + "value": 3, + "description": "Pad setting level 3" + }, + { + "name": "SETTING_4", + "value": 4, + "description": "Pad setting level 4" + }, + { + "name": "SETTING_5", + "value": 5, + "description": "Pad setting level 5" + }, + { + "name": "SETTING_6", + "value": 6, + "description": "Pad setting level 6" + }, + { + "name": "SETTING_7", + "value": 7, + "description": "Pad setting level 7" + }, + { + "name": "SETTING_8", + "value": 8, + "description": "Pad setting level 8" + }, + { + "name": "SETTING_9", + "value": 9, + "description": "Pad setting level 9" + }, + { + "name": "SETTING_10", + "value": 10, + "description": "Pad setting level 10" + }, + { + "name": "SETTING_11", + "value": 11, + "description": "Pad setting level 11" + }, + { + "name": "SETTING_12", + "value": 12, + "description": "Pad setting level 12" + }, + { + "name": "SETTING_13", + "value": 13, + "description": "Pad setting level 13" + }, + { + "name": "SETTING_14", + "value": 14, + "description": "Pad setting level 14" + }, + { + "name": "SETTING_15", + "value": 15, + "description": "Pad setting level 15" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-20", + "name": "Power_Cycle_Enable", + "description": "Power cycle enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "No power cycle", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-21", + "name": "uSDHC_Override_Pad_Settings", + "description": "uSDHC override pad settings " + }, + { + "width": 1, + "id": "fuse25-bit-22", + "name": "uSDHC_DLL_Enable", + "description": "uSDHC DLL enable ", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-23", + "name": "BT_FREQ_SET", + "description": "Boot Frequency Set", + "values": [ + { + "name": "NO_SET", + "value": 0, + "description": "BT_FREQ_SEL_1 and BT_FREQ_SEL have not been set" + }, + { + "name": "SET", + "value": 1, + "description": "BT_FREQ_SEL_1 and BT_FREQ_SEL have been set to indicate boot mode voltage." + } + ] + }, + { + "width": 7, + "id": "fuse25-bits-24-30", + "name": "MMC_DLL_DLY", + "description": "MMC DLL delay : Delay target for uSDHC DLL, it is applied to slave mode target delay or override mode target delay depends on DLL Override fuse bit value\n", + "values": [ + { + "name": "DELAY_MIN", + "value": 0, + "description": "Minimum delay value (0000000)", + "deprecated_names": [ + "1111111", + "DELAY_0" + ] + }, + { + "name": "DELAY_1", + "value": 1, + "description": "Delay value 1 - 0000001" + }, + { + "name": "DELAY_2", + "value": 2, + "description": "Delay value 2 - 0000010" + }, + { + "name": "DELAY_3", + "value": 3, + "description": "Delay value 3 - 0000011" + }, + { + "name": "DELAY_4", + "value": 4, + "description": "Delay value 4 - 0000100" + }, + { + "name": "DELAY_5", + "value": 5, + "description": "Delay value 5 - 0000101" + }, + { + "name": "DELAY_6", + "value": 6, + "description": "Delay value 6 - 0000110" + }, + { + "name": "DELAY_7", + "value": 7, + "description": "Delay value 7 - 0000111" + }, + { + "name": "DELAY_8", + "value": 8, + "description": "Delay value 8 - 0001000" + }, + { + "name": "DELAY_9", + "value": 9, + "description": "Delay value 9 - 0001001" + }, + { + "name": "DELAY_10", + "value": 10, + "description": "Delay value 10 - 0001010" + }, + { + "name": "DELAY_11", + "value": 11, + "description": "Delay value 11 - 0001011" + }, + { + "name": "DELAY_12", + "value": 12, + "description": "Delay value 12 - 0001100" + }, + { + "name": "DELAY_13", + "value": 13, + "description": "Delay value 13 - 0001101" + }, + { + "name": "DELAY_14", + "value": 14, + "description": "Delay value 14 - 0001110" + }, + { + "name": "DELAY_15", + "value": 15, + "description": "Delay value 15 - 0001111" + }, + { + "name": "DELAY_16", + "value": 16, + "description": "Delay value 16 - 0010000" + }, + { + "name": "DELAY_17", + "value": 17, + "description": "Delay value 17 - 0010001" + }, + { + "name": "DELAY_18", + "value": 18, + "description": "Delay value 18 - 0010010" + }, + { + "name": "DELAY_19", + "value": 19, + "description": "Delay value 19 - 0010011" + }, + { + "name": "DELAY_20", + "value": 20, + "description": "Delay value 20 - 0010100" + }, + { + "name": "DELAY_21", + "value": 21, + "description": "Delay value 21 - 0010101" + }, + { + "name": "DELAY_22", + "value": 22, + "description": "Delay value 22 - 0010110" + }, + { + "name": "DELAY_23", + "value": 23, + "description": "Delay value 23 - 0010111" + }, + { + "name": "DELAY_24", + "value": 24, + "description": "Delay value 24 - 0011000" + }, + { + "name": "DELAY_25", + "value": 25, + "description": "Delay value 25 - 0011001" + }, + { + "name": "DELAY_26", + "value": 26, + "description": "Delay value 26 - 0011010" + }, + { + "name": "DELAY_27", + "value": 27, + "description": "Delay value 27 - 0011011" + }, + { + "name": "DELAY_28", + "value": 28, + "description": "Delay value 28 - 0011100" + }, + { + "name": "DELAY_29", + "value": 29, + "description": "Delay value 29 - 0011101" + }, + { + "name": "DELAY_30", + "value": 30, + "description": "Delay value 30 - 0011110" + }, + { + "name": "DELAY_31", + "value": 31, + "description": "Delay value 31 - 0011111" + }, + { + "name": "DELAY_32", + "value": 32, + "description": "Delay value 32 - 0100000" + }, + { + "name": "DELAY_33", + "value": 33, + "description": "Delay value 33 - 0100001" + }, + { + "name": "DELAY_34", + "value": 34, + "description": "Delay value 34 - 0100010" + }, + { + "name": "DELAY_35", + "value": 35, + "description": "Delay value 35 - 0100011" + }, + { + "name": "DELAY_36", + "value": 36, + "description": "Delay value 36 - 0100100" + }, + { + "name": "DELAY_37", + "value": 37, + "description": "Delay value 37 - 0100101" + }, + { + "name": "DELAY_38", + "value": 38, + "description": "Delay value 38 - 0100110" + }, + { + "name": "DELAY_39", + "value": 39, + "description": "Delay value 39 - 0100111" + }, + { + "name": "DELAY_40", + "value": 40, + "description": "Delay value 40 - 0101000" + }, + { + "name": "DELAY_41", + "value": 41, + "description": "Delay value 41 - 0101001" + }, + { + "name": "DELAY_42", + "value": 42, + "description": "Delay value 42 - 0101010" + }, + { + "name": "DELAY_43", + "value": 43, + "description": "Delay value 43 - 0101011" + }, + { + "name": "DELAY_44", + "value": 44, + "description": "Delay value 44 - 0101100" + }, + { + "name": "DELAY_45", + "value": 45, + "description": "Delay value 45 - 0101101" + }, + { + "name": "DELAY_46", + "value": 46, + "description": "Delay value 46 - 0101110" + }, + { + "name": "DELAY_47", + "value": 47, + "description": "Delay value 47 - 0101111" + }, + { + "name": "DELAY_48", + "value": 48, + "description": "Delay value 48 - 0110000" + }, + { + "name": "DELAY_49", + "value": 49, + "description": "Delay value 49 - 0110001" + }, + { + "name": "DELAY_50", + "value": 50, + "description": "Delay value 50 - 0110010" + }, + { + "name": "DELAY_51", + "value": 51, + "description": "Delay value 51 - 0110011" + }, + { + "name": "DELAY_52", + "value": 52, + "description": "Delay value 52 - 0110100" + }, + { + "name": "DELAY_53", + "value": 53, + "description": "Delay value 53 - 0110101" + }, + { + "name": "DELAY_54", + "value": 54, + "description": "Delay value 54 - 0110110" + }, + { + "name": "DELAY_55", + "value": 55, + "description": "Delay value 55 - 0110111" + }, + { + "name": "DELAY_56", + "value": 56, + "description": "Delay value 56 - 0111000" + }, + { + "name": "DELAY_57", + "value": 57, + "description": "Delay value 57 - 0111001" + }, + { + "name": "DELAY_58", + "value": 58, + "description": "Delay value 58 - 0111010" + }, + { + "name": "DELAY_59", + "value": 59, + "description": "Delay value 59 - 0111011" + }, + { + "name": "DELAY_60", + "value": 60, + "description": "Delay value 60 - 0111100" + }, + { + "name": "DELAY_61", + "value": 61, + "description": "Delay value 61 - 0111101" + }, + { + "name": "DELAY_62", + "value": 62, + "description": "Delay value 62 - 0111110" + }, + { + "name": "DELAY_63", + "value": 63, + "description": "Delay value 63 - 0111111" + }, + { + "name": "DELAY_64", + "value": 64, + "description": "Delay value 64 - 1000000" + }, + { + "name": "DELAY_65", + "value": 65, + "description": "Delay value 65 - 1000001" + }, + { + "name": "DELAY_66", + "value": 66, + "description": "Delay value 66 - 1000010" + }, + { + "name": "DELAY_67", + "value": 67, + "description": "Delay value 67 - 1000011" + }, + { + "name": "DELAY_68", + "value": 68, + "description": "Delay value 68 - 1000100" + }, + { + "name": "DELAY_69", + "value": 69, + "description": "Delay value 69 - 1000101" + }, + { + "name": "DELAY_70", + "value": 70, + "description": "Delay value 70 - 1000110" + }, + { + "name": "DELAY_71", + "value": 71, + "description": "Delay value 71 - 1000111" + }, + { + "name": "DELAY_72", + "value": 72, + "description": "Delay value 72 - 1001000" + }, + { + "name": "DELAY_73", + "value": 73, + "description": "Delay value 73 - 1001001" + }, + { + "name": "DELAY_74", + "value": 74, + "description": "Delay value 74 - 1001010" + }, + { + "name": "DELAY_75", + "value": 75, + "description": "Delay value 75 - 1001011" + }, + { + "name": "DELAY_76", + "value": 76, + "description": "Delay value 76 - 1001100" + }, + { + "name": "DELAY_77", + "value": 77, + "description": "Delay value 77 - 1001101" + }, + { + "name": "DELAY_78", + "value": 78, + "description": "Delay value 78 - 1001110" + }, + { + "name": "DELAY_79", + "value": 79, + "description": "Delay value 79 - 1001111" + }, + { + "name": "DELAY_80", + "value": 80, + "description": "Delay value 80 - 1010000" + }, + { + "name": "DELAY_81", + "value": 81, + "description": "Delay value 81 - 1010001" + }, + { + "name": "DELAY_82", + "value": 82, + "description": "Delay value 82 - 1010010" + }, + { + "name": "DELAY_83", + "value": 83, + "description": "Delay value 83 - 1010011" + }, + { + "name": "DELAY_84", + "value": 84, + "description": "Delay value 84 - 1010100" + }, + { + "name": "DELAY_85", + "value": 85, + "description": "Delay value 85 - 1010101" + }, + { + "name": "DELAY_86", + "value": 86, + "description": "Delay value 86 - 1010110" + }, + { + "name": "DELAY_87", + "value": 87, + "description": "Delay value 87 - 1010111" + }, + { + "name": "DELAY_88", + "value": 88, + "description": "Delay value 88 - 1011000" + }, + { + "name": "DELAY_89", + "value": 89, + "description": "Delay value 89 - 1011001" + }, + { + "name": "DELAY_90", + "value": 90, + "description": "Delay value 90 - 1011010" + }, + { + "name": "DELAY_91", + "value": 91, + "description": "Delay value 91 - 1011011" + }, + { + "name": "DELAY_92", + "value": 92, + "description": "Delay value 92 - 1011100" + }, + { + "name": "DELAY_93", + "value": 93, + "description": "Delay value 93 - 1011101" + }, + { + "name": "DELAY_94", + "value": 94, + "description": "Delay value 94 - 1011110" + }, + { + "name": "DELAY_95", + "value": 95, + "description": "Delay value 95 - 1011111" + }, + { + "name": "DELAY_96", + "value": 96, + "description": "Delay value 96 - 1100000" + }, + { + "name": "DELAY_97", + "value": 97, + "description": "Delay value 97 - 1100001" + }, + { + "name": "DELAY_98", + "value": 98, + "description": "Delay value 98 - 1100010" + }, + { + "name": "DELAY_99", + "value": 99, + "description": "Delay value 99 - 1100011" + }, + { + "name": "DELAY_100", + "value": 100, + "description": "Delay value 100 - 1100100" + }, + { + "name": "DELAY_101", + "value": 101, + "description": "Delay value 101 - 1100101" + }, + { + "name": "DELAY_102", + "value": 102, + "description": "Delay value 102 - 1100110" + }, + { + "name": "DELAY_103", + "value": 103, + "description": "Delay value 103 - 1100111" + }, + { + "name": "DELAY_104", + "value": 104, + "description": "Delay value 104 - 1101000" + }, + { + "name": "DELAY_105", + "value": 105, + "description": "Delay value 105 - 1101001" + }, + { + "name": "DELAY_106", + "value": 106, + "description": "Delay value 106 - 1101010" + }, + { + "name": "DELAY_107", + "value": 107, + "description": "Delay value 107 - 1101011" + }, + { + "name": "DELAY_108", + "value": 108, + "description": "Delay value 108 - 1101100" + }, + { + "name": "DELAY_109", + "value": 109, + "description": "Delay value 109 - 1101101" + }, + { + "name": "DELAY_110", + "value": 110, + "description": "Delay value 110 - 1101110" + }, + { + "name": "DELAY_111", + "value": 111, + "description": "Delay value 111 - 1101111" + }, + { + "name": "DELAY_112", + "value": 112, + "description": "Delay value 112 - 1110000" + }, + { + "name": "DELAY_113", + "value": 113, + "description": "Delay value 113 - 1110001" + }, + { + "name": "DELAY_114", + "value": 114, + "description": "Delay value 114 - 1110010" + }, + { + "name": "DELAY_115", + "value": 115, + "description": "Delay value 115 - 1110011" + }, + { + "name": "DELAY_116", + "value": 116, + "description": "Delay value 116 - 1110100" + }, + { + "name": "DELAY_117", + "value": 117, + "description": "Delay value 117 - 1110101" + }, + { + "name": "DELAY_118", + "value": 118, + "description": "Delay value 118 - 1110110" + }, + { + "name": "DELAY_119", + "value": 119, + "description": "Delay value 119 - 1110111" + }, + { + "name": "DELAY_120", + "value": 120, + "description": "Delay value 120 - 1111000" + }, + { + "name": "DELAY_121", + "value": 121, + "description": "Delay value 121 - 1111001" + }, + { + "name": "DELAY_122", + "value": 122, + "description": "Delay value 122 - 1111010" + }, + { + "name": "DELAY_123", + "value": 123, + "description": "Delay value 123 - 1111011" + }, + { + "name": "DELAY_124", + "value": 124, + "description": "Delay value 124 - 1111100" + }, + { + "name": "DELAY_125", + "value": 125, + "description": "Delay value 125 - 1111101" + }, + { + "name": "DELAY_126", + "value": 126, + "description": "Delay value 126 - 1111110" + }, + { + "name": "DELAY_MAX", + "value": 127, + "description": "Maximum delay value (1111111)", + "deprecated_names": [ + "DELAY_127" + ] + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-31", + "name": "uSDHC_DLL_Select", + "description": "uSDHC DLL select", + "values": [ + { + "name": "DLL_SLAVE", + "value": 0, + "description": "DLL Slave Mode for" + }, + { + "name": "DLL_OVERRIDE", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x001A", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse26-bits-0-1", + "name": "xSPI_NAND_Column_Address_Width", + "description": "xSPI NAND Column Address Width", + "values": [ + { + "name": "WIDTH_12_BITS", + "value": 0, + "description": "12-bit column address width" + }, + { + "name": "WIDTH_13_BITS", + "value": 1, + "description": "13-bit column address width" + }, + { + "name": "WIDTH_14_BITS", + "value": 2, + "description": "14-bit column address width" + }, + { + "name": "WIDTH_15_BITS", + "value": 3, + "description": "15-bit column address width" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-2-3", + "name": "xSPI_NAND_CS_Interval", + "description": "xSPI NAND CS Interval", + "values": [ + { + "name": "INTERVAL_100NS", + "value": 0, + "description": "100 ns" + }, + { + "name": "INTERVAL_200NS", + "value": 1, + "description": "200 ns" + }, + { + "name": "INTERVAL_400NS", + "value": 2, + "description": "400 ns" + }, + { + "name": "INTERVAL_50NS", + "value": 3, + "description": "50 ns" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-4-5", + "name": "xSPI_NAND_Search_Count", + "description": "xSPI NAND Search Count", + "values": [ + { + "name": "SEARCH_COUNT_2", + "value": 0, + "description": "xSPI_NAND_Search_Count: 2", + "deprecated_names": [ + "2" + ] + }, + { + "name": "2_redudant", + "value": 1, + "description": "2 redudant" + }, + { + "name": "SEARCH_COUNT_4", + "value": 2, + "description": "xSPI_NAND_Search_Count: 4", + "deprecated_names": [ + "4" + ] + }, + { + "name": "SEARCH_COUNT_8", + "value": 3, + "description": "xSPI_NAND_Search_Count: 8", + "deprecated_names": [ + "8" + ] + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-6-7", + "name": "xSPI_NAND_Search_Stride", + "description": "xSPI NAND Search Stride", + "values": [ + { + "name": "64_pages", + "value": 0, + "description": "64 pages" + }, + { + "name": "128_pages", + "value": 1, + "description": "128 pages" + }, + { + "name": "256_pages", + "value": 2, + "description": "256 pages" + }, + { + "name": "32_pages", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 8 + }, + { + "width": 1, + "id": "fuse26-bit-16", + "name": "SPI_Clock_Data_Phase_Control", + "description": "SPI clock data phase control ", + "values": [ + { + "name": "TX_FALL_RX_RISE", + "value": 0, + "description": "Tx on falling, Rx on rising", + "deprecated_names": [ + "0" + ] + }, + { + "name": "TX_RISE_RX_FALL", + "value": 1, + "description": "Tx on rising, Rx on falling", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-17", + "name": "SPI_SCLK_Active", + "description": "SPI SCLK active", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high" + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-18", + "name": "SPI_SS_Active", + "description": "SPI SS active", + "values": [ + { + "name": "ACTIVE_LOW", + "value": 0, + "description": "Active low" + }, + { + "name": "ACTIVE_HIGH", + "value": 1, + "description": "Active high" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-19", + "name": "Recovery_SPI_Addressing", + "description": "Recovery SPI addressing", + "values": [ + { + "name": "ADDRESSING_24BIT", + "value": 0, + "description": "3-bytes (24-bit)", + "deprecated_names": [ + "3-bytes" + ] + }, + { + "name": "ADDRESSING_16BIT", + "value": 1, + "description": "2-bytes (16-bit)", + "deprecated_names": [ + "2-bytes" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-20", + "name": "XSPI_NOR_AUTO_PROBE_EN", + "description": "xSPI NOR auto probe enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Auto probe is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Auto probe is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 3, + "id": "fuse26-bits-21-23", + "name": "xSPI_NAND_Busy_Bit_Offset_Override", + "description": "xSPI NAND busy bit offset override ", + "values": [ + { + "name": "BIT_OFFSET_0", + "value": 0, + "description": "Busy bit at offset 0 in 8-bit register" + }, + { + "name": "BIT_OFFSET_1", + "value": 1, + "description": "Busy bit at offset 1 in 8-bit register" + }, + { + "name": "BIT_OFFSET_2", + "value": 2, + "description": "Busy bit at offset 2 in 8-bit register" + }, + { + "name": "BIT_OFFSET_3", + "value": 3, + "description": "Busy bit at offset 3 in 8-bit register" + }, + { + "name": "BIT_OFFSET_4", + "value": 4, + "description": "Busy bit at offset 4 in 8-bit register" + }, + { + "name": "BIT_OFFSET_5", + "value": 5, + "description": "Busy bit at offset 5 in 8-bit register" + }, + { + "name": "BIT_OFFSET_6", + "value": 6, + "description": "Busy bit at offset 6 in 8-bit register" + }, + { + "name": "BIT_OFFSET_7", + "value": 7, + "description": "Busy bit at offset 7 in 8-bit register" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-24", + "name": "Recovery_CS_Select", + "description": "Recovery CS select", + "values": [ + { + "name": "CS0", + "value": 0, + "description": "Recovery_CS_Select: CS0" + }, + { + "name": "CS1", + "value": 1, + "description": "Recovery_CS_Select: CS1" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse26-bits-26-27", + "name": "Recovery_Port_Select", + "description": "Recovery Port Select in LP boot mode ", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + } + ] + }, + { + "width": 4, + "id": "fuse26-bits-28-31", + "name": "XSPI_DUMMY_CYCLE_SEL", + "description": "xSPI Dummy Cycle Select", + "values": [ + { + "name": "0_cycle", + "value": 0, + "description": "0 cycle" + }, + { + "name": "CYCLE_1", + "value": 1, + "description": "1 cycle" + }, + { + "name": "CYCLE_2", + "value": 2, + "description": "2 cycles" + }, + { + "name": "CYCLE_3", + "value": 3, + "description": "3 cycles" + }, + { + "name": "CYCLE_4", + "value": 4, + "description": "4 cycles" + }, + { + "name": "CYCLE_5", + "value": 5, + "description": "5 cycles" + }, + { + "name": "CYCLE_6", + "value": 6, + "description": "6 cycles" + }, + { + "name": "CYCLE_7", + "value": 7, + "description": "7 cycles" + }, + { + "name": "CYCLE_8", + "value": 8, + "description": "8 cycles" + }, + { + "name": "CYCLE_9", + "value": 9, + "description": "9 cycles" + }, + { + "name": "CYCLE_10", + "value": 10, + "description": "10 cycles" + }, + { + "name": "CYCLE_11", + "value": 11, + "description": "11 cycles" + }, + { + "name": "CYCLE_12", + "value": 12, + "description": "12 cycles" + }, + { + "name": "CYCLE_13", + "value": 13, + "description": "13 cycles" + }, + { + "name": "CYCLE_14", + "value": 14, + "description": "14 cycles" + }, + { + "name": "15_cycles", + "value": 15, + "description": "15 cycles" + } + ] + } + ] + }, + { + "id": "Reserved27", + "name": "Reserved 0x1B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001B", + "is_reserved": true, + "bitfields": [ + { + "width": 24 + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse28", + "name": "BOOT_CFG4", + "description": "BOOT Configuration", + "index_int": "0x001C", + "bitfields": [ + { + "width": 32, + "id": "fuse28-bits-0-31", + "name": "XSPI_FLASH_SDR_DLLCRA", + "description": "The fuse value is used to override the XSPI register DLLCRA in SDR mode.\nIf a customizable value is available in FCB, it will be used to override the register." + } + ] + }, + { + "id": "fuse29", + "name": "BOOT_CFG5", + "description": "BOOT Configuration", + "index_int": "0x001D", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse29-bits-0-31", + "name": "XSPI_FLASH_SDR_SMPR", + "description": "The fuse value is used to override the XSPI register SMPR in SDR mode.\nIf a customizable value is available in FCB, it will be used to override the register." + } + ] + }, + { + "id": "fuse30", + "name": "BOOT_CFG6", + "description": "BOOT Configuration", + "index_int": "0x001E", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse30-bits-0-31", + "name": "XSPI_DLASH_DDR_DLLCRA", + "description": "The fuse value is used to override the XSPI register DLLCRA in DDR mode.\nIf a customizable value is available in FCB, it will be used to override the register." + } + ] + }, + { + "id": "fuse31", + "name": "BOOT_CFG7", + "description": "BOOT Configuration", + "index_int": "0x001F", + "bitfields": [ + { + "width": 32, + "id": "fuse31-bits-0-31", + "name": "XSPI_FLASH_DDR_SMPR", + "description": "The fuse value is used to override the XSPI register SMPR in DDR mode.\nIf a customizable value is available in FCB, it will be used to override the register." + } + ] + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0020", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-1", + "name": "BBNSM_EN", + "description": "BBNSM enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-2", + "name": "SION_EN", + "description": "SION enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-3", + "name": "CCM_CLKO_MUX", + "description": "CCM Clock Mux Select", + "values": [ + { + "name": "CCM_CLKO", + "value": 0, + "description": "Default, Select CCM CLKO", + "deprecated_names": [ + "0" + ] + }, + { + "name": "Select_GPIO", + "value": 1, + "description": "Select GPIO" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-4", + "name": "ROMCP_LOCK", + "description": "Rom CP Lock", + "values": [ + { + "name": "NOT_LOCKED", + "value": 0, + "description": "Not Locked" + }, + { + "name": "LOCKED", + "value": 1, + "description": "Locked" + } + ] + }, + { + "width": 3 + }, + { + "width": 8, + "id": "fuse32-bits-8-15", + "name": "Secondary_boot_offset", + "description": "Secondary boot offset", + "values": [ + { + "name": "OFFSET_4MB", + "value": 0, + "description": "Secondary_boot_offset: 4 MB", + "deprecated_names": [ + "4_MB" + ] + }, + { + "name": "OFFSET_2MB", + "value": 1, + "description": "Secondary_boot_offset: 2 MB", + "deprecated_names": [ + "2_MB" + ] + }, + { + "name": "OFFSET_1MB", + "value": 2, + "description": "Secondary_boot_offset: 1 MB", + "deprecated_names": [ + "1_MB" + ] + }, + { + "name": "OFFSET_8MB", + "value": 3, + "description": "Secondary_boot_offset: 8 MB", + "deprecated_names": [ + "8_MB" + ] + }, + { + "name": "OFFSET_16MB", + "value": 4, + "description": "Secondary_boot_offset: 8MB", + "deprecated_names": [ + "8MB" + ] + }, + { + "name": "OFFSET_32MB", + "value": 5, + "description": "Secondary_boot_offset: 32MB", + "deprecated_names": [ + "32MB" + ] + }, + { + "name": "OFFSET_64MB", + "value": 6, + "description": "Offset = 64 MB" + }, + { + "name": "OFFSET_128MB", + "value": 7, + "description": "Offset = 128 MB" + }, + { + "name": "OFFSET_256MB", + "value": 8, + "description": "Offset = 256 MB" + }, + { + "name": "OFFSET_512MB", + "value": 9, + "description": "Offset = 512 MB", + "deprecated_names": [ + "512_MB" + ] + }, + { + "name": "EMMC_LAST_128MB", + "value": 254, + "description": "EMMC last 128 MB", + "deprecated_names": [ + "last_128_MB" + ] + }, + { + "name": "EMMC_LAST_24KB", + "value": 255, + "description": "EMMC last 24KB", + "deprecated_names": [ + "last_24_KB" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-17", + "name": "M33_D_Cache_Disable", + "description": "M33 D cache disable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-19", + "name": "M33_Recovery_Disable", + "description": "Disable A55 SPI recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-20", + "name": "M33_Recovery_Device", + "description": "Disable M33 SPI recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-22", + "name": "AHAB_Reauth", + "description": "AHAB reauth", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Re-authenticate the whole boot code after standby exit is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Re-authenticate the whole boot code after standby exit is enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-23", + "name": "M33_WDOG_Enable", + "description": "M33 WDOG enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-24", + "name": "A55_I_Cache_Dis", + "description": "A55 I cache dis", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable A55 I-Cache during ROM Boot" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable A55 I-Cache during ROM Boot" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-25", + "name": "M33_I_Cache_Dis", + "description": "M33 I cache dis", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable M33 I-Cache during ROM Boot" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable M33 I-Cache during ROM Boot" + } + ] + }, + { + "width": 2, + "id": "fuse32-bits-26-27", + "name": "WDOG_Timeout_Select", + "description": "WDOG timeout select", + "values": [ + { + "name": "TIMEOUT_2S", + "value": 0, + "description": "WDOG_Timeout_Select: 2 s", + "deprecated_names": [ + "2_s" + ] + }, + { + "name": "TIMEOUT_1_5S", + "value": 1, + "description": "1.5 s", + "deprecated_names": [ + "1.5_s" + ] + }, + { + "name": "TIMEOUT_1S", + "value": 2, + "description": "WDOG_Timeout_Select: 1 s", + "deprecated_names": [ + "1_s" + ] + }, + { + "name": "TIMEOUT_0_5S", + "value": 3, + "description": "0.5 s", + "deprecated_names": [ + "0.5_s" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-29", + "name": "USB_HID_EP1_Out_Disable", + "description": "USB HID EP1 out disable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "USB EP1 Transfer(EP1 Out enable)" + }, + { + "name": "DISABLED", + "value": 1, + "description": "USB EP1 Transfer(EP1 Out disable)" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-30", + "name": "PLL_LATE_EN", + "description": "PLL late en", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Configure PLLs before installing ROM patch", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Configure PLLs after install ROM patch", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-31", + "name": "M33_TCM_MBIST_AT_BOOT_EN", + "description": "M33 TCM MBIST at boot enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + } + ] + }, + { + "id": "fuse33", + "name": "BOOT_CFG9", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0021", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse33-bits-7-8", + "name": "XSPI_HOLD_TIME", + "description": "Delay XSPI_HOLD_TIME until the nor flash getting ready when powered on if needed.\n500us is an estimated time from powered on to the start of xspi initialization.", + "values": [ + { + "name": "DELAY_500US", + "value": 0, + "description": "delay 500us" + }, + { + "name": "DELAY_1MS", + "value": 1, + "description": "delay 1ms" + }, + { + "name": "DELAY_3MS", + "value": 2, + "description": "delay 3ms" + }, + { + "name": "DELAY_10MS", + "value": 3, + "description": "delay 10ms" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse33-bits-13-19", + "name": "XSPI_DELAY_CELL_NUM", + "description": "Fuse configured SLV_DLY_COARSE in DLLCR. The value in the field is multiplied by kxSpiHighdllDelayCellUnit_Min to calculate the read delay in each delay tap. \nThe read delay for each delay tap is calculated as : \nXSPI_DELAY_CELL_NUM * kxSpiHighdllDelayCellUnit_Min(ps)\nwhere kxSpiHighdllDelayCellUnit_Min = 30ps\nNote: This fuse only works when frequency is under 60M for external input DQS.", + "values": [ + { + "name": "DELAY_CELLS_0", + "value": 0, + "description": "No delay cells active" + }, + { + "name": "DELAY_CELLS_1", + "value": 1, + "description": "1 delay cell active" + }, + { + "name": "DELAY_CELLS_2", + "value": 2, + "description": "2 delay cells active" + }, + { + "name": "DELAY_CELLS_3", + "value": 3, + "description": "3 delay cells active" + }, + { + "name": "DELAY_CELLS_4", + "value": 4, + "description": "4 delay cells active" + }, + { + "name": "DELAY_CELLS_5", + "value": 5, + "description": "5 delay cells active" + }, + { + "name": "DELAY_CELLS_6", + "value": 6, + "description": "6 delay cells active" + }, + { + "name": "DELAY_CELLS_7", + "value": 7, + "description": "7 delay cells active" + }, + { + "name": "DELAY_CELLS_8", + "value": 8, + "description": "8 delay cells active" + }, + { + "name": "DELAY_CELLS_9", + "value": 9, + "description": "9 delay cells active" + }, + { + "name": "DELAY_CELLS_10", + "value": 10, + "description": "10 delay cells active" + }, + { + "name": "DELAY_CELLS_11", + "value": 11, + "description": "11 delay cells active" + }, + { + "name": "DELAY_CELLS_12", + "value": 12, + "description": "12 delay cells active" + }, + { + "name": "DELAY_CELLS_13", + "value": 13, + "description": "13 delay cells active" + }, + { + "name": "DELAY_CELLS_14", + "value": 14, + "description": "14 delay cells active" + }, + { + "name": "DELAY_CELLS_15", + "value": 15, + "description": "15 delay cells active" + }, + { + "name": "DELAY_CELLS_16", + "value": 16, + "description": "16 delay cells" + }, + { + "name": "DELAY_CELLS_17", + "value": 17, + "description": "17 delay cells" + }, + { + "name": "DELAY_CELLS_18", + "value": 18, + "description": "18 delay cells" + }, + { + "name": "DELAY_CELLS_19", + "value": 19, + "description": "19 delay cells" + }, + { + "name": "DELAY_CELLS_20", + "value": 20, + "description": "20 delay cells" + }, + { + "name": "DELAY_CELLS_21", + "value": 21, + "description": "21 delay cells" + }, + { + "name": "DELAY_CELLS_22", + "value": 22, + "description": "22 delay cells" + }, + { + "name": "DELAY_CELLS_23", + "value": 23, + "description": "23 delay cells" + }, + { + "name": "DELAY_CELLS_24", + "value": 24, + "description": "24 delay cells" + }, + { + "name": "DELAY_CELLS_25", + "value": 25, + "description": "25 delay cells" + }, + { + "name": "DELAY_CELLS_26", + "value": 26, + "description": "26 delay cells" + }, + { + "name": "DELAY_CELLS_27", + "value": 27, + "description": "27 delay cells" + }, + { + "name": "DELAY_CELLS_28", + "value": 28, + "description": "28 delay cells" + }, + { + "name": "DELAY_CELLS_29", + "value": 29, + "description": "29 delay cells" + }, + { + "name": "DELAY_CELLS_30", + "value": 30, + "description": "30 delay cells" + }, + { + "name": "DELAY_CELLS_31", + "value": 31, + "description": "31 delay cells" + }, + { + "name": "DELAY_CELLS_32", + "value": 32, + "description": "32 delay cells" + }, + { + "name": "DELAY_CELLS_33", + "value": 33, + "description": "33 delay cells" + }, + { + "name": "DELAY_CELLS_34", + "value": 34, + "description": "34 delay cells" + }, + { + "name": "DELAY_CELLS_35", + "value": 35, + "description": "35 delay cells" + }, + { + "name": "DELAY_CELLS_36", + "value": 36, + "description": "36 delay cells" + }, + { + "name": "DELAY_CELLS_37", + "value": 37, + "description": "37 delay cells" + }, + { + "name": "DELAY_CELLS_38", + "value": 38, + "description": "38 delay cells" + }, + { + "name": "DELAY_CELLS_39", + "value": 39, + "description": "39 delay cells" + }, + { + "name": "DELAY_CELLS_40", + "value": 40, + "description": "40 delay cells" + }, + { + "name": "DELAY_CELLS_41", + "value": 41, + "description": "41 delay cells" + }, + { + "name": "DELAY_CELLS_42", + "value": 42, + "description": "42 delay cells" + }, + { + "name": "DELAY_CELLS_43", + "value": 43, + "description": "43 delay cells" + }, + { + "name": "DELAY_CELLS_44", + "value": 44, + "description": "44 delay cells" + }, + { + "name": "DELAY_CELLS_45", + "value": 45, + "description": "45 delay cells" + }, + { + "name": "DELAY_CELLS_46", + "value": 46, + "description": "46 delay cells" + }, + { + "name": "DELAY_CELLS_47", + "value": 47, + "description": "47 delay cells" + }, + { + "name": "DELAY_CELLS_48", + "value": 48, + "description": "48 delay cells" + }, + { + "name": "DELAY_CELLS_49", + "value": 49, + "description": "49 delay cells" + }, + { + "name": "DELAY_CELLS_50", + "value": 50, + "description": "50 delay cells" + }, + { + "name": "DELAY_CELLS_51", + "value": 51, + "description": "51 delay cells" + }, + { + "name": "DELAY_CELLS_52", + "value": 52, + "description": "52 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"value": 64, + "description": "64 delay cells" + }, + { + "name": "DELAY_CELLS_65", + "value": 65, + "description": "65 delay cells" + }, + { + "name": "DELAY_CELLS_66", + "value": 66, + "description": "66 delay cells" + }, + { + "name": "DELAY_CELLS_67", + "value": 67, + "description": "67 delay cells" + }, + { + "name": "DELAY_CELLS_68", + "value": 68, + "description": "68 delay cells" + }, + { + "name": "DELAY_CELLS_69", + "value": 69, + "description": "69 delay cells" + }, + { + "name": "DELAY_CELLS_70", + "value": 70, + "description": "70 delay cells" + }, + { + "name": "DELAY_CELLS_71", + "value": 71, + "description": "71 delay cells" + }, + { + "name": "DELAY_CELLS_72", + "value": 72, + "description": "72 delay cells" + }, + { + "name": "DELAY_CELLS_73", + "value": 73, + "description": "73 delay cells" + }, + { + "name": "DELAY_CELLS_74", + "value": 74, + "description": "74 delay cells" + }, + { + "name": "DELAY_CELLS_75", + "value": 75, + "description": "75 delay cells" + }, + { + "name": "DELAY_CELLS_76", + "value": 76, + "description": "76 delay cells" + }, + { + "name": "DELAY_CELLS_77", + "value": 77, + "description": "77 delay cells" + }, + { + "name": "DELAY_CELLS_78", + "value": 78, + "description": "78 delay cells" + }, + { + "name": "DELAY_CELLS_79", + "value": 79, + "description": "79 delay cells" + }, + { + "name": "DELAY_CELLS_80", + "value": 80, + "description": "80 delay cells" + }, + { + "name": "DELAY_CELLS_81", + "value": 81, + "description": "81 delay cells" + }, + { + "name": "DELAY_CELLS_82", + "value": 82, + "description": "82 delay cells" + }, + { + "name": "DELAY_CELLS_83", + "value": 83, + "description": "83 delay cells" + }, + { + "name": "DELAY_CELLS_84", + "value": 84, + "description": "84 delay cells" + }, + { + "name": "DELAY_CELLS_85", + "value": 85, + "description": "85 delay cells" + }, + { + "name": "DELAY_CELLS_86", + "value": 86, + "description": "86 delay cells" + }, + { + "name": "DELAY_CELLS_87", + "value": 87, + "description": "87 delay cells" + }, + { + "name": "DELAY_CELLS_88", + "value": 88, + "description": "88 delay cells" + }, + { + "name": "DELAY_CELLS_89", + "value": 89, + "description": "89 delay cells" + }, + { + "name": "DELAY_CELLS_90", + "value": 90, + "description": "90 delay cells" + }, + { + "name": "DELAY_CELLS_91", + "value": 91, + "description": "91 delay cells" + }, + { + "name": "DELAY_CELLS_92", + "value": 92, + "description": "92 delay cells" + }, + { + "name": "DELAY_CELLS_93", + "value": 93, + "description": "93 delay cells" + }, + { + "name": "DELAY_CELLS_94", + "value": 94, + "description": "94 delay cells" + }, + { + "name": "DELAY_CELLS_95", + "value": 95, + "description": "95 delay cells" + }, + { + "name": "DELAY_CELLS_96", + "value": 96, + "description": "96 delay cells" + }, + { + "name": "DELAY_CELLS_97", + "value": 97, + "description": "97 delay cells" + }, + { + "name": "DELAY_CELLS_98", + "value": 98, + "description": "98 delay cells" + }, + { + "name": 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0034", + "is_reserved": true + }, + { + "id": "Reserved53", + "name": "Reserved 0x35", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0035", + "is_reserved": true + }, + { + "id": "Reserved54", + "name": "Reserved 0x36", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0036", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved55", + "name": "Reserved 0x37", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0037", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "fuse56", + "name": "ELE_MISC_CTRL0", + "description": "OEM controlled Fuse.", + "index_int": "0x0038", + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse56-bits-0-3", + "name": "SOC_SCOPE_PRIMARY_DBG_DISABLE", + "description": "Debug Disable for CM33 domain. The 4 bits correspond to : {spiden,sniden,dbgen,niden} ", + "values": [ + { + "name": "ALL_DOMAINS_ENABLED", + "value": 0, + "description": "1111 : Any debug domain can be disabled individually.", + "deprecated_names": [ + "0000" + ] + }, + { + "name": "DOMAIN_0_DISABLED", + "value": 1, + "description": "Debug domain 0 disabled, others enabled" + }, + { + "name": "DOMAIN_1_DISABLED", + "value": 2, + "description": "Debug domain 1 disabled, others enabled" + }, + { + "name": "DOMAINS_0_1_DISABLED", + "value": 3, + "description": "Debug domains 0-1 disabled, others enabled" + }, + { + "name": "DOMAIN_2_DISABLED", + "value": 4, + "description": "Debug domain 2 disabled, others enabled" + }, + { + "name": "DOMAINS_0_2_DISABLED", + "value": 5, + "description": "Debug domains 0,2 disabled, others enabled" + }, + { + "name": "DOMAINS_1_2_DISABLED", + "value": 6, + "description": "Debug domains 1-2 disabled, others enabled" + }, + { + "name": "DOMAINS_0_1_2_DISABLED", + "value": 7, + "description": "Debug domains 0-2 disabled, domain 3 enabled" + }, + { + "name": "DOMAIN_3_DISABLED", + "value": 8, + "description": "Debug domain 3 disabled, others enabled" + }, + { + "name": "DOMAINS_0_3_DISABLED", + "value": 9, + "description": "Debug domains 0,3 disabled, others enabled" + }, + { + "name": "DOMAINS_1_3_DISABLED", + "value": 10, + "description": "Debug domains 1,3 disabled, others enabled" + }, + { + "name": "DOMAINS_0_1_3_DISABLED", + "value": 11, + "description": "Debug domains 0-1,3 disabled, domain 2 enabled" + }, + { + "name": "DOMAINS_2_3_DISABLED", + "value": 12, + "description": "Debug domains 2-3 disabled, others enabled" + }, + { + "name": "DOMAINS_0_2_3_DISABLED", + "value": 13, + "description": "Debug domains 0,2-3 disabled, domain 1 enabled" + }, + { + "name": "DOMAINS_1_2_3_DISABLED", + "value": 14, + "description": "Debug domains 1-3 disabled, domain 0 enabled" + }, + { + "name": "ALL_DOMAINS_DISABLED", + "value": 15, + "description": "All debug domains are disabled" + } + ] + }, + { + "width": 4, + "id": "fuse56-bits-4-7", + "name": "SOC_SCOPE1_DBG_DISABLE", + "description": "Debug disable for Trace Memory controller. The 4 bits correspond to : {spiden,sniden,dbgen,niden}", + "values": [ + { + "name": "ALL_DOMAINS_ENABLED", + "value": 0, + "description": "1111 : Any debug domain can be disabled individually.", + "deprecated_names": [ + "0000" + ] + }, + { + "name": "DOMAIN_0_DISABLED", + "value": 1, + "description": "Debug domain 0 is disabled" + }, + { + "name": "DOMAIN_1_DISABLED", + "value": 2, + "description": "Debug domain 1 is disabled" + }, + { + "name": "DOMAIN_0_1_DISABLED", + "value": 3, + "description": "Debug domains 0 and 1 are disabled" + }, + { + "name": "DOMAIN_2_DISABLED", + "value": 4, + "description": "Debug domain 2 is disabled" + }, + { + "name": "DOMAIN_0_2_DISABLED", + "value": 5, + "description": "Debug domains 0 and 2 are disabled" + }, + { + "name": "DOMAIN_1_2_DISABLED", + "value": 6, + "description": "Debug domains 1 and 2 are disabled" + }, + { + "name": "DOMAIN_0_1_2_DISABLED", + "value": 7, + "description": "Debug domains 0, 1 and 2 are disabled" + }, + { + "name": "DOMAIN_3_DISABLED", + "value": 8, + "description": "Debug domain 3 is disabled" + }, + { + "name": "DOMAIN_0_3_DISABLED", + "value": 9, + "description": "Debug domains 0 and 3 are disabled" + }, + { + "name": "DOMAIN_1_3_DISABLED", + "value": 10, + "description": "Debug domains 1 and 3 are disabled" + }, + { + "name": "DOMAIN_0_1_3_DISABLED", + "value": 11, + "description": "Debug domains 0, 1 and 3 are disabled" + }, + { + "name": "DOMAIN_2_3_DISABLED", + "value": 12, + "description": "Debug domains 2 and 3 are disabled" + }, + { + "name": "DOMAIN_0_2_3_DISABLED", + "value": 13, + "description": "Debug domains 0, 2 and 3 are disabled" + }, + { + "name": "DOMAIN_1_2_3_DISABLED", + "value": 14, + "description": "Debug domains 1, 2 and 3 are disabled" + }, + { + "name": "ALL_DOMAINS_DISABLED", + "value": 15, + "description": "All debug domains are disabled" + } + ] + }, + { + "width": 4, + "id": "fuse56-bits-8-11", + "name": "SOC_SCOPE2_DBG_DISABLE", + "description": "Debug disable for Cortex M70, M71 and M33_sync . The 4 bits correspond to : {spiden,sniden,dbgen,niden}", + "values": [ + { + "name": "ALL_DOMAINS_ENABLED", + "value": 0, + "description": "1111 : Any debug domain can be disabled individually.", + "deprecated_names": [ + "0000" + ] + }, + { + "name": "DOMAIN_0_DISABLED", + "value": 1, + "description": "Debug domain 0 is disabled" + }, + { + "name": "DOMAIN_1_DISABLED", + "value": 2, + "description": "Debug domain 1 is disabled" + }, + { + "name": "DOMAINS_0_1_DISABLED", + "value": 3, + "description": "Debug domains 0 and 1 are disabled" + }, + { + "name": "DOMAIN_2_DISABLED", + "value": 4, + "description": "Debug domain 2 is disabled" + }, + { + "name": "DOMAINS_0_2_DISABLED", + "value": 5, + "description": "Debug domains 0 and 2 are disabled" + }, + { + "name": "DOMAINS_1_2_DISABLED", + "value": 6, + "description": "Debug domains 1 and 2 are disabled" + }, + { + "name": "DOMAINS_0_1_2_DISABLED", + "value": 7, + "description": "Debug domains 0, 1 and 2 are disabled" + }, + { + "name": "DOMAIN_3_DISABLED", + "value": 8, + "description": "Debug domain 3 is disabled" + }, + { + "name": "DOMAINS_0_3_DISABLED", + "value": 9, + "description": "Debug domains 0 and 3 are disabled" + }, + { + "name": "DOMAINS_1_3_DISABLED", + "value": 10, + "description": "Debug domains 1 and 3 are disabled" + }, + { + "name": "DOMAINS_0_1_3_DISABLED", + "value": 11, + "description": "Debug domains 0, 1 and 3 are disabled" + }, + { + "name": "DOMAINS_2_3_DISABLED", + "value": 12, + "description": "Debug domains 2 and 3 are disabled" + }, + { + "name": "DOMAINS_0_2_3_DISABLED", + "value": 13, + "description": "Debug domains 0, 2 and 3 are disabled" + }, + { + "name": "DOMAINS_1_2_3_DISABLED", + "value": 14, + "description": "Debug domains 1, 2 and 3 are disabled" + }, + { + "name": "ALL_DOMAINS_DISABLED", + "value": 15, + "description": "All debug domains are disabled" + } + ] + }, + { + "width": 4, + "id": "fuse56-bits-12-15", + "name": "SOC_SCOPE3_DBG_DISABLE", + "description": "Debug disable for DAP AHB-AP. The 4 bits correspond to : {spiden,sniden,dbgen,niden}", + "values": [ + { + "name": "ALL_ENABLED", + "value": 0, + "description": "1111 : Any debug domain can be disabled individually.", + "deprecated_names": [ + "0000" + ] + }, + { + "name": "DOMAIN_0_DISABLED", + "value": 1, + "description": "Debug domain 0 is disabled" + }, + { + "name": "DOMAIN_1_DISABLED", + "value": 2, + "description": "Debug domain 1 is disabled" + }, + { + "name": "DOMAINS_0_1_DISABLED", + "value": 3, + "description": "Debug domains 0 and 1 are disabled" + }, + { + "name": "DOMAIN_2_DISABLED", + "value": 4, + "description": "Debug domain 2 is disabled" + }, + { + "name": "DOMAINS_0_2_DISABLED", + "value": 5, + "description": "Debug domains 0 and 2 are disabled" + }, + { + "name": "DOMAINS_1_2_DISABLED", + "value": 6, + "description": "Debug domains 1 and 2 are disabled" + }, + { + "name": "DOMAIN_012_DISABLED", + "value": 7, + "description": "Debug domains 0, 1 and 2 disabled", + "deprecated_names": [ + "DOMAINS_0_1_2_DISABLED" + ] + }, + { + "name": "DOMAIN_3_DISABLED", + "value": 8, + "description": "Debug domain 3 is disabled" + }, + { + "name": "DOMAINS_0_3_DISABLED", + "value": 9, + "description": "Debug domains 0 and 3 are disabled" + }, + { + "name": "DOMAINS_1_3_DISABLED", + "value": 10, + "description": "Debug domains 1 and 3 are disabled" + }, + { + "name": "DOMAIN_013_DISABLED", + "value": 11, + "description": "Debug domains 0, 1 and 3 disabled", + "deprecated_names": [ + "DOMAINS_0_1_3_DISABLED" + ] + }, + { + "name": "DOMAINS_2_3_DISABLED", + "value": 12, + "description": "Debug domains 2 and 3 are disabled" + }, + { + "name": "DOMAIN_023_DISABLED", + "value": 13, + "description": "Debug domains 0, 2 and 3 disabled", + "deprecated_names": [ + "DOMAINS_0_2_3_DISABLED" + ] + }, + { + "name": "DOMAIN_123_DISABLED", + "value": 14, + "description": "Debug domains 1, 2 and 3 disabled", + "deprecated_names": [ + "DOMAINS_1_2_3_DISABLED" + ] + }, + { + "name": "ALL_DISABLED", + "value": 15, + "description": "All debug domains disabled" + } + ] + } + ] + }, + { + "id": "fuse57", + "name": "ELE_MISC_CTRL1", + "description": "OEM controlled Fuse.", + "index_int": "0x0039", + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse57-bits-0-3", + "name": "SOC_SCOPE4_DBG_DISABLE", + "description": "Debug disable for apps cores, Cortex A55. The 4 bits correspond to : {spiden,sniden,dbgen,niden}", + "values": [ + { + "name": "ALL_ENABLED", + "value": 0, + "description": "1111 : Any debug domain can be disabled individually.", + "deprecated_names": [ + "0000" + ] + }, + { + "name": "DOMAIN_0_DISABLED", + "value": 1, + "description": "Debug domain 0 disabled, others enabled" + }, + { + "name": "DOMAIN_1_DISABLED", + "value": 2, + "description": "Debug domain 1 disabled, others enabled" + }, + { + "name": "DOMAIN_0_1_DISABLED", + "value": 3, + "description": "Debug domains 0-1 disabled, others enabled" + }, + { + "name": "DOMAIN_2_DISABLED", + "value": 4, + "description": "Debug domain 2 disabled, others enabled" + }, + { + "name": "DOMAIN_0_2_DISABLED", + "value": 5, + "description": "Debug domains 0,2 disabled, others enabled" + }, + { + "name": "DOMAIN_1_2_DISABLED", + "value": 6, + "description": "Debug domains 1-2 disabled, others enabled" + }, + { + "name": "DOMAIN_0_1_2_DISABLED", + "value": 7, + "description": "Debug domains 0-2 disabled, domain 3 enabled" + }, + { + "name": "DOMAIN_3_DISABLED", + "value": 8, + "description": "Debug domain 3 disabled, others enabled" + }, + { + "name": "DOMAIN_0_3_DISABLED", + "value": 9, + "description": "Debug domains 0,3 disabled, others enabled" + }, + { + "name": "DOMAIN_1_3_DISABLED", + "value": 10, + "description": "Debug domains 1,3 disabled, others enabled" + }, + { + "name": "DOMAIN_0_1_3_DISABLED", + "value": 11, + "description": "Debug domains 0-1,3 disabled, domain 2 enabled" + }, + { + "name": "DOMAIN_2_3_DISABLED", + "value": 12, + "description": "Debug domains 2-3 disabled, others enabled" + }, + { + "name": "DOMAIN_0_2_3_DISABLED", + "value": 13, + "description": "Debug domains 0,2-3 disabled, domain 1 enabled" + }, + { + "name": "DOMAIN_1_2_3_DISABLED", + "value": 14, + "description": "Debug domains 1-3 disabled, domain 0 enabled" + }, + { + "name": "ALL_DISABLED", + "value": 15, + "description": "All debug domains disabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse58", + "name": "ELE_MISC_CTRL2", + "description": "OEM controlled Fuse.", + "index_int": "0x003A", + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse58-bit-0", + "name": "OEM_AGDET_DISABLE", + "description": "Disable for analog glitch detector during boot", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Sensor is enabled if it passes NXP tests", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Sensor is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-1", + "name": "OEM_VDET_DISABLE", + "description": "Disable for voltage detector during boot", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Sensor is enabled if it passes NXP tests", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Sensor is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-2", + "name": "OEM_TMPSNS_DISABLE", + "description": "Disable for temperature sensor during boot", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Sensor is enabled if it passes NXP tests", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Sensor is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-3", + "name": "OEM_DGDET_DISABLE", + "description": "Disable for digital glitch detector during boot", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Sensor is enabled if it passes NXP tests", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Sensor is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-4", + "name": "FAST_BOOT_DISABLE", + "description": "OEM controlled Fuse.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Fastboot enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Fastboot is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-5", + "name": "SJC_DISABLE", + "description": "Hardware disablement of SJC. Disables JTAG debugger, including ability for boundary scan.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "SJC is enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "SJC is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse58-bit-8", + "name": "SOC_GLBL_DBG_DISABLE", + "description": "Disable all debug. ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Debug is enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Debug is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-10", + "name": "TZ_GLBL_DBG_DISABLE", + "description": "Disables all secure debug. ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Trustzone Debug can be enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Trustzone Debug is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-12", + "name": "OEM_FDET_DISABLE", + "description": "Disable for Frequency detector during boot", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Sensor is enabled if it passes NXP testing", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "Sensor is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-13", + "name": "ALLOW_FIPS_UNAPPROVED_ALGOS", + "description": "If FIPS mode is enabled, Allow FIPS unapproved algorithms", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow FIPS algorithms if FIPS_ENABLE is set." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Even though FIPS_ENABLE is set, allow FIPS unapproved algorithms", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-14", + "name": "CRRM_ENABLE", + "description": "Enable CRRM feature. See SRM for details. ", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "CRRM is not enabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "CRRM is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-15", + "name": "OSCCA_SELFTEST_DISABLE", + "description": "Disable OSCCA selftest", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "In OSCCA mode, perform OSCCA selftest", + "deprecated_names": [ + "0" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "In OSCCA mode, disable OSCCA self-test", + "deprecated_names": [ + "1" + ] + } + ] + } + ] + }, + { + "id": "Reserved59", + "name": "Reserved 0x3B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse60", + "name": "ELE_MISC_CTRL4", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003C", + "reg_width": 16, + "bitfields": [ + { + "width": 12, + "id": "fuse60-bits-0-11", + "name": "EXPORT_CONTROL", + "description": "Each fuse disables the following : \n[11] : Reserved for ELE\n[10] : Reserved for ELE\n[9] : Reserved\n[8] : Reserved for ELE\n[7] : A55 Crypto extension\n[6] : Reserved\n[5] : Reserved\n[4] : OTFADs\n[3]: Reserved for V2X\n[2]: Reserved for V2X \n[1]: Reserved for V2X \n[0]: IEE", + "values": [ + { + "name": "ALL_ENABLED", + "value": 0, + "description": "All crypto accelerators are enabled" + }, + { + "name": "AES_DISABLED", + "value": 1, + "description": "AES crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_0_DISABLED" + ] + }, + { + "name": "SHA_DISABLED", + "value": 2, + "description": "SHA crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_1_DISABLED" + ] + }, + { + "name": "RSA_DISABLED", + "value": 4, + "description": "RSA crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_2_DISABLED" + ] + }, + { + "name": "ECC_DISABLED", + "value": 8, + "description": "ECC crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_3_DISABLED" + ] + }, + { + "name": "DES_DISABLED", + "value": 16, + "description": "DES crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_4_DISABLED" + ] + }, + { + "name": "RNG_DISABLED", + "value": 32, + "description": "Random Number Generator is disabled", + "deprecated_names": [ + "ACCEL_5_DISABLED" + ] + }, + { + "name": "PKC_DISABLED", + "value": 64, + "description": "Public Key Crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_6_DISABLED" + ] + }, + { + "name": "HASH_DISABLED", + "value": 128, + "description": "Hash crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_7_DISABLED" + ] + }, + { + "name": "CIPHER_DISABLED", + "value": 256, + "description": "Cipher crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_8_DISABLED" + ] + }, + { + "name": "MAC_DISABLED", + "value": 512, + "description": "MAC crypto accelerator is disabled", + "deprecated_names": [ + "ACCEL_9_DISABLED" + ] + }, + { + "name": "KDF_DISABLED", + "value": 1024, + "description": "Key Derivation Function accelerator is disabled", + "deprecated_names": [ + "ACCEL_10_DISABLED" + ] + }, + { + "name": "TRNG_DISABLED", + "value": 2048, + "description": "True Random Number Generator is disabled", + "deprecated_names": [ + "ACCEL_11_DISABLED" + ] + }, + { + "name": "ALL_DISABLED", + "value": 4095, + "description": "All crypto accelerators are disabled" + } + ] + }, + { + "width": 3, + "id": "fuse60-bits-12-14", + "name": "ELE_BOOT_CRYPTO", + "description": "Determine boot algorithms to be used", + "values": [ + { + "name": "CLASSIC_BOOT", + "value": 0, + "description": "Classic boot" + }, + { + "name": "HYBRID_BOOT", + "value": 1, + "description": "Hybrid boot (Classic + PQC)", + "deprecated_names": [ + "001" + ] + }, + { + "name": "PQC_BOOT_ONLY", + "value": 2, + "description": "PQC boot only" + }, + { + "name": "REVERT_CLASSIC", + "value": 4, + "description": "Revert to Classic boot" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved61", + "name": "Reserved 0x3D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved62", + "name": "Reserved 0x3E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse63", + "name": "ELE_MISC_CTRL7", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003F", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4, + "id": "fuse63-bits-4-7", + "name": "OEM_PQC_SRK_RVK", + "description": "Revoke bits that correspond to the revoked public keys in the OEM container. These cannot be written using the write fuse command. When the corresponding key in the container is revoked, and the commit command is run after boot, then ELE will set the fuse to match the container. " + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse63-bits-12-15", + "name": "OEM_SRK_RVK", + "description": "Revoke bits that correspond to the revoked public keys in the OEM container. These cannot be written using the write fuse command. When the corresponding key in the container is revoked, and the commit command is run after boot, then ELE will set the fuse to match the container. " + } + ] + }, + { + "id": "Reserved64", + "name": "Reserved 0x40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0040", + "is_reserved": true + }, + { + "id": "Reserved65", + "name": "Reserved 0x41", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0041", + "is_reserved": true + }, + { + "id": "Reserved66", + "name": "Reserved 0x42", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0042", + "is_reserved": true + }, + { + "id": "Reserved67", + "name": "Reserved 0x43", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0043", + "is_reserved": true + }, + { + "id": "Reserved68", + "name": "Reserved 0x44", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0044", + "is_reserved": true + }, + { + "id": "Reserved69", + "name": "Reserved 0x45", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0045", + "is_reserved": true + }, + { + "id": "Reserved70", + "name": "Reserved 0x46", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0046", + "is_reserved": true + }, + { + "id": "Reserved71", + "name": "Reserved 0x47", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0047", + "is_reserved": true + }, + { + "id": "Reserved72", + "name": "Reserved 0x48", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0048", + "is_reserved": true + }, + { + "id": "Reserved73", + "name": "Reserved 0x49", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0049", + "is_reserved": true + }, + { + "id": "Reserved74", + "name": "Reserved 0x4A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004A", + "is_reserved": true + }, + { + "id": "Reserved75", + "name": "Reserved 0x4B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004B", + "is_reserved": true + }, + { + "id": "Reserved76", + "name": "Reserved 0x4C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004C", + "is_reserved": true + }, + { + "id": "Reserved77", + "name": "Reserved 0x4D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004D", + "is_reserved": true + }, + { + "id": "Reserved78", + "name": "Reserved 0x4E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004E", + "is_reserved": true + }, + { + "id": "Reserved79", + "name": "Reserved 0x4F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004F", + "is_reserved": true + }, + { + "id": "Reserved80", + "name": "Reserved 0x50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0050", + "is_reserved": true + }, + { + "id": "Reserved81", + "name": "Reserved 0x51", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0051", + "is_reserved": true + }, + { + "id": "Reserved82", + "name": "Reserved 0x52", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0052", + "is_reserved": true + }, + { + "id": "Reserved83", + "name": "Reserved 0x53", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0053", + "is_reserved": true + }, + { + "id": "Reserved84", + "name": "Reserved 0x54", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0054", + "is_reserved": true + }, + { + "id": "Reserved85", + "name": "Reserved 0x55", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0055", + "is_reserved": true + }, + { + "id": "Reserved86", + "name": "Reserved 0x56", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0056", + "is_reserved": true + }, + { + "id": "Reserved87", + "name": "Reserved 0x57", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0057", + "is_reserved": true + }, + { + "id": "Reserved88", + "name": "Reserved 0x58", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0058", + "is_reserved": true + }, + { + "id": "Reserved89", + "name": "Reserved 0x59", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0059", + "is_reserved": true + }, + { + "id": "Reserved90", + "name": "Reserved 0x5A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005A", + "is_reserved": true + }, + { + "id": "Reserved91", + "name": "Reserved 0x5B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005B", + "is_reserved": true + }, + { + "id": "Reserved92", + "name": "Reserved 0x5C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005C", + "is_reserved": true + }, + { + "id": "Reserved93", + "name": "Reserved 0x5D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005D", + "is_reserved": true + }, + { + "id": "Reserved94", + "name": "Reserved 0x5E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005E", + "is_reserved": true + }, + { + "id": "Reserved95", + "name": "Reserved 0x5F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005F", + "is_reserved": true + }, + { + "id": "Reserved96", + "name": "Reserved 0x60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0060", + "is_reserved": true + }, + { + "id": "Reserved97", + "name": "Reserved 0x61", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0061", + "is_reserved": true + }, + { + "id": "Reserved98", + "name": "Reserved 0x62", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0062", + "is_reserved": true + }, + { + "id": "Reserved99", + "name": "Reserved 0x63", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0063", + "is_reserved": true + }, + { + "id": "Reserved100", + "name": "Reserved 0x64", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0064", + "is_reserved": true + }, + { + "id": "Reserved101", + "name": "Reserved 0x65", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0065", + "is_reserved": true + }, + { + "id": "Reserved102", + "name": "Reserved 0x66", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0066", + "is_reserved": true + }, + { + "id": "Reserved103", + "name": "Reserved 0x67", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0067", + "is_reserved": true + }, + { + "id": "Reserved104", + "name": "Reserved 0x68", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0068", + "is_reserved": true + }, + { + "id": "Reserved105", + "name": "Reserved 0x69", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0069", + "is_reserved": true + }, + { + "id": "Reserved106", + "name": "Reserved 0x6A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006A", + "is_reserved": true + }, + { + "id": "Reserved107", + "name": "Reserved 0x6B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006B", + "is_reserved": true + }, + { + "id": "Reserved108", + "name": "Reserved 0x6C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006C", + "is_reserved": true + }, + { + "id": "Reserved109", + "name": "Reserved 0x6D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006D", + "is_reserved": true + }, + { + "id": "Reserved110", + "name": "Reserved 0x6E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006E", + "is_reserved": true + }, + { + "id": "Reserved111", + "name": "Reserved 0x6F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006F", + "is_reserved": true + }, + { + "id": "Reserved112", + "name": "Reserved 0x70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0070", + "is_reserved": true + }, + { + "id": "Reserved113", + "name": "Reserved 0x71", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0071", + "is_reserved": true + }, + { + "id": "Reserved114", + "name": "Reserved 0x72", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0072", + "is_reserved": true + }, + { + "id": "Reserved115", + "name": "Reserved 0x73", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0073", + "is_reserved": true + }, + { + "id": "Reserved116", + "name": "Reserved 0x74", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0074", + "is_reserved": true + }, + { + "id": "Reserved117", + "name": "Reserved 0x75", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0075", + "is_reserved": true + }, + { + "id": "Reserved118", + "name": "Reserved 0x76", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0076", + "is_reserved": true + }, + { + "id": "Reserved119", + "name": "Reserved 0x77", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0077", + "is_reserved": true + }, + { + "id": "Reserved120", + "name": "Reserved 0x78", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0078", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved121", + "name": "Reserved 0x79", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0079", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved122", + "name": "Reserved 0x7A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007A", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved123", + "name": "Reserved 0x7B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved124", + "name": "Reserved 0x7C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007C", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved125", + "name": "Reserved 0x7D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved126", + "name": "Reserved 0x7E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved127", + "name": "Reserved 0x7F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved128", + "name": "Reserved 0x80", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0080", + "is_reserved": true + }, + { + "id": "Reserved129", + "name": "Reserved 0x81", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0081", + "is_reserved": true + }, + { + "id": "Reserved130", + "name": "Reserved 0x82", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0082", + "is_reserved": true + }, + { + "id": "Reserved131", + "name": "Reserved 0x83", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0083", + "is_reserved": true + }, + { + "id": "Reserved132", + "name": "Reserved 0x84", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0084", + "is_reserved": true + }, + { + "id": "Reserved133", + "name": "Reserved 0x85", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0085", + "is_reserved": true + }, + { + "id": "Reserved134", + "name": "Reserved 0x86", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0086", + "is_reserved": true + }, + { + "id": "Reserved135", + "name": "Reserved 0x87", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0087", + "is_reserved": true + }, + { + "id": "Reserved136", + "name": "Reserved 0x88", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0088", + "is_reserved": true + }, + { + "id": "Reserved137", + "name": "Reserved 0x89", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0089", + "is_reserved": true + }, + { + "id": "Reserved138", + "name": "Reserved 0x8A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008A", + "is_reserved": true + }, + { + "id": "Reserved139", + "name": "Reserved 0x8B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008B", + "is_reserved": true + }, + { + "id": "Reserved140", + "name": "Reserved 0x8C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008C", + "is_reserved": true + }, + { + "id": "Reserved141", + "name": "Reserved 0x8D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008D", + "is_reserved": true + }, + { + "id": "Reserved142", + "name": "Reserved 0x8E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008E", + "is_reserved": true + }, + { + "id": "Reserved143", + "name": "Reserved 0x8F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008F", + "is_reserved": true + }, + { + "id": "Reserved144", + "name": "Reserved 0x90", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0090", + "is_reserved": true + }, + { + "id": "Reserved145", + "name": "Reserved 0x91", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0091", + "is_reserved": true + }, + { + "id": "Reserved146", + "name": "Reserved 0x92", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0092", + "is_reserved": true + }, + { + "id": "Reserved147", + "name": "Reserved 0x93", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0093", + "is_reserved": true + }, + { + "id": "Reserved148", + "name": "Reserved 0x94", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0094", + "is_reserved": true + }, + { + "id": "Reserved149", + "name": "Reserved 0x95", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0095", + "is_reserved": true + }, + { + "id": "Reserved150", + "name": "Reserved 0x96", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0096", + "is_reserved": true + }, + { + "id": "Reserved151", + "name": "Reserved 0x97", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0097", + "is_reserved": true + }, + { + "id": "Reserved152", + "name": "Reserved 0x98", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0098", + "is_reserved": true + }, + { + "id": "Reserved153", + "name": "Reserved 0x99", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0099", + "is_reserved": true + }, + { + "id": "Reserved154", + "name": "Reserved 0x9A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009A", + "is_reserved": true + }, + { + "id": "Reserved155", + "name": "Reserved 0x9B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009B", + "is_reserved": true + }, + { + "id": "Reserved156", + "name": "Reserved 0x9C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009C", + "is_reserved": true + }, + { + "id": "Reserved157", + "name": "Reserved 0x9D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009D", + "is_reserved": true + }, + { + "id": "Reserved158", + "name": "Reserved 0x9E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009E", + "is_reserved": true + }, + { + "id": "Reserved159", + "name": "Reserved 0x9F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009F", + "is_reserved": true + }, + { + "id": "Reserved160", + "name": "Reserved 0xA0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A0", + "is_reserved": true + }, + { + "id": "Reserved161", + "name": "Reserved 0xA1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A1", + "is_reserved": true + }, + { + "id": "Reserved162", + "name": "Reserved 0xA2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A2", + "is_reserved": true + }, + { + "id": "Reserved163", + "name": "Reserved 0xA3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A3", + "is_reserved": true + }, + { + "id": "Reserved164", + "name": "Reserved 0xA4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A4", + "is_reserved": true + }, + { + "id": "Reserved165", + "name": "Reserved 0xA5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A5", + "is_reserved": true + }, + { + "id": "Reserved166", + "name": "Reserved 0xA6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A6", + "is_reserved": true + }, + { + "id": "Reserved167", + "name": "Reserved 0xA7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A7", + "is_reserved": true + }, + { + "id": "Reserved168", + "name": "Reserved 0xA8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A8", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved169", + "name": "Reserved 0xA9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A9", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved170", + "name": "Reserved 0xAA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AA", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved171", + "name": "Reserved 0xAB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AB", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved172", + "name": "Reserved 0xAC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AC", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved173", + "name": "Reserved 0xAD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AD", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved174", + "name": "Reserved 0xAE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AE", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved175", + "name": "Reserved 0xAF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AF", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved176", + "name": "Reserved 0xB0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B0", + "is_reserved": true + }, + { + "id": "Reserved177", + "name": "Reserved 0xB1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B1", + "is_reserved": true + }, + { + "id": "Reserved178", + "name": "Reserved 0xB2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B2", + "is_reserved": true + }, + { + "id": "Reserved179", + "name": "Reserved 0xB3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B3", + "is_reserved": true + }, + { + "id": "fuse180", + "name": "IPED0_KEY0", + "description": "IPED Key for IPED connected to cSPI interface 0", + "index_int": "0x00B4", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse181", + "name": "IPED0_KEY1", + "description": "IPED Key for IPED connected to cSPI interface 0", + "index_int": "0x00B5", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse182", + "name": "IPED0_KEY2", + "description": "IPED Key for IPED connected to cSPI interface 0", + "index_int": "0x00B6", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse183", + "name": "IPED0_KEY3", + "description": "IPED Key for IPED connected to cSPI interface 0", + "index_int": "0x00B7", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse184", + "name": "IPED1_KEY0", + "description": "IPED Key for IPED connected to cSPI interface 1", + "index_int": "0x00B8", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse185", + "name": "IPED1_KEY1", + "description": "IPED Key for IPED connected to cSPI interface 1", + "index_int": "0x00B9", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse186", + "name": "IPED1_KEY2", + "description": "IPED Key for IPED connected to cSPI interface 1", + "index_int": "0x00BA", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse187", + "name": "IPED1_KEY3", + "description": "IPED Key for IPED connected to cSPI interface 1", + "index_int": "0x00BB", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "Reserved188", + "name": "Reserved 0xBC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BC", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved189", + "name": "Reserved 0xBD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BD", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved190", + "name": "Reserved 0xBE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BE", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved191", + "name": "Reserved 0xBF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BF", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved192", + "name": "Reserved 0xC0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C0", + "is_reserved": true + }, + { + "id": "Reserved193", + "name": "Reserved 0xC1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C1", + "is_reserved": true + }, + { + "id": "Reserved194", + "name": "Reserved 0xC2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C2", + "is_reserved": true + }, + { + "id": "Reserved195", + "name": "Reserved 0xC3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C3", + "is_reserved": true + }, + { + "id": "Reserved196", + "name": "Reserved 0xC4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C4", + "is_reserved": true + }, + { + "id": "Reserved197", + "name": "Reserved 0xC5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C5", + "is_reserved": true + }, + { + "id": "Reserved198", + "name": "Reserved 0xC6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C6", + "is_reserved": true + }, + { + "id": "Reserved199", + "name": "Reserved 0xC7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C7", + "is_reserved": true + }, + { + "id": "Reserved200", + "name": "Reserved 0xC8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C8", + "is_reserved": true + }, + { + "id": "Reserved201", + "name": "Reserved 0xC9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C9", + "is_reserved": true + }, + { + "id": "Reserved202", + "name": "Reserved 0xCA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CA", + "is_reserved": true + }, + { + "id": "Reserved203", + "name": "Reserved 0xCB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CB", + "is_reserved": true + }, + { + "id": "Reserved204", + "name": "Reserved 0xCC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CC", + "is_reserved": true + }, + { + "id": "Reserved205", + "name": "Reserved 0xCD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CD", + "is_reserved": true + }, + { + "id": "Reserved206", + "name": "Reserved 0xCE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CE", + "is_reserved": true + }, + { + "id": "Reserved207", + "name": "Reserved 0xCF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CF", + "is_reserved": true + }, + { + "id": "Reserved208", + "name": "Reserved 0xD0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D0", + "is_reserved": true + }, + { + "id": "Reserved209", + "name": "Reserved 0xD1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D1", + "is_reserved": true + }, + { + "id": "Reserved210", + "name": "Reserved 0xD2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D2", + "is_reserved": true + }, + { + "id": "Reserved211", + "name": "Reserved 0xD3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D3", + "is_reserved": true + }, + { + "id": "Reserved212", + "name": "Reserved 0xD4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D4", + "is_reserved": true + }, + { + "id": "Reserved213", + "name": "Reserved 0xD5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D5", + "is_reserved": true + }, + { + "id": "Reserved214", + "name": "Reserved 0xD6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D6", + "is_reserved": true + }, + { + "id": "Reserved215", + "name": "Reserved 0xD7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D7", + "is_reserved": true + }, + { + "id": "Reserved216", + "name": "Reserved 0xD8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D8", + "is_reserved": true + }, + { + "id": "Reserved217", + "name": "Reserved 0xD9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D9", + "is_reserved": true + }, + { + "id": "Reserved218", + "name": "Reserved 0xDA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DA", + "is_reserved": true + }, + { + "id": "Reserved219", + "name": "Reserved 0xDB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DB", + "is_reserved": true + }, + { + "id": "Reserved220", + "name": "Reserved 0xDC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DC", + "is_reserved": true + }, + { + "id": "Reserved221", + "name": "Reserved 0xDD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DD", + "is_reserved": true + }, + { + "id": "Reserved222", + "name": "Reserved 0xDE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DE", + "is_reserved": true + }, + { + "id": "Reserved223", + "name": "Reserved 0xDF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DF", + "is_reserved": true + }, + { + "id": "Reserved224", + "name": "Reserved 0xE0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E0", + "is_reserved": true + }, + { + "id": "Reserved225", + "name": "Reserved 0xE1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E1", + "is_reserved": true + }, + { + "id": "Reserved226", + "name": "Reserved 0xE2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E2", + "is_reserved": true + }, + { + "id": "Reserved227", + "name": "Reserved 0xE3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E3", + "is_reserved": true + }, + { + "id": "Reserved228", + "name": "Reserved 0xE4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E4", + "is_reserved": true + }, + { + "id": "Reserved229", + "name": "Reserved 0xE5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E5", + "is_reserved": true + }, + { + "id": "Reserved230", + "name": "Reserved 0xE6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E6", + "is_reserved": true + }, + { + "id": "Reserved231", + "name": "Reserved 0xE7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E7", + "is_reserved": true + }, + { + "id": "Reserved232", + "name": "Reserved 0xE8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E8", + "is_reserved": true + }, + { + "id": "Reserved233", + "name": "Reserved 0xE9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E9", + "is_reserved": true + }, + { + "id": "Reserved234", + "name": "Reserved 0xEA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EA", + "is_reserved": true + }, + { + "id": "Reserved235", + "name": "Reserved 0xEB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EB", + "is_reserved": true + }, + { + "id": "Reserved236", + "name": "Reserved 0xEC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EC", + "is_reserved": true + }, + { + "id": "Reserved237", + "name": "Reserved 0xED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00ED", + "is_reserved": true + }, + { + "id": "Reserved238", + "name": "Reserved 0xEE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EE", + "is_reserved": true + }, + { + "id": "Reserved239", + "name": "Reserved 0xEF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EF", + "is_reserved": true + }, + { + "id": "Reserved240", + "name": "Reserved 0xF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F0", + "is_reserved": true + }, + { + "id": "Reserved241", + "name": "Reserved 0xF1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F1", + "is_reserved": true + }, + { + "id": "Reserved242", + "name": "Reserved 0xF2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F2", + "is_reserved": true + }, + { + "id": "Reserved243", + "name": "Reserved 0xF3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F3", + "is_reserved": true + }, + { + "id": "Reserved244", + "name": "Reserved 0xF4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F4", + "is_reserved": true + }, + { + "id": "Reserved245", + "name": "Reserved 0xF5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F5", + "is_reserved": true + }, + { + "id": "Reserved246", + "name": "Reserved 0xF6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F6", + "is_reserved": true + }, + { + "id": "Reserved247", + "name": "Reserved 0xF7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F7", + "is_reserved": true + }, + { + "id": "Reserved248", + "name": "Reserved 0xF8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F8", + "is_reserved": true + }, + { + "id": "Reserved249", + "name": "Reserved 0xF9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F9", + "is_reserved": true + }, + { + "id": "Reserved250", + "name": "Reserved 0xFA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FA", + "is_reserved": true + }, + { + "id": "Reserved251", + "name": "Reserved 0xFB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FB", + "is_reserved": true + }, + { + "id": "Reserved252", + "name": "Reserved 0xFC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FC", + "is_reserved": true + }, + { + "id": "Reserved253", + "name": "Reserved 0xFD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FD", + "is_reserved": true + }, + { + "id": "Reserved254", + "name": "Reserved 0xFE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FE", + "is_reserved": true + }, + { + "id": "Reserved255", + "name": "Reserved 0xFF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FF", + "is_reserved": true + }, + { + "id": "Reserved256", + "name": "Reserved 0x100", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0100", + "is_reserved": true + }, + { + "id": "Reserved257", + "name": "Reserved 0x101", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0101", + "is_reserved": true + }, + { + "id": "Reserved258", + "name": "Reserved 0x102", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0102", + "is_reserved": true + }, + { + "id": "Reserved259", + "name": "Reserved 0x103", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0103", + "is_reserved": true + }, + { + "id": "Reserved260", + "name": "Reserved 0x104", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0104", + "is_reserved": true + }, + { + "id": "Reserved261", + "name": "Reserved 0x105", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0105", + "is_reserved": true + }, + { + "id": "Reserved262", + "name": "Reserved 0x106", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0106", + "is_reserved": true + }, + { + "id": "Reserved263", + "name": "Reserved 0x107", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0107", + "is_reserved": true + }, + { + "id": "Reserved264", + "name": "Reserved 0x108", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0108", + "is_reserved": true + }, + { + "id": "Reserved265", + "name": "Reserved 0x109", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0109", + "is_reserved": true + }, + { + "id": "Reserved266", + "name": "Reserved 0x10A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010A", + "is_reserved": true + }, + { + "id": "Reserved267", + "name": "Reserved 0x10B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010B", + "is_reserved": true + }, + { + "id": "Reserved268", + "name": "Reserved 0x10C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010C", + "is_reserved": true + }, + { + "id": "Reserved269", + "name": "Reserved 0x10D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010D", + "is_reserved": true + }, + { + "id": "Reserved270", + "name": "Reserved 0x10E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010E", + "is_reserved": true + }, + { + "id": "Reserved271", + "name": "Reserved 0x10F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010F", + "is_reserved": true + }, + { + "id": "Reserved272", + "name": "Reserved 0x110", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0110", + "is_reserved": true + }, + { + "id": "Reserved273", + "name": "Reserved 0x111", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0111", + "is_reserved": true + }, + { + "id": "Reserved274", + "name": "Reserved 0x112", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0112", + "is_reserved": true + }, + { + "id": "Reserved275", + "name": "Reserved 0x113", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0113", + "is_reserved": true + }, + { + "id": "Reserved276", + "name": "Reserved 0x114", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0114", + "is_reserved": true + }, + { + "id": "Reserved277", + "name": "Reserved 0x115", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0115", + "is_reserved": true + }, + { + "id": "Reserved278", + "name": "Reserved 0x116", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0116", + "is_reserved": true + }, + { + "id": "Reserved279", + "name": "Reserved 0x117", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0117", + "is_reserved": true + }, + { + "id": "Reserved280", + "name": "Reserved 0x118", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0118", + "is_reserved": true + }, + { + "id": "Reserved281", + "name": "Reserved 0x119", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0119", + "is_reserved": true + }, + { + "id": "Reserved282", + "name": "Reserved 0x11A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011A", + "is_reserved": true + }, + { + "id": "Reserved283", + "name": "Reserved 0x11B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011B", + "is_reserved": true + }, + { + "id": "Reserved284", + "name": "Reserved 0x11C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011C", + "is_reserved": true + }, + { + "id": "Reserved285", + "name": "Reserved 0x11D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011D", + "is_reserved": true + }, + { + "id": "Reserved286", + "name": "Reserved 0x11E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011E", + "is_reserved": true + }, + { + "id": "Reserved287", + "name": "Reserved 0x11F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x011F", + "is_reserved": true + }, + { + "id": "Reserved288", + "name": "Reserved 0x120", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0120", + "is_reserved": true + }, + { + "id": "Reserved289", + "name": "Reserved 0x121", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0121", + "is_reserved": true + }, + { + "id": "Reserved290", + "name": "Reserved 0x122", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0122", + "is_reserved": true + }, + { + "id": "Reserved291", + "name": "Reserved 0x123", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0123", + "is_reserved": true + }, + { + "id": "Reserved292", + "name": "Reserved 0x124", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0124", + "is_reserved": true + }, + { + "id": "Reserved293", + "name": "Reserved 0x125", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0125", + "is_reserved": true + }, + { + "id": "Reserved294", + "name": "Reserved 0x126", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0126", + "is_reserved": true + }, + { + "id": "Reserved295", + "name": "Reserved 0x127", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0127", + "is_reserved": true + }, + { + "id": "Reserved296", + "name": "Reserved 0x128", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0128", + "is_reserved": true + }, + { + "id": "Reserved297", + "name": "Reserved 0x129", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0129", + "is_reserved": true + }, + { + "id": "Reserved298", + "name": "Reserved 0x12A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012A", + "is_reserved": true + }, + { + "id": "Reserved299", + "name": "Reserved 0x12B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012B", + "is_reserved": true + }, + { + "id": "Reserved300", + "name": "Reserved 0x12C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012C", + "is_reserved": true + }, + { + "id": "Reserved301", + "name": "Reserved 0x12D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012D", + "is_reserved": true + }, + { + "id": "Reserved302", + "name": "Reserved 0x12E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012E", + "is_reserved": true + }, + { + "id": "Reserved303", + "name": "Reserved 0x12F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012F", + "is_reserved": true + }, + { + "id": "Reserved304", + "name": "Reserved 0x130", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0130", + "is_reserved": true + }, + { + "id": "Reserved305", + "name": "Reserved 0x131", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0131", + "is_reserved": true + }, + { + "id": "Reserved306", + "name": "Reserved 0x132", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0132", + "is_reserved": true + }, + { + "id": "Reserved307", + "name": "Reserved 0x133", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0133", + "is_reserved": true + }, + { + "id": "Reserved308", + "name": "Reserved 0x134", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0134", + "is_reserved": true + }, + { + "id": "Reserved309", + "name": "Reserved 0x135", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0135", + "is_reserved": true + }, + { + "id": "Reserved310", + "name": "Reserved 0x136", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0136", + "is_reserved": true + }, + { + "id": "Reserved311", + "name": "Reserved 0x137", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0137", + "is_reserved": true + }, + { + "id": "fuse312", + "name": "V2X_SHE_SECRET_KEY0", + "description": "V2X SHE Key", + "index_int": "0x0138", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse313", + "name": "V2X_SHE_SECRET_KEY1", + "description": "V2X SHE Key", + "index_int": "0x0139", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse314", + "name": "V2X_SHE_SECRET_KEY2", + "description": "V2X SHE Key", + "index_int": "0x013A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse315", + "name": "V2X_SHE_SECRET_KEY3", + "description": "V2X SHE Key", + "index_int": "0x013B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse316", + "name": "V2X_SHE_PRNG_KEY0", + "description": "V2X SHE Key", + "index_int": "0x013C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse317", + "name": "V2X_SHE_PRNG_KEY1", + "description": "V2X SHE Key", + "index_int": "0x013D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse318", + "name": "V2X_SHE_PRNG_KEY2", + "description": "V2X SHE Key", + "index_int": "0x013E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse319", + "name": "V2X_SHE_PRNG_KEY3", + "description": "V2X SHE Key", + "index_int": "0x013F", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "Reserved320", + "name": "Reserved 0x140", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0140", + "is_reserved": true + }, + { + "id": "Reserved321", + "name": "Reserved 0x141", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0141", + "is_reserved": true + }, + { + "id": "Reserved322", + "name": "Reserved 0x142", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0142", + "is_reserved": true + }, + { + "id": "Reserved323", + "name": "Reserved 0x143", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0143", + "is_reserved": true + }, + { + "id": "Reserved324", + "name": "Reserved 0x144", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0144", + "is_reserved": true + }, + { + "id": "Reserved325", + "name": "Reserved 0x145", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0145", + "is_reserved": true + }, + { + "id": "Reserved326", + "name": "Reserved 0x146", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0146", + "is_reserved": true + }, + { + "id": "Reserved327", + "name": "Reserved 0x147", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0147", + "is_reserved": true + }, + { + "id": "Reserved328", + "name": "Reserved 0x148", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0148", + "is_reserved": true + }, + { + "id": "Reserved329", + "name": "Reserved 0x149", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0149", + "is_reserved": true + }, + { + "id": "Reserved330", + "name": "Reserved 0x14A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014A", + "is_reserved": true + }, + { + "id": "Reserved331", + "name": "Reserved 0x14B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014B", + "is_reserved": true + }, + { + "id": "Reserved332", + "name": "Reserved 0x14C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014C", + "is_reserved": true + }, + { + "id": "Reserved333", + "name": "Reserved 0x14D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014D", + "is_reserved": true + }, + { + "id": "Reserved334", + "name": "Reserved 0x14E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014E", + "is_reserved": true + }, + { + "id": "Reserved335", + "name": "Reserved 0x14F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014F", + "is_reserved": true + }, + { + "id": "fuse336", + "name": "GPR1_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0150" + }, + { + "id": "fuse337", + "name": "GPR1_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0151" + }, + { + "id": "fuse338", + "name": "GPR1_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0152", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse339", + "name": "GPR1_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0153" + }, + { + "id": "fuse340", + "name": "GPR1_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0154", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse341", + "name": "GPR1_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0155", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse342", + "name": "GPR1_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0156" + }, + { + "id": "fuse343", + "name": "GPR1_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0157" + }, + { + "id": "fuse344", + "name": "GPR2_CFG0", + "description": "General purpose fuse", + "index_int": "0x0158" + }, + { + "id": "fuse345", + "name": "GPR2_CFG1", + "description": "General purpose fuse", + "index_int": "0x0159", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse346", + "name": "GPR2_CFG2", + "description": "General purpose fuse", + "index_int": "0x015A" + }, + { + "id": "fuse347", + "name": "GPR2_CFG3", + "description": "General purpose fuse", + "index_int": "0x015B" + }, + { + "id": "fuse348", + "name": "GPR2_CFG4", + "description": "General purpose fuse", + "index_int": "0x015C" + }, + { + "id": "fuse349", + "name": "GPR2_CFG5", + "description": "General purpose fuse", + "index_int": "0x015D" + }, + { + "id": "fuse350", + "name": "GPR2_CFG6", + "description": "General purpose fuse", + "index_int": "0x015E" + }, + { + "id": "fuse351", + "name": "GPR2_CFG7", + "description": "General purpose fuse", + "index_int": "0x015F" + }, + { + "id": "fuse352", + "name": "GPR3_CFG0", + "description": "General purpose fuse", + "index_int": "0x0160", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse353", + "name": "GPR3_CFG1", + "description": "General purpose fuse", + "index_int": "0x0161" + }, + { + "id": "fuse354", + "name": "GPR3_CFG2", + "description": "General purpose fuse", + "index_int": "0x0162" + }, + { + "id": "fuse355", + "name": "GPR3_CFG3", + "description": "General purpose fuse", + "index_int": "0x0163", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse356", + "name": "GPR3_CFG4", + "description": "General purpose fuse", + "index_int": "0x0164" + }, + { + "id": "fuse357", + "name": "GPR3_CFG5", + "description": "General purpose fuse", + "index_int": "0x0165" + }, + { + "id": "fuse358", + "name": "GPR3_CFG6", + "description": "General purpose fuse", + "index_int": "0x0166" + }, + { + "id": "fuse359", + "name": "GPR3_CFG7", + "description": "General purpose fuse", + "index_int": "0x0167", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse360", + "name": "GPR4_CFG0", + "description": "General purpose fuse", + "index_int": "0x0168", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse361", + "name": "GPR4_CFG1", + "description": "General purpose fuse", + "index_int": "0x0169", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse362", + "name": "GPR4_CFG2", + "description": "General purpose fuse", + "index_int": "0x016A" + }, + { + "id": "fuse363", + "name": "GPR4_CFG3", + "description": "General purpose fuse", + "index_int": "0x016B" + }, + { + "id": "fuse364", + "name": "GPR4_CFG4", + "description": "General purpose fuse", + "index_int": "0x016C" + }, + { + "id": "fuse365", + "name": "GPR4_CFG5", + "description": "General purpose fuse", + "index_int": "0x016D" + }, + { + "id": "fuse366", + "name": "GPR4_CFG6", + "description": "General purpose fuse", + "index_int": "0x016E" + }, + { + "id": "fuse367", + "name": "GPR4_CFG7", + "description": "General purpose fuse", + "index_int": "0x016F" + }, + { + "id": "fuse368", + "name": "GPR5_CFG0", + "description": "General purpose fuse", + "index_int": "0x0170", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse369", + "name": "GPR5_CFG1", + "description": "General purpose fuse", + "index_int": "0x0171" + }, + { + "id": "fuse370", + "name": "GPR5_CFG2", + "description": "General purpose fuse", + "index_int": "0x0172" + }, + { + "id": "fuse371", + "name": "GPR5_CFG3", + "description": "General purpose fuse", + "index_int": "0x0173", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse372", + "name": "GPR5_CFG4", + "description": "General purpose fuse", + "index_int": "0x0174" + }, + { + "id": "fuse373", + "name": "GPR5_CFG5", + "description": "General purpose fuse", + "index_int": "0x0175" + }, + { + "id": "fuse374", + "name": "GPR5_CFG6", + "description": "General purpose fuse", + "index_int": "0x0176" + }, + { + "id": "fuse375", + "name": "GPR5_CFG7", + "description": "General purpose fuse", + "index_int": "0x0177" + }, + { + "id": "fuse376", + "name": "GPR6_CFG0", + "description": "General purpose fuse", + "index_int": "0x0178" + }, + { + "id": "fuse377", + "name": "GPR6_CFG1", + "description": "General purpose fuse", + "index_int": "0x0179" + }, + { + "id": "fuse378", + "name": "GPR6_CFG2", + "description": "General purpose fuse", + "index_int": "0x017A" + }, + { + "id": "fuse379", + "name": "GPR6_CFG3", + "description": "General purpose fuse", + "index_int": "0x017B" + }, + { + "id": "fuse380", + "name": "GPR6_CFG4", + "description": "General purpose fuse", + "index_int": "0x017C" + }, + { + "id": "fuse381", + "name": "GPR6_CFG5", + "description": "General purpose fuse", + "index_int": "0x017D" + }, + { + "id": "fuse382", + "name": "GPR6_CFG6", + "description": "General purpose fuse", + "index_int": "0x017E" + }, + { + "id": "fuse383", + "name": "GPR6_CFG7", + "description": "General purpose fuse", + "index_int": "0x017F" + }, + { + "id": "fuse384", + "name": "GPR7_CFG0", + "description": "General purpose fuse", + "index_int": "0x0180" + }, + { + "id": "fuse385", + "name": "GPR7_CFG1", + "description": "General purpose fuse", + "index_int": "0x0181" + }, + { + "id": "fuse386", + "name": "GPR7_CFG2", + "description": "General purpose fuse", + "index_int": "0x0182" + }, + { + "id": "fuse387", + "name": "GPR7_CFG3", + "description": "General purpose fuse", + "index_int": "0x0183" + }, + { + "id": "fuse388", + "name": "GPR7_CFG4", + "description": "General purpose fuse", + "index_int": "0x0184" + }, + { + "id": "fuse389", + "name": "GPR7_CFG5", + "description": "General purpose fuse", + "index_int": "0x0185" + }, + { + "id": "fuse390", + "name": "GPR7_CFG6", + "description": "General purpose fuse", + "index_int": "0x0186" + }, + { + "id": "fuse391", + "name": "GPR7_CFG7", + "description": "General purpose fuse", + "index_int": "0x0187" + }, + { + "id": "fuse392", + "name": "GPR8_CFG0", + "description": "General purpose fuse", + "index_int": "0x0188" + }, + { + "id": "fuse393", + "name": "GPR8_CFG1", + "description": "General purpose fuse", + "index_int": "0x0189" + }, + { + "id": "fuse394", + "name": "GPR8_CFG2", + "description": "General purpose fuse", + "index_int": "0x018A" + }, + { + "id": "fuse395", + "name": "GPR8_CFG3", + "description": "General purpose fuse", + "index_int": "0x018B" + }, + { + "id": "fuse396", + "name": "GPR8_CFG4", + "description": "General purpose fuse", + "index_int": "0x018C" + }, + { + "id": "fuse397", + "name": "GPR8_CFG5", + "description": "General purpose fuse", + "index_int": "0x018D" + }, + { + "id": "fuse398", + "name": "GPR8_CFG6", + "description": "General purpose fuse", + "index_int": "0x018E" + }, + { + "id": "fuse399", + "name": "GPR8_CFG7", + "description": "General purpose fuse", + "index_int": "0x018F" + }, + { + "id": "fuse400", + "name": "GPR9_CFG0", + "description": "General purpose fuse", + "index_int": "0x0190" + }, + { + "id": "fuse401", + "name": "GPR9_CFG1", + "description": "General purpose fuse", + "index_int": "0x0191" + }, + { + "id": "fuse402", + "name": "GPR9_CFG2", + "description": "General purpose fuse", + "index_int": "0x0192" + }, + { + "id": "fuse403", + "name": "GPR9_CFG3", + "description": "General purpose fuse", + "index_int": "0x0193" + }, + { + "id": "fuse404", + "name": "GPR9_CFG4", + "description": "General purpose fuse", + "index_int": "0x0194" + }, + { + "id": "fuse405", + "name": "GPR9_CFG5", + "description": "General purpose fuse", + "index_int": "0x0195" + }, + { + "id": "fuse406", + "name": "GPR9_CFG6", + "description": "General purpose fuse", + "index_int": "0x0196" + }, + { + "id": "fuse407", + "name": "GPR9_CFG7", + "description": "General purpose fuse", + "index_int": "0x0197" + }, + { + "id": "fuse408", + "name": "GPR10_CFG0", + "description": "General purpose fuse", + "index_int": "0x0198" + }, + { + "id": "fuse409", + "name": "GPR10_CFG1", + "description": "General purpose fuse", + "index_int": "0x0199" + }, + { + "id": "fuse410", + "name": "GPR10_CFG2", + "description": "General purpose fuse", + "index_int": "0x019A" + }, + { + "id": "fuse411", + "name": "GPR10_CFG3", + "description": "General purpose fuse", + "index_int": "0x019B" + }, + { + "id": "fuse412", + "name": "GPR10_CFG4", + "description": "General purpose fuse", + "index_int": "0x019C" + }, + { + "id": "fuse413", + "name": "GPR10_CFG5", + "description": "General purpose fuse", + "index_int": "0x019D" + }, + { + "id": "fuse414", + "name": "GPR10_CFG6", + "description": "General purpose fuse", + "index_int": "0x019E" + }, + { + "id": "fuse415", + "name": "GPR10_CFG7", + "description": "General purpose fuse", + "index_int": "0x019F" + }, + { + "id": "fuse416", + "name": "GPR11_CFG0", + "description": "General purpose fuse", + "index_int": "0x01A0" + }, + { + "id": "fuse417", + "name": "GPR11_CFG1", + "description": "General purpose fuse", + "index_int": "0x01A1" + }, + { + "id": "fuse418", + "name": "GPR11_CFG2", + "description": "General purpose fuse", + "index_int": "0x01A2" + }, + { + "id": "fuse419", + "name": "GPR11_CFG3", + "description": "General purpose fuse", + "index_int": "0x01A3" + }, + { + "id": "fuse420", + "name": "GPR11_CFG4", + "description": "General purpose fuse", + "index_int": "0x01A4" + }, + { + "id": "fuse421", + "name": "GPR11_CFG5", + "description": "General purpose fuse", + "index_int": "0x01A5" + }, + { + "id": "fuse422", + "name": "GPR11_CFG6", + "description": "General purpose fuse", + "index_int": "0x01A6" + }, + { + "id": "fuse423", + "name": "GPR11_CFG7", + "description": "General purpose fuse", + "index_int": "0x01A7" + }, + { + "id": "fuse424", + "name": "GPR12_CFG0", + "description": "General purpose fuse", + "index_int": "0x01A8" + }, + { + "id": "fuse425", + "name": "GPR12_CFG1", + "description": "General purpose fuse", + "index_int": "0x01A9" + }, + { + "id": "fuse426", + "name": "GPR12_CFG2", + "description": "General purpose fuse", + "index_int": "0x01AA" + }, + { + "id": "fuse427", + "name": "GPR12_CFG3", + "description": "General purpose fuse", + "index_int": "0x01AB" + }, + { + "id": "fuse428", + "name": "GPR12_CFG4", + "description": "General purpose fuse", + "index_int": "0x01AC" + }, + { + "id": "fuse429", + "name": "GPR12_CFG5", + "description": "General purpose fuse", + "index_int": "0x01AD" + }, + { + "id": "fuse430", + "name": "GPR12_CFG6", + "description": "General purpose fuse", + "index_int": "0x01AE" + }, + { + "id": "fuse431", + "name": "GPR12_CFG7", + "description": "General purpose fuse", + "index_int": "0x01AF" + }, + { + "id": "fuse432", + "name": "GPR13_CFG0", + "description": "General purpose fuse", + "index_int": "0x01B0" + }, + { + "id": "fuse433", + "name": "GPR13_CFG1", + "description": "General purpose fuse", + "index_int": "0x01B1" + }, + { + "id": "fuse434", + "name": "GPR13_CFG2", + "description": "General purpose fuse", + "index_int": "0x01B2" + }, + { + "id": "fuse435", + "name": "GPR13_CFG3", + "description": "General purpose fuse", + "index_int": "0x01B3" + }, + { + "id": "fuse436", + "name": "GPR13_CFG4", + "description": "General purpose fuse", + "index_int": "0x01B4" + }, + { + "id": "fuse437", + "name": "GPR13_CFG5", + "description": "General purpose fuse", + "index_int": "0x01B5" + }, + { + "id": "fuse438", + "name": "GPR13_CFG6", + "description": "General purpose fuse", + "index_int": "0x01B6" + }, + { + "id": "fuse439", + "name": "GPR13_CFG7", + "description": "General purpose fuse", + "index_int": "0x01B7" + }, + { + "id": "fuse440", + "name": "GPR14_CFG0", + "description": "General purpose fuse", + "index_int": "0x01B8" + }, + { + "id": "fuse441", + "name": "GPR14_CFG1", + "description": "General purpose fuse", + "index_int": "0x01B9" + }, + { + "id": "fuse442", + "name": "GPR14_CFG2", + "description": "General purpose fuse", + "index_int": "0x01BA" + }, + { + "id": "fuse443", + "name": "GPR14_CFG3", + "description": "General purpose fuse", + "index_int": "0x01BB" + }, + { + "id": "fuse444", + "name": "GPR14_CFG4", + "description": "General purpose fuse", + "index_int": "0x01BC" + }, + { + "id": "fuse445", + "name": "GPR14_CFG5", + "description": "General purpose fuse", + "index_int": "0x01BD" + }, + { + "id": "fuse446", + "name": "GPR14_CFG6", + "description": "General purpose fuse", + "index_int": "0x01BE" + }, + { + "id": "fuse447", + "name": "GPR14_CFG7", + "description": "General purpose fuse", + "index_int": "0x01BF" + }, + { + "id": "fuse448", + "name": "GPR15_CFG0", + "description": "General purpose fuse", + "index_int": "0x01C0" + }, + { + "id": "fuse449", + "name": "GPR15_CFG1", + "description": "General purpose fuse", + "index_int": "0x01C1" + }, + { + "id": "fuse450", + "name": "GPR15_CFG2", + "description": "General purpose fuse", + "index_int": "0x01C2" + }, + { + "id": "fuse451", + "name": "GPR15_CFG3", + "description": "General purpose fuse", + "index_int": "0x01C3" + }, + { + "id": "fuse452", + "name": "GPR15_CFG4", + "description": "General purpose fuse", + "index_int": "0x01C4" + }, + { + "id": "fuse453", + "name": "GPR15_CFG5", + "description": "General purpose fuse", + "index_int": "0x01C5" + }, + { + "id": "fuse454", + "name": "GPR15_CFG6", + "description": "General purpose fuse", + "index_int": "0x01C6" + }, + { + "id": "fuse455", + "name": "GPR15_CFG7", + "description": "General purpose fuse", + "index_int": "0x01C7" + }, + { + "id": "fuse456", + "name": "GPR16_CFG0", + "description": "General purpose fuse", + "index_int": "0x01C8" + }, + { + "id": "fuse457", + "name": "GPR16_CFG1", + "description": "General purpose fuse", + "index_int": "0x01C9" + }, + { + "id": "fuse458", + "name": "GPR16_CFG2", + "description": "General purpose fuse", + "index_int": "0x01CA" + }, + { + "id": "fuse459", + "name": "GPR16_CFG3", + "description": "General purpose fuse", + "index_int": "0x01CB", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse460", + "name": "GPR16_CFG4", + "description": "General purpose fuse", + "index_int": "0x01CC", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse461", + "name": "GPR16_CFG5", + "description": "General purpose fuse", + "index_int": "0x01CD", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse462", + "name": "GPR16_CFG6", + "description": "General purpose fuse", + "index_int": "0x01CE" + }, + { + "id": "fuse463", + "name": "GPR16_CFG7", + "description": "General purpose fuse", + "index_int": "0x01CF" + }, + { + "id": "fuse464", + "name": "GPR17_CFG0", + "description": "General purpose fuse", + "index_int": "0x01D0" + }, + { + "id": "fuse465", + "name": "GPR17_CFG1", + "description": "General purpose fuse", + "index_int": "0x01D1" + }, + { + "id": "fuse466", + "name": "GPR17_CFG2", + "description": "General purpose fuse", + "index_int": "0x01D2" + }, + { + "id": "fuse467", + "name": "GPR17_CFG3", + "description": "General purpose fuse", + "index_int": "0x01D3" + }, + { + "id": "fuse468", + "name": "GPR17_CFG4", + "description": "General purpose fuse", + "index_int": "0x01D4" + }, + { + "id": "fuse469", + "name": "GPR17_CFG5", + "description": "General purpose fuse", + "index_int": "0x01D5" + }, + { + "id": "fuse470", + "name": "GPR17_CFG6", + "description": "General purpose fuse", + "index_int": "0x01D6" + }, + { + "id": "fuse471", + "name": "GPR17_CFG7", + "description": "General purpose fuse", + "index_int": "0x01D7" + }, + { + "id": "fuse472", + "name": "GPR18_CFG0", + "description": "General purpose fuse", + "index_int": "0x01D8", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse473", + "name": "GPR18_CFG1", + "description": "General purpose fuse", + "index_int": "0x01D9", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse474", + "name": "GPR18_CFG2", + "description": "General purpose fuse", + "index_int": "0x01DA" + }, + { + "id": "fuse475", + "name": "GPR18_CFG3", + "description": "General purpose fuse", + "index_int": "0x01DB" + }, + { + "id": "fuse476", + "name": "GPR18_CFG4", + "description": "General purpose fuse", + "index_int": "0x01DC" + }, + { + "id": "fuse477", + "name": "GPR18_CFG5", + "description": "General purpose fuse", + "index_int": "0x01DD" + }, + { + "id": "fuse478", + "name": "GPR18_CFG6", + "description": "General purpose fuse", + "index_int": "0x01DE" + }, + { + "id": "fuse479", + "name": "GPR18_CFG7", + "description": "General purpose fuse", + "index_int": "0x01DF" + }, + { + "id": "fuse480", + "name": "GPR19_CFG0", + "description": "General purpose fuse", + "index_int": "0x01E0", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse481", + "name": "GPR19_CFG1", + "description": "General purpose fuse", + "index_int": "0x01E1" + }, + { + "id": "fuse482", + "name": "GPR19_CFG2", + "description": "General purpose fuse", + "index_int": "0x01E2" + }, + { + "id": "fuse483", + "name": "GPR19_CFG3", + "description": "General purpose fuse", + "index_int": "0x01E3" + }, + { + "id": "fuse484", + "name": "GPR19_CFG4", + "description": "General purpose fuse", + "index_int": "0x01E4" + }, + { + "id": "fuse485", + "name": "GPR19_CFG5", + "description": "General purpose fuse", + "index_int": "0x01E5" + }, + { + "id": "fuse486", + "name": "GPR19_CFG6", + "description": "General purpose fuse", + "index_int": "0x01E6" + }, + { + "id": "fuse487", + "name": "GPR19_CFG7", + "description": "General purpose fuse", + "index_int": "0x01E7" + }, + { + "id": "Reserved488", + "name": "Reserved 0x1E8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E8", + "is_reserved": true + }, + { + "id": "Reserved489", + "name": "Reserved 0x1E9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E9", + "is_reserved": true + }, + { + "id": "Reserved490", + "name": "Reserved 0x1EA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EA", + "is_reserved": true + }, + { + "id": "Reserved491", + "name": "Reserved 0x1EB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EB", + "is_reserved": true + }, + { + "id": "Reserved492", + "name": "Reserved 0x1EC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EC", + "is_reserved": true + }, + { + "id": "Reserved493", + "name": "Reserved 0x1ED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01ED", + "is_reserved": true + }, + { + "id": "Reserved494", + "name": "Reserved 0x1EE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EE", + "is_reserved": true + }, + { + "id": "Reserved495", + "name": "Reserved 0x1EF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EF", + "is_reserved": true + }, + { + "id": "Reserved496", + "name": "Reserved 0x1F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F0", + "is_reserved": true + }, + { + "id": "Reserved497", + "name": "Reserved 0x1F1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F1", + "is_reserved": true + }, + { + "id": "Reserved498", + "name": "Reserved 0x1F2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F2", + "is_reserved": true + }, + { + "id": "Reserved499", + "name": "Reserved 0x1F3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F3", + "is_reserved": true + }, + { + "id": "Reserved500", + "name": "Reserved 0x1F4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F4", + "is_reserved": true + }, + { + "id": "Reserved501", + "name": "Reserved 0x1F5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F5", + "is_reserved": true + }, + { + "id": "Reserved502", + "name": "Reserved 0x1F6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F6", + "is_reserved": true + }, + { + "id": "Reserved503", + "name": "Reserved 0x1F7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F7", + "is_reserved": true + }, + { + "id": "Reserved504", + "name": "Reserved 0x1F8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F8", + "is_reserved": true + }, + { + "id": "Reserved505", + "name": "Reserved 0x1F9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F9", + "is_reserved": true + }, + { + "id": "Reserved506", + "name": "Reserved 0x1FA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FA", + "is_reserved": true + }, + { + "id": "Reserved507", + "name": "Reserved 0x1FB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FB", + "is_reserved": true + }, + { + "id": "Reserved508", + "name": "Reserved 0x1FC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FC", + "is_reserved": true + }, + { + "id": "Reserved509", + "name": "Reserved 0x1FD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FD", + "is_reserved": true + }, + { + "id": "Reserved510", + "name": "Reserved 0x1FE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FE", + "is_reserved": true + }, + { + "id": "Reserved511", + "name": "Reserved 0x1FF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FF", + "is_reserved": true + }, + { + "id": "Reserved512", + "name": "Reserved 0x200", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0200", + "is_reserved": true + }, + { + "id": "Reserved513", + "name": "Reserved 0x201", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0201", + "is_reserved": true + }, + { + "id": "Reserved514", + "name": "Reserved 0x202", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0202", + "is_reserved": true + }, + { + "id": "Reserved515", + "name": "Reserved 0x203", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0203", + "is_reserved": true + }, + { + "id": "Reserved516", + "name": "Reserved 0x204", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0204", + "is_reserved": true + }, + { + "id": "Reserved517", + "name": "Reserved 0x205", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0205", + "is_reserved": true + }, + { + "id": "Reserved518", + "name": "Reserved 0x206", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0206", + "is_reserved": true + }, + { + "id": "Reserved519", + "name": "Reserved 0x207", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0207", + "is_reserved": true + }, + { + "id": "Reserved520", + "name": "Reserved 0x208", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0208", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 20 + } + ] + }, + { + "id": "Reserved521", + "name": "Reserved 0x209", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0209", + "is_reserved": true + }, + { + "id": "Reserved522", + "name": "Reserved 0x20A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020A", + "is_reserved": true + }, + { + "id": "Reserved523", + "name": "Reserved 0x20B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020B", + "is_reserved": true + }, + { + "id": "Reserved524", + "name": "Reserved 0x20C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020C", + "is_reserved": true, + "bitfields": [ + { + "width": 9 + }, + { + "width": 23 + } + ] + }, + { + "id": "Reserved525", + "name": "Reserved 0x20D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved526", + "name": "Reserved 0x20E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved527", + "name": "Reserved 0x20F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x020F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 15 + } + ] + }, + { + "id": "Reserved528", + "name": "Reserved 0x210", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0210", + "is_reserved": true + }, + { + "id": "Reserved529", + "name": "Reserved 0x211", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0211", + "is_reserved": true + }, + { + "id": "fuse530", + "name": "COM_DEVICE_ID_CFG0", + "description": "COM_DEVICE_ID_CFG0", + "index_int": "0x0212", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse530-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse530-bits-16-31", + "name": "USB1_PID", + "description": "USB1 Product ID" + } + ] + }, + { + "id": "fuse531", + "name": "COM_DEVICE_ID_CFG1", + "description": "COM_DEVICE_ID_CFG1", + "index_int": "0x0213", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse531-bits-0-15", + "name": "USB2_PID", + "description": "USB2 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved532", + "name": "Reserved 0x214", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0214", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse533", + "name": "COM_DEVICE_ID_CFG3", + "description": "COM_DEVICE_ID_CFG3", + "index_int": "0x0215", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse533-bits-0-7", + "name": "MAC_ADDR_47_39", + "description": "MAC Base Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse533-bits-8-15", + "name": "MAC_ADDR_39_32", + "description": "MAC Base Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse533-bits-16-23", + "name": "MAC_ADDR_31_24", + "description": "MAC Base Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse533-bits-24-31", + "name": "MAC_ADDR_23_16", + "description": "MAC Base Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse534", + "name": "COM_DEVICE_ID_CFG4", + "description": "COM_DEVICE_ID_CFG4", + "index_int": "0x0216", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse534-bits-0-7", + "name": "MAC_ADDR_15_8", + "description": "MAC Base Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse534-bits-8-15", + "name": "MAC_ADDR_7_0", + "description": "MAC Base Address. Reserved for customer SW" + }, + { + "width": 8 + }, + { + "width": 8, + "id": "fuse534-bits-24-31", + "name": "NUM_OF_MACS", + "description": "Number of MACs supported. Reserved for customer SW" + } + ] + }, + { + "id": "Reserved535", + "name": "Reserved 0x217", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0217", + "is_reserved": true, + "bitfields": [ + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved536", + "name": "Reserved 0x218", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0218", + "is_reserved": true + }, + { + "id": "Reserved537", + "name": "Reserved 0x219", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0219", + "is_reserved": true + }, + { + "id": "Reserved538", + "name": "Reserved 0x21A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021A", + "is_reserved": true + }, + { + "id": "Reserved539", + "name": "Reserved 0x21B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021B", + "is_reserved": true + }, + { + "id": "Reserved540", + "name": "Reserved 0x21C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021C", + "is_reserved": true + }, + { + "id": "Reserved541", + "name": "Reserved 0x21D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021D", + "is_reserved": true + }, + { + "id": "Reserved542", + "name": "Reserved 0x21E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021E", + "is_reserved": true + }, + { + "id": "Reserved543", + "name": "Reserved 0x21F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x021F", + "is_reserved": true + }, + { + "id": "Reserved544", + "name": "Reserved 0x220", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0220", + "is_reserved": true + }, + { + "id": "Reserved545", + "name": "Reserved 0x221", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0221", + "is_reserved": true + }, + { + "id": "Reserved546", + "name": "Reserved 0x222", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0222", + "is_reserved": true + }, + { + "id": "Reserved547", + "name": "Reserved 0x223", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0223", + "is_reserved": true + }, + { + "id": "Reserved548", + "name": "Reserved 0x224", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0224", + "is_reserved": true + }, + { + "id": "Reserved549", + "name": "Reserved 0x225", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0225", + "is_reserved": true + }, + { + "id": "Reserved550", + "name": "Reserved 0x226", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0226", + "is_reserved": true + }, + { + "id": "Reserved551", + "name": "Reserved 0x227", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0227", + "is_reserved": true + }, + { + "id": "Reserved552", + "name": "Reserved 0x228", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0228", + "is_reserved": true + }, + { + "id": "Reserved553", + "name": "Reserved 0x229", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0229", + "is_reserved": true + }, + { + "id": "Reserved554", + "name": "Reserved 0x22A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022A", + "is_reserved": true + }, + { + "id": "Reserved555", + "name": "Reserved 0x22B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022B", + "is_reserved": true + }, + { + "id": "Reserved556", + "name": "Reserved 0x22C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022C", + "is_reserved": true + }, + { + "id": "Reserved557", + "name": "Reserved 0x22D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022D", + "is_reserved": true + }, + { + "id": "Reserved558", + "name": "Reserved 0x22E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022E", + "is_reserved": true + }, + { + "id": "Reserved559", + "name": "Reserved 0x22F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x022F", + "is_reserved": true + }, + { + "id": "Reserved560", + "name": "Reserved 0x230", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0294", + "is_reserved": true + }, + { + "id": "Reserved661", + "name": "Reserved 0x295", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0295", + "is_reserved": true + }, + { + "id": "Reserved662", + "name": "Reserved 0x296", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0296", + "is_reserved": true + }, + { + "id": "Reserved663", + "name": "Reserved 0x297", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0297", + "is_reserved": true + }, + { + "id": "Reserved664", + "name": "Reserved 0x298", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x029C", + "is_reserved": true + }, + { + "id": "Reserved669", + "name": "Reserved 0x29D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x029D", + "is_reserved": true + }, + { + "id": "Reserved670", + "name": "Reserved 0x29E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x029E", + "is_reserved": true + }, + { + "id": "Reserved671", + "name": "Reserved 0x29F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x029F", + "is_reserved": true + }, + { + "id": "Reserved672", + "name": "Reserved 0x2A0", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02A4", + "is_reserved": true + }, + { + "id": "Reserved677", + "name": "Reserved 0x2A5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02A5", + "is_reserved": true + }, + { + "id": "Reserved678", + "name": "Reserved 0x2A6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02A6", + "is_reserved": true + }, + { + "id": "Reserved679", + "name": "Reserved 0x2A7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02A7", + "is_reserved": true + }, + { + "id": "Reserved680", + "name": "Reserved 0x2A8", + "description": "Reserved for future use. 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B0", + "is_reserved": true + }, + { + "id": "Reserved689", + "name": "Reserved 0x2B1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B1", + "is_reserved": true + }, + { + "id": "Reserved690", + "name": "Reserved 0x2B2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B2", + "is_reserved": true + }, + { + "id": "Reserved691", + "name": "Reserved 0x2B3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B3", + "is_reserved": true + }, + { + "id": "Reserved692", + "name": "Reserved 0x2B4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B4", + "is_reserved": true + }, + { + "id": "Reserved693", + "name": "Reserved 0x2B5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B5", + "is_reserved": true + }, + { + "id": "Reserved694", + "name": "Reserved 0x2B6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B6", + "is_reserved": true + }, + { + "id": "Reserved695", + "name": "Reserved 0x2B7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B7", + "is_reserved": true + }, + { + "id": "Reserved696", + "name": "Reserved 0x2B8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B8", + "is_reserved": true + }, + { + "id": "Reserved697", + "name": "Reserved 0x2B9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02B9", + "is_reserved": true + }, + { + "id": "Reserved698", + "name": "Reserved 0x2BA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BA", + "is_reserved": true + }, + { + "id": "Reserved699", + "name": "Reserved 0x2BB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BB", + "is_reserved": true + }, + { + "id": "Reserved700", + "name": "Reserved 0x2BC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BC", + "is_reserved": true + }, + { + "id": "Reserved701", + "name": "Reserved 0x2BD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BD", + "is_reserved": true + }, + { + "id": "Reserved702", + "name": "Reserved 0x2BE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BE", + "is_reserved": true + }, + { + "id": "Reserved703", + "name": "Reserved 0x2BF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02BF", + "is_reserved": true + }, + { + "id": "Reserved704", + "name": "Reserved 0x2C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C0", + "is_reserved": true + }, + { + "id": "Reserved705", + "name": "Reserved 0x2C1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C1", + "is_reserved": true + }, + { + "id": "Reserved706", + "name": "Reserved 0x2C2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C2", + "is_reserved": true + }, + { + "id": "Reserved707", + "name": "Reserved 0x2C3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C3", + "is_reserved": true + }, + { + "id": "Reserved708", + "name": "Reserved 0x2C4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C4", + "is_reserved": true + }, + { + "id": "Reserved709", + "name": "Reserved 0x2C5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C5", + "is_reserved": true + }, + { + "id": "Reserved710", + "name": "Reserved 0x2C6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C6", + "is_reserved": true + }, + { + "id": "Reserved711", + "name": "Reserved 0x2C7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C7", + "is_reserved": true + }, + { + "id": "Reserved712", + "name": "Reserved 0x2C8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C8", + "is_reserved": true + }, + { + "id": "Reserved713", + "name": "Reserved 0x2C9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02C9", + "is_reserved": true + }, + { + "id": "Reserved714", + "name": "Reserved 0x2CA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CA", + "is_reserved": true + }, + { + "id": "Reserved715", + "name": "Reserved 0x2CB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CB", + "is_reserved": true + }, + { + "id": "Reserved716", + "name": "Reserved 0x2CC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CC", + "is_reserved": true + }, + { + "id": "Reserved717", + "name": "Reserved 0x2CD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CD", + "is_reserved": true + }, + { + "id": "Reserved718", + "name": "Reserved 0x2CE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CE", + "is_reserved": true + }, + { + "id": "Reserved719", + "name": "Reserved 0x2CF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02CF", + "is_reserved": true + }, + { + "id": "Reserved720", + "name": "Reserved 0x2D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D0", + "is_reserved": true + }, + { + "id": "Reserved721", + "name": "Reserved 0x2D1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D1", + "is_reserved": true + }, + { + "id": "Reserved722", + "name": "Reserved 0x2D2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D2", + "is_reserved": true + }, + { + "id": "Reserved723", + "name": "Reserved 0x2D3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D3", + "is_reserved": true + }, + { + "id": "Reserved724", + "name": "Reserved 0x2D4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D4", + "is_reserved": true + }, + { + "id": "Reserved725", + "name": "Reserved 0x2D5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D5", + "is_reserved": true + }, + { + "id": "Reserved726", + "name": "Reserved 0x2D6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D6", + "is_reserved": true + }, + { + "id": "Reserved727", + "name": "Reserved 0x2D7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D7", + "is_reserved": true + }, + { + "id": "Reserved728", + "name": "Reserved 0x2D8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D8", + "is_reserved": true + }, + { + "id": "Reserved729", + "name": "Reserved 0x2D9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02D9", + "is_reserved": true + }, + { + "id": "Reserved730", + "name": "Reserved 0x2DA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DA", + "is_reserved": true + }, + { + "id": "Reserved731", + "name": "Reserved 0x2DB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DB", + "is_reserved": true + }, + { + "id": "Reserved732", + "name": "Reserved 0x2DC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DC", + "is_reserved": true + }, + { + "id": "Reserved733", + "name": "Reserved 0x2DD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DD", + "is_reserved": true + }, + { + "id": "Reserved734", + "name": "Reserved 0x2DE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DE", + "is_reserved": true + }, + { + "id": "Reserved735", + "name": "Reserved 0x2DF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02DF", + "is_reserved": true + }, + { + "id": "Reserved736", + "name": "Reserved 0x2E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E0", + "is_reserved": true + }, + { + "id": "Reserved737", + "name": "Reserved 0x2E1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E1", + "is_reserved": true + }, + { + "id": "Reserved738", + "name": "Reserved 0x2E2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E2", + "is_reserved": true + }, + { + "id": "Reserved739", + "name": "Reserved 0x2E3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E3", + "is_reserved": true + }, + { + "id": "Reserved740", + "name": "Reserved 0x2E4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E4", + "is_reserved": true + }, + { + "id": "Reserved741", + "name": "Reserved 0x2E5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E5", + "is_reserved": true + }, + { + "id": "Reserved742", + "name": "Reserved 0x2E6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E6", + "is_reserved": true + }, + { + "id": "Reserved743", + "name": "Reserved 0x2E7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E7", + "is_reserved": true + }, + { + "id": "Reserved744", + "name": "Reserved 0x2E8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E8", + "is_reserved": true + }, + { + "id": "Reserved745", + "name": "Reserved 0x2E9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02E9", + "is_reserved": true + }, + { + "id": "Reserved746", + "name": "Reserved 0x2EA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02EA", + "is_reserved": true + }, + { + "id": "Reserved747", + "name": "Reserved 0x2EB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02EB", + "is_reserved": true + }, + { + "id": "Reserved748", + "name": "Reserved 0x2EC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02EC", + "is_reserved": true + }, + { + "id": "Reserved749", + "name": "Reserved 0x2ED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02ED", + "is_reserved": true + }, + { + "id": "Reserved750", + "name": "Reserved 0x2EE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02EE", + "is_reserved": true + }, + { + "id": "Reserved751", + "name": "Reserved 0x2EF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x02EF", + "is_reserved": true + }, + { + "id": "Reserved752", + "name": "Reserved 0x2F0", + "description": "Reserved for future use. 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at 0x20000000 for M7 view + cm7_dtcm_ns: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + # M7 ITCM (256KB) - at 0x00000000 for M7 view + cm7_itcm_ns: + start_int: 0x00000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + # OCRAM (352KB) + ocram_ns: + start_int: 0x20480000 + size_int: 0x58000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x30480000 + size_int: 0x58000 + external: false + non_xip_type: int_ram + # External Serial Peripheral Interface (XSPI1/FlexSPI1) + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + # Neutron SRAM (400KB) + neutron_sram_ns: + start_int: 0x4AA00000 + size_int: 0x64000 + external: false + mirror_of: neutron_sram_s + non_xip_type: int_ram + neutron_sram_s: + start_int: 0x5AA00000 + size_int: 0x64000 + external: false + non_xip_type: int_ram + # # OCRAM_C (96KB) + # ocram_c_ns: + # start_int: 0x4AF80000 + # size_int: 0x18000 + # external: false + # mirror_of: ocram_c_s + # non_xip_type: int_ram + # ocram_c_s: + # start_int: 0x5AF80000 + # size_int: 0x18000 + # external: false + # non_xip_type: int_ram + # # OCRAM_D (36KB) + # ocram_d_ns: + # start_int: 0x4B300000 + # size_int: 0x9000 + # external: false + # mirror_of: ocram_d_s + # non_xip_type: int_ram + # ocram_d_s: + # start_int: 0x5B300000 + # size_int: 0x9000 + # external: false + # non_xip_type: int_ram + # DRAM regions (256MB each) + dram1_ns: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram1_s: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_ns: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_s: + start_int: 0xB0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_ns: + start_int: 0xC0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_s: + start_int: 0xD0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + isp: + rom: + protocol: sdps + interfaces: [usb] + usb: + - vid: 0x1FC9 + pid: 0x0028 + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: otfad1_key + name: OTFAD1_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD1 Key known as KEK. + sub_regs: [fuse184, fuse185, fuse186, fuse187] + - uid: srkh + name: SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + "fuse136", + "fuse137", + "fuse138", + "fuse139", + "fuse140", + "fuse141", + "fuse142", + "fuse143", + ] + + - uid: pqc_srkh + name: PQC_SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse448", + "fuse449", + "fuse450", + "fuse451", + "fuse452", + "fuse453", + "fuse454", + "fuse455", + "fuse456", + "fuse457", + "fuse458", + "fuse459", + "fuse460", + "fuse461", + "fuse462", + "fuse463", + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x9280_0000 + size: 0x30000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab_v2" + + # ======== DAT section ======== + dat: + socc: 0x4D58005F # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + auth_beacon_length: 4 # The length in bytes of authentication beacon + ele_cnt_version: 2 + dac_version_is_swapped: True + sub_features: ["ele_pqc"] + test_address: 0x2048_0000 + dmbox_ap_ix: 0 + dac_rot_type: not_available # The Dac packet doesn't contains the ROT hash + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: ../mimx9596/fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== AHAB section ======== + ahab: + sub_features: [ahab_image, certificate_supported] + containers_max_cnt: 3 + valid_offset_minimal_alignment: 0x400 + container_types: [2, 1] # Supported container types (keep order 2, 1 - this defines default 2) + fuses_0: + _name: "AHAB SRKH" + srkh: "__srk_hash0" # SRK hash fuse + fuses_1: + _name: "AHAB SRKH PQC" + pqc_srkh: "__srk_hash1" # SRK PQC hash fuse + + core_ids: + DUMMY_CORE: [0, "dummy", "Virtual dummy core (used for data)"] + CORTEX_M33: [1, "cortex-m33", "Cortex M33 - Boot core"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + ELE: [6, "ele", "EdgeLock Enclave"] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + CORTEX_M7_1: [11, "cortex-m7-1", "Cortex M7 Core ID 1"] + DDR: [14, "ddr", "DDR Core"] + + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + OEI: [0x05, oei, OEI Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION_FCB_CHK: + [0x08, dek_validation_fcb_chk, DEK validation FCB check Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + EXECUTABLE_FAST_BOOT_IMAGE: + [0x0A, executable_fast_boot_image, Executable fast boot Image] + OEI_DDR: [0x0D, oei_ddr, Executable boot Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + + ele: + ELE_AS_IMAGE: [0x05, ele_as_image, EdgeLock Enclave Image in OEM Image] + ELE: [0x06, ele, EdgeLock Enclave Image] + + v2x: + V2X_AS_IMAGE: [0x0A, v2x_as_image, V2X image as OEM Image] + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + oei_ddr_load_address: 0x1ffc0000 + oei_ddr_entry_point: 0x1ffc0001 + oei_ddr_core_id: cortex-m33 + oei_ddr_image_type: oei + oei_ddr_image_size_alignment: 0x400 + oei_ddr_gap_after_image: 0 + oei_ddr_qb_data_dummy: True + + oei_tcm_load_address: 0x1ffc0000 + oei_tcm_entry_point: 0x1ffc0001 + oei_tcm_core_id: cortex-m33 + oei_tcm_image_type: oei + oei_tcm_image_size_alignment: 0x400 + + system_manager_load_address: 0x1ffc0000 + system_manager_entry_point: 0x1ffc0000 + system_manager_core_id: cortex-m33 + system_manager_image_size_alignment: 0x400 + + cortex_m7_app_load_address: 0x303c0000 + cortex_m7_app_entry_point: 0 + cortex_m7_app_core_id: cortex-m7-1 + cortex_m7_app_meta_data_start_cpu_id: 1 + cortex_m7_app_image_size_alignment: 0x400 + + spl_load_address: 0x20480000 + spl_core_id: cortex-a55 + spl_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + v2x_dummy_load_address: 0x8b000000 + v2x_dummy_image_type: v2x_dummy + v2x_dummy_core_id: cortex-m33 + + atf_load_address: 0x8a200000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + + uboot_load_address: 0x90200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x8c000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + + kernel_load_address: 0x90400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 2 + kernel_chunk_size: 0x700000 + kernel_revisions_to_split: [a0, a1] + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x93000000 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_entry_point: 0x0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: + [ + double_authentication, + oei_ddr, + oei_tcm, + system_manager, + cortex_m7_app, + v2x_dummy, + spl, + atf, + uboot, + tee, + kernel, + dtb, + ] + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + # flexspi_nand: + # segments: + # xmcd: 0x00 + # primary_image_container_set: 0x400 + # secondary_image_container_set_ahab: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI1/2for Low power boot and LPSPI/3/4 for Single boot. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 8 + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + + fuses_1: # Fuses for OTFAD1 + _name: Configuration of fuses for OTFAD1 + _no_verify: True + fuse188: # OTFAD CFG Fuse + fuse188-bit-3: 1 # OTFAD Enable + fuse188-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse188-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse189: __key_scramble_mask # OTFAD Scramble Key + otfad1_key: __kek # OTFAD Key + + additional_template: ["otfad_scramble"] + additional_template_text: | + Is important to use physical addresses (non-secure) in settings of OTFAD to proper run the decryption on device. + For example: + In case of using FlexSPI2 the secure base address address is 0x1400_0000. But in setting of the OTFAD use 0x0400_0000 as a base address. + The code must be still linked on secure base address 0x1400_0000 to proper run of OTFAD hardware. + + Same is for FlexSPI1, but instead of 0x3800_0000 base address, the 0x2800_0000 must be used in OTFAD configuration. + + # # ======== Device Hardware Security Module (HSM) section ======== + # devhsm: EdgeLock 2 Go + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x9280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx95294/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx95294/fuses.json new file mode 100644 index 0000000..f8164e4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx95294/fuses.json @@ -0,0 +1,11632 @@ +{ + "cpu": "mimx95294", + "shadow_reg_base_addr_int": "0x00000000", + "groups": [ + { + "group": { + "name": "LOCK_CFG", + "description": "LOCK_CFG" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "shadow_reg_offset_int": "0", + "access": "RO", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "shadow_reg_offset_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse1-bits3-5", + "name": "SENTINEL_MISC1_LOCK", + "description": "Sentinel Misc. Config lock 1 - Used to lock OEM owned configuration fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "shadow_reg_offset_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse2-bits6-8", + "name": "SENTINEL_IPED_KEY_LOCK", + "description": "Sentinel IPED0 config lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved3", + "name": "Reserved 0x3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0003", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4", + "index_int": "0x0004", + "shadow_reg_offset_int": "0x0010", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse4-bits12-14", + "name": "SENTINEL_OEM_SRKH0_LOCK", + "description": "Sentinel OEM SRK Hash Lock (First bank)", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0005", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse6", + "name": "LOCK_CFG6", + "description": "LOCK_CFG6", + "index_int": "0x0006", + "shadow_reg_offset_int": "0x0018", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse6-bits9-11", + "name": "GPR0_LOCK", + "description": "GPR0 lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse7", + "name": "LOCK_CFG7", + "description": "LOCK_CFG7", + "index_int": "0x0007", + "shadow_reg_offset_int": "0x001C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse7-bits3-5", + "name": "OEM_SW_CFG_LOCK", + "description": "OEM SW CFG lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse7-bits6-8", + "name": "BOOT_CFG_LOCK", + "description": "Boot config lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse7-bits9-11", + "name": "BOOT2_CFG_LOCK", + "description": "Boot config lock Second set", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse7-bits12-14", + "name": "GPR1_LOCK", + "description": "GPR 1 lock bis", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse8", + "name": "LOCK_CFG8", + "description": "LOCK_CFG8", + "index_int": "0x0008", + "shadow_reg_offset_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse8-bits9-11", + "name": "SENTINEL_OEM_SRKH1_LOCK", + "description": "Sentinel OEM SRKH Lock (Second set for SRKH[511:256])", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse8-bits12-14", + "name": "SENTINEL_OEM_PQC_SRKH_LOCK", + "description": "OEM PQC hash of public keys" + }, + { + "width": 1, + "access": "RO" + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG9", + "description": "LOCK_CFG9", + "index_int": "0x0009", + "shadow_reg_offset_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse9-bits9-11", + "name": "V2X_SHE_MC_LOCK", + "description": "V2X SHE monotonic counter lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse9-bits12-14", + "name": "V2X_SHE_KEY_LOCK", + "description": "V2X SHE key lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1, + "access": "RO" + } + ] + }, + { + "id": "fuse10", + "name": "LOCK_CFG10", + "description": "LOCK_CFG10", + "index_int": "0x000A", + "shadow_reg_offset_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse10-bits0-2", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID0 Lock - Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse10-bits3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 3, + "id": "fuse10-bits9-11", + "name": "BBSM_MC_LOCK", + "description": "BBSM monotonic counter lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "access": "RO" + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse11", + "name": "LOCK_CFG11", + "description": "LOCK_CFG11", + "index_int": "0x000B", + "shadow_reg_offset_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse11-bits0-2", + "name": "GPR2_LOCK", + "description": "General Purpose group 2 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse11-bits3-5", + "name": "GPR3_LOCK", + "description": "General Purpose group 3 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse11-bits6-8", + "name": "GPR4_LOCK", + "description": "General Purpose group 4 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse11-bits9-11", + "name": "GPR5_LOCK", + "description": "General Purpose group 5 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse11-bits12-14", + "name": "GPR6_LOCK", + "description": "General Purpose group 6 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "TESTER0_CFG", + "description": "TESTER0_CFG" + }, + "registers": [ + { + "id": "Reserved12", + "name": "Reserved 0xC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0xD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0xE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved15", + "name": "Reserved 0xF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x000F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved16", + "name": "Reserved 0x10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0010", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 19 + } + ] + } + ] + }, + { + "group": { + "name": "HSW_CFG", + "description": "HSW_CFG" + }, + "registers": [ + { + "id": "Reserved17", + "name": "Reserved 0x11", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0011", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 2 + }, + { + "width": 6 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x12", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0012", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x13", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0013", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x14", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0014", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 21 + } + ] + } + ] + }, + { + "group": { + "name": "ANALOG_CFG", + "description": "ANALOG_CFG" + }, + "registers": [ + { + "id": "Reserved21", + "name": "Reserved 0x15", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0015", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x16", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0016", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x17", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0017", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved38", + "name": "Reserved 0x26", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0026", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved39", + "name": "Reserved 0x27", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0027", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved40", + "name": "Reserved 0x28", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0028", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved41", + "name": "Reserved 0x29", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0029", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved42", + "name": "Reserved 0x2A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 12 + }, + { + "width": 6 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved43", + "name": "Reserved 0x2B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved44", + "name": "Reserved 0x2C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "BOOT_CFG" + }, + "registers": [ + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0018", + "shadow_reg_offset_int": "0x0060", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse24-bits0-3", + "name": "BOOT_MODE_FUSES", + "description": "Boot_Mode_Fuses" + }, + { + "width": 1, + "id": "fuse24-bit4", + "name": "OVERRIDE_XSPI_NOR_BOOT_SELECTION", + "description": "Override xSPI NOR Boot Selection" + }, + { + "width": 2, + "id": "fuse24-bits5-6", + "name": "XSPI_NOR_BOOT_OVERRIDE_SELECTION", + "description": "xSPI NOR Boot Override Selection" + }, + { + "width": 1, + "id": "fuse24-bit7", + "name": "XSPI_NAND_4K_PAGE_SELECTION", + "description": "xSPI NAND 4K Page Selection" + }, + { + "width": 1, + "id": "fuse24-bit8", + "name": "USDHC_DEVICE_TYPE", + "description": "uSDHC_Device_Type" + }, + { + "width": 1, + "id": "fuse24-bit9", + "name": "XSPI_NOR_DATA_IOMUX_SION_EN", + "description": "xSPI NOR data IOMUX SION EN" + }, + { + "width": 2, + "id": "fuse24-bits10-11", + "name": "XSPI_NOR_FCB_OFFSET", + "description": "xSPI NOR FCB offset" + }, + { + "width": 3, + "id": "fuse24-bits12-14", + "name": "XSPI_NOR_AUTO_PROBE_FEQ_SEL", + "description": "xSPI autoprobe freq sel" + }, + { + "width": 1, + "id": "fuse24-bit15", + "name": "XSPI_NOR_FCB_CHECK", + "description": "xSPI FCB copy flag" + }, + { + "width": 1, + "id": "fuse24-bit16", + "name": "SD_LOOPBACK_CLOCK_SOURCE_SEL", + "description": "SD loopback clock source sel" + }, + { + "width": 2, + "id": "fuse24-bits17-18", + "name": "SD_SPEED_SELECTION", + "description": "SD speed selection" + }, + { + "width": 1, + "id": "fuse24-bit19", + "name": "EMMC_SPEED_SELECTION", + "description": "eMMC speed selection" + }, + { + "width": 1, + "id": "fuse24-bit20", + "name": "EMMC_FAST_BOOT", + "description": "eMMC fast boot" + }, + { + "width": 1, + "id": "fuse24-bit21", + "name": "BT_FREQ_SEL_1", + "description": "Boot frequency / voltage select[0]" + }, + { + "width": 1, + "id": "fuse24-bit22", + "name": "EMMC_VOLTAGE_SELECTION", + "description": "eMMC voltage select" + }, + { + "width": 5, + "id": "fuse24-bits23-27", + "name": "XSPI_NOR_RESET_PIN_SELECTIONS", + "description": "xSPI NOR reset pin selections" + }, + { + "width": 1, + "id": "fuse24-bit28", + "name": "BT_FREQ_SEL", + "description": "Boot frequency / voltage select [0]" + }, + { + "width": 1, + "id": "fuse24-bit29", + "name": "BT_FUSE_SEL", + "description": "Boot Fuse indication" + }, + { + "width": 1, + "id": "fuse24-bit30", + "name": "FORCE_BOOT_FROM_FUSE", + "description": "Force boot from fuse" + }, + { + "width": 1, + "id": "fuse24-bit31", + "name": "FORCE_SERIAL_DOWNLOAD", + "description": "Force serial download", + "access": "RO" + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0019", + "shadow_reg_offset_int": "0x0064", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse25-bit0", + "name": "FAST_BOOT_ACKNOWLEDGE_DISABLE", + "description": "Fast boot acknowledge disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot Ack Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot Ack Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit1", + "name": "USDHC2_DEVICE_TYPE", + "description": "uSDHC 2 Device Type", + "values": [ + { + "name": "SD_DEVICE", + "value": 0, + "description": "SD" + }, + { + "name": "EMMC_DEVICE", + "value": 1, + "description": "eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit2", + "name": "USDHC_POWER_ON_POLARITY", + "description": "uSDHC power on polarity", + "values": [ + { + "name": "LOW", + "value": 0, + "description": "Low" + }, + { + "name": "HIGH", + "value": 1, + "description": "High" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit3", + "name": "USDHC_POWER_CYCLEDELAY", + "description": "uSDHC power cycle delay", + "values": [ + { + "name": "INTERVAL_5MS", + "value": 0, + "description": "5 ms" + }, + { + "name": "INTERVAL_2_5MS", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse25-bits4-5", + "name": "USDHC_POWER_CYCLE_INTERVAL", + "description": "uSDHC power cycle interval", + "values": [ + { + "name": "INTERVAL_20MS", + "value": 0, + "description": "20 ms" + }, + { + "name": "INTERVAL_10MS", + "value": 1, + "description": "10 ms" + } + ] + }, + { + "width": 2, + "id": "fuse25-bits6-7", + "name": "SD_CALIBRATION_STEP", + "description": "SD calibration step", + "values": [ + { + "name": "1_delay_cell", + "value": 0, + "description": "1 delay cell" + }, + { + "name": "2_delay_cell", + "value": 1, + "description": "2 delay cell" + } + ] + }, + { + "width": 8, + "id": "fuse25-bits8-15", + "name": "USDHC_PAD_SETTINGS_LOW_BITS", + "description": "uSDHC pad settings low bits. The override value for uSDHC pad settings", + "values": [ + { + "name": "11111111", + "value": 0, + "description": "11111111" + } + ] + }, + { + "width": 4, + "id": "fuse25-bits16-19", + "name": "USDHC_PAD_SETTING_HIGH_BITS", + "description": "uSDHC pad settings high bits. The override value for uSDHC pad settings", + "values": [ + { + "name": "1111", + "value": 0, + "description": "1111" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit20", + "name": "POWER_CYCLE_ENABLE", + "description": "Power cycle enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "No power cycle" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit21", + "name": "USDHC_OVERRIDE_PAD_SETTINGS", + "description": "uSDHC override pad settings" + }, + { + "width": 1, + "id": "fuse25-bit22", + "name": "USDHC_DLL_ENABLE", + "description": "uSDHC DLL enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit23", + "name": "BT_FREQ_SET", + "description": "BT_FREQ_SET", + "values": [ + { + "name": "SET", + "value": 1, + "description": "BT_FREQ_SEL_1 and BT_FREQ_SEL have been set to indicate boot mode voltage." + }, + { + "name": "NO_SET", + "value": 0, + "description": "BT_FREQ_SEL_1 and BT_FREQ_SEL have not been set" + } + ] + }, + { + "width": 7, + "id": "fuse25-bits24-30", + "name": "MMC_DLL_DLY", + "description": "MMC DLL delay : Delay target for uSDHC DLL, it is applied to slave mode target delay or override mode target delay depends on DLL Override fuse bit value", + "values": [ + { + "name": "1111111", + "value": 0, + "description": "1111111" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit31", + "name": "USDHC_DLL_SELECT", + "description": "uSDHC DLL select", + "values": [ + { + "name": "DLL_SLAVE", + "value": 0, + "description": "DLL Slave Mode for" + }, + { + "name": "DLL_OVERRIDE", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x001A", + "shadow_reg_offset_int": "0x0068", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse26-bits0-1", + "name": "XSPI_NAND_COLUMN_ADDRESS_WIDTH", + "description": "xSPI NAND Column Address Width" + }, + { + "width": 2, + "id": "fuse26-bits2-3", + "name": "XSPI_NAND_CS_INTERVAL", + "description": "xSPI NAND CS Interval" + }, + { + "width": 2, + "id": "fuse26-bits4-5", + "name": "XSPI_NAND_SEARCH_COUNT", + "description": "xSPI NAND Search Count" + }, + { + "width": 2, + "id": "fuse26-bits6-7", + "name": "XSPI_NAND_SEARCH_STRIDE", + "description": "xSPI NAND Search Stride" + }, + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse26-bit19", + "name": "RECOVERY_SPI_ADDRESSING", + "description": "Recovery SPI addressing" + }, + { + "width": 1, + "id": "fuse26-bit20", + "name": "XSPI_NOR_AUTO_PROBE_EN", + "description": "xSPI NOR auto probe enable" + }, + { + "width": 3, + "id": "fuse26-bits21-23", + "name": "XSPI_NAND_BUSY_BIT_OFFSET_OVERRIDE", + "description": "xSPI NAND busy bit offset override" + }, + { + "width": 1, + "id": "fuse26-bit24", + "name": "RECOVERY_CS_SELECT", + "description": "Recovery CS select" + }, + { + "width": 1, + "id": "fuse26-bit25", + "name": "POWER_UP_M7", + "description": "Power up M7" + }, + { + "width": 2, + "id": "fuse26-bits26-27", + "name": "RECOVERY_PORT_SELECT", + "description": "Recovery Port Select" + }, + { + "width": 4, + "id": "fuse26-bits28-31", + "name": "XSPI_DUMMY_CYCLE_SEL", + "description": "xSPI Dummy Cycle Select" + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_CFG3", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x001B", + "shadow_reg_offset_int": "0x006C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse27-bits0-2", + "name": "XSPI_NOR_RESET_PORT", + "description": "xSPI NOR Reset Pin Selection" + }, + { + "width": 3, + "id": "fuse27-bits3-5", + "name": "XSPI_NOR_AUTO_PROBE_TYPE", + "description": "xSPI NOR AUTO PROBE type" + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse27-bits7-8", + "name": "XSPI_HOLD_TIME", + "description": "xSPI Auto probe DDR support" + }, + { + "width": 1, + "id": "fuse27-bit9", + "name": "XSPI_DUMMY_CYCLE_UPPER_SEL", + "description": "xSPI dummy cycle select 1" + }, + { + "width": 1, + "id": "fuse27-bit10", + "name": "EDMA_INIT_M7_TCM", + "description": "eDMA initialize M7 TCM" + }, + { + "width": 2 + }, + { + "width": 4, + "id": "fuse27-bits13-16", + "name": "XSPI_DELAY_CELL_NUM", + "description": "XSPI_DELAY_CELL_NUM" + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse27-bits20-22", + "name": "XSPI_FLASH_ENHANCE_MODE", + "description": "XSPI_FLASH_ENHANCE_MODE" + }, + { + "width": 1 + }, + { + "width": 8, + "id": "fuse27-bits24-31", + "name": "CA55_MFI_MAX_FREQ_FUSE", + "description": "A55 Max. Frequency Support" + } + ] + }, + { + "id": "fuse28", + "name": "BOOT_CFG4", + "description": "BOOT Configuration", + "index_int": "0x001C", + "shadow_reg_offset_int": "0x0070", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse28-bits0-31", + "name": "XSPI_FLASH_DLLCRA", + "description": "The fuse value is used to override the XSPI register DLLCRA in SDR mode.\nIf a customizable value is available in FCB, it will be used to override the register." + } + ] + }, + { + "id": "fuse29", + "name": "BOOT_CFG5", + "description": "BOOT Configuration", + "index_int": "0x001D", + "shadow_reg_offset_int": "0x0074", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse30", + "name": "BOOT_CFG6", + "description": "BOOT Configuration", + "index_int": "0x001E", + "shadow_reg_offset_int": "0x0078", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse31", + "name": "BOOT_CFG7", + "description": "BOOT Configuration", + "index_int": "0x001F", + "shadow_reg_offset_int": "0x007C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0020", + "shadow_reg_offset_int": "0x0080", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit1", + "name": "BBNSM_EN", + "description": "BBNSM enable" + }, + { + "width": 1, + "id": "fuse32-bit2", + "name": "SION_EN", + "description": "SION_EN" + }, + { + "width": 1, + "id": "fuse32-bit3", + "name": "CCM_CLKO_MUX", + "description": "CCM_CLKO_MUX" + }, + { + "width": 1, + "id": "fuse32-bit4", + "name": "ROMCP_LOCK", + "description": "ROMCP_LOCK" + }, + { + "width": 3 + }, + { + "width": 8, + "id": "fuse32-bits8-15", + "name": "SECONDARY_BOOT_OFFSET", + "description": "Secondary boot offset" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit19", + "name": "M33_RECOVERY_DISABLE", + "description": "Disable A55 SPI recovery" + }, + { + "width": 1, + "id": "fuse32-bit20", + "name": "M33_RECOVERY_DEVICE", + "description": "Disable M33 SPI recovery" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit22", + "name": "AHAB_REAUTH", + "description": "AHAB reauth" + }, + { + "width": 1, + "id": "fuse32-bit23", + "name": "M33_WDOG_ENABLE", + "description": "M33 WDOG enable" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit25", + "name": "M33_I_CACHE_DIS", + "description": "M33 I cache dis" + }, + { + "width": 2, + "id": "fuse32-bits26-27", + "name": "WDOG_TIMEOUT_SELECT", + "description": "WDOG timeout select" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit29", + "name": "USB_HID_EP1_OUT_DISABLE", + "description": "USB HID EP1 out disable" + }, + { + "width": 1, + "id": "fuse32-bit30", + "name": "PLL_LATE_EN", + "description": "PLL late en" + }, + { + "width": 1, + "id": "fuse32-bit31", + "name": "M33_TCM_MBIST_AT_BOOT_EN", + "description": "M33 TCM MBIST at boot enable" + } + ] + }, + { + "id": "fuse33", + "name": "BOOT_CFG9", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0021", + "shadow_reg_offset_int": "0x0084", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit6", + "name": "M33_TZ_WDOG_ENABLE", + "description": "M33 TZ WDOG Enable (non-ROM)" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit8", + "name": "CM33_RST_RELEASE_ACK", + "description": "CM33 RST Release ACK (non-ROM)", + "values": [ + { + "name": "NO_ACK", + "value": 0, + "description": "No Ack from Sentinel to release M33 Reset" + }, + { + "name": "ACK_RECEIVED", + "value": 1, + "description": "Ack from Sentinel to release M33 Reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit11", + "name": "REC_DEVICE_BOOT_OFFSET_ENABLE", + "description": "Enable application of device boot offset for USB, and LPSPI boot devices" + }, + { + "width": 1, + "id": "fuse33-bit12", + "name": "DEVICE_BOOT_OFFSET_MULTIPLIER", + "description": "defining boot offset multiplier" + }, + { + "width": 3, + "id": "fuse33-bits13-15", + "name": "DEVICE_BOOT_OFFSET", + "description": "device boot offset" + }, + { + "width": 8 + }, + { + "width": 1, + "id": "fuse33-bit24", + "name": "SENTINEL_SRAM_REN_PWRDN", + "description": "Enable double authentication of NXP code." + }, + { + "width": 1, + "id": "fuse33-bit25", + "name": "DOUBLE_AUTH_EN", + "description": "Enable double authentication of NXP code." + }, + { + "width": 1, + "id": "fuse33-bit26", + "name": "IPED0_ENABLE", + "description": "IPED0_ENABLE" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 3 + } + ] + }, + { + "id": "fuse34", + "name": "BOOT_CFG10", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0022", + "shadow_reg_offset_int": "0x0088", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 2 + }, + { + "width": 1, + "id": "fuse34-bit2", + "name": "SDP_DISABLE", + "description": "if blow to 1, ROM code disable USB SDP (Serial download protocol) at all." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 27, + "access": "RO" + } + ] + }, + { + "id": "fuse35", + "name": "BOOT_CFG11", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0023", + "shadow_reg_offset_int": "0x008C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse35-bit1", + "name": "USB_SDP_PORT_SEL", + "description": "USB1 Serial Download Port Disable" + }, + { + "width": 28 + }, + { + "width": 1, + "id": "fuse35-bit30", + "name": "XSPI_SWRST_EN", + "description": "XSPI_SWRST_EN" + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "RESERVED", + "description": "RESERVED" + }, + "registers": [ + { + "id": "fuse36", + "name": "GPR0_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0024", + "shadow_reg_offset_int": "0x0090", + "access": "RO", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse36-bits0-15", + "name": "GPR0_CFG0", + "description": "GPR0_CFG0" + } + ] + }, + { + "id": "fuse37", + "name": "GPR0_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0025", + "shadow_reg_offset_int": "0x0094", + "access": "RO", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse37-bits0-15", + "name": "GPR0_CFG1", + "description": "GPR0_CFG1" + } + ] + }, + { + "id": "Reserved80", + "name": "Reserved 0x50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0050", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved81", + "name": "Reserved 0x51", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0051", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved82", + "name": "Reserved 0x52", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0052", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved83", + "name": "Reserved 0x53", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0053", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved84", + "name": "Reserved 0x54", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0054", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved85", + "name": "Reserved 0x55", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0055", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved86", + "name": "Reserved 0x56", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0056", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved87", + "name": "Reserved 0x57", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0057", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved136", + "name": "Reserved 0x88", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0088", + "is_reserved": true + }, + { + "id": "Reserved137", + "name": "Reserved 0x89", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0089", + "is_reserved": true + }, + { + "id": "Reserved138", + "name": "Reserved 0x8A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008A", + "is_reserved": true + }, + { + "id": "Reserved139", + "name": "Reserved 0x8B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008B", + "is_reserved": true + }, + { + "id": "Reserved140", + "name": "Reserved 0x8C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008C", + "is_reserved": true + }, + { + "id": "Reserved141", + "name": "Reserved 0x8D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008D", + "is_reserved": true + }, + { + "id": "Reserved142", + "name": "Reserved 0x8E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008E", + "is_reserved": true + }, + { + "id": "Reserved143", + "name": "Reserved 0x8F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x008F", + "is_reserved": true + }, + { + "id": "fuse180", + "name": "GPR1_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x00B4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse180-bits0-31", + "name": "GPR1_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse181", + "name": "GPR1_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x00B5", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse181-bits0-31", + "name": "GPR1_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse182", + "name": "GPR1_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x00B6", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse182-bits0-31", + "name": "GPR1_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse183", + "name": "GPR1_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x00B7", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse183-bits0-31", + "name": "GPR1_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "Reserved188", + "name": "Reserved 0xBC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BC", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved189", + "name": "Reserved 0xBD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BD", + "is_reserved": true, + "access": "RO" + }, + { + "id": "fuse320", + "name": "GPR3_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0140", + "shadow_reg_offset_int": "0x0500", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse320-bits0-31", + "name": "GPR3_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + } + ] + }, + { + "group": { + "name": "SENTINEL", + "description": "SENTINEL" + }, + "registers": [ + { + "id": "Reserved45", + "name": "Reserved 0x2D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved46", + "name": "Reserved 0x2E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 7 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved47", + "name": "Reserved 0x2F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved48", + "name": "Reserved 0x30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0030", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved49", + "name": "Reserved 0x31", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0031", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved50", + "name": "Reserved 0x32", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0032", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved51", + "name": "Reserved 0x33", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0033", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved52", + "name": "Reserved 0x34", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0034", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved53", + "name": "Reserved 0x35", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0035", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved54", + "name": "Reserved 0x36", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0036", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved55", + "name": "Reserved 0x37", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0037", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "fuse56", + "name": "SENTINEL_MISC_CTRL0", + "description": "OEM controlled Fuse.", + "index_int": "0x0038", + "shadow_reg_offset_int": "0x00E0", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse56-bits0-3", + "name": "SOC_SCOPE_PRIMARY_DBG_DISABLE", + "description": "Debug Disable for CM33 domain. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 4, + "id": "fuse56-bits4-7", + "name": "SOC_SCOPE1_DBG_DISABLE", + "description": "Debug disable for Trace Memory controller. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 4, + "id": "fuse56-bits8-11", + "name": "SOC_SCOPE2_DBG_DISABLE", + "description": "Debug disable for CM7. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 4, + "id": "fuse56-bits12-15", + "name": "SOC_SCOPE3_DBG_DISABLE", + "description": "Debug disable for DAP AHB-AP. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + } + ] + }, + { + "id": "fuse57", + "name": "SENTINEL_MISC_CTRL1", + "description": "OEM controlled Fuse.", + "index_int": "0x0039", + "shadow_reg_offset_int": "0x00E4", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse57-bits0-3", + "name": "SOC_SCOPE4_DBG_DISABLE", + "description": "Debug disable for apps cores, Camera SS and GPU. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse58", + "name": "SENTINEL_MISC_CTRL2", + "description": "OEM controlled Fuse.", + "index_int": "0x003A", + "shadow_reg_offset_int": "0x00E8", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse58-bit0", + "name": "OEM_AGDET_DISABLE", + "description": "Disable for analog glitch detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit1", + "name": "OEM_VDET_DISABLE", + "description": "Disable for voltage detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit2", + "name": "OEM_TMPSNS_DISABLE", + "description": "Disable for temperature sensor during boot" + }, + { + "width": 1, + "id": "fuse58-bit3", + "name": "OEM_DGDET_DISABLE", + "description": "Disable for digital glitch detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit4", + "name": "FAST_BOOT_ENABLE", + "description": "Enable Fast boot datapath" + }, + { + "width": 1, + "id": "fuse58-bit5", + "name": "SJC_DISABLE", + "description": "Hardware disablement of SJC. Disables JTAG debugger, including ability for boundary scan.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "SJC is enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "SJC is disabled" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse58-bit8", + "name": "SOC_GLBL_DBG_DISABLE", + "description": "Disable all debug." + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit10", + "name": "TZ_GLBL_DBG_DISABLE", + "description": "TZ_GLBL_DBG_DISABLE" + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit12", + "name": "OEM_FDET_DISABLE", + "description": "Disable for Frequency detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit13", + "name": "ALLOW_FIPS_UNAPPROVED_ALGOS", + "description": "If FIPS mode is enabled, Allow FIPS unapproved algorithms", + "access": "RO", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow FIPS algorithms if FIPS_ENABLE is set." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Even though FIPS_ENABLE is set, allow FIPS unapproved algorithms" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit14", + "name": "CRRM_ENABLE", + "description": "Enable CRRM feature. See SRM for details.", + "access": "RO", + "values": [ + { + "name": "ENABLED", + "value": 1, + "description": "CRRM is enabled" + }, + { + "name": "DISABLED", + "value": 0, + "description": "CRRM is not enabled" + } + ] + }, + { + "width": 1, + "id": "fuse58-bit15", + "name": "OSCCA_SELFTEST_DISABLE", + "description": "Disable OSCCA selftest", + "access": "RO", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "In OSCCA mode, perform OSCCA selftest" + }, + { + "name": "DISABLED", + "value": 1, + "description": "In OSCCA mode, disable OSCCA self-test" + } + ] + } + ] + }, + { + "id": "Reserved59", + "name": "Reserved 0x3B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "access": "RO" + }, + { + "width": 2, + "access": "RO" + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1 + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1 + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1, + "access": "RO" + }, + { + "width": 1 + }, + { + "width": 4, + "access": "RO" + } + ] + }, + { + "id": "fuse60", + "name": "SENTINEL_MISC_CTRL4", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003C", + "shadow_reg_offset_int": "0x00F0", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 12, + "id": "fuse60-bits0-11", + "name": "EXPORT_CONTROL", + "description": "Each fuse disables the following : \n[11] : SGI in S401\n[10] : PKC in S401 \n[9] : Reserved\n[8] : Reserved for S401\n[7] : A55 Crypto extension\n[6] : M7 MMCAU (Reserved)\n[5] : M33 MMCAU (Reserved)\n[4] : IPED (Reserved)\n[3]: V2X SGI\n[2]: V2X PKC\n[1]: V2X BA414\n[0]: IEE", + "access": "RO" + }, + { + "width": 3, + "id": "fuse60-bits12-14", + "name": "SENTINEL_BOOT_CRYPTO", + "description": "Boot Cryptographic selection between Classic, PQC and Hybrid." + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved61", + "name": "Reserved 0x3D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003D", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved62", + "name": "Reserved 0x3E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003E", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse63", + "name": "SENTINEL_MISC_CTRL7", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003F", + "shadow_reg_offset_int": "0x00FC", + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse63-bits12-15", + "name": "OEM_SRK_RVK", + "description": "OEM key revoke fuses for tree of public keys" + } + ] + }, + { + "id": "Reserved64", + "name": "Reserved 0x40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0040", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved65", + "name": "Reserved 0x41", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0041", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved66", + "name": "Reserved 0x42", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0042", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved67", + "name": "Reserved 0x43", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0043", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved68", + "name": "Reserved 0x44", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0044", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved69", + "name": "Reserved 0x45", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0045", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved70", + "name": "Reserved 0x46", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0046", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved71", + "name": "Reserved 0x47", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0047", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved72", + "name": "Reserved 0x48", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0048", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved73", + "name": "Reserved 0x49", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0049", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved74", + "name": "Reserved 0x4A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved75", + "name": "Reserved 0x4B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved76", + "name": "Reserved 0x4C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved77", + "name": "Reserved 0x4D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved78", + "name": "Reserved 0x4E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved79", + "name": "Reserved 0x4F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved88", + "name": "Reserved 0x58", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0058", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved89", + "name": "Reserved 0x59", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0059", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved90", + "name": "Reserved 0x5A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005A", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved91", + "name": "Reserved 0x5B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved92", + "name": "Reserved 0x5C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005C", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved93", + "name": "Reserved 0x5D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved94", + "name": "Reserved 0x5E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved95", + "name": "Reserved 0x5F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005F", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved96", + "name": "Reserved 0x60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0060", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved97", + "name": "Reserved 0x61", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0061", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved98", + "name": "Reserved 0x62", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0062", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved99", + "name": "Reserved 0x63", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0063", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved100", + "name": "Reserved 0x64", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0064", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved101", + "name": "Reserved 0x65", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0065", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved102", + "name": "Reserved 0x66", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0066", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved103", + "name": "Reserved 0x67", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0067", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved104", + "name": "Reserved 0x68", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0068", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved105", + "name": "Reserved 0x69", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0069", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved106", + "name": "Reserved 0x6A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved107", + "name": "Reserved 0x6B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved108", + "name": "Reserved 0x6C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved109", + "name": "Reserved 0x6D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved110", + "name": "Reserved 0x6E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved111", + "name": "Reserved 0x6F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved112", + "name": "Reserved 0x70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0070", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved113", + "name": "Reserved 0x71", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0071", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved114", + "name": "Reserved 0x72", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0072", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved115", + "name": "Reserved 0x73", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0073", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved116", + "name": "Reserved 0x74", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0074", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved117", + "name": "Reserved 0x75", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0075", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved118", + "name": "Reserved 0x76", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0076", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved119", + "name": "Reserved 0x77", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0077", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved120", + "name": "Reserved 0x78", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0078", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved121", + "name": "Reserved 0x79", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0079", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved122", + "name": "Reserved 0x7A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007A", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved123", + "name": "Reserved 0x7B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007B", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved124", + "name": "Reserved 0x7C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007C", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved125", + "name": "Reserved 0x7D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007D", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved126", + "name": "Reserved 0x7E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. 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Software should not rely on the value.", + "index_int": "0x012F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved304", + "name": "Reserved 0x130", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0130", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved305", + "name": "Reserved 0x131", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0131", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved306", + "name": "Reserved 0x132", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0132", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved307", + "name": "Reserved 0x133", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0133", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved308", + "name": "Reserved 0x134", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0134", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved309", + "name": "Reserved 0x135", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0135", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved310", + "name": "Reserved 0x136", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0136", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved311", + "name": "Reserved 0x137", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0137", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved312", + "name": "Reserved 0x138", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0138", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 12 + }, + { + "width": 20 + } + ] + }, + { + "id": "Reserved316", + "name": "Reserved 0x13C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013C", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "OEM", + "description": "OEM group" + }, + "registers": [ + { + "id": "Reserved176", + "name": "Reserved 0xB0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B0", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved177", + "name": "Reserved 0xB1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B1", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved178", + "name": "Reserved 0xB2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B2", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved179", + "name": "Reserved 0xB3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B3", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse313", + "name": "GPR2_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0139", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004" + } + }, + { + "id": "fuse314", + "name": "GPR2_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x013A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004" + } + }, + { + "id": "fuse315", + "name": "GPR2_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x013B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004" + } + }, + { + "id": "fuse376", + "name": "GPR4_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0178", + "shadow_reg_offset_int": "0x05E0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse376-bits0-31", + "name": "GPR4_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse377", + "name": "GPR4_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0179", + "shadow_reg_offset_int": "0x05E4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse377-bits0-31", + "name": "GPR4_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse378", + "name": "GPR4_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017A", + "shadow_reg_offset_int": "0x05E8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse378-bits0-31", + "name": "GPR4_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse379", + "name": "GPR4_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017B", + "shadow_reg_offset_int": "0x05EC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse379-bits0-31", + "name": "GPR4_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse380", + "name": "GPR4_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017C", + "shadow_reg_offset_int": "0x05F0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse380-bits0-31", + "name": "GPR4_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse381", + "name": "GPR4_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017D", + "shadow_reg_offset_int": "0x05F4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse381-bits0-31", + "name": "GPR4_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse382", + "name": "GPR4_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017E", + "shadow_reg_offset_int": "0x05F8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse382-bits0-31", + "name": "GPR4_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse383", + "name": "GPR4_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017F", + "shadow_reg_offset_int": "0x05FC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse383-bits0-31", + "name": "GPR4_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse384", + "name": "GPR4_CFG8", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0180", + "shadow_reg_offset_int": "0x0600", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse384-bits0-31", + "name": "GPR4_CFG8", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse385", + "name": "GPR4_CFG9", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0181", + "shadow_reg_offset_int": "0x0604", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse385-bits0-31", + "name": "GPR4_CFG9", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse386", + "name": "GPR4_CFG10", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0182", + "shadow_reg_offset_int": "0x0608", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse386-bits0-31", + "name": "GPR4_CFG10", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse387", + "name": "GPR4_CFG11", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0183", + "shadow_reg_offset_int": "0x060C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse387-bits0-31", + "name": "GPR4_CFG11", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse388", + "name": "GPR4_CFG12", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0184", + "shadow_reg_offset_int": "0x0610", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse388-bits0-31", + "name": "GPR4_CFG12", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse389", + "name": "GPR4_CFG13", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0185", + "shadow_reg_offset_int": "0x0614", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse389-bits0-31", + "name": "GPR4_CFG13", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse390", + "name": "GPR4_CFG14", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0186", + "shadow_reg_offset_int": "0x0618", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse390-bits0-31", + "name": "GPR4_CFG14", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse391", + "name": "GPR4_CFG15", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0187", + "shadow_reg_offset_int": "0x061C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse391-bits0-31", + "name": "GPR4_CFG15", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed." + } + ] + }, + { + "id": "fuse392", + "name": "GPR5_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0188", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse392-bits0-31", + "name": "GPR5_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse393", + "name": "GPR5_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0189", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse393-bits0-31", + "name": "GPR5_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse394", + "name": "GPR5_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018A", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse394-bits0-31", + "name": "GPR5_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse395", + "name": "GPR5_CFG3", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018B", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse395-bits0-31", + "name": "GPR5_CFG3", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse396", + "name": "GPR5_CFG4", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse396-bits0-31", + "name": "GPR5_CFG4", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse397", + "name": "GPR5_CFG5", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018D", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse397-bits0-31", + "name": "GPR5_CFG5", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse398", + "name": "GPR5_CFG6", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018E", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse398-bits0-31", + "name": "GPR5_CFG6", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse399", + "name": "GPR5_CFG7", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x018F", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse399-bits0-31", + "name": "GPR5_CFG7", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse400", + "name": "GPR5_CFG8", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0190", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse400-bits0-31", + "name": "GPR5_CFG8", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse401", + "name": "GPR5_CFG9", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0191", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse401-bits0-31", + "name": "GPR5_CFG9", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse402", + "name": "GPR5_CFG10", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0192", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse402-bits0-31", + "name": "GPR5_CFG10", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse403", + "name": "GPR5_CFG11", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0193", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse403-bits0-31", + "name": "GPR5_CFG11", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse404", + "name": "GPR5_CFG12", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0194", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse404-bits0-31", + "name": "GPR5_CFG12", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse405", + "name": "GPR5_CFG13", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0195", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse405-bits0-31", + "name": "GPR5_CFG13", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse406", + "name": "GPR5_CFG14", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0196", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse406-bits0-31", + "name": "GPR5_CFG14", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse407", + "name": "GPR5_CFG15", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0197", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse407-bits0-31", + "name": "GPR5_CFG15", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse408", + "name": "GPR6_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0198", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse408-bits0-15", + "name": "GPR6_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse409", + "name": "GPR6_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x0199", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse409-bits0-15", + "name": "GPR6_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse410", + "name": "GPR6_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019A", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse410-bits0-15", + "name": "GPR6_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse411", + "name": "GPR6_CFG3", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019B", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse411-bits0-15", + "name": "GPR6_CFG3", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse412", + "name": "GPR6_CFG4", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019C", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse412-bits0-15", + "name": "GPR6_CFG4", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse413", + "name": "GPR6_CFG5", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019D", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse413-bits0-15", + "name": "GPR6_CFG5", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse414", + "name": "GPR6_CFG6", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019E", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse414-bits0-15", + "name": "GPR6_CFG6", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "fuse415", + "name": "GPR6_CFG7", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls.", + "index_int": "0x019F", + "access": "RO", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse415-bits0-15", + "name": "GPR6_CFG7", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure Sentinel API calls." + } + ] + }, + { + "id": "Reserved416", + "name": "Reserved 0x1A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A0", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved417", + "name": "Reserved 0x1A1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A1", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved418", + "name": "Reserved 0x1A2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A2", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved419", + "name": "Reserved 0x1A3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A3", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved420", + "name": "Reserved 0x1A4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A4", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved421", + "name": "Reserved 0x1A5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A5", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved422", + "name": "Reserved 0x1A6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A6", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved423", + "name": "Reserved 0x1A7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A7", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved424", + "name": "Reserved 0x1A8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A8", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved425", + "name": "Reserved 0x1A9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A9", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved426", + "name": "Reserved 0x1AA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AA", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved427", + "name": "Reserved 0x1AB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AB", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved428", + "name": "Reserved 0x1AC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AC", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved429", + "name": "Reserved 0x1AD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AD", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved430", + "name": "Reserved 0x1AE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AE", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved431", + "name": "Reserved 0x1AF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AF", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved432", + "name": "Reserved 0x1B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B0", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved433", + "name": "Reserved 0x1B1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B1", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved434", + "name": "Reserved 0x1B2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B2", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved435", + "name": "Reserved 0x1B3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B3", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved436", + "name": "Reserved 0x1B4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B4", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved437", + "name": "Reserved 0x1B5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B5", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved438", + "name": "Reserved 0x1B6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B6", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved439", + "name": "Reserved 0x1B7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B7", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved440", + "name": "Reserved 0x1B8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B8", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved441", + "name": "Reserved 0x1B9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B9", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved442", + "name": "Reserved 0x1BA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BA", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved443", + "name": "Reserved 0x1BB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BB", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved444", + "name": "Reserved 0x1BC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BC", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved445", + "name": "Reserved 0x1BD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BD", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved446", + "name": "Reserved 0x1BE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BE", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved447", + "name": "Reserved 0x1BF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BF", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse448", + "name": "OEM_PQC_SRKH0", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C0", + "shadow_reg_offset_int": "0x0700", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse448-bits0-31", + "name": "OEM_PQC_SRKH[31:0]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse449", + "name": "OEM_PQC_SRKH1", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C1", + "shadow_reg_offset_int": "0x0704", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse449-bits0-31", + "name": "OEM_PQC_SRKH[63:32]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse450", + "name": "OEM_PQC_SRKH2", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C2", + "shadow_reg_offset_int": "0x0708", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse450-bits0-31", + "name": "OEM_PQC_SRKH[95:64]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse451", + "name": "OEM_PQC_SRKH3", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C3", + "shadow_reg_offset_int": "0x070C", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse451-bits0-31", + "name": "OEM_PQC_SRKH[127:96]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse452", + "name": "OEM_PQC_SRKH4", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C4", + "shadow_reg_offset_int": "0x0710", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse452-bits0-31", + "name": "OEM_PQC_SRKH[159:128]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse453", + "name": "OEM_PQC_SRKH5", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C5", + "shadow_reg_offset_int": "0x0714", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse453-bits0-31", + "name": "OEM_PQC_SRKH[191:160]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse454", + "name": "OEM_PQC_SRKH6", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C6", + "shadow_reg_offset_int": "0x0718", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse454-bits0-31", + "name": "OEM_PQC_SRKH[223:192]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse455", + "name": "OEM_PQC_SRKH7", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C7", + "shadow_reg_offset_int": "0x071C", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse455-bits0-31", + "name": "OEM_PQC_SRKH[255:224]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse456", + "name": "OEM_PQC_SRKH8", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C8", + "shadow_reg_offset_int": "0x0720", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse456-bits0-31", + "name": "OEM_PQC_SRKH[287:256]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse457", + "name": "OEM_PQC_SRKH9", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01C9", + "shadow_reg_offset_int": "0x0724", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse457-bits0-31", + "name": "OEM_PQC_SRKH[319:288]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse458", + "name": "OEM_PQC_SRKH10", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CA", + "shadow_reg_offset_int": "0x0728", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse458-bits0-31", + "name": "OEM_PQC_SRKH[351:320]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse459", + "name": "OEM_PQC_SRKH11", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CB", + "shadow_reg_offset_int": "0x072C", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse459-bits0-31", + "name": "OEM_PQC_SRKH[383:352]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse460", + "name": "OEM_PQC_SRKH12", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CC", + "shadow_reg_offset_int": "0x0730", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse460-bits0-31", + "name": "OEM_PQC_SRKH[415:384]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse461", + "name": "OEM_PQC_SRKH13", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CD", + "shadow_reg_offset_int": "0x0734", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse461-bits0-31", + "name": "OEM_PQC_SRKH[447:416]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse462", + "name": "OEM_PQC_SRKH14", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CE", + "shadow_reg_offset_int": "0x0738", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse462-bits0-31", + "name": "OEM_PQC_SRKH[479:448]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + }, + { + "id": "fuse463", + "name": "OEM_PQC_SRKH15", + "description": "Hash of OEM PQC public keys in FW container", + "index_int": "0x01CF", + "shadow_reg_offset_int": "0x073C", + "access": "RW", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse463-bits0-31", + "name": "OEM_PQC_SRKH[511:480]", + "description": "Hash of OEM PQC public keys in FW container" + } + ] + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "PRINCE" + }, + "registers": [ + { + "id": "fuse184", + "name": "IPED_KEY0", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00B8", + "shadow_reg_offset_int": "0x02E0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse184-bits0-31", + "name": "IPED_KEY[31:0]", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image" + } + ] + }, + { + "id": "fuse185", + "name": "IPED_KEY1", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00B9", + "shadow_reg_offset_int": "0x02E4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse185-bits0-31", + "name": "IPED_KEY[63:32]", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image" + } + ] + }, + { + "id": "fuse186", + "name": "IPED_KEY2", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00BA", + "shadow_reg_offset_int": "0x02E8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse186-bits0-31", + "name": "IPED_KEY[95:64]", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image" + } + ] + }, + { + "id": "fuse187", + "name": "IPED_KEY3", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00BB", + "shadow_reg_offset_int": "0x02EC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse187-bits0-31", + "name": "IPED_KEY[127:96]", + "description": "128-bit IPED key for key blob unwrap. Key blob is in primary boot image" + } + ] + }, + { + "id": "Reserved608", + "name": "Reserved 0x260", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0260", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved609", + "name": "Reserved 0x261", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0261", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "V2X", + "description": "V2X group" + }, + "registers": [ + { + "id": "Reserved191", + "name": "Reserved 0xBF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BF", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 9 + }, + { + "width": 23 + } + ] + }, + { + "id": "Reserved272", + "name": "Reserved 0x110", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0110", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved273", + "name": "Reserved 0x111", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0111", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved274", + "name": "Reserved 0x112", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0112", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved275", + "name": "Reserved 0x113", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0113", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved276", + "name": "Reserved 0x114", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0114", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved277", + "name": "Reserved 0x115", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0115", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved278", + "name": "Reserved 0x116", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0116", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved279", + "name": "Reserved 0x117", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0117", + "is_reserved": true, + "access": "RO" + }, + { + "id": "fuse280", + "name": "V2X_SHE_SECRET_KEY0", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x0118", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse280-bits0-31", + "name": "V2X_SHE_SECRET_KEY[31:0]", + "description": "V2X SHE secret key -f used to export or import material to she, using key_update protocol" + } + ] + }, + { + "id": "fuse281", + "name": "V2X_SHE_SECRET_KEY1", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x0119", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse281-bits0-31", + "name": "V2X_SHE_SECRET_KEY[63:32]", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol" + } + ] + }, + { + "id": "fuse282", + "name": "V2X_SHE_SECRET_KEY2", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x011A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse282-bits0-31", + "name": "V2X_SHE_SECRET_KEY[95:64]", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol" + } + ] + }, + { + "id": "fuse283", + "name": "V2X_SHE_SECRET_KEY3", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x011B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse283-bits0-31", + "name": "V2X_SHE_SECRET_KEY[127:96]", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol" + } + ] + }, + { + "id": "fuse284", + "name": "V2X_SHE_PRNG_KEY0", + "description": "V2X SHE PRNG value", + "index_int": "0x011C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse284-bits0-31", + "name": "V2X_SHE_PRNG_KEY[31:0]", + "description": "V2X SHE PRNG value" + } + ] + }, + { + "id": "fuse285", + "name": "V2X_SHE_PRNG_KEY1", + "description": "V2X SHE PRNG value", + "index_int": "0x011D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse285-bits0-31", + "name": "V2X_SHE_PRNG_KEY[63:32]", + "description": "V2X SHE PRNG value" + } + ] + }, + { + "id": "fuse286", + "name": "V2X_SHE_PRNG_KEY2", + "description": "V2X SHE PRNG value", + "index_int": "0x011E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse286-bits0-31", + "name": "V2X_SHE_PRNG_KEY[95:64]", + "description": "V2X SHE PRNG value" + } + ] + }, + { + "id": "fuse287", + "name": "V2X_SHE_PRNG_KEY3", + "description": "V2X SHE PRNG value", + "index_int": "0x011F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse287-bits0-31", + "name": "V2X_SHE_PRNG_KEY[127:96]", + "description": "V2X SHE PRNG value" + } + ] + }, + { + "id": "Reserved317", + "name": "Reserved 0x13D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013D", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved318", + "name": "Reserved 0x13E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013E", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved319", + "name": "Reserved 0x13F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013F", + "is_reserved": true, + "access": "RO", + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 15 + } + ] + }, + { + "id": "fuse528", + "name": "V2X_SHE_MONO_CNT0", + "description": "V2X_SHE_MONO_CNT0", + "index_int": "0x0210", + "shadow_reg_offset_int": "0x0840", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse528-bits0-31", + "name": "V2X_SHE_MONO_CNT[31:0]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse529", + "name": "V2X_SHE_MONO_CNT1", + "description": "V2X_SHE_MONO_CNT1", + "index_int": "0x0211", + "shadow_reg_offset_int": "0x0844", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse529-bits0-31", + "name": "V2X_SHE_MONO_CNT[63:32]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse530", + "name": "V2X_SHE_MONO_CNT2", + "description": "V2X_SHE_MONO_CNT2", + "index_int": "0x0212", + "shadow_reg_offset_int": "0x0848", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse530-bits0-31", + "name": "V2X_SHE_MONO_CNT[95:64]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse531", + "name": "V2X_SHE_MONO_CNT3", + "description": "V2X_SHE_MONO_CNT3", + "index_int": "0x0213", + "shadow_reg_offset_int": "0x084C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse531-bits0-31", + "name": "V2X_SHE_MONO_CNT[127:96]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse532", + "name": "V2X_SHE_MONO_CNT4", + "description": "V2X_SHE_MONO_CNT4", + "index_int": "0x0214", + "shadow_reg_offset_int": "0x0850", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse532-bits0-31", + "name": "V2X_SHE_MONO_CNT[159:128]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse533", + "name": "V2X_SHE_MONO_CNT5", + "description": "V2X_SHE_MONO_CNT5", + "index_int": "0x0215", + "shadow_reg_offset_int": "0x0854", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse533-bits0-31", + "name": "V2X_SHE_MONO_CNT[191:160]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse534", + "name": "V2X_SHE_MONO_CNT6", + "description": "V2X_SHE_MONO_CNT6", + "index_int": "0x0216", + "shadow_reg_offset_int": "0x0858", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse534-bits0-31", + "name": "V2X_SHE_MONO_CNT[223:192]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse535", + "name": "V2X_SHE_MONO_CNT7", + "description": "V2X_SHE_MONO_CNT7", + "index_int": "0x0217", + "shadow_reg_offset_int": "0x085C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse535-bits0-31", + "name": "V2X_SHE_MONO_CNT[255:224]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse536", + "name": "V2X_SHE_MONO_CNT8", + "description": "V2X_SHE_MONO_CNT8", + "index_int": "0x0218", + "shadow_reg_offset_int": "0x0860", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse536-bits0-31", + "name": "V2X_SHE_MONO_CNT[287:256]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse537", + "name": "V2X_SHE_MONO_CNT9", + "description": "V2X_SHE_MONO_CNT9", + "index_int": "0x0219", + "shadow_reg_offset_int": "0x0864", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse537-bits0-31", + "name": "V2X_SHE_MONO_CNT[319:288]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse538", + "name": "V2X_SHE_MONO_CNT10", + "description": "V2X_SHE_MONO_CNT10", + "index_int": "0x021A", + "shadow_reg_offset_int": "0x0868", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse538-bits0-31", + "name": "V2X_SHE_MONO_CNT[351:320]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse539", + "name": "V2X_SHE_MONO_CNT11", + "description": "V2X_SHE_MONO_CNT11", + "index_int": "0x021B", + "shadow_reg_offset_int": "0x086C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse539-bits0-31", + "name": "V2X_SHE_MONO_CNT[383:352]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse540", + "name": "V2X_SHE_MONO_CNT12", + "description": "V2X_SHE_MONO_CNT12", + "index_int": "0x021C", + "shadow_reg_offset_int": "0x0870", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse540-bits0-31", + "name": "V2X_SHE_MONO_CNT[415:384]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse541", + "name": "V2X_SHE_MONO_CNT13", + "description": "V2X_SHE_MONO_CNT13", + "index_int": "0x021D", + "shadow_reg_offset_int": "0x0874", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse541-bits0-31", + "name": "V2X_SHE_MONO_CNT[447:416]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse542", + "name": "V2X_SHE_MONO_CNT14", + "description": "V2X_SHE_MONO_CNT14", + "index_int": "0x021E", + "shadow_reg_offset_int": "0x0878", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse542-bits0-31", + "name": "V2X_SHE_MONO_CNT[479:448]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse543", + "name": "V2X_SHE_MONO_CNT15", + "description": "V2X_SHE_MONO_CNT15", + "index_int": "0x021F", + "shadow_reg_offset_int": "0x087C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse543-bits0-31", + "name": "V2X_SHE_MONO_CNT[511:480]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse544", + "name": "V2X_SHE_MONO_CNT16", + "description": "V2X_SHE_MONO_CNT16", + "index_int": "0x0220", + "shadow_reg_offset_int": "0x0880", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse544-bits0-31", + "name": "V2X_SHE_MONO_CNT[543:512]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse545", + "name": "V2X_SHE_MONO_CNT17", + "description": "V2X_SHE_MONO_CNT17", + "index_int": "0x0221", + "shadow_reg_offset_int": "0x0884", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse545-bits0-31", + "name": "V2X_SHE_MONO_CNT[575:544]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse546", + "name": "V2X_SHE_MONO_CNT18", + "description": "V2X_SHE_MONO_CNT18", + "index_int": "0x0222", + "shadow_reg_offset_int": "0x0888", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse546-bits0-31", + "name": "V2X_SHE_MONO_CNT[607:576]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse547", + "name": "V2X_SHE_MONO_CNT19", + "description": "V2X_SHE_MONO_CNT19", + "index_int": "0x0223", + "shadow_reg_offset_int": "0x088C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse547-bits0-31", + "name": "V2X_SHE_MONO_CNT[639:608]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse548", + "name": "V2X_SHE_MONO_CNT20", + "description": "V2X_SHE_MONO_CNT20", + "index_int": "0x0224", + "shadow_reg_offset_int": "0x0890", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse548-bits0-31", + "name": "V2X_SHE_MONO_CNT[671:640]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse549", + "name": "V2X_SHE_MONO_CNT21", + "description": "V2X_SHE_MONO_CNT21", + "index_int": "0x0225", + "shadow_reg_offset_int": "0x0894", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse549-bits0-31", + "name": "V2X_SHE_MONO_CNT[703:672]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse550", + "name": "V2X_SHE_MONO_CNT22", + "description": "V2X_SHE_MONO_CNT22", + "index_int": "0x0226", + "shadow_reg_offset_int": "0x0898", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse550-bits0-31", + "name": "V2X_SHE_MONO_CNT[735:704]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse551", + "name": "V2X_SHE_MONO_CNT23", + "description": "V2X_SHE_MONO_CNT23", + "index_int": "0x0227", + "shadow_reg_offset_int": "0x089C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse551-bits0-31", + "name": "V2X_SHE_MONO_CNT[767:736]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse552", + "name": "V2X_SHE_MONO_CNT24", + "description": "V2X_SHE_MONO_CNT24", + "index_int": "0x0228", + "shadow_reg_offset_int": "0x08A0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse552-bits0-31", + "name": "V2X_SHE_MONO_CNT[799:768]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse553", + "name": "V2X_SHE_MONO_CNT25", + "description": "V2X_SHE_MONO_CNT25", + "index_int": "0x0229", + "shadow_reg_offset_int": "0x08A4", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse553-bits0-31", + "name": "V2X_SHE_MONO_CNT[831:800]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse554", + "name": "V2X_SHE_MONO_CNT26", + "description": "V2X_SHE_MONO_CNT26", + "index_int": "0x022A", + "shadow_reg_offset_int": "0x08A8", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse554-bits0-31", + "name": "V2X_SHE_MONO_CNT[863:832]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse555", + "name": "V2X_SHE_MONO_CNT27", + "description": "V2X_SHE_MONO_CNT27", + "index_int": "0x022B", + "shadow_reg_offset_int": "0x08AC", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse555-bits0-31", + "name": "V2X_SHE_MONO_CNT[895:864]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse556", + "name": "V2X_SHE_MONO_CNT28", + "description": "V2X_SHE_MONO_CNT28", + "index_int": "0x022C", + "shadow_reg_offset_int": "0x08B0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse556-bits0-31", + "name": "V2X_SHE_MONO_CNT[927:896]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse557", + "name": "V2X_SHE_MONO_CNT29", + "description": "V2X_SHE_MONO_CNT29", + "index_int": "0x022D", + "shadow_reg_offset_int": "0x08B4", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse557-bits0-31", + "name": "V2X_SHE_MONO_CNT[959:928]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse558", + "name": "V2X_SHE_MONO_CNT30", + "description": "V2X_SHE_MONO_CNT30", + "index_int": "0x022E", + "shadow_reg_offset_int": "0x08B8", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse558-bits0-31", + "name": "V2X_SHE_MONO_CNT[991:960]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse559", + "name": "V2X_SHE_MONO_CNT31", + "description": "V2X_SHE_MONO_CNT31", + "index_int": "0x022F", + "shadow_reg_offset_int": "0x08BC", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse559-bits0-31", + "name": "V2X_SHE_MONO_CNT[1023:992]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse560", + "name": "V2X_SHE_MONO_CNT32", + "description": "V2X_SHE_MONO_CNT32", + "index_int": "0x0230", + "shadow_reg_offset_int": "0x08C0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse560-bits0-31", + "name": "V2X_SHE_MONO_CNT[1055:1024]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse561", + "name": "V2X_SHE_MONO_CNT33", + "description": "V2X_SHE_MONO_CNT33", + "index_int": "0x0231", + "shadow_reg_offset_int": "0x08C4", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse561-bits0-31", + "name": "V2X_SHE_MONO_CNT[1087:1056]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse562", + "name": "V2X_SHE_MONO_CNT34", + "description": "V2X_SHE_MONO_CNT34", + "index_int": "0x0232", + "shadow_reg_offset_int": "0x08C8", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse562-bits0-31", + "name": "V2X_SHE_MONO_CNT[1119:1088]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse563", + "name": "V2X_SHE_MONO_CNT35", + "description": "V2X_SHE_MONO_CNT35", + "index_int": "0x0233", + "shadow_reg_offset_int": "0x08CC", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse563-bits0-31", + "name": "V2X_SHE_MONO_CNT[1151:1120]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse564", + "name": "V2X_SHE_MONO_CNT36", + "description": "V2X_SHE_MONO_CNT36", + "index_int": "0x0234", + "shadow_reg_offset_int": "0x08D0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse564-bits0-31", + "name": "V2X_SHE_MONO_CNT[1183:1152]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse565", + "name": "V2X_SHE_MONO_CNT37", + "description": "V2X_SHE_MONO_CNT37", + "index_int": "0x0235", + "shadow_reg_offset_int": "0x08D4", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse565-bits0-31", + "name": "V2X_SHE_MONO_CNT[1215:1184]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse566", + "name": "V2X_SHE_MONO_CNT38", + "description": "V2X_SHE_MONO_CNT38", + "index_int": "0x0236", + "shadow_reg_offset_int": "0x08D8", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse566-bits0-31", + "name": "V2X_SHE_MONO_CNT[1247:1216]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse567", + "name": "V2X_SHE_MONO_CNT39", + "description": "V2X_SHE_MONO_CNT39", + "index_int": "0x0237", + "shadow_reg_offset_int": "0x08DC", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse567-bits0-31", + "name": "V2X_SHE_MONO_CNT[1279:1248]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse568", + "name": "V2X_SHE_MONO_CNT40", + "description": "V2X_SHE_MONO_CNT40", + "index_int": "0x0238", + "shadow_reg_offset_int": "0x08E0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse568-bits0-31", + "name": "V2X_SHE_MONO_CNT[1311:1280]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse569", + "name": "V2X_SHE_MONO_CNT41", + "description": "V2X_SHE_MONO_CNT41", + "index_int": "0x0239", + "shadow_reg_offset_int": "0x08E4", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse569-bits0-31", + "name": "V2X_SHE_MONO_CNT[1343:1312]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse570", + "name": "V2X_SHE_MONO_CNT42", + "description": "V2X_SHE_MONO_CNT42", + "index_int": "0x023A", + "shadow_reg_offset_int": "0x08E8", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse570-bits0-31", + "name": "V2X_SHE_MONO_CNT[1375:1344]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse571", + "name": "V2X_SHE_MONO_CNT43", + "description": "V2X_SHE_MONO_CNT43", + "index_int": "0x023B", + "shadow_reg_offset_int": "0x08EC", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse571-bits0-31", + "name": "V2X_SHE_MONO_CNT[1407:1376]", + "description": "V2X_SHE_MONO_CNT" + } + ] + }, + { + "id": "fuse572", + "name": "V2X_SHE_MONO_CNT44", + "description": "V2X_SHE_MONO_CNT44", + "index_int": "0x023C", + "shadow_reg_offset_int": "0x08F0", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse572-bits0-31", + "name": "V2X_SHE_MONO_CNT[1439:1408]", + "description": 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Software should not rely on the value.", + "index_int": "0x00EB", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved236", + "name": "Reserved 0xEC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EC", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved237", + "name": "Reserved 0xED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00ED", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved238", + "name": "Reserved 0xEE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EE", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved239", + "name": "Reserved 0xEF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EF", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved240", + "name": "Reserved 0xF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F0", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved241", + "name": "Reserved 0xF1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F1", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved242", + "name": "Reserved 0xF2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F2", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved243", + "name": "Reserved 0xF3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F3", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved244", + "name": "Reserved 0xF4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F4", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved245", + "name": "Reserved 0xF5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F5", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved246", + "name": "Reserved 0xF6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F6", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved247", + "name": "Reserved 0xF7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F7", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved248", + "name": "Reserved 0xF8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F8", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved249", + "name": "Reserved 0xF9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F9", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved250", + "name": "Reserved 0xFA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FA", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved251", + "name": "Reserved 0xFB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FB", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved252", + "name": "Reserved 0xFC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FC", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved253", + "name": "Reserved 0xFD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FD", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved254", + "name": "Reserved 0xFE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FE", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved255", + "name": "Reserved 0xFF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FF", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved328", + "name": "Reserved 0x148", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0148", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved329", + "name": "Reserved 0x149", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0149", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved330", + "name": "Reserved 0x14A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved331", + "name": "Reserved 0x14B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved332", + "name": "Reserved 0x14C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved333", + "name": "Reserved 0x14D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved334", + "name": "Reserved 0x14E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved335", + "name": "Reserved 0x14F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved336", + "name": "Reserved 0x150", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0150", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved337", + "name": "Reserved 0x151", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0151", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved338", + "name": "Reserved 0x152", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0152", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved339", + "name": "Reserved 0x153", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0153", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved340", + "name": "Reserved 0x154", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0154", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved341", + "name": "Reserved 0x155", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0155", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved342", + "name": "Reserved 0x156", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0156", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved343", + "name": "Reserved 0x157", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0157", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved344", + "name": "Reserved 0x158", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0158", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved345", + "name": "Reserved 0x159", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0159", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved346", + "name": "Reserved 0x15A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved347", + "name": "Reserved 0x15B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved348", + "name": "Reserved 0x15C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved349", + "name": "Reserved 0x15D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved350", + "name": "Reserved 0x15E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved351", + "name": "Reserved 0x15F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved352", + "name": "Reserved 0x160", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0160", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved353", + "name": "Reserved 0x161", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0161", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved354", + "name": "Reserved 0x162", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0162", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved355", + "name": "Reserved 0x163", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0163", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved356", + "name": "Reserved 0x164", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0164", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved357", + "name": "Reserved 0x165", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0165", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved358", + "name": "Reserved 0x166", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0166", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved359", + "name": "Reserved 0x167", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0167", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved360", + "name": "Reserved 0x168", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0168", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved361", + "name": "Reserved 0x169", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0169", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved362", + "name": "Reserved 0x16A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016A", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved363", + "name": "Reserved 0x16B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016B", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved364", + "name": "Reserved 0x16C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016C", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved365", + "name": "Reserved 0x16D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016D", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved366", + "name": "Reserved 0x16E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved367", + "name": "Reserved 0x16F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved368", + "name": "Reserved 0x170", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0170", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved369", + "name": "Reserved 0x171", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0171", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved370", + "name": "Reserved 0x172", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0172", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved371", + "name": "Reserved 0x173", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0173", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved372", + "name": "Reserved 0x174", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0174", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved373", + "name": "Reserved 0x175", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0175", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved374", + "name": "Reserved 0x176", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0176", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved375", + "name": "Reserved 0x177", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0177", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "CRC", + "description": "CRC group" + }, + "registers": [ + { + "id": "Reserved256", + "name": "Reserved 0x100", + "description": "Reserved for future use. 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Software should not rely on the value.", + "index_int": "0x0103", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved260", + "name": "Reserved 0x104", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0104", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved261", + "name": "Reserved 0x105", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0105", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved262", + "name": "Reserved 0x106", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0106", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved263", + "name": "Reserved 0x107", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0107", + "is_reserved": true, + "access": "RO" + } + ] + }, + { + "group": { + "name": "SENTINEL_GPR0_CFG", + "description": "SENTINEL_GPR0_CFG" + }, + "registers": [ + { + "id": "Reserved264", + "name": "Reserved 0x108", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0108", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved265", + "name": "Reserved 0x109", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0109", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved266", + "name": "Reserved 0x10A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010A", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved267", + "name": "Reserved 0x10B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010B", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved268", + "name": "Reserved 0x10C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010C", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved269", + "name": "Reserved 0x10D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010D", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved270", + "name": "Reserved 0x10E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010E", + "is_reserved": true, + "access": "RO" + }, + { + "id": "Reserved271", + "name": "Reserved 0x10F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010F", + "is_reserved": true, + "access": "RO" + } + ] + }, + { + "group": { + "name": "OEM_SW_CFG", + "description": "OEM_SW_CFG" + }, + "registers": [ + { + "id": "fuse321", + "name": "OEM_SW_CFG", + "description": "OEM Software Configuration", + "index_int": "0x0141", + "shadow_reg_offset_int": "0x0504", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse321-bits0-31", + "name": "OEM_SW_CFG", + "description": "OEM Software Configuration" + } + ] + } + ] + }, + { + "group": { + "name": "COM_DEVICE_ID_CFG", + "description": "COM_DEVICE_ID_CFG" + }, + "registers": [ + { + "id": "fuse322", + "name": "COM_DEVICE_ID_CFG0", + "description": "COM_DEVICE_ID_CFG0", + "index_int": "0x0142", + "shadow_reg_offset_int": "0x0508", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse322-bits0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse322-bits16-31", + "name": "USB1_PID", + "description": "USB1 Product ID" + } + ] + }, + { + "id": "fuse323", + "name": "COM_DEVICE_ID_CFG1", + "description": "COM_DEVICE_ID_CFG1", + "index_int": "0x0143", + "shadow_reg_offset_int": "0x050C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse323-bits0-15", + "name": "USB2_PID", + "description": "USB2 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved324", + "name": "Reserved 0x144", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0144", + "is_reserved": true, + "access": "RO" + }, + { + "id": "fuse325", + "name": "COM_DEVICE_ID_CFG3", + "description": "COM_DEVICE_ID_CFG3", + "index_int": "0x0145", + "shadow_reg_offset_int": "0x0514", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse325-bits0-7", + "name": "MAC_ADDR_47_40", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits8-15", + "name": "MAC_ADDR_39_32", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits16-23", + "name": "MAC_ADDR_31_24", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits24-31", + "name": "MAC_ADDR_23_16", + "description": "MAC Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse326", + "name": "COM_DEVICE_ID_CFG4", + "description": "COM_DEVICE_ID_CFG4", + "index_int": "0x0146", + "shadow_reg_offset_int": "0x0518", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse326-bits0-7", + "name": "MAC_ADDR_15_8", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse326-bits8-15", + "name": "MAC_ADDR_7_0", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8 + }, + { + "width": 8, + "id": "fuse326-bits24-31", + "name": "NUM_OF_MACS", + "description": "Max. Number of MACs supported." + } + ] + } + ] + }, + { + "group": { + "name": "MIX_BLK_CFG", + "description": "MIX_BLK_CFG" + }, + "registers": [ + { + "id": "Reserved327", + "name": "Reserved 0x147", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0147", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + } + ] + }, + { + "group": { + "name": "V2X_ROMPATCH", + "description": "V2X_ROMPATCH" + }, + "registers": [ + { + "id": "Reserved464", + "name": "Reserved 0x1D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D0", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved465", + "name": "Reserved 0x1D1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D1", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved466", + "name": "Reserved 0x1D2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D2", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved467", + "name": "Reserved 0x1D3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D3", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved468", + "name": "Reserved 0x1D4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D4", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved469", + "name": "Reserved 0x1D5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D5", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved470", + "name": "Reserved 0x1D6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D6", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved471", + "name": "Reserved 0x1D7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D7", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved472", + "name": "Reserved 0x1D8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D8", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved473", + "name": "Reserved 0x1D9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D9", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved474", + "name": "Reserved 0x1DA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DA", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved475", + "name": "Reserved 0x1DB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DB", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved476", + "name": "Reserved 0x1DC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DC", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved477", + "name": "Reserved 0x1DD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DD", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved478", + "name": "Reserved 0x1DE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DE", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved479", + "name": "Reserved 0x1DF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DF", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved480", + "name": "Reserved 0x1E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E0", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved481", + "name": "Reserved 0x1E1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E1", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved482", + "name": "Reserved 0x1E2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E2", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved483", + "name": "Reserved 0x1E3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E3", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved484", + "name": "Reserved 0x1E4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E4", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved485", + "name": "Reserved 0x1E5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E5", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved486", + "name": "Reserved 0x1E6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E6", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved487", + "name": "Reserved 0x1E7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E7", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved488", + "name": "Reserved 0x1E8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E8", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved489", + "name": "Reserved 0x1E9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01E9", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved490", + "name": "Reserved 0x1EA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EA", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved491", + "name": "Reserved 0x1EB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EB", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved492", + "name": "Reserved 0x1EC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EC", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved493", + "name": "Reserved 0x1ED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01ED", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved494", + "name": "Reserved 0x1EE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EE", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved495", + "name": "Reserved 0x1EF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01EF", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved496", + "name": "Reserved 0x1F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F0", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved497", + "name": "Reserved 0x1F1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F1", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved498", + "name": "Reserved 0x1F2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F2", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved499", + "name": "Reserved 0x1F3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F3", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved500", + "name": "Reserved 0x1F4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F4", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved501", + "name": "Reserved 0x1F5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F5", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved502", + "name": "Reserved 0x1F6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F6", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved503", + "name": "Reserved 0x1F7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F7", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved504", + "name": "Reserved 0x1F8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F8", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved505", + "name": "Reserved 0x1F9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01F9", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved506", + "name": "Reserved 0x1FA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FA", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved507", + "name": "Reserved 0x1FB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FB", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved508", + "name": "Reserved 0x1FC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FC", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved509", + "name": "Reserved 0x1FD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FD", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved510", + "name": "Reserved 0x1FE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FE", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved511", + "name": "Reserved 0x1FF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01FF", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved512", + "name": "Reserved 0x200", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0200", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved513", + "name": "Reserved 0x201", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0201", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved514", + "name": "Reserved 0x202", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0202", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved515", + "name": "Reserved 0x203", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0203", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved516", + "name": "Reserved 0x204", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0204", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved517", + "name": "Reserved 0x205", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0205", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved518", + "name": "Reserved 0x206", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0206", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved519", + "name": "Reserved 0x207", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0207", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved520", + "name": "Reserved 0x208", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0208", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved521", + "name": "Reserved 0x209", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. 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Software should not rely on the value.", + "index_int": "0x025E", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved607", + "name": "Reserved 0x25F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025F", + "is_reserved": true, + "access": "RO", + "bitfields": [ + { + "width": 32 + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/database.yaml new file mode 100644 index 0000000..2509d43 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/database.yaml @@ -0,0 +1,538 @@ +# Copyright 2023-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + a1: {} + b0: + features: + ahab: + sub_features: [ahab_image, certificate_supported] + container_types: [2, 1] # Supported container types (keep order 2, 1 - this defines default 2) + fuses_0: + _name: "AHAB SRKH" + srkh: "__srk_hash0" # SRK hash fuse + fuses_1: + _name: "AHAB SRKH PQC" + pqc_srkh: "__srk_hash1" # SRK PQC hash fuse + # B0 revision requires dummy image for OEI DDR + oei_ddr_gap_after_image: 0 + oei_ddr_qb_data_dummy: True + # ======== Certificate block section ======== + cert_block: + rot_type: "srk_table_ahab_v2" + dat: + ele_cnt_version: 2 # DAT container is based on New AHAB container version 2 + + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: otfad1_key + name: OTFAD1_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD1 Key known as KEK. + sub_regs: [fuse184, fuse185, fuse186, fuse187] + - uid: srkh + name: SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + "fuse136", + "fuse137", + "fuse138", + "fuse139", + "fuse140", + "fuse141", + "fuse142", + "fuse143", + ] + + - uid: pqc_srkh + name: PQC_SRKH + width: 512 + reversed: True + config_as_hexstring: True + description: "SHA512 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse448", + "fuse449", + "fuse450", + "fuse451", + "fuse452", + "fuse453", + "fuse454", + "fuse455", + "fuse456", + "fuse457", + "fuse458", + "fuse459", + "fuse460", + "fuse461", + "fuse462", + "fuse463", + ] + +latest: b0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: i.MX Application Processors + spsdk_predecessor_name: mx95 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95 + memory_map: + code-tcm_ns: + start_int: 0x0FF80000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + code-tcm_s: + start_int: 0x1FF80000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + system-tcm_ns: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + system-tcm_s: + start_int: 0x30000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_itcm_ns: + start_int: 0x20380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_itcm_s: + start_int: 0x30380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_ns: + start_int: 0x20400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_s: + start_int: 0x30400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram_ns: + start_int: 0x20480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + ocram_s: + start_int: 0x30480000 + size_int: 0x60000 + external: false + non_xip_type: int_ram + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + neutron_sram_ns: + start_int: 0x4AA00000 + size_int: 0x00100000 + external: false + mirror_of: neutron_sram_s + non_xip_type: int_ram + neutron_sram_s: + start_int: 0x5AA00000 + size_int: 0x00100000 + external: false + non_xip_type: int_ram + dram1_ns: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram1_s: + start_int: 0x90000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_ns: + start_int: 0xA0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram2_s: + start_int: 0xB0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_ns: + start_int: 0xC0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + dram3_s: + start_int: 0xD0000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_ddr + isp: + rom: + protocol: sdps + interfaces: [usb] + usb: + - vid: 0x1FC9 + pid: 0x015D + - vid: 0x1FC9 + pid: 0x015C + protocol_params: + no_cmd: True + hid_ep1: True + hid_pack_size: 1020 + +features: + # ======== Fuses description section ======== + fuses: + tool: nxpele + grouped_registers: + - uid: srkh + name: SRKH + width: 256 + reversed: True + config_as_hexstring: True + description: "SHA256 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x9280_0000 + size: 0x30000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_ahab" + + # ======== DAT section ======== + dat: + socc: 0x4D58005F # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + auth_beacon_length: 4 # The length in bytes of authentication beacon + ele_cnt_version: 1 + dac_version_is_swapped: True + sub_features: ["ele_pqc"] + test_address: 0x2048_0000 + dmbox_ap_ix: 0 + dac_rot_type: not_available # The Dac packet doesn't contains the ROT hash + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== AHAB section ======== + ahab: + containers_max_cnt: 3 + valid_offset_minimal_alignment: 0x400 + container_types: [1] # Supported container types + core_ids: + DUMMY_CORE: [0, "dummy", "Virtual dummy core (used for data)"] + CORTEX_M33: [1, "cortex-m33", "Cortex M33 - Boot core"] + CORTEX_A55: [2, "cortex-a55", "Cortex A55"] + ELE: [6, "ele", "EdgeLock Enclave"] + V2X_1: [9, "v2x-1", "V2X 1"] + V2X_2: [10, "v2x-2", "V2X 2"] + CORTEX_M7_1: [11, "cortex-m7-1", "Cortex M7 Core ID 1"] + DDR: [14, "ddr", "DDR Core"] + + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + OEI: [0x05, oei, OEI Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + DEK_VALIDATION_FCB_CHK: + [0x08, dek_validation_fcb_chk, DEK validation FCB check Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + EXECUTABLE_FAST_BOOT_IMAGE: + [0x0A, executable_fast_boot_image, Executable fast boot Image] + OEI_DDR: [0x0D, oei_ddr, Executable boot Image] + V2X_DUMMY: [0x0E, v2x_dummy, V2X dummy Image] + + ele: + ELE_AS_IMAGE: [0x05, ele_as_image, EdgeLock Enclave Image in OEM Image] + ELE: [0x06, ele, EdgeLock Enclave Image] + + v2x: + V2X_AS_IMAGE: [0x0A, v2x_as_image, V2X image as OEM Image] + V2X_PRIMARY: [0x0B, v2x_primary, V2X primary Image] + V2X_SECONDARY: [0x0C, v2x_secondary, V2X secondary Image] + V2X_ROM_PATCH: [0x0D, v2x_rom_patch, V2X rom patch Image] + + image_types_mapping: + ele: [6] + v2x: [9, 10] + + # AHAB extra images + oei_ddr_load_address: 0x1ffc0000 + oei_ddr_entry_point: 0x1ffc0001 + oei_ddr_core_id: cortex-m33 + oei_ddr_image_type: oei + oei_ddr_image_size_alignment: 0x400 + oei_ddr_gap_after_image: 0x10000 + + oei_ddr_no_qb_load_address: 0x1ffc0000 + oei_ddr_no_qb_entry_point: 0x1ffc0001 + oei_ddr_no_qb_core_id: cortex-m33 + oei_ddr_no_qb_image_type: oei + oei_ddr_no_qb_image_size_alignment: 0x400 + oei_ddr_no_qb_gap_after_image: 0x10000 + + oei_tcm_load_address: 0x1ffc0000 + oei_tcm_entry_point: 0x1ffc0001 + oei_tcm_core_id: cortex-m33 + oei_tcm_image_type: oei + oei_tcm_image_size_alignment: 0x400 + + system_manager_load_address: 0x1ffc0000 + system_manager_entry_point: 0x1ffc0000 + system_manager_core_id: cortex-m33 + system_manager_image_size_alignment: 0x400 + + cortex_m7_app_load_address: 0x303c0000 + cortex_m7_app_entry_point: 0 + cortex_m7_app_core_id: cortex-m7-1 + cortex_m7_app_meta_data_start_cpu_id: 1 + cortex_m7_app_image_size_alignment: 0x400 + + spl_load_address: 0x20480000 + spl_core_id: cortex-a55 + spl_meta_data_start_cpu_id: 2 + spl_ddr_image_size_alignment: 0x400 + + v2x_dummy_load_address: 0x8b000000 + v2x_dummy_image_type: v2x_dummy + v2x_dummy_core_id: cortex-m33 + + atf_load_address: 0x8a200000 + atf_core_id: cortex-a55 + atf_meta_data_start_cpu_id: 2 + atf_image_size_alignment: 0x400 + atf_filename: bl31-imx95.bin + + uboot_load_address: 0x90200000 + uboot_core_id: cortex-a55 + uboot_meta_data_start_cpu_id: 2 + uboot_image_size_alignment: 0x400 + + tee_load_address: 0x8c000000 + tee_core_id: cortex-a55 + tee_meta_data_start_cpu_id: 2 + tee_image_size_alignment: 0x400 + tee_filename: tee.bin + + kernel_load_address: 0x90400000 + kernel_core_id: cortex-a55 + kernel_meta_data_start_cpu_id: 2 + kernel_chunk_size: 0x700000 + kernel_revisions_to_split: [a0, a1] + kernel_image_size_alignment: 0x400 + + dtb_load_address: 0x93000000 + dtb_core_id: cortex-a55 + dtb_meta_data_start_cpu_id: 0 + dtb_entry_point: 0x0 + dtb_image_type: data + dtb_image_size_alignment: 0x400 + + extra_images: + [ + double_authentication, + oei_ddr_no_qb, + oei_tcm, + system_manager, + cortex_m7_app, + spl, + v2x_dummy, + atf, + uboot, + tee, + kernel, + dtb, + ] + # ======== EdgeLock Enclave section ======== + ele: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + #not_used: 0xC00 + primary_image_container_set: 0x1_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + emmc_boot: + segments: + primary_image_container_set: 0x0 + secondary_image_container_set: -1 # Just behind previous segment + sd: + segments: + primary_image_container_set: 0x8_000 + secondary_image_container_set: -1 # Just behind previous segment + # flexspi_nand: + # segments: + # xmcd: 0x00 + # primary_image_container_set: 0x400 + # secondary_image_container_set_ahab: -1 # Just behind previous segment + recovery_spi: + note: Connected to LPSPI1/2for Low power boot and LPSPI/3/4 for Single boot. SPI NOR recovery image + segments: + primary_image_container_set: 0x00 + secondary_image_container_set: -1 # Just behind previous segment + + # Template definitions for bootable image generation + templates: + imx_boot_flash_all: + description: "Complete imx-bootloader image" + mem_type: serial_downloader + configs: + - name: spl + type: spl + containers: + - name: nxp_container + path: "mx95b0-ahab-container.img" + - name: spl_container + images: + [oei_ddr_no_qb, system_manager, cortex_m7_app, spl, v2x_dummy] + - name: uboot + type: uboot + containers: + - name: uboot_container + images: [atf, uboot, tee] + + boards: + imx95-15x15-lpddr4x-evk: + lpddr_imem: lpddr4x_imem_v202409.bin + lpddr_dmem: lpddr4x_dmem_v202409.bin + lpddr_imem_qb: lpddr4x_imem_qb_v202409.bin + lpddr_dmem_qb: lpddr4x_dmem_qb_v202409.bin + oei_ddr: oei-m33-ddr.bin + system_manager: m33_image-mx95evk.bin + cortex_m7_app: imx95-15x15-evk_m7_TCM_power_mode_switch.bin + spl: u-boot-spl.bin-imx95-15x15-lpddr4x-evk-sd + atf: bl31-imx95.bin + uboot: u-boot-imx95-15x15-lpddr4x-evk.bin-sd + tee: tee.bin + imx95-19x19-lpddr5-evk: + lpddr_imem: lpddr5_imem_v202409.bin + lpddr_dmem: lpddr5_dmem_v202409.bin + lpddr_imem_qb: lpddr5_imem_qb_v202409.bin + lpddr_dmem_qb: lpddr5_dmem_qb_v202409.bin + oei_ddr: oei-m33-ddr.bin + system_manager: m33_image-mx95evk.bin + cortex_m7_app: imx95-19x19-evk_m7_TCM_power_mode_switch.bin + spl: u-boot-spl.bin-imx95-19x19-lpddr5-evk-sd + atf: bl31-imx95.bin + uboot: u-boot-imx95-19x19-lpddr5-evk.bin-sd + tee: tee.bin + imx95-19x19-verdin: + lpddr_imem: lpddr5_imem_v202409.bin + lpddr_dmem: lpddr5_dmem_v202409.bin + lpddr_imem_qb: lpddr5_imem_qb_v202409.bin + lpddr_dmem_qb: lpddr5_dmem_qb_v202409.bin + oei_ddr: oei-m33-ddr.bin + system_manager: m33_image-mx95evk.bin + cortex_m7_app: imx95-verdin-evk_m7_TCM_power_mode_switch.bin + spl: u-boot-spl.bin-imx95-19x19-verdin-sd + atf: bl31-imx95.bin + uboot: u-boot-imx95-19x19-verdin.bin-sd + tee: tee.bin + + # # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 8 + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + + fuses_1: # Fuses for OTFAD1 + _name: Configuration of fuses for OTFAD1 + _no_verify: True + fuse188: # OTFAD CFG Fuse + fuse188-bit-3: 1 # OTFAD Enable + fuse188-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse188-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse189: __key_scramble_mask # OTFAD Scramble Key + otfad1_key: __kek # OTFAD Key + + additional_template: ["otfad_scramble"] + additional_template_text: | + Is important to use physical addresses (non-secure) in settings of OTFAD to proper run the decryption on device. + For example: + In case of using FlexSPI2 the secure base address address is 0x1400_0000. But in setting of the OTFAD use 0x0400_0000 as a base address. + The code must be still linked on secure base address 0x1400_0000 to proper run of OTFAD hardware. + + Same is for FlexSPI1, but instead of 0x3800_0000 base address, the 0x2800_0000 must be used in OTFAD configuration. + + # # ======== Device Hardware Security Module (HSM) section ======== + # devhsm: EdgeLock 2 Go + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ======== Fastboot ======== + fastboot: + address: 0x9280_0000 + size: 0x2000_0000 + + # ======== nxpuuu ========== + nxpuuu: {} + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fcb_flexspi_nor.json new file mode 100644 index 0000000..afebe53 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fcb_flexspi_nor.json @@ -0,0 +1,25685 @@ +{ + "cpu": "MIMX9596", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010000", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "bugfix", + "access": "RW", + "description": "[07:00] Bugfix - 0" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "minor", + "access": "RW", + "description": "[15:08] Minor" + }, + { + "id": "field004-bits16-23", + "width": 8, + "name": "major", + "access": "RW", + "description": "[23:16] Major - 1" + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type: 0 - Generic, 1 - Quad Enable, 2 - SPI-to-xSPI, 3 - xSPI-to-SPI", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration. effective only when deviceModeCfgEnable = 1", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "Reserved01D", + "offset_int": "0x1d", + "reg_width": 24, + "name": "reserved1", + "description": " [0x01d-0x019] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved3", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 64, + "name": "reserved4", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 8, + "name": "csPadSettingOverrideEn", + "description": " [0x060-0x060] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field061", + "offset_int": "0x61", + "reg_width": 8, + "name": "csPadSettingOverride", + "description": " [0x061-0x061] Overriding pad setting of CS", + "default_value_int": "0x0" + }, + { + "id": "Reserved062", + "offset_int": "0x62", + "reg_width": 16, + "name": "reserved5", + "description": " [0x062-0x063] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 8, + "name": "sclkPadSettingOverrideEn", + "description": " [0x064-0x064] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field065", + "offset_int": "0x65", + "reg_width": 8, + "name": "sclkPadSettingOverride", + "description": " [0x065-0x065] Overriding pad setting of SCLK", + "default_value_int": "0x0" + }, + { + "id": "Reserved066", + "offset_int": "0x66", + "reg_width": 16, + "name": "reserved6", + "description": " [0x066-0x067] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 8, + "name": "dataPadSettingOverrideEn", + "description": " [0x068-0x068] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field069", + "offset_int": "0x69", + "reg_width": 8, + "name": "dataPadSettingOverride", + "description": " [0x069-0x069] Overriding pad setting of data signals", + "default_value_int": "0x0" + }, + { + "id": "Reserved06A", + "offset_int": "0x6a", + "reg_width": 16, + "name": "reserved7", + "description": " [0x06a-0x06b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 8, + "name": "dqsPadSettingOverrideEn", + "description": " [0x06c-0x06c] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field06D", + "offset_int": "0x6d", + "reg_width": 8, + "name": "dqsPadSettingOverride", + "description": " [0x06d-0x06d] Overriding pad setting of DQS", + "default_value_int": "0x0" + }, + { + "id": "Reserved06E", + "offset_int": "0x6e", + "reg_width": 16, + "name": "reserved8", + "description": " [0x06e-0x06f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "dataValidTime", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-15", + "width": 16, + "name": "dllAValidTime", + "access": "RW", + "description": " Data valid time for DLLA in terms of 0.1 ns" + }, + { + "id": "field078-bits16-31", + "width": 16, + "name": "dllBValidTime", + "access": "RW", + "description": " Data valid time for DLLB in terms of 0.1 ns" + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved9_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved9_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved9_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved9_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " The data order is swapped in OPI DDR mode", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved10_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "reserved10_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "reserved10_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "reserved10_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "reserved10_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context after being configured", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D4-bits0-7", + "width": 8, + "name": "flashPorMode", + "access": "RW", + "description": " Flash POR Mode" + }, + { + "id": "field1D4-bits8-15", + "width": 8, + "name": "flashCurrentMode", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "width": 8 + }, + { + "id": "field1D4-bits24-31", + "width": 8, + "name": "flashRestoringSequence", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + } + ] + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserved11_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserved11_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserved11_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserved11_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserved11_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserved11_5", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserved11_6", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserved11_7", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserved11_8", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserved11_9", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fuses.json new file mode 100644 index 0000000..d8bcef5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimx9596/fuses.json @@ -0,0 +1,11246 @@ +{ + "cpu": "mimx9596", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for fuse lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "ELE_MISC1_LOCK", + "description": "EdgeLock Enclave Misc. Config lock 1 - Used to lock OEM owned configuration fuses", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-6-8", + "name": "ELE_OTFAD1_KEY_LOCK", + "description": "EdgeLock Enclave OTFAD config lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved3", + "name": "Reserved 0x3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0003", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse4-bits-12-14", + "name": "ELE_OEM_SRKH0_LOCK", + "description": "EdgeLock Enclave OEM SRK Hash lock (First set for SRKH[255:0])", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0005", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse6", + "name": "LOCK_CFG6", + "description": "LOCK_CFG6", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse6-bits-3-5", + "name": "ELE_UNIQ_ID_LOCK", + "description": "EdgeLock Enclave unique ID lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "Write Protect, the controlled field can not be burned" + }, + { + "name": "OP", + "value": 2, + "description": "Over-ride Protect, the controlled field shadow registers can not be over-written" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Over-ride + Write Protect, the controlled field can not be overridden nor burned" + }, + { + "name": "RP", + "value": 4, + "description": "Read Protect, the controlled field can be sensed only, but can't be read from shadow registers" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned" + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written" + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register" + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse7", + "name": "LOCK_CFG7", + "description": "LOCK_CFG7", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse7-bits-6-8", + "name": "BOOT_CFG_LOCK", + "description": "Boot config lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-9-11", + "name": "BOOT2_CFG_LOCK", + "description": "Boot config lock - second set", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "WP_OP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "Read Protect + Write Protect - the controlled field can be sensed and overridden, but can't be read or burned", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "Read Protect + Over-ride Protect - the controlled field can be sensed and burned, but can't be read or over-written", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse7-bits-12-14", + "name": "GPR1_LOCK", + "description": "GPR 1 lock bis", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse8", + "name": "LOCK_CFG8", + "description": "LOCK_CFG8", + "index_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse8-bits-9-11", + "name": "ELE_OEM_SRKH1_LOCK", + "description": "EdgeLock Enclave OEM SRKH Lock (Second set for SRKH[511:256])", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG9", + "description": "LOCK_CFG9", + "index_int": "0x0009", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse9-bits-9-11", + "name": "V2X_SHE_MC_LOCK", + "description": "V2X SHE monotonic counter lock bits", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse9-bits-12-14", + "name": "V2X_SHE_KEY_LOCK", + "description": "V2X SHE key", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse10", + "name": "LOCK_CFG10", + "description": "LOCK_CFG10", + "index_int": "0x000A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse10-bits-0-2", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID0 Lock - Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "Write Protect + Over-ride Protect - the controlled field can not be burned and shadow registers can not be over-written", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse10-bits-3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All protection enabled - the controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse11", + "name": "LOCK_CFG11", + "description": "LOCK_CFG11", + "index_int": "0x000B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse11-bits-0-2", + "name": "GPR2_LOCK", + "description": "General Purpose group 2 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-3-5", + "name": "GPR3_LOCK", + "description": "General Purpose group 3 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-6-8", + "name": "GPR4_LOCK", + "description": "General Purpose group 4 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-9-11", + "name": "GPR5_LOCK", + "description": "General Purpose group 5 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 3, + "id": "fuse11-bits-12-14", + "name": "GPR6_LOCK", + "description": "General Purpose group 6 Fuse Lock", + "values": [ + { + "name": "UNLOCKED", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP_WP", + "value": 3, + "description": "OP+WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)", + "deprecated_names": [ + "OP+WP" + ] + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP_WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)", + "deprecated_names": [ + "RP+WP" + ] + }, + { + "name": "RP_OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)", + "deprecated_names": [ + "RP+OP" + ] + }, + { + "name": "ALL_LOCKS", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)", + "deprecated_names": [ + "All locks" + ] + } + ] + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "ECID", + "description": "Device Unique ID" + }, + "registers": [ + { + "id": "fuse12", + "name": "ECID3", + "description": "Device Unique ID", + "index_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse13", + "name": "ECID2", + "description": "Device Unique ID", + "index_int": "0x000D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse14", + "name": "ECID1", + "description": "Device Unique ID", + "index_int": "0x000E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse15", + "name": "ECID0", + "description": "Device Unique ID", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + } + ] + }, + { + "group": { + "name": "Reserved 0x10-0x17", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 22 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x11", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 2 + }, + { + "width": 6 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x12", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x13", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 6 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x14", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 19 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x15", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0015", + "is_reserved": true + }, + { + "id": "Reserved22", + "name": "Reserved 0x16", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0016", + "is_reserved": true + }, + { + "id": "Reserved23", + "name": "Reserved 0x17", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0017", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0018", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse24-bits-0-3", + "name": "Boot_Mode_Fuses", + "description": "Boot_Mode_Fuses", + "values": [ + { + "name": "BOOT_INTERNAL_FUSES", + "value": 8, + "description": "Cortex-M33 From internal fuses" + }, + { + "name": "BOOT_SERIAL_DOWNLOADER", + "value": 9, + "description": "Cortex-M33 Serial Downloader USB 1" + }, + { + "name": "BOOT_EMMC", + "value": 10, + "description": "Cortex-M33 USDHC1 8-bit eMMC 5.1" + }, + { + "name": "BOOT_SD_CARD", + "value": 11, + "description": "Cortex-M33 USDHC2 4-bit SD3.0" + }, + { + "name": "BOOT_FLEXSPI_NOR", + "value": 12, + "description": "Cortex-M33 FlexSPI Serial NOR" + }, + { + "name": "BOOT_FLEXSPI_NAND", + "value": 13, + "description": "Cortex-M33 FlexSPI Serial NAND 2K page" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-4", + "name": "Override_FlexSPI_NOR_Boot_Selection", + "description": "Override FlexSPI NOR Boot Selection", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Do not override", + "deprecated_names": [ + "0" + ] + }, + { + "name": "Override", + "value": 1, + "description": "Override" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-5-6", + "name": "FlexSPI_NOR_Boot_Override_Selection", + "description": "FlexSPI NOR Boot Override Selection", + "values": [ + { + "name": "FLEXSPI_HYPERFLASH", + "value": 0, + "description": "Flex SPI (Hyperflash 1.8V)", + "deprecated_names": [ + "00" + ] + }, + { + "name": "FLEXSPI_4B_READ", + "value": 1, + "description": "Flex SPI (Flash with 4B READ(0x13)default supported)", + "deprecated_names": [ + "01" + ] + }, + { + "name": "OCTAL_MICRON", + "value": 2, + "description": "Default Octal mode\u00a0(Micron, Nice to have)", + "deprecated_names": [ + "10" + ] + }, + { + "name": "OCTAL_MXIC", + "value": 3, + "description": "Default Octal mode (Mxic, Nice to have )", + "deprecated_names": [ + "11" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-7", + "name": "FlexSPI_NAND_4K_Page_Selection", + "description": "FlexSPI NAND 4K Page Selection", + "values": [ + { + "name": "DEFAULT_2K_PAGE", + "value": 0, + "description": "Not override the default selection (2K page)", + "deprecated_names": [ + "0" + ] + }, + { + "name": "OVERRIDE_4K_PAGE", + "value": 1, + "description": "Override, 4K page is selected.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-8", + "name": "uSDHC_Device_Type", + "description": "uSDHC_Device_Type", + "values": [ + { + "name": "EMMC", + "value": 0, + "description": "uSDHC_Device_Type: eMMC" + }, + { + "name": "SD", + "value": 1, + "description": "uSDHC_Device_Type: SD" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-9", + "name": "FLEXSPI_NOR_DATA_IOMUX_SION_EN", + "description": "FlexSPI NOR data IOMUX SION EN", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "SION is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "SION is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-10-11", + "name": "FLEXSPI_NOR_FCB_OFFSET", + "description": "FlexSPI NOR FCB offset", + "values": [ + { + "name": "OFFSET_400B", + "value": 0, + "description": "Select the offset of FlexSPI NOR FCB at 0x400B", + "deprecated_names": [ + "0x400B" + ] + }, + { + "name": "OFFSET_600B", + "value": 1, + "description": "Select the offset of FlexSPI NOR FCB at 0x600B", + "deprecated_names": [ + "0x600B" + ] + }, + { + "name": "OFFSET_800B", + "value": 2, + "description": "Select the offset of FlexSPI NOR FCB at 0x800B", + "deprecated_names": [ + "0x800B" + ] + }, + { + "name": "OFFSET_A00B", + "value": 3, + "description": "Select the offset of FlexSPI NOR FCB at 0xA00B", + "deprecated_names": [ + "0xA00B" + ] + } + ] + }, + { + "width": 3, + "id": "fuse24-bits-12-14", + "name": "FLEXSPI_AUTOPROBE_FREQ_SEL", + "description": "FlexSPI autoprobe freq sel", + "values": [ + { + "name": "FREQ_24MHZ", + "value": 0, + "description": "24MHz", + "deprecated_names": [ + "24MHz" + ] + }, + { + "name": "FREQ_133MHZ", + "value": 1, + "description": "133 MHz", + "deprecated_names": [ + "133_MHz" + ] + }, + { + "name": "FREQ_166MHZ", + "value": 2, + "description": "166 MHz", + "deprecated_names": [ + "166_MHz" + ] + }, + { + "name": "FREQ_200MHZ", + "value": 3, + "description": "200 MHz", + "deprecated_names": [ + "200_MHz" + ] + }, + { + "name": "FREQ_80MHZ", + "value": 4, + "description": "80MHz", + "deprecated_names": [ + "80MHz" + ] + }, + { + "name": "FREQ_60MHZ", + "value": 5, + "description": "60MHz", + "deprecated_names": [ + "60MHz" + ] + }, + { + "name": "FREQ_100MHZ", + "value": 6, + "description": "100 MHz" + }, + { + "name": "FREQ_100MHZ_DEFAULT", + "value": 7, + "description": "100 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-15", + "name": "FLEXSPI_FCB_COPY_FLAG", + "description": "FlexSPI FCB copy flag", + "values": [ + { + "name": "MUST HAVE", + "value": 0, + "description": "FCB copy is must-have;" + }, + { + "name": "OPTIONAL", + "value": 1, + "description": "FCB copy is optional." + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-16", + "name": "SD_Loopback_Clock_Source_Sel", + "description": "SD loopback clock source sel", + "values": [ + { + "name": "THROUGH_SD_PAD", + "value": 0, + "description": "Through SD pad", + "deprecated_names": [ + "0" + ] + }, + { + "name": "DIRECT", + "value": 1, + "description": "Direct" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-17-18", + "name": "SD_Speed_Selection", + "description": "SD speed selection ", + "values": [ + { + "name": "BIT_4_MODE", + "value": 0, + "description": "4 bit", + "deprecated_names": [ + "4_bit" + ] + }, + { + "name": "BIT_8_MODE", + "value": 1, + "description": "8 bit", + "deprecated_names": [ + "8_bit" + ] + }, + { + "name": "BIT_4_DDR_MODE", + "value": 2, + "description": "4 bit DDR (eMMC 4.4)", + "deprecated_names": [ + "10" + ] + }, + { + "name": "BIT_8_DDR_MODE", + "value": 3, + "description": "8 bit DDR (eMMC 4.4)", + "deprecated_names": [ + "11" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-19", + "name": "eMMC_Speed_Selection", + "description": "eMMC speed selection", + "values": [ + { + "name": "NORMAL_SPEED", + "value": 0, + "description": "Normal Speed" + }, + { + "name": "HIGH_SPEED", + "value": 1, + "description": "High Speed" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-20", + "name": "eMMC_fast_boot", + "description": "eMMC fast boot", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-21", + "name": "BT_FREQ_SEL_1", + "description": "Boot frequency / voltage select[1]", + "values": [ + { + "name": "SEE_BT_FREQ_SEL", + "value": 0, + "description": "See BT_FREQ_SEL BOOT_CFG0[28]", + "deprecated_names": [ + "0" + ] + }, + { + "name": "OVERDRIVE_FREQ_SEL", + "value": 1, + "description": "Overdrive Frequency Select.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-22", + "name": "eMMC_voltage_selection", + "description": "eMMC voltage select", + "values": [ + { + "name": "VOLTAGE_3V3", + "value": 0, + "description": "eMMC_voltage_selection: 3.3v", + "deprecated_names": [ + "3.3v" + ] + }, + { + "name": "VOLTAGE_1V8", + "value": 1, + "description": "eMMC_voltage_selection: 1.8v", + "deprecated_names": [ + "1.8v" + ] + } + ] + }, + { + "width": 5, + "id": "fuse24-bits-23-27", + "name": "FlexSPI_NOR_Reset_Pin_selections", + "description": "FlexSPI NOR reset pin selections", + "values": [ + { + "name": "GPIO_PIN_0", + "value": 0, + "description": "GPIO[x].0", + "deprecated_names": [ + "GPIO[x].0" + ] + }, + { + "name": "GPIO_PIN_1", + "value": 1, + "description": "GPIO[x].1" + }, + { + "name": "GPIO_PIN_2", + "value": 2, + "description": "GPIO[x].2" + }, + { + "name": "GPIO_PIN_3", + "value": 3, + "description": "GPIO[x].3" + }, + { + "name": "GPIO_PIN_4", + "value": 4, + "description": "GPIO[x].4" + }, + { + "name": "GPIO_PIN_5", + "value": 5, + "description": "GPIO[x].5" + }, + { + "name": "GPIO_PIN_6", + "value": 6, + "description": "GPIO[x].6" + }, + { + "name": "GPIO_PIN_7", + "value": 7, + "description": "GPIO[x].7" + }, + { + "name": "GPIO_PIN_8", + "value": 8, + "description": "GPIO[x].8" + }, + { + "name": "GPIO_PIN_9", + "value": 9, + "description": "GPIO[x].9" + }, + { + "name": "GPIO_PIN_10", + "value": 10, + "description": "GPIO[x].10" + }, + { + "name": "GPIO_PIN_11", + "value": 11, + "description": "GPIO[x].11" + }, + { + "name": "GPIO_PIN_12", + "value": 12, + "description": "GPIO[x].12" + }, + { + "name": "GPIO_PIN_13", + "value": 13, + "description": "GPIO[x].13" + }, + { + "name": "GPIO_PIN_14", + "value": 14, + "description": "GPIO[x].14" + }, + { + "name": "GPIO_PIN_15", + "value": 15, + "description": "GPIO[x].15" + }, + { + "name": "GPIO_PIN_16", + "value": 16, + "description": "GPIO[x].16" + }, + { + "name": "GPIO_PIN_17", + "value": 17, + "description": "GPIO[x].17" + }, + { + "name": "GPIO_PIN_18", + "value": 18, + "description": "GPIO[x].18" + }, + { + "name": "GPIO_PIN_19", + "value": 19, + "description": "GPIO[x].19" + }, + { + "name": "GPIO_PIN_20", + "value": 20, + "description": "GPIO[x].20" + }, + { + "name": "GPIO_PIN_21", + "value": 21, + "description": "GPIO[x].21" + }, + { + "name": "GPIO_PIN_22", + "value": 22, + "description": "GPIO[x].22" + }, + { + "name": "GPIO_PIN_23", + "value": 23, + "description": "GPIO[x].23" + }, + { + "name": "GPIO_PIN_24", + "value": 24, + "description": "GPIO[x].24" + }, + { + "name": "GPIO_PIN_25", + "value": 25, + "description": "GPIO[x].25" + }, + { + "name": "GPIO_PIN_26", + "value": 26, + "description": "GPIO[x].26" + }, + { + "name": "GPIO_PIN_27", + "value": 27, + "description": "GPIO[x].27" + }, + { + "name": "GPIO_PIN_28", + "value": 28, + "description": "GPIO[x].28" + }, + { + "name": "GPIO_PIN_29", + "value": 29, + "description": "GPIO[x].29" + }, + { + "name": "GPIO_PIN_30", + "value": 30, + "description": "GPIO[x].30" + }, + { + "name": "GPIO_PIN_31", + "value": 31, + "description": "GPIO[x].31", + "deprecated_names": [ + "GPIO[x].31" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-28", + "name": "BT_FREQ_SEL", + "description": "Boot frequency / voltage select [0]", + "values": [ + { + "name": "NORMAL_FREQUENCY", + "value": 0, + "description": "Normal clock frequency", + "deprecated_names": [ + "0" + ] + }, + { + "name": "LOW_FREQUENCY", + "value": 1, + "description": "Low clock frequency", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-29", + "name": "BT_FUSE_SEL", + "description": "Boot Fuse indication", + "values": [ + { + "name": "NOT_PROGRAMMED", + "value": 0, + "description": "Boot fuses not programmed", + "deprecated_names": [ + "0" + ] + }, + { + "name": "PROGRAMMED", + "value": 1, + "description": "Boot fuses programmed yet", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-30", + "name": "Force_Boot_from_Fuse", + "description": "Force boot from fuse", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override Boot_Mode pins by boot mode fuses", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-31", + "name": "Force_Serial_Download", + "description": "Force serial download", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Normal boot mode selection based on Boot_Mode and Boot Mode Fuses" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override all other Boot_Mode and Boot Mode Fuses and enter Serial Download" + } + ] + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0019", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse25-bit-0", + "name": "Fast_Boot_Acknowledge_Disable", + "description": "Fast boot acknowledge disable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot Ack Disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot Ack Enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse25-bit-2", + "name": "uSDHC_Power_On_Polarity", + "description": "uSDHC power on polarity", + "values": [ + { + "name": "LOW", + "value": 0, + "description": "uSDHC_Power_On_Polarity: Low" + }, + { + "name": "HIGH", + "value": 1, + "description": "uSDHC_Power_On_Polarity: High" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-3", + "name": "uSDHC_Power_CycleDelay", + "description": "uSDHC power cycle delay", + "values": [ + { + "name": "DELAY_5MS", + "value": 0, + "description": "uSDHC_Power_CycleDelay: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "DELAY_2_5MS", + "value": 1, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-4-5", + "name": "uSDHC_Power_Cycle_Interval", + "description": "uSDHC power cycle interval", + "values": [ + { + "name": "INTERVAL_20MS", + "value": 0, + "description": "20 ms", + "deprecated_names": [ + "20_ms" + ] + }, + { + "name": "INTERVAL_10MS", + "value": 1, + "description": "10 ms", + "deprecated_names": [ + "10_ms" + ] + }, + { + "name": "INTERVAL_5MS", + "value": 2, + "description": "uSDHC_Power_Cycle_Interval: 5 ms", + "deprecated_names": [ + "5_ms" + ] + }, + { + "name": "INTERVAL_2_5MS", + "value": 3, + "description": "2.5 ms", + "deprecated_names": [ + "2.5_ms" + ] + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-6-7", + "name": "SD_Calibration_Step", + "description": "SD calibration step ", + "values": [ + { + "name": "1_delay_cell", + "value": 0, + "description": "1 delay cell" + }, + { + "name": "2_delay_cell", + "value": 1, + "description": "2 delay cell" + }, + { + "name": "3_delay_cell", + "value": 2, + "description": "3 delay cell" + }, + { + "name": "5_delay_cell", + "value": 3, + "description": "5 delay cell" + } + ] + }, + { + "width": 8, + "id": "fuse25-bits-8-15", + "name": "uSDHC_PAD_Settings_Low_bits", + "description": "uSDHC pad settings low bits. The override value for uSDHC pad settings ", + "values": [ + { + "name": "MIN_SETTING", + "value": 0, + "description": "Minimum pad setting value (00000000)", + "deprecated_names": [ + "11111111" + ] + }, + { + "name": "SETTING_1", + "value": 1, + "description": "Pad setting configuration 1" + }, + { + "name": "VALUE_002", + "value": 2, + "description": "Value 2" + }, + { + "name": "VALUE_003", + "value": 3, + "description": "Value 3" + }, + { + "name": "VALUE_004", + "value": 4, + "description": "Value 4" + }, + { + "name": "VALUE_005", + "value": 5, + "description": "Value 5" + }, + { + "name": "VALUE_006", + "value": 6, + "description": "Value 6" + }, + { + "name": "VALUE_007", + "value": 7, + "description": "Value 7" + }, + { + "name": "VALUE_008", + "value": 8, + "description": "Value 8" + }, + { + "name": "VALUE_009", + "value": 9, + "description": "Value 9" + }, + { + "name": "VALUE_010", + "value": 10, + "description": "Value 10" + }, + { + "name": "SETTING_15", + "value": 15, + "description": "Pad setting configuration 15" + }, + { + "name": "VALUE_016", + "value": 16, + "description": "Value 16" + }, + { + "name": "SETTING_31", + "value": 31, + "description": "Pad setting configuration 31" + }, + { + "name": "VALUE_032", + "value": 32, + "description": "Value 32" + }, + { + "name": "SETTING_63", + "value": 63, + "description": "Pad setting configuration 63" + }, + { + "name": "VALUE_064", + "value": 64, + "description": "Value 64" + }, + { + "name": "SETTING_127", + "value": 127, + "description": "Pad setting configuration 127" + }, + { + "name": "SETTING_128", + "value": 128, + "description": "Pad setting configuration 128" + }, + { + "name": "SETTING_191", + "value": 191, + "description": "Pad setting configuration 191" + }, + { + "name": "VALUE_192", + "value": 192, + "description": "Value 192" + }, + { + "name": "VALUE_223", + "value": 223, + "description": "Value 223" + }, + { + "name": "SETTING_224", + "value": 224, + "description": "Pad setting configuration 224" + }, + { + "name": "SETTING_240", + "value": 240, + "description": "Pad setting configuration 240" + }, + { + "name": "SETTING_248", + "value": 248, + "description": "Pad setting configuration 248" + }, + { + "name": "SETTING_252", + "value": 252, + "description": "Pad setting configuration 252" + }, + { + "name": "SETTING_254", + "value": 254, + "description": "Pad setting configuration 254" + }, + { + "name": "MAX_SETTING", + "value": 255, + "description": "Maximum pad setting value (11111111)" + } + ] + }, + { + "width": 4, + "id": "fuse25-bits-16-19", + "name": "uSDHC_PAD_Setting_High_bits", + "description": "uSDHC pad settings high bits. The override value for uSDHC pad settings", + "values": [ + { + "name": "LEVEL_0", + "value": 0, + "description": "uSDHC_PAD_Setting_High_bits: 1111", + "deprecated_names": [ + "1111" + ] + }, + { + "name": "LEVEL_1", + "value": 1, + "description": "Pad setting level 1" + }, + { + "name": "LEVEL_2", + "value": 2, + "description": "Pad setting level 2" + }, + { + "name": "LEVEL_3", + "value": 3, + "description": "Pad setting level 3" + }, + { + "name": "LEVEL_4", + "value": 4, + "description": "Pad setting level 4" + }, + { + "name": "LEVEL_5", + "value": 5, + "description": "Pad setting level 5" + }, + { + "name": "LEVEL_6", + "value": 6, + "description": "Pad setting level 6" + }, + { + "name": "LEVEL_7", + "value": 7, + "description": "Pad setting level 7" + }, + { + "name": "LEVEL_8", + "value": 8, + "description": "Pad setting level 8" + }, + { + "name": "LEVEL_9", + "value": 9, + "description": "Pad setting level 9" + }, + { + "name": "LEVEL_10", + "value": 10, + "description": "Pad setting level 10" + }, + { + "name": "LEVEL_11", + "value": 11, + "description": "Pad setting level 11" + }, + { + "name": "LEVEL_12", + "value": 12, + "description": "Pad setting level 12" + }, + { + "name": "LEVEL_13", + "value": 13, + "description": "Pad setting level 13" + }, + { + "name": "LEVEL_14", + "value": 14, + "description": "Pad setting level 14" + }, + { + "name": "LEVEL_15", + "value": 15, + "description": "Pad setting level 15" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-20", + "name": "Power_Cycle_Enable", + "description": "Power cycle enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "No power cycle", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-21", + "name": "uSDHC_Override_Pad_Settings", + "description": "uSDHC override pad settings " + }, + { + "width": 1, + "id": "fuse25-bit-22", + "name": "uSDHC_DLL_Enable", + "description": "uSDHC DLL enable ", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse25-bits-24-30", + "name": "MMC_DLL_DLY", + "description": "MMC DLL delay : Delay target for uSDHC DLL, it is applied to slave mode target delay or override mode target delay depends on DLL Override fuse bit value\n", + "values": [ + { + "name": "DELAY_MIN", + "value": 0, + "description": "Minimum DLL delay setting", + "deprecated_names": [ + "1111111" + ] + }, + { + "name": "DELAY_STEP_1", + "value": 1, + "description": "DLL delay step 1" + }, + { + "name": "DELAY_002", + "value": 2, + "description": "Delay setting 2" + }, + { + "name": "DELAY_003", + "value": 3, + "description": "Delay setting 3" + }, + { + "name": "DELAY_004", + "value": 4, + "description": "Delay setting 4" + }, + { + "name": "DELAY_005", + "value": 5, + "description": "Delay setting 5" + }, + { + "name": "DELAY_6", + "value": 6, + "description": "Delay setting 6" + }, + { + "name": "DELAY_7", + "value": 7, + "description": "Delay setting 7" + }, + { + "name": "DELAY_8", + "value": 8, + "description": "Delay setting 8" + }, + { + "name": "DELAY_9", + "value": 9, + "description": "Delay setting 9" + }, + { + "name": "DELAY_010", + "value": 10, + "description": "Delay setting 10" + }, + { + "name": "DELAY_11", + "value": 11, + "description": "Delay setting 11" + }, + { + "name": "DELAY_12", + "value": 12, + "description": "Delay setting 12" + }, + { + "name": "DELAY_13", + "value": 13, + "description": "Delay setting 13" + }, + { + "name": "DELAY_14", + "value": 14, + "description": "Delay setting 14" + }, + { + "name": "DELAY_STEP_15", + "value": 15, + "description": "DLL delay step 15" + }, + { + "name": "DELAY_016", + "value": 16, + "description": "Delay setting 16" + }, + { + "name": "DELAY_17", + "value": 17, + "description": "Delay setting 17" + }, + { + "name": "DELAY_18", + "value": 18, + "description": "Delay setting 18" + }, + { + "name": "DELAY_19", + "value": 19, + "description": "Delay setting 19" + }, + { + "name": "DELAY_20", + "value": 20, + "description": "Delay setting 20" + }, + { + "name": "DELAY_21", + "value": 21, + "description": "Delay setting 21" + }, + { + "name": "DELAY_22", + "value": 22, + "description": "Delay setting 22" + }, + { + "name": "DELAY_23", + "value": 23, + "description": "Delay setting 23" + }, + { + "name": "DELAY_24", + "value": 24, + "description": "Delay setting 24" + }, + { + "name": "DELAY_25", + "value": 25, + "description": "Delay setting 25" + }, + { + "name": "DELAY_26", + "value": 26, + "description": "Delay setting 26" + }, + { + "name": "DELAY_27", + "value": 27, + "description": "Delay setting 27" + }, + { + "name": "DELAY_28", + "value": 28, + "description": "Delay setting 28" + }, + { + "name": "DELAY_29", + "value": 29, + "description": "Delay setting 29" + }, + { + "name": "DELAY_30", + "value": 30, + "description": "Delay setting 30" + }, + { + "name": "DELAY_STEP_31", + "value": 31, + "description": "DLL delay step 31" + }, + { + "name": "DELAY_032", + "value": 32, + "description": "Delay setting 32" + }, + { + "name": "DELAY_33", + "value": 33, + "description": "Delay setting 33" + }, + { + "name": "DELAY_34", + "value": 34, + "description": "Delay setting 34" + }, + { + "name": "DELAY_35", + "value": 35, + "description": "Delay setting 35" + }, + { + "name": "DELAY_36", + "value": 36, + "description": "Delay setting 36" + }, + { + "name": "DELAY_37", + "value": 37, + "description": "Delay setting 37" + }, + { + "name": "DELAY_38", + "value": 38, + "description": "Delay setting 38" + }, + { + "name": "DELAY_39", + "value": 39, + "description": "Delay setting 39" + }, + { + "name": "DELAY_40", + "value": 40, + "description": "Delay setting 40" + }, + { + "name": "DELAY_41", + "value": 41, + "description": "Delay setting 41" + }, + { + "name": "DELAY_42", + "value": 42, + "description": "Delay setting 42" + }, + { + "name": "DELAY_43", + "value": 43, + "description": "Delay setting 43" + }, + { + "name": "DELAY_44", + "value": 44, + "description": "Delay setting 44" + }, + { + "name": "DELAY_45", + "value": 45, + "description": "Delay setting 45" + }, + { + "name": "DELAY_46", + "value": 46, + "description": "Delay setting 46" + }, + { + "name": "DELAY_47", + "value": 47, + "description": "Delay setting 47" + }, + { + "name": "DELAY_48", + "value": 48, + "description": "Delay setting 48" + }, + { + "name": "DELAY_49", + "value": 49, + "description": "Delay setting 49" + }, + { + "name": "DELAY_50", + "value": 50, + "description": "Delay setting 50" + }, + { + "name": "DELAY_51", + "value": 51, + "description": "Delay setting 51" + }, + { + "name": "DELAY_52", + "value": 52, + "description": "Delay setting 52" + }, + { + "name": "DELAY_53", + "value": 53, + "description": "Delay setting 53" + }, + { + "name": "DELAY_54", + "value": 54, + "description": "Delay setting 54" + }, + { + "name": "DELAY_55", + "value": 55, + "description": "Delay setting 55" + }, + { + "name": "DELAY_56", + "value": 56, + "description": "Delay setting 56" + }, + { + "name": "DELAY_57", + "value": 57, + "description": "Delay setting 57" + }, + { + "name": "DELAY_58", + "value": 58, + "description": "Delay setting 58" + }, + { + "name": "DELAY_59", + "value": 59, + "description": "Delay setting 59" + }, + { + "name": "DELAY_60", + "value": 60, + "description": "Delay setting 60" + }, + { + "name": "DELAY_61", + "value": 61, + "description": "Delay setting 61" + }, + { + "name": "DELAY_62", + "value": 62, + "description": "Delay setting 62" + }, + { + "name": "DELAY_MID", + "value": 63, + "description": "Mid-range DLL delay setting" + }, + { + "name": "DELAY_064", + "value": 64, + "description": "Delay setting 64" + }, + { + "name": "DELAY_65", + "value": 65, + "description": "Delay setting 65" + }, + { + "name": "DELAY_66", + "value": 66, + "description": "Delay setting 66" + }, + { + "name": "DELAY_67", + "value": 67, + "description": "Delay setting 67" + }, + { + "name": "DELAY_68", + "value": 68, + "description": "Delay setting 68" + }, + { + "name": "DELAY_69", + "value": 69, + "description": "Delay setting 69" + }, + { + "name": "DELAY_70", + "value": 70, + "description": "Delay setting 70" + }, + { + "name": "DELAY_71", + "value": 71, + "description": "Delay setting 71" + }, + { + "name": "DELAY_72", + "value": 72, + "description": "Delay setting 72" + }, + { + "name": "DELAY_73", + "value": 73, + "description": "Delay setting 73" + }, + { + "name": "DELAY_74", + "value": 74, + "description": "Delay setting 74" + }, + { + "name": "DELAY_75", + "value": 75, + "description": "Delay setting 75" + }, + { + "name": "DELAY_76", + "value": 76, + "description": "Delay setting 76" + }, + { + "name": "DELAY_77", + "value": 77, + "description": "Delay setting 77" + }, + { + "name": "DELAY_78", + "value": 78, + "description": "Delay setting 78" + }, + { + "name": "DELAY_79", + "value": 79, + "description": "Delay setting 79" + }, + { + "name": "DELAY_80", + "value": 80, + "description": "Delay setting 80" + }, + { + "name": "DELAY_81", + "value": 81, + "description": "Delay setting 81" + }, + { + "name": "DELAY_82", + "value": 82, + "description": "Delay setting 82" + }, + { + "name": "DELAY_83", + "value": 83, + "description": "Delay setting 83" + }, + { + "name": "DELAY_84", + "value": 84, + "description": "Delay setting 84" + }, + { + "name": "DELAY_85", + "value": 85, + "description": "Delay setting 85" + }, + { + "name": "DELAY_86", + "value": 86, + "description": "Delay setting 86" + }, + { + "name": "DELAY_87", + "value": 87, + "description": "Delay setting 87" + }, + { + "name": "DELAY_88", + "value": 88, + "description": "Delay setting 88" + }, + { + "name": "DELAY_89", + "value": 89, + "description": "Delay setting 89" + }, + { + "name": "DELAY_90", + "value": 90, + "description": "Delay setting 90" + }, + { + "name": "DELAY_91", + "value": 91, + "description": "Delay setting 91" + }, + { + "name": "DELAY_92", + "value": 92, + "description": "Delay setting 92" + }, + { + "name": "DELAY_93", + "value": 93, + "description": "Delay setting 93" + }, + { + "name": "DELAY_94", + "value": 94, + "description": "Delay setting 94" + }, + { + "name": "DELAY_STEP_95", + "value": 95, + "description": "DLL delay step 95" + }, + { + "name": "DELAY_096", + "value": 96, + "description": "Delay setting 96" + }, + { + "name": "DELAY_97", + "value": 97, + "description": "Delay setting 97" + }, + { + "name": "DELAY_98", + "value": 98, + "description": "Delay setting 98" + }, + { + "name": "DELAY_99", + "value": 99, + "description": "Delay setting 99" + }, + { + "name": "DELAY_100", + "value": 100, + "description": "Delay setting 100" + }, + { + "name": "DELAY_101", + "value": 101, + "description": "Delay setting 101" + }, + { + "name": "DELAY_102", + "value": 102, + "description": "Delay setting 102" + }, + { + "name": "DELAY_103", + "value": 103, + "description": "Delay setting 103" + }, + { + "name": "DELAY_104", + "value": 104, + "description": "Delay setting 104" + }, + { + "name": "DELAY_105", + "value": 105, + "description": "Delay setting 105" + }, + { + "name": "DELAY_106", + "value": 106, + "description": "Delay setting 106" + }, + { + "name": "DELAY_107", + "value": 107, + "description": "Delay setting 107" + }, + { + "name": "DELAY_108", + "value": 108, + "description": "Delay setting 108" + }, + { + "name": "DELAY_109", + "value": 109, + "description": "Delay setting 109" + }, + { + "name": "DELAY_110", + "value": 110, + "description": "Delay setting 110" + }, + { + "name": "DELAY_STEP_111", + "value": 111, + "description": "DLL delay step 111" + }, + { + "name": "DELAY_112", + "value": 112, + "description": "Delay setting 112" + }, + { + "name": "DELAY_113", + "value": 113, + "description": "Delay setting 113" + }, + { + "name": "DELAY_114", + "value": 114, + "description": "Delay setting 114" + }, + { + "name": "DELAY_115", + "value": 115, + "description": "Delay setting 115" + }, + { + "name": "DELAY_116", + "value": 116, + "description": "Delay setting 116" + }, + { + "name": "DELAY_117", + "value": 117, + "description": "Delay setting 117" + }, + { + "name": "DELAY_118", + "value": 118, + "description": "Delay setting 118" + }, + { + "name": "DELAY_119", + "value": 119, + "description": "Delay setting 119" + }, + { + "name": "DELAY_120", + "value": 120, + "description": "Delay setting 120" + }, + { + "name": "DELAY_121", + "value": 121, + "description": "Delay setting 121" + }, + { + "name": "DELAY_122", + "value": 122, + "description": "Delay setting 122" + }, + { + "name": "DELAY_123", + "value": 123, + "description": "Delay setting 123" + }, + { + "name": "DELAY_124", + "value": 124, + "description": "Delay setting 124" + }, + { + "name": "DELAY_125", + "value": 125, + "description": "Delay setting 125" + }, + { + "name": "DELAY_126", + "value": 126, + "description": "Delay setting 126" + }, + { + "name": "DELAY_MAX", + "value": 127, + "description": "Maximum DLL delay setting" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-31", + "name": "uSDHC_DLL_Select", + "description": "uSDHC DLL select", + "values": [ + { + "name": "DLL_SLAVE", + "value": 0, + "description": "DLL Slave Mode for" + }, + { + "name": "DLL_OVERRIDE", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x001A", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse26-bits-0-1", + "name": "FlexSPI_NAND_Column_Address_Width", + "description": "FlexSPI NAND Column Address Width", + "values": [ + { + "name": "WIDTH_12_BITS", + "value": 0, + "description": "12 bit column address width" + }, + { + "name": "WIDTH_13_BITS", + "value": 1, + "description": "13 bit column address width" + }, + { + "name": "WIDTH_14_BITS", + "value": 2, + "description": "14 bit column address width" + }, + { + "name": "WIDTH_15_BITS", + "value": 3, + "description": "15 bit column address width" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-2-3", + "name": "FlexSPI_NAND_CS_Interval", + "description": "FlexSPI NAND CS Interval", + "values": [ + { + "name": "INTERVAL_100NS", + "value": 0, + "description": "100 ns" + }, + { + "name": "INTERVAL_200NS", + "value": 1, + "description": "200 ns" + }, + { + "name": "INTERVAL_400NS", + "value": 2, + "description": "400 ns" + }, + { + "name": "INTERVAL_50NS", + "value": 3, + "description": "50 ns" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-4-5", + "name": "FlexSPI_NAND_Search_Count", + "description": "FlexSPI NAND Search Count", + "values": [ + { + "name": "COUNT_2", + "value": 0, + "description": "FlexSPI_NAND_Search_Count: 2", + "deprecated_names": [ + "2" + ] + }, + { + "name": "2_redudant", + "value": 1, + "description": "2 redudant" + }, + { + "name": "COUNT_4", + "value": 2, + "description": "FlexSPI_NAND_Search_Count: 4", + "deprecated_names": [ + "4" + ] + }, + { + "name": "COUNT_8", + "value": 3, + "description": "FlexSPI_NAND_Search_Count: 8", + "deprecated_names": [ + "8" + ] + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-6-7", + "name": "FlexSPI_NAND_Search_Stride", + "description": "FlexSPI NAND Search Stride", + "values": [ + { + "name": "64_pages", + "value": 0, + "description": "64 pages" + }, + { + "name": "128_pages", + "value": 1, + "description": "128 pages" + }, + { + "name": "256_pages", + "value": 2, + "description": "256 pages" + }, + { + "name": "32_pages", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 8, + "id": "fuse26-bits-8-15", + "name": "FlexSPI_DLL_Value", + "description": "FlexSPI DLL Value", + "values": [ + { + "name": "DLL_DELAY_MIN", + "value": 0, + "description": "The delay line value only for HyperFlash - minimum delay (0)", + "deprecated_names": [ + "11111111" + ] + }, + { + "name": "DLL_DELAY_1", + "value": 1, + "description": "The delay line value only for HyperFlash - delay value 1" + }, + { + "name": "DLL_DELAY_2", + "value": 2, + "description": "The delay line value only for HyperFlash - delay value 2" + }, + { + "name": "DLL_DELAY_3", + "value": 3, + "description": "The delay line value only for HyperFlash - delay value 3" + }, + { + "name": "DLL_DELAY_4", + "value": 4, + "description": "The delay line value only for HyperFlash - delay value 4" + }, + { + "name": "DLL_DELAY_5", + "value": 5, + "description": "The delay line value only for HyperFlash - delay value 5" + }, + { + "name": "DLL_DELAY_6", + "value": 6, + "description": "The delay line value only for HyperFlash - delay value 6" + }, + { + "name": "DLL_DELAY_7", + "value": 7, + "description": "The delay line value only for HyperFlash - delay value 7" + }, + { + "name": "DLL_DELAY_8", + "value": 8, + "description": "The delay line value only for HyperFlash - delay value 8" + }, + { + "name": "DLL_DELAY_9", + "value": 9, + "description": "The delay line value only for HyperFlash - delay value 9" + }, + { + "name": "DLL_DELAY_10", + "value": 10, + "description": "The delay line value only for HyperFlash - delay value 10" + }, + { + "name": "DLL_DELAY_11", + "value": 11, + "description": "The delay line value only for HyperFlash - delay value 11" + }, + { + "name": "DLL_DELAY_12", + "value": 12, + "description": "The delay line value only for HyperFlash - delay value 12" + }, + { + "name": "DLL_DELAY_13", + "value": 13, + "description": "The delay line value only for HyperFlash - delay value 13" + }, + { + "name": "DLL_DELAY_14", + "value": 14, + "description": "The delay line value only for HyperFlash - delay value 14" + }, + { + "name": "DLL_DELAY_15", + "value": 15, + "description": "The delay line value only for HyperFlash - delay value 15" + }, + { + "name": "DLL_DELAY_16", + "value": 16, + "description": "The delay line value only for HyperFlash - delay value 16" + }, + { + "name": "DLL_DELAY_17", + "value": 17, + "description": "The delay line value only for HyperFlash - delay value 17" + }, + { + "name": "DLL_DELAY_18", + "value": 18, + "description": "The delay line value only for HyperFlash - delay value 18" + }, + { + "name": "DLL_DELAY_19", + "value": 19, + "description": "The delay line value only for HyperFlash - delay value 19" + }, + { + "name": "DLL_DELAY_20", + "value": 20, + "description": "The delay line value only for HyperFlash - delay value 20" + }, + { + "name": "DLL_DELAY_21", + "value": 21, + "description": "The delay line value only for HyperFlash - delay value 21" + }, + { + "name": "DLL_DELAY_22", + "value": 22, + "description": "The delay line value only for HyperFlash - delay value 22" + }, + { + "name": "DLL_DELAY_23", + "value": 23, + "description": "The delay line value only for HyperFlash - delay value 23" + }, + { + "name": "DLL_DELAY_24", + "value": 24, + "description": "The delay line value only for HyperFlash - delay value 24" + }, + { + "name": "DLL_DELAY_25", + "value": 25, + "description": "The delay line value only for HyperFlash - delay value 25" + }, + { + "name": "DLL_DELAY_26", + "value": 26, + "description": "The delay line value only for HyperFlash - delay value 26" + }, + { + "name": "DLL_DELAY_27", + "value": 27, + "description": "The delay line value only for HyperFlash - delay value 27" + }, + { + "name": "DLL_DELAY_28", + "value": 28, + "description": "The delay line value only for HyperFlash - delay value 28" + }, + { + "name": "DLL_DELAY_29", + "value": 29, + "description": "The delay line value only for HyperFlash - delay value 29" + }, + { + "name": "DLL_DELAY_30", + "value": 30, + "description": "The delay line value only for HyperFlash - delay value 30" + }, + { + "name": "DLL_DELAY_31", + "value": 31, + "description": "The delay line value only for HyperFlash - delay value 31" + }, + { + "name": "DLL_DELAY_32", + "value": 32, + "description": "The delay line value only for HyperFlash - delay value 32" + }, + { + "name": "DLL_DELAY_33", + "value": 33, + "description": "The delay line value only for HyperFlash - delay value 33" + }, + { + "name": "DLL_DELAY_34", + "value": 34, + "description": "The delay line value only for HyperFlash - delay value 34" + }, + { + "name": "DLL_DELAY_35", + "value": 35, + "description": "The delay line value only for HyperFlash - delay value 35" + }, + { + "name": "DLL_DELAY_36", + "value": 36, + "description": "The delay line value only for HyperFlash - delay value 36" + }, + { + "name": "DLL_DELAY_37", + "value": 37, + "description": "The delay line value only for HyperFlash - delay value 37" + }, + { + "name": "DLL_DELAY_38", + "value": 38, + "description": "The delay line value only for HyperFlash - delay value 38" + }, + { + "name": "DLL_DELAY_39", + "value": 39, + "description": "The delay line value only for HyperFlash - delay value 39" + }, + { + "name": "DLL_DELAY_40", + "value": 40, + "description": "The delay line value only for HyperFlash - delay value 40" + }, + { + "name": "DLL_DELAY_41", + "value": 41, + "description": "The delay line value only for HyperFlash - delay value 41" + }, + { + "name": "DLL_DELAY_42", + "value": 42, + "description": "The delay line value only for HyperFlash - delay value 42" + }, + { + "name": "DLL_DELAY_43", + "value": 43, + "description": "The delay line value only for HyperFlash - delay value 43" + }, + { + "name": "DLL_DELAY_44", + "value": 44, + "description": "The delay line value only for HyperFlash - delay value 44" + }, + { + "name": "DLL_DELAY_45", + "value": 45, + "description": "The delay line value only for HyperFlash - delay value 45" + }, + { + "name": "DLL_DELAY_46", + "value": 46, + "description": "The delay line value only for HyperFlash - delay value 46" + }, + { + "name": "DLL_DELAY_47", + "value": 47, + "description": "The delay line value only for HyperFlash - delay value 47" + }, + { + "name": "DLL_DELAY_48", + "value": 48, + "description": "The delay line value only for HyperFlash - delay value 48" + }, + { + "name": "DLL_DELAY_49", + "value": 49, + "description": "The delay line value only for HyperFlash - delay value 49" + }, + { + "name": "DLL_DELAY_50", + "value": 50, + "description": "The delay line value only for HyperFlash - delay value 50" + }, + { + "name": "DLL_DELAY_51", + "value": 51, + "description": "The delay line value only for HyperFlash - delay value 51" + }, + { + "name": "DLL_DELAY_52", + "value": 52, + "description": "The delay line value only for HyperFlash - delay value 52" + }, + { + "name": "DLL_DELAY_53", + "value": 53, + "description": "The delay line value only for HyperFlash - delay value 53" + }, + { + "name": "DLL_DELAY_54", + "value": 54, + "description": "The delay line value only for HyperFlash - delay value 54" + }, + { + "name": "DLL_DELAY_55", + "value": 55, + "description": "The delay line value only for HyperFlash - delay value 55" + }, + { + "name": "DLL_DELAY_56", + "value": 56, + "description": "The delay line value only for HyperFlash - delay value 56" + }, + { + "name": "DLL_DELAY_57", + "value": 57, + "description": "The delay line value only for HyperFlash - delay value 57" + }, + { + "name": "DLL_DELAY_58", + "value": 58, + "description": "The delay line value only for HyperFlash - delay value 58" + }, + { + "name": "DLL_DELAY_59", + "value": 59, + "description": "The delay line value only for HyperFlash - delay value 59" + }, + { + "name": "DLL_DELAY_60", + "value": 60, + "description": "The delay line value only for HyperFlash - delay value 60" + }, + { + "name": "DLL_DELAY_61", + "value": 61, + "description": "The delay line value only for HyperFlash - delay value 61" + }, + { + "name": "DLL_DELAY_62", + "value": 62, + "description": "The delay line value only for HyperFlash - delay value 62" + }, + { + "name": "DLL_DELAY_63", + "value": 63, + "description": "The delay line value only for HyperFlash - delay value 63" + }, + { + "name": "DLL_DELAY_64", + "value": 64, + "description": "The delay line value only for HyperFlash - delay value 64" + }, + { + "name": "DLL_DELAY_65", + "value": 65, + "description": "The delay line value only for HyperFlash - delay value 65" + }, + { + "name": "DLL_DELAY_66", + "value": 66, + "description": "The delay line value only for HyperFlash - delay value 66" + }, + { + "name": "DLL_DELAY_67", + "value": 67, + "description": "The delay line value only for HyperFlash - delay value 67" + }, + { + "name": "DLL_DELAY_68", + "value": 68, + "description": "The delay line value only for HyperFlash - delay value 68" + }, + { + "name": "DLL_DELAY_69", + "value": 69, + "description": "The delay line value only for HyperFlash - delay value 69" + }, + { + "name": "DLL_DELAY_70", + "value": 70, + "description": "The delay line value only for HyperFlash - delay value 70" + }, + { + "name": "DLL_DELAY_71", + "value": 71, + "description": "The delay line value only for HyperFlash - delay value 71" + }, + { + "name": "DLL_DELAY_72", + "value": 72, + "description": "The delay line value only for HyperFlash - delay value 72" + }, + { + "name": "DLL_DELAY_73", + "value": 73, + "description": "The delay line value only for HyperFlash - delay value 73" + }, + { + "name": "DLL_DELAY_74", + "value": 74, + "description": "The delay line value only for HyperFlash - delay value 74" + }, + { + "name": "DLL_DELAY_75", + "value": 75, + "description": "The delay line value only for HyperFlash - delay value 75" + }, + { + "name": "DLL_DELAY_76", + "value": 76, + "description": "The delay line value only for HyperFlash - delay value 76" + }, + { + "name": "DLL_DELAY_77", + "value": 77, + "description": "The delay line value only for HyperFlash - delay value 77" + }, + { + "name": "DLL_DELAY_78", + "value": 78, + "description": "The delay line value only for HyperFlash - delay value 78" + }, + { + "name": "DLL_DELAY_79", + "value": 79, + "description": "The delay line value only for HyperFlash - delay value 79" + }, + { + "name": "DLL_DELAY_80", + "value": 80, + "description": "The delay line value only for HyperFlash - delay value 80" + }, + { + "name": "DLL_DELAY_81", + "value": 81, + "description": "The delay line value only for HyperFlash - delay value 81" + }, + { + "name": "DLL_DELAY_82", + "value": 82, + "description": "The delay line value only for HyperFlash - delay value 82" + }, + { + "name": "DLL_DELAY_83", + "value": 83, + "description": "The delay line value only for HyperFlash - delay value 83" + }, + { + "name": "DLL_DELAY_84", + "value": 84, + "description": "The delay line value only for HyperFlash - delay value 84" + }, + { + "name": "DLL_DELAY_85", + "value": 85, + "description": "The delay line value only for HyperFlash - delay value 85" + }, + { + "name": "DLL_DELAY_86", + "value": 86, + "description": "The delay line value only for HyperFlash - delay value 86" + }, + { + "name": "DLL_DELAY_87", + "value": 87, + "description": "The delay line value only for HyperFlash - delay value 87" + }, + { + "name": "DLL_DELAY_88", + "value": 88, + "description": "The delay line value only for HyperFlash - delay value 88" + }, + { + "name": "DLL_DELAY_89", + "value": 89, + "description": "The delay line value only for HyperFlash - delay value 89" + }, + { + "name": "DLL_DELAY_90", + "value": 90, + "description": "The delay line value only for HyperFlash - delay value 90" + }, + { + "name": "DLL_DELAY_91", + "value": 91, + "description": "The delay line value only for HyperFlash - delay value 91" + }, + { + "name": "DLL_DELAY_92", + "value": 92, + "description": "The delay line value only for HyperFlash - delay value 92" + }, + { + "name": "DLL_DELAY_93", + "value": 93, + "description": "The delay line value only for HyperFlash - delay value 93" + }, + { + "name": "DLL_DELAY_94", + "value": 94, + "description": "The delay line value only for HyperFlash - delay value 94" + }, + { + "name": "DLL_DELAY_95", + "value": 95, + "description": "The delay line value only for HyperFlash - delay value 95" + }, + { + "name": "DLL_DELAY_96", + "value": 96, + "description": "The delay line value only for HyperFlash - delay value 96" + }, + { + "name": "DLL_DELAY_97", + "value": 97, + "description": "The delay line value only for HyperFlash - delay value 97" + }, + { + "name": "DLL_DELAY_98", + "value": 98, + "description": "The delay line value only for HyperFlash - delay value 98" + }, + { + "name": "DLL_DELAY_99", + "value": 99, + "description": "The delay line value only for HyperFlash - delay value 99" + }, + { + "name": "DLL_DELAY_100", + "value": 100, + "description": "The delay line value only for HyperFlash - delay value 100" + }, + { + "name": "DLL_DELAY_101", + "value": 101, + "description": "The delay line value only for HyperFlash - delay value 101" + }, + { + "name": "DLL_DELAY_102", + "value": 102, + "description": "The delay line value only for HyperFlash - delay value 102" + }, + { + "name": "DLL_DELAY_103", + "value": 103, + "description": "The delay line value only for HyperFlash - delay value 103" + }, + { + "name": "DLL_DELAY_104", + "value": 104, + "description": "The delay line value only for HyperFlash - delay value 104" + }, + { + "name": "DLL_DELAY_105", + "value": 105, + "description": "The delay line value only for HyperFlash - delay value 105" + }, + { + "name": "DLL_DELAY_106", + "value": 106, + "description": "The delay line value only for HyperFlash - delay value 106" + }, + { + "name": "DLL_DELAY_107", + "value": 107, + "description": "The delay line value only for HyperFlash - delay value 107" + }, + { + "name": "DLL_DELAY_108", + "value": 108, + "description": "The delay line value only for HyperFlash - delay value 108" + }, + { + "name": "DLL_DELAY_109", + "value": 109, + "description": "The delay line value only for HyperFlash - delay value 109" + }, + { + "name": "DLL_DELAY_110", + "value": 110, + "description": "The delay line value only for HyperFlash - delay value 110" + }, + { + "name": "DLL_DELAY_111", + "value": 111, + "description": "The delay line value only for HyperFlash - delay value 111" + }, + { + "name": "DLL_DELAY_112", + "value": 112, + "description": "The delay line value only for HyperFlash - delay value 112" + }, + { + "name": "DLL_DELAY_113", + "value": 113, + "description": "The delay line value only for HyperFlash - delay value 113" + }, + { + "name": "DLL_DELAY_114", + "value": 114, + "description": "The delay line value only for HyperFlash - delay value 114" + }, + { + "name": "DLL_DELAY_115", + "value": 115, + "description": "The delay line value only for HyperFlash - delay value 115" + }, + { + "name": "DLL_DELAY_116", + "value": 116, + "description": "The delay line value only for HyperFlash - delay value 116" + }, + { + "name": "DLL_DELAY_117", + "value": 117, + "description": "The delay line value only for HyperFlash - delay value 117" + }, + { + "name": "DLL_DELAY_118", + "value": 118, + "description": "The delay line value only for HyperFlash - delay value 118" + }, + { + "name": "DLL_DELAY_119", + "value": 119, + "description": "The delay line value only for HyperFlash - delay value 119" + }, + { + "name": "DLL_DELAY_120", + "value": 120, + "description": "The delay line value only for HyperFlash - delay value 120" + }, + { + "name": "DLL_DELAY_121", + "value": 121, + "description": "The delay line value only for HyperFlash - delay value 121" + }, + { + "name": "DLL_DELAY_122", + "value": 122, + "description": "The delay line value only for HyperFlash - delay value 122" + }, + { + "name": "DLL_DELAY_123", + "value": 123, + "description": "The delay line value only for HyperFlash - delay value 123" + }, + { + "name": "DLL_DELAY_124", + "value": 124, + "description": "The delay line value only for HyperFlash - delay value 124" + }, + { + "name": "DLL_DELAY_125", + "value": 125, + "description": "The delay line value only for HyperFlash - delay value 125" + }, + { + "name": "DLL_DELAY_126", + "value": 126, + "description": "The delay line value only for HyperFlash - delay value 126" + }, + { + "name": "DLL_DELAY_127", + "value": 127, + "description": "The delay line value only for HyperFlash - delay value 127" + }, + { + "name": "DLL_DELAY_128", + "value": 128, + "description": "The delay line value only for HyperFlash - delay value 128" + }, + { + "name": "DLL_DELAY_129", + "value": 129, + "description": "The delay line value only for HyperFlash - delay value 129" + }, + { + "name": "DLL_DELAY_130", + "value": 130, + "description": "The delay line value only for HyperFlash - delay value 130" + }, + { + "name": "DLL_DELAY_131", + "value": 131, + "description": "The delay line value only for HyperFlash - delay value 131" + }, + { + "name": "DLL_DELAY_132", + "value": 132, + "description": "The delay line value only for HyperFlash - delay value 132" + }, + { + "name": "DLL_DELAY_133", + "value": 133, + "description": "The delay line value only for HyperFlash - delay value 133" + }, + { + "name": "DLL_DELAY_134", + "value": 134, + "description": "The delay line value only for HyperFlash - delay value 134" + }, + { + "name": "DLL_DELAY_135", + "value": 135, + "description": "The delay line value only for HyperFlash - delay value 135" + }, + { + "name": "DLL_DELAY_136", + "value": 136, + "description": "The delay line value only for HyperFlash - delay value 136" + }, + { + "name": "DLL_DELAY_137", + "value": 137, + "description": "The delay line value only for HyperFlash - delay value 137" + }, + { + "name": "DLL_DELAY_138", + "value": 138, + "description": "The delay line value only for HyperFlash - delay value 138" + }, + { + "name": "DLL_DELAY_139", + "value": 139, + "description": "The delay line value only for HyperFlash - delay value 139" + }, + { + "name": "DLL_DELAY_140", + "value": 140, + "description": "The delay line value only for HyperFlash - delay value 140" + }, + { + "name": "DLL_DELAY_141", + "value": 141, + "description": "The delay line value only for HyperFlash - delay value 141" + }, + { + "name": "DLL_DELAY_142", + "value": 142, + "description": "The delay line value only for HyperFlash - delay value 142" + }, + { + "name": "DLL_DELAY_143", + "value": 143, + "description": "The delay line value only for HyperFlash - delay value 143" + }, + { + "name": "DLL_DELAY_144", + "value": 144, + "description": "The delay line value only for HyperFlash - delay value 144" + }, + { + "name": "DLL_DELAY_145", + "value": 145, + "description": "The delay line value only for HyperFlash - delay value 145" + }, + { + "name": "DLL_DELAY_146", + "value": 146, + "description": "The delay line value only for HyperFlash - delay value 146" + }, + { + "name": "DLL_DELAY_147", + "value": 147, + "description": "The delay line value only for HyperFlash - delay value 147" + }, + { + "name": "DELAY_148", + "value": 148, + "description": "The delay line value only for HyperFlash - delay value 148" + }, + { + "name": "DELAY_149", + "value": 149, + "description": "The delay line value only for HyperFlash - delay value 149" + }, + { + "name": "DELAY_150", + "value": 150, + "description": "The delay line value only for HyperFlash - delay value 150" + }, + { + "name": "DELAY_151", + "value": 151, + "description": "The delay line value only for HyperFlash - delay value 151" + }, + { + "name": "DELAY_152", + "value": 152, + "description": "The delay line value only for HyperFlash - delay value 152" + }, + { + "name": "DELAY_153", + "value": 153, + "description": "The delay line value only for HyperFlash - delay value 153" + }, + { + "name": "DELAY_154", + "value": 154, + "description": "The delay line value only for HyperFlash - delay value 154" + }, + { + "name": "DELAY_155", + "value": 155, + "description": "The delay line value only for HyperFlash - delay value 155" + }, + { + "name": "DELAY_156", + "value": 156, + "description": "The delay line value only for HyperFlash - delay value 156" + }, + { + "name": "DELAY_157", + "value": 157, + "description": "The delay line value only for HyperFlash - delay value 157" + }, + { + "name": "DELAY_158", + "value": 158, + "description": "The delay line value only for HyperFlash - delay value 158" + }, + { + "name": "DELAY_159", + "value": 159, + "description": "The delay line value only for HyperFlash - delay value 159" + }, + { + "name": "DELAY_160", + "value": 160, + "description": "The delay line value only for HyperFlash - delay value 160" + }, + { + "name": "DELAY_161", + "value": 161, + "description": "The delay line value only for HyperFlash - delay value 161" + }, + { + "name": "DELAY_162", + "value": 162, + "description": "The delay line value only for HyperFlash - delay value 162" + }, + { + "name": "DELAY_163", + "value": 163, + "description": "The delay line value only for HyperFlash - delay value 163" + }, + { + "name": "DELAY_164", + "value": 164, + "description": "The delay line value only for HyperFlash - delay value 164" + }, + { + "name": "DELAY_165", + "value": 165, + "description": "The delay line value only for HyperFlash - delay value 165" + }, + { + "name": "DELAY_166", + "value": 166, + "description": "The delay line value only for H" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-16", + "name": "SPI_Clock_Data_Phase_Control", + "description": "SPI clock data phase control ", + "values": [ + { + "name": "TX_FALL_RX_RISE", + "value": 0, + "description": "Tx on falling, Rx on rising", + "deprecated_names": [ + "0" + ] + }, + { + "name": "TX_RISE_RX_FALL", + "value": 1, + "description": "Tx on rising, Rx on falling", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-17", + "name": "SPI_SCLK_Active", + "description": "SPI SCLK active", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high" + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-18", + "name": "SPI_SS_Active", + "description": "SPI SS active", + "values": [ + { + "name": "ACTIVE_LOW", + "value": 0, + "description": "Active low" + }, + { + "name": "ACTIVE_HIGH", + "value": 1, + "description": "Active high" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-19", + "name": "Recovery_SPI_Addressing", + "description": "Recovery SPI addressing", + "values": [ + { + "name": "ADDRESSING_3BYTE", + "value": 0, + "description": "3-bytes (24-bit)", + "deprecated_names": [ + "3-bytes" + ] + }, + { + "name": "ADDRESSING_2BYTE", + "value": 1, + "description": "2-bytes (16-bit)", + "deprecated_names": [ + "2-bytes" + ] + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-20", + "name": "FLEXSPI_NOR_AUTO_PROBE_EN", + "description": "FlexSPI NOR auto probe enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Auto probe is disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Auto probe is enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 3, + "id": "fuse26-bits-21-23", + "name": "FlexSPI_NAND_Busy_Bit_Offset_Override", + "description": "FlexSPI NAND busy bit offset override ", + "values": [ + { + "name": "BIT_OFFSET_0", + "value": 0, + "description": "Busy bit at offset 0 in 8-bit register" + }, + { + "name": "BIT_OFFSET_1", + "value": 1, + "description": "Busy bit at offset 1 in 8-bit register" + }, + { + "name": "BIT_OFFSET_2", + "value": 2, + "description": "Busy bit at offset 2 in 8-bit register" + }, + { + "name": "BIT_OFFSET_3", + "value": 3, + "description": "Busy bit at offset 3 in 8-bit register" + }, + { + "name": "BIT_OFFSET_4", + "value": 4, + "description": "Busy bit at offset 4 in 8-bit register" + }, + { + "name": "BIT_OFFSET_5", + "value": 5, + "description": "Busy bit at offset 5 in 8-bit register" + }, + { + "name": "BIT_OFFSET_6", + "value": 6, + "description": "Busy bit at offset 6 in 8-bit register" + }, + { + "name": "BIT_OFFSET_7", + "value": 7, + "description": "Busy bit at offset 7 in 8-bit register" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-24", + "name": "Recovery_CS_Select", + "description": "Recovery CS select", + "values": [ + { + "name": "CS0", + "value": 0, + "description": "Recovery_CS_Select: CS0" + }, + { + "name": "CS1", + "value": 1, + "description": "Recovery_CS_Select: CS1" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse26-bits-26-27", + "name": "Recovery_Port_Select", + "description": "Recovery Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 4, + "id": "fuse26-bits-28-31", + "name": "FLEXSPI_DUMMY_CYCLE_SEL", + "description": "FlexSPI Dummy Cycle Select", + "values": [ + { + "name": "0_cycle", + "value": 0, + "description": "0 cycle" + }, + { + "name": "CYCLES_1", + "value": 1, + "description": "1 cycle" + }, + { + "name": "CYCLES_2", + "value": 2, + "description": "2 cycles" + }, + { + "name": "CYCLES_3", + "value": 3, + "description": "3 cycles" + }, + { + "name": "CYCLES_4", + "value": 4, + "description": "4 cycles" + }, + { + "name": "CYCLES_5", + "value": 5, + "description": "5 cycles" + }, + { + "name": "CYCLES_6", + "value": 6, + "description": "6 cycles" + }, + { + "name": "CYCLES_7", + "value": 7, + "description": "7 cycles" + }, + { + "name": "CYCLES_8", + "value": 8, + "description": "8 cycles" + }, + { + "name": "CYCLES_9", + "value": 9, + "description": "9 cycles" + }, + { + "name": "CYCLES_10", + "value": 10, + "description": "10 cycles" + }, + { + "name": "CYCLES_11", + "value": 11, + "description": "11 cycles" + }, + { + "name": "CYCLES_12", + "value": 12, + "description": "12 cycles" + }, + { + "name": "CYCLES_13", + "value": 13, + "description": "13 cycles" + }, + { + "name": "CYCLES_14", + "value": 14, + "description": "14 cycles" + }, + { + "name": "15_cycles", + "value": 15, + "description": "15 cycles" + } + ] + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_CFG3", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x001B", + "bitfields": [ + { + "width": 3, + "id": "fuse27-bits-0-2", + "name": "FlexSPI_NOR_Reset_Port", + "description": "FlexSPI NOR Reset Pin Selection", + "values": [ + { + "name": "NOT_RESET_BOOT", + "value": 0, + "description": "Not reset boot device" + }, + { + "name": "GPIO_PORT1", + "value": 1, + "description": "GPIO port1" + }, + { + "name": "GPIO_PORT2", + "value": 2, + "description": "GPIO port2" + }, + { + "name": "GPIO_PORT3", + "value": 3, + "description": "GPIO port3" + }, + { + "name": "GPIO_PORT4", + "value": 4, + "description": "GPIO port4" + }, + { + "name": "GPIO_PORT5", + "value": 5, + "description": "GPIO port5" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-3-4", + "name": "FLEXSPI_NOR_AUTO_PROBE_TYPE", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_AUTO_PROBE", + "value": 0, + "description": "QuadSPI/OctalSPI NOR auto probe (quad sdr auto probe by default, quad ddr if Override_FlexSPI_NOR_Boot_Selection=1 and FlexSPI_NOR_Boot_Override_Selection=01)" + }, + { + "name": "MXIC_OCTAL", + "value": 1, + "description": "MxicOctal" + }, + { + "name": "MICRON_OCTAL", + "value": 2, + "description": "MicronOctal" + }, + { + "name": "ADESTO_OCTAL", + "value": 3, + "description": "AdestoOctal" + } + ] + }, + { + "width": 3, + "id": "fuse27-bits-5-7", + "name": "FLEXSPI_AUTO_PROBE_DATA_PAD", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MXIC_OCTAL", + "value": 2, + "description": "MxicOctal" + }, + { + "name": "MICRON_OCTAL", + "value": 4, + "description": "MicronOctal" + }, + { + "name": "ADESTO_OCTAL", + "value": 6, + "description": "AdestoOctal" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-8", + "name": "FLEXSPI_AUTO_PROBE_DDR_SUPPORT", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "QuadSPI NOR and OctalSPI NOR auto probe disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "OctalSPI NOR auto probe enabled (MxicOctal, MicronOctal, AdestoOctal)" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-9", + "name": "FLEXSPI_DUMMY_CYCLE_SEL1", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MXIC_OCTAL", + "value": 1, + "description": "MxicOctal" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-10", + "name": "EDMA_INIT_M7_TCM", + "description": "FLEXSPI NOR AUTO PROBE type", + "values": [ + { + "name": "QUADSPI_NOR", + "value": 0, + "description": "EDMA M7 TCM initialization disabled" + }, + { + "name": "OCTAL_FLASH", + "value": 1, + "description": "Octal flash type (MxicOctal, MicronOctal, or AdestoOctal)" + } + ] + }, + { + "width": 21 + } + ] + }, + { + "id": "Reserved28", + "name": "Reserved 0x1C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001C", + "is_reserved": true + }, + { + "id": "Reserved29", + "name": "Reserved 0x1D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001D", + "is_reserved": true + }, + { + "id": "Reserved30", + "name": "Reserved 0x1E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001E", + "is_reserved": true + }, + { + "id": "Reserved31", + "name": "Reserved 0x1F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x001F", + "is_reserved": true + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0020", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8, + "id": "fuse32-bits-8-15", + "name": "Secondary_boot_offset", + "description": "Secondary boot offset", + "values": [ + { + "name": "OFFSET_4MB", + "value": 0, + "description": "Secondary_boot_offset: 4 MB", + "deprecated_names": [ + "4_MB" + ] + }, + { + "name": "OFFSET_2MB", + "value": 1, + "description": "Secondary_boot_offset: 2 MB", + "deprecated_names": [ + "2_MB" + ] + }, + { + "name": "OFFSET_1MB", + "value": 2, + "description": "Secondary_boot_offset: 1 MB", + "deprecated_names": [ + "1_MB" + ] + }, + { + "name": "OFFSET_8MB", + "value": 3, + "description": "Secondary_boot_offset: 8 MB", + "deprecated_names": [ + "8_MB" + ] + }, + { + "name": "OFFSET_16MB", + "value": 4, + "description": "Secondary_boot_offset: 8MB,", + "deprecated_names": [ + "8MB," + ] + }, + { + "name": "OFFSET_32MB", + "value": 5, + "description": "Secondary_boot_offset: 32MB", + "deprecated_names": [ + "32MB" + ] + }, + { + "name": "OFFSET_64MB", + "value": 6, + "description": "Offset = 64 MB" + }, + { + "name": "OFFSET_128MB", + "value": 7, + "description": "Offset = 128 MB" + }, + { + "name": "OFFSET_256MB", + "value": 8, + "description": "Offset = 256 MB" + }, + { + "name": "OFFSET_512MB", + "value": 9, + "description": "Offset = 512 MB", + "deprecated_names": [ + "512_MB" + ] + }, + { + "name": "EMMC_LAST_128MB", + "value": 254, + "description": "EMMC last 128 MB" + }, + { + "name": "EMMC_LAST_24KB", + "value": 255, + "description": "EMMC last 24 KB", + "deprecated_names": [ + "last_24K" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-17", + "name": "M33_D_Cache_Disable", + "description": "M33 D cache disable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "Enabled" + }, + { + "name": "DISABLED", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-19", + "name": "M33_Recovery_Disable", + "description": "Disable A55 SPI recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-20", + "name": "M33_Recovery_Device", + "description": "Disable M33 SPI recovery", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-22", + "name": "AHAB_Reauth", + "description": "AHAB reauth", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Re-authenticate the whole boot code after standby exit is disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Re-authenticate the whole boot code after standby exit is enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-23", + "name": "M33_WDOG_Enable", + "description": "M33 WDOG enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-24", + "name": "A55_I_Cache_Dis", + "description": "A55 I cache dis", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable A55 I-Cache during ROM Boot" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable A55 I-Cache during ROM Boot" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-25", + "name": "M33_I_Cache_Dis", + "description": "M33 I cache dis", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable M33 I-Cache during ROM Boot" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable M33 I-Cache during ROM Boot" + } + ] + }, + { + "width": 2, + "id": "fuse32-bits-26-27", + "name": "WDOG_Timeout_Select", + "description": "WDOG timeout select", + "values": [ + { + "name": "TIMEOUT_32S", + "value": 0, + "description": "WDOG_Timeout_Select: 32 s", + "deprecated_names": [ + "32_s" + ] + }, + { + "name": "TIMEOUT_16S", + "value": 1, + "description": "WDOG_Timeout_Select: 16 s", + "deprecated_names": [ + "16_s" + ] + }, + { + "name": "TIMEOUT_8S", + "value": 2, + "description": "WDOG_Timeout_Select: 8 s", + "deprecated_names": [ + "8_s" + ] + }, + { + "name": "TIMEOUT_4S", + "value": 3, + "description": "WDOG_Timeout_Select: 4 s", + "deprecated_names": [ + "4_s" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse32-bit-29", + "name": "USB_HID_EP1_Out_Disable", + "description": "USB HID EP1 out disable", + "values": [ + { + "name": "USB_EP1", + "value": 0, + "description": "USB EP1 Transfer(EP1 Out enable)" + }, + { + "name": "USB_EP0", + "value": 1, + "description": "USB EP0 Transfer(EP1 Out disable)" + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-30", + "name": "PLL_LATE_EN", + "description": "PLL late en", + "values": [ + { + "name": "BEFORE_ROM_PATCH", + "value": 0, + "description": "Configure PLLs before installing ROM patch", + "deprecated_names": [ + "0" + ] + }, + { + "name": "AFTER_ROM_PATCH", + "value": 1, + "description": "Configure PLLs after install ROM patch", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse32-bit-31", + "name": "M33_TCM_MBIST_AT_BOOT_EN", + "description": "M33 TCM MBIST at boot enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + } + ] + }, + { + "id": "fuse33", + "name": "BOOT_CFG9", + "description": "Boot Configuration See tab BOOT_CFG", + "index_int": "0x0021", + "lock": { + "register_id": "fuse7", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-6", + "name": "M33_TZ_WDOG_Enable(non-ROM)", + "description": "M33 TZ WDOG Enable (non-ROM)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-8", + "name": "CM33_RST_Release_ACK (non-ROM)", + "description": "CM33 RST Release ACK (non-ROM)", + "values": [ + { + "name": "NO_ACK", + "value": 0, + "description": "No Ack from EdgeLock Enclave to release M33 Reset", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ACK_RECEIVED", + "value": 1, + "description": "Ack from EdgeLock Enclave to release M33 Reset", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1 + }, + { + "width": 14 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse33-bit-25", + "name": "DOUBLE_AUTH_EN", + "description": "Enable double authentication of NXP code. " + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse33-bit-28", + "name": "CONTAINER_FORMAT", + "description": "Selection between AHAB and AHAB with PQC container format", + "values": [ + { + "name": "AHAB_PQC", + "value": 0, + "description": "AHAB with PQC container format" + }, + { + "name": "AHAB_CLASSIC", + "value": 1, + "description": "AHAB container format" + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "Reserved34", + "name": "Reserved 0x22", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0022", + "is_reserved": true, + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 27 + } + ] + }, + { + "id": "fuse35", + "name": "BOOT_CFG11", + "description": "NXP Reserved - BOOT Configuration", + "index_int": "0x0023", + "bitfields": [ + { + "width": 1, + "id": "fuse35-bit-0", + "name": "USB2_SDP_Enable", + "description": "USB2 Serial Download Port Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "USB2 SDP is Disabled", + "deprecated_names": [ + "Disable" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "USB2 SDP is Enabled", + "deprecated_names": [ + "Enable" + ] + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-1", + "name": "USB1_SDP_Disable", + "description": "USB1 Serial Download Port Disable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "USB1_SDP_Disable: USB1", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "USB1 SDP is Disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 29 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x24-0x2F", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved36", + "name": "Reserved 0x24", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0024", + "is_reserved": true, + "reg_width": 16 + }, + { + "id": "Reserved37", + "name": "Reserved 0x25", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0025", + "is_reserved": true, + "reg_width": 16 + }, + { + "id": "Reserved38", + "name": "Reserved 0x26", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0026", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved39", + "name": "Reserved 0x27", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0027", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved40", + "name": "Reserved 0x28", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0028", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved41", + "name": "Reserved 0x29", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0029", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved42", + "name": "Reserved 0x2A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002A", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 6 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved43", + "name": "Reserved 0x2B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002B", + "is_reserved": true, + "bitfields": [ + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved44", + "name": "Reserved 0x2C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002C", + "is_reserved": true, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 5 + }, + { + "width": 5 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved45", + "name": "Reserved 0x2D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002D", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved46", + "name": "Reserved 0x2E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002E", + "is_reserved": true, + "bitfields": [ + { + "width": 7 + }, + { + "width": 7 + }, + { + "width": 6 + }, + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved47", + "name": "Reserved 0x2F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x002F", + "is_reserved": true, + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "OTP_UNIQ_ID", + "description": "Used by EdgeLock Enclave" + }, + "registers": [ + { + "id": "fuse48", + "name": "OTP_UNIQ_ID3", + "description": "Used by EdgeLock Enclave for:", + "index_int": "0x0030", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse49", + "name": "OTP_UNIQ_ID2", + "description": "Used by EdgeLock Enclave for:", + "index_int": "0x0031", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse50", + "name": "OTP_UNIQ_ID1", + "description": "Used by EdgeLock Enclave for:", + "index_int": "0x0032", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse51", + "name": "OTP_UNIQ_ID0", + "description": "Used by EdgeLock Enclave for:", + "index_int": "0x0033", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + } + ] + }, + { + "group": { + "name": "Reserved 0x34-0x37", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved52", + "name": "Reserved 0x34", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0034", + "is_reserved": true + }, + { + "id": "Reserved53", + "name": "Reserved 0x35", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0035", + "is_reserved": true + }, + { + "id": "Reserved54", + "name": "Reserved 0x36", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0036", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved55", + "name": "Reserved 0x37", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0037", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "ELE_MISC_CTRL", + "description": "ELE miscellaneous configuration" + }, + "registers": [ + { + "id": "fuse56", + "name": "ELE_MISC_CTRL0", + "description": "OEM controlled Fuse.", + "index_int": "0x0038", + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse56-bits-0-3", + "name": "SOC_SCOPE_PRIMARY_DBG_DISABLE", + "description": "Debug Disable for CM33 domain. The 4 bits correspond to : {spiden,sniden,dbgen,niden} " + }, + { + "width": 4, + "id": "fuse56-bits-4-7", + "name": "SOC_SCOPE1_DBG_DISABLE", + "description": "Debug disable for Trace Memory controller. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 4, + "id": "fuse56-bits-8-11", + "name": "SOC_SCOPE2_DBG_DISABLE", + "description": "Debug disable for CM7. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 4, + "id": "fuse56-bits-12-15", + "name": "SOC_SCOPE3_DBG_DISABLE", + "description": "Debug disable for DAP AHB-AP. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + } + ] + }, + { + "id": "fuse57", + "name": "ELE_MISC_CTRL1", + "description": "OEM controlled Fuse.", + "index_int": "0x0039", + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse57-bits-0-3", + "name": "SOC_SCOPE4_DBG_DISABLE", + "description": "Debug disable for apps cores, Camera SS and GPU. The 4 bits correspond to : {spiden,sniden,dbgen,niden}" + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse58", + "name": "ELE_MISC_CTRL2", + "description": "OEM controlled Fuse.", + "index_int": "0x003A", + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse58-bit-0", + "name": "OEM_AGDET_DISABLE", + "description": "Disable for analog glitch detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit-1", + "name": "OEM_VDET_DISABLE", + "description": "Disable for voltage detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit-2", + "name": "OEM_TMPSNS_DISABLE", + "description": "Disable for temperature sensor during boot" + }, + { + "width": 1, + "id": "fuse58-bit-3", + "name": "OEM_DGDET_DISABLE", + "description": "Disable for digital glitch detector during boot" + }, + { + "width": 1, + "id": "fuse58-bit-4", + "name": "FAST_BOOT_ENABLE", + "description": "Enable Fast boot. If set, Customer can choose secure fast boot / secure boot option using the container. ", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Only Secure boot using ELE possible.", + "deprecated_names": [ + "0" + ] + }, + { + "name": "ENABLED", + "value": 1, + "description": "Fast boot capable on the SoC.", + "deprecated_names": [ + "1" + ] + } + ] + }, + { + "width": 1, + "id": "fuse58-bit-5", + "name": "SJC_DISABLE", + "description": "Hardware disablement of SJC. Disables JTAG debugger, including ability for boundary scan.", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "SJC is enabled", + "deprecated_names": [ + "Enable" + ] + }, + { + "name": "DISABLED", + "value": 1, + "description": "SJC is disabled", + "deprecated_names": [ + "Disable" + ] + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse58-bit-8", + "name": "SOC_GLBL_DBG_DISABLE", + "description": "Disable all debug. " + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-10", + "name": "TZ_GLBL_DBG_DISABLE", + "description": "OEM controlled Fuse." + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse58-bit-12", + "name": "OEM_FDET_DISABLE", + "description": "Disable for Frequency detector during boot" + }, + { + "width": 3 + } + ] + }, + { + "id": "Reserved59", + "name": "Reserved 0x3B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse60", + "name": "ELE_MISC_CTRL4", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003C", + "reg_width": 16, + "bitfields": [ + { + "width": 12, + "id": "fuse60-bits-0-11", + "name": "EXPORT_CONTROL", + "description": "Each fuse disables the following cryptographic cores: \n[11] : SGI in S401 (Reserved)\n[10] : PKC in S401 (Reserved)\n[9] : Reserved\n[8] : Reserved for S401\n[7] : A55 Crypto extension\n[6] : M7 MMCAU (Reserved)\n[5] : M33 MMCAU (Reserved)\n[4] : OTFADs\n[3]: V2X SGI (Reserved)\n[2]: V2X PKC (Reserved)\n[1]: V2X BA414 (Reserved)\n[0]: IEE" + }, + { + "width": 3, + "id": "fuse60-bits-12-14", + "name": "ELE_BOOT_CRYPTO", + "description": "Boot Cryptographic selection between Classic, PQC and Hybrid. ", + "values": [ + { + "name": "CLASSIC_CRYPTO", + "value": 0, + "description": "Classic Crypto signature verification" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved61", + "name": "Reserved 0x3D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved62", + "name": "Reserved 0x3E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x003E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse63", + "name": "ELE_MISC_CTRL7", + "description": "OEM and NXP controlled. NXP should set OP to 1 so the shadows cannot be overwritten.", + "index_int": "0x003F", + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse63-bits-12-15", + "name": "OEM_SRK_RVK", + "description": "OEM key revoke fuses for tree of public keys" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x40-0x7F", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved64", + "name": "Reserved 0x40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0040", + "is_reserved": true + }, + { + "id": "Reserved65", + "name": "Reserved 0x41", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0041", + "is_reserved": true + }, + { + "id": "Reserved66", + "name": "Reserved 0x42", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0042", + "is_reserved": true + }, + { + "id": "Reserved67", + "name": "Reserved 0x43", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0043", + "is_reserved": true + }, + { + "id": "Reserved68", + "name": "Reserved 0x44", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0044", + "is_reserved": true + }, + { + "id": "Reserved69", + "name": "Reserved 0x45", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0045", + "is_reserved": true + }, + { + "id": "Reserved70", + "name": "Reserved 0x46", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0046", + "is_reserved": true + }, + { + "id": "Reserved71", + "name": "Reserved 0x47", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0047", + "is_reserved": true + }, + { + "id": "Reserved72", + "name": "Reserved 0x48", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0048", + "is_reserved": true + }, + { + "id": "Reserved73", + "name": "Reserved 0x49", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0049", + "is_reserved": true + }, + { + "id": "Reserved74", + "name": "Reserved 0x4A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004A", + "is_reserved": true + }, + { + "id": "Reserved75", + "name": "Reserved 0x4B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004B", + "is_reserved": true + }, + { + "id": "Reserved76", + "name": "Reserved 0x4C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004C", + "is_reserved": true + }, + { + "id": "Reserved77", + "name": "Reserved 0x4D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004D", + "is_reserved": true + }, + { + "id": "Reserved78", + "name": "Reserved 0x4E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004E", + "is_reserved": true + }, + { + "id": "Reserved79", + "name": "Reserved 0x4F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x004F", + "is_reserved": true + }, + { + "id": "Reserved80", + "name": "Reserved 0x50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0050", + "is_reserved": true + }, + { + "id": "Reserved81", + "name": "Reserved 0x51", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0051", + "is_reserved": true + }, + { + "id": "Reserved82", + "name": "Reserved 0x52", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0052", + "is_reserved": true + }, + { + "id": "Reserved83", + "name": "Reserved 0x53", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0053", + "is_reserved": true + }, + { + "id": "Reserved84", + "name": "Reserved 0x54", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0054", + "is_reserved": true + }, + { + "id": "Reserved85", + "name": "Reserved 0x55", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0055", + "is_reserved": true + }, + { + "id": "Reserved86", + "name": "Reserved 0x56", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0056", + "is_reserved": true + }, + { + "id": "Reserved87", + "name": "Reserved 0x57", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0057", + "is_reserved": true + }, + { + "id": "Reserved88", + "name": "Reserved 0x58", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0058", + "is_reserved": true + }, + { + "id": "Reserved89", + "name": "Reserved 0x59", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0059", + "is_reserved": true + }, + { + "id": "Reserved90", + "name": "Reserved 0x5A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005A", + "is_reserved": true + }, + { + "id": "Reserved91", + "name": "Reserved 0x5B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005B", + "is_reserved": true + }, + { + "id": "Reserved92", + "name": "Reserved 0x5C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005C", + "is_reserved": true + }, + { + "id": "Reserved93", + "name": "Reserved 0x5D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005D", + "is_reserved": true + }, + { + "id": "Reserved94", + "name": "Reserved 0x5E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005E", + "is_reserved": true + }, + { + "id": "Reserved95", + "name": "Reserved 0x5F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x005F", + "is_reserved": true + }, + { + "id": "Reserved96", + "name": "Reserved 0x60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0060", + "is_reserved": true + }, + { + "id": "Reserved97", + "name": "Reserved 0x61", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0061", + "is_reserved": true + }, + { + "id": "Reserved98", + "name": "Reserved 0x62", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0062", + "is_reserved": true + }, + { + "id": "Reserved99", + "name": "Reserved 0x63", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0063", + "is_reserved": true + }, + { + "id": "Reserved100", + "name": "Reserved 0x64", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0064", + "is_reserved": true + }, + { + "id": "Reserved101", + "name": "Reserved 0x65", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0065", + "is_reserved": true + }, + { + "id": "Reserved102", + "name": "Reserved 0x66", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0066", + "is_reserved": true + }, + { + "id": "Reserved103", + "name": "Reserved 0x67", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0067", + "is_reserved": true + }, + { + "id": "Reserved104", + "name": "Reserved 0x68", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0068", + "is_reserved": true + }, + { + "id": "Reserved105", + "name": "Reserved 0x69", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0069", + "is_reserved": true + }, + { + "id": "Reserved106", + "name": "Reserved 0x6A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006A", + "is_reserved": true + }, + { + "id": "Reserved107", + "name": "Reserved 0x6B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006B", + "is_reserved": true + }, + { + "id": "Reserved108", + "name": "Reserved 0x6C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006C", + "is_reserved": true + }, + { + "id": "Reserved109", + "name": "Reserved 0x6D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006D", + "is_reserved": true + }, + { + "id": "Reserved110", + "name": "Reserved 0x6E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006E", + "is_reserved": true + }, + { + "id": "Reserved111", + "name": "Reserved 0x6F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x006F", + "is_reserved": true + }, + { + "id": "Reserved112", + "name": "Reserved 0x70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0070", + "is_reserved": true + }, + { + "id": "Reserved113", + "name": "Reserved 0x71", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0071", + "is_reserved": true + }, + { + "id": "Reserved114", + "name": "Reserved 0x72", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0072", + "is_reserved": true + }, + { + "id": "Reserved115", + "name": "Reserved 0x73", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0073", + "is_reserved": true + }, + { + "id": "Reserved116", + "name": "Reserved 0x74", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0074", + "is_reserved": true + }, + { + "id": "Reserved117", + "name": "Reserved 0x75", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0075", + "is_reserved": true + }, + { + "id": "Reserved118", + "name": "Reserved 0x76", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0076", + "is_reserved": true + }, + { + "id": "Reserved119", + "name": "Reserved 0x77", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0077", + "is_reserved": true + }, + { + "id": "Reserved120", + "name": "Reserved 0x78", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0078", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved121", + "name": "Reserved 0x79", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0079", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved122", + "name": "Reserved 0x7A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007A", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved123", + "name": "Reserved 0x7B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007B", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved124", + "name": "Reserved 0x7C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007C", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved125", + "name": "Reserved 0x7D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved126", + "name": "Reserved 0x7E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved127", + "name": "Reserved 0x7F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x007F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "OEM_SRKH", + "description": "OEM SRK Hash" + }, + "registers": [ + { + "id": "fuse128", + "name": "OEM_SRKH0", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0080", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse129", + "name": "OEM_SRKH1", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0081", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse130", + "name": "OEM_SRKH2", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0082", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse131", + "name": "OEM_SRKH3", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0083", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse132", + "name": "OEM_SRKH4", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0084", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse133", + "name": "OEM_SRKH5", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0085", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse134", + "name": "OEM_SRKH6", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0086", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse135", + "name": "OEM_SRKH7", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0087", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse136", + "name": "OEM_SRKH8", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0088" + }, + { + "id": "fuse137", + "name": "OEM_SRKH9", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x0089", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse138", + "name": "OEM_SRKH10", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008A" + }, + { + "id": "fuse139", + "name": "OEM_SRKH11", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008B" + }, + { + "id": "fuse140", + "name": "OEM_SRKH12", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008C" + }, + { + "id": "fuse141", + "name": "OEM_SRKH13", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008D" + }, + { + "id": "fuse142", + "name": "OEM_SRKH14", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008E", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse143", + "name": "OEM_SRKH15", + "description": "HASH of OEM SRK table in container for boot image.", + "index_int": "0x008F", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + } + ] + }, + { + "group": { + "name": "Reserved 0x90-0xB3", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved144", + "name": "Reserved 0x90", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0090", + "is_reserved": true + }, + { + "id": "Reserved145", + "name": "Reserved 0x91", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0091", + "is_reserved": true + }, + { + "id": "Reserved146", + "name": "Reserved 0x92", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0092", + "is_reserved": true + }, + { + "id": "Reserved147", + "name": "Reserved 0x93", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0093", + "is_reserved": true + }, + { + "id": "Reserved148", + "name": "Reserved 0x94", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0094", + "is_reserved": true + }, + { + "id": "Reserved149", + "name": "Reserved 0x95", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0095", + "is_reserved": true + }, + { + "id": "Reserved150", + "name": "Reserved 0x96", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0096", + "is_reserved": true + }, + { + "id": "Reserved151", + "name": "Reserved 0x97", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0097", + "is_reserved": true + }, + { + "id": "Reserved152", + "name": "Reserved 0x98", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0098", + "is_reserved": true + }, + { + "id": "Reserved153", + "name": "Reserved 0x99", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0099", + "is_reserved": true + }, + { + "id": "Reserved154", + "name": "Reserved 0x9A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009A", + "is_reserved": true + }, + { + "id": "Reserved155", + "name": "Reserved 0x9B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009B", + "is_reserved": true + }, + { + "id": "Reserved156", + "name": "Reserved 0x9C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009C", + "is_reserved": true + }, + { + "id": "Reserved157", + "name": "Reserved 0x9D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009D", + "is_reserved": true + }, + { + "id": "Reserved158", + "name": "Reserved 0x9E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009E", + "is_reserved": true + }, + { + "id": "Reserved159", + "name": "Reserved 0x9F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x009F", + "is_reserved": true + }, + { + "id": "Reserved160", + "name": "Reserved 0xA0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A0", + "is_reserved": true + }, + { + "id": "Reserved161", + "name": "Reserved 0xA1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A1", + "is_reserved": true + }, + { + "id": "Reserved162", + "name": "Reserved 0xA2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A2", + "is_reserved": true + }, + { + "id": "Reserved163", + "name": "Reserved 0xA3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A3", + "is_reserved": true + }, + { + "id": "Reserved164", + "name": "Reserved 0xA4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A4", + "is_reserved": true + }, + { + "id": "Reserved165", + "name": "Reserved 0xA5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A5", + "is_reserved": true + }, + { + "id": "Reserved166", + "name": "Reserved 0xA6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A6", + "is_reserved": true + }, + { + "id": "Reserved167", + "name": "Reserved 0xA7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A7", + "is_reserved": true + }, + { + "id": "Reserved168", + "name": "Reserved 0xA8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A8", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved169", + "name": "Reserved 0xA9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00A9", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved170", + "name": "Reserved 0xAA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AA", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved171", + "name": "Reserved 0xAB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AB", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved172", + "name": "Reserved 0xAC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AC", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved173", + "name": "Reserved 0xAD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AD", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved174", + "name": "Reserved 0xAE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AE", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved175", + "name": "Reserved 0xAF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00AF", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved176", + "name": "Reserved 0xB0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B0", + "is_reserved": true + }, + { + "id": "Reserved177", + "name": "Reserved 0xB1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B1", + "is_reserved": true + }, + { + "id": "Reserved178", + "name": "Reserved 0xB2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B2", + "is_reserved": true + }, + { + "id": "Reserved179", + "name": "Reserved 0xB3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00B3", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "GPR1_CFG", + "description": "General purpose fuse 1" + }, + "registers": [ + { + "id": "fuse180", + "name": "GPR1_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM CLOSED.", + "index_int": "0x00B4" + }, + { + "id": "fuse181", + "name": "GPR1_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM CLOSED.", + "index_int": "0x00B5" + }, + { + "id": "fuse182", + "name": "GPR1_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM CLOSED.", + "index_int": "0x00B6" + }, + { + "id": "fuse183", + "name": "GPR1_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM CLOSED.", + "index_int": "0x00B7" + } + ] + }, + { + "group": { + "name": "OTFAD1", + "description": "OTFAD configuration" + }, + "registers": [ + { + "id": "fuse184", + "name": "OTFAD1_KEY3", + "description": "128-bit OTFAD key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00B8", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse185", + "name": "OTFAD1_KEY2", + "description": "128-bit OTFAD key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00B9", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse186", + "name": "OTFAD1_KEY1", + "description": "128-bit OTFAD key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00BA", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse187", + "name": "OTFAD1_KEY0", + "description": "128-bit OTFAD key for key blob unwrap. Key blob is in primary boot image", + "index_int": "0x00BB", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse188", + "name": "OTFAD1_CFG4", + "description": "OTFAD Control fuses", + "index_int": "0x00BC", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 3 + }, + { + "width": 1, + "id": "fuse188-bit-3", + "name": "OTFAD1_ENABLE", + "description": "Enable OTFAD decryption " + }, + { + "width": 1, + "id": "fuse188-bit-4", + "name": "OTFAD1_DISABLE_OVERRIDE", + "description": "Disable OTFAD function. " + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse188-bit-6", + "name": "OTFAD1_KEY_SCRAMBLE_CRC_EN", + "description": "Enable Key blob CRC" + }, + { + "width": 1, + "id": "fuse188-bit-7", + "name": "OTFAD1_KEY_SCRAMBLE_EN", + "description": "Enable OTFAD Key scramble using OTFAD1_KEY_SCRAMBLE during key blob process " + }, + { + "width": 8, + "id": "fuse188-bits-8-15", + "name": "OTFAD1_KEY_SCRAMBLE_ALIGN", + "description": "4x 2-bit key scramble align select for key blob unwrap" + }, + { + "width": 1, + "id": "fuse188-bit-16", + "name": "OTFAD1_RESTRICT_OTFAD_IPS", + "description": "Restrict IPS access to CR, SR and CRC" + }, + { + "width": 15 + } + ] + }, + { + "id": "fuse189", + "name": "OTFAD1_KEY_SCRAMBLE", + "description": "Key scramble data value for key blob unwrap", + "index_int": "0x00BD", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + } + ] + }, + { + "group": { + "name": "Reserved 0xBE-0x117", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved190", + "name": "Reserved 0xBE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BE", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved191", + "name": "Reserved 0xBF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00BF", + "is_reserved": true, + "bitfields": [ + { + "width": 9 + }, + { + "width": 23 + } + ] + }, + { + "id": "Reserved192", + "name": "Reserved 0xC0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C0", + "is_reserved": true + }, + { + "id": "Reserved193", + "name": "Reserved 0xC1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C1", + "is_reserved": true + }, + { + "id": "Reserved194", + "name": "Reserved 0xC2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C2", + "is_reserved": true + }, + { + "id": "Reserved195", + "name": "Reserved 0xC3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C3", + "is_reserved": true + }, + { + "id": "Reserved196", + "name": "Reserved 0xC4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C4", + "is_reserved": true + }, + { + "id": "Reserved197", + "name": "Reserved 0xC5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C5", + "is_reserved": true + }, + { + "id": "Reserved198", + "name": "Reserved 0xC6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C6", + "is_reserved": true + }, + { + "id": "Reserved199", + "name": "Reserved 0xC7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C7", + "is_reserved": true + }, + { + "id": "Reserved200", + "name": "Reserved 0xC8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C8", + "is_reserved": true + }, + { + "id": "Reserved201", + "name": "Reserved 0xC9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00C9", + "is_reserved": true + }, + { + "id": "Reserved202", + "name": "Reserved 0xCA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CA", + "is_reserved": true + }, + { + "id": "Reserved203", + "name": "Reserved 0xCB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CB", + "is_reserved": true + }, + { + "id": "Reserved204", + "name": "Reserved 0xCC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CC", + "is_reserved": true + }, + { + "id": "Reserved205", + "name": "Reserved 0xCD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CD", + "is_reserved": true + }, + { + "id": "Reserved206", + "name": "Reserved 0xCE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CE", + "is_reserved": true + }, + { + "id": "Reserved207", + "name": "Reserved 0xCF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00CF", + "is_reserved": true + }, + { + "id": "Reserved208", + "name": "Reserved 0xD0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D0", + "is_reserved": true + }, + { + "id": "Reserved209", + "name": "Reserved 0xD1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D1", + "is_reserved": true + }, + { + "id": "Reserved210", + "name": "Reserved 0xD2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D2", + "is_reserved": true + }, + { + "id": "Reserved211", + "name": "Reserved 0xD3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D3", + "is_reserved": true + }, + { + "id": "Reserved212", + "name": "Reserved 0xD4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D4", + "is_reserved": true + }, + { + "id": "Reserved213", + "name": "Reserved 0xD5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D5", + "is_reserved": true + }, + { + "id": "Reserved214", + "name": "Reserved 0xD6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D6", + "is_reserved": true + }, + { + "id": "Reserved215", + "name": "Reserved 0xD7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D7", + "is_reserved": true + }, + { + "id": "Reserved216", + "name": "Reserved 0xD8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D8", + "is_reserved": true + }, + { + "id": "Reserved217", + "name": "Reserved 0xD9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00D9", + "is_reserved": true + }, + { + "id": "Reserved218", + "name": "Reserved 0xDA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DA", + "is_reserved": true + }, + { + "id": "Reserved219", + "name": "Reserved 0xDB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DB", + "is_reserved": true + }, + { + "id": "Reserved220", + "name": "Reserved 0xDC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DC", + "is_reserved": true + }, + { + "id": "Reserved221", + "name": "Reserved 0xDD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DD", + "is_reserved": true + }, + { + "id": "Reserved222", + "name": "Reserved 0xDE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DE", + "is_reserved": true + }, + { + "id": "Reserved223", + "name": "Reserved 0xDF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00DF", + "is_reserved": true + }, + { + "id": "Reserved224", + "name": "Reserved 0xE0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E0", + "is_reserved": true + }, + { + "id": "Reserved225", + "name": "Reserved 0xE1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E1", + "is_reserved": true + }, + { + "id": "Reserved226", + "name": "Reserved 0xE2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E2", + "is_reserved": true + }, + { + "id": "Reserved227", + "name": "Reserved 0xE3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E3", + "is_reserved": true + }, + { + "id": "Reserved228", + "name": "Reserved 0xE4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E4", + "is_reserved": true + }, + { + "id": "Reserved229", + "name": "Reserved 0xE5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E5", + "is_reserved": true + }, + { + "id": "Reserved230", + "name": "Reserved 0xE6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E6", + "is_reserved": true + }, + { + "id": "Reserved231", + "name": "Reserved 0xE7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E7", + "is_reserved": true + }, + { + "id": "Reserved232", + "name": "Reserved 0xE8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E8", + "is_reserved": true + }, + { + "id": "Reserved233", + "name": "Reserved 0xE9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00E9", + "is_reserved": true + }, + { + "id": "Reserved234", + "name": "Reserved 0xEA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EA", + "is_reserved": true + }, + { + "id": "Reserved235", + "name": "Reserved 0xEB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EB", + "is_reserved": true + }, + { + "id": "Reserved236", + "name": "Reserved 0xEC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EC", + "is_reserved": true + }, + { + "id": "Reserved237", + "name": "Reserved 0xED", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00ED", + "is_reserved": true + }, + { + "id": "Reserved238", + "name": "Reserved 0xEE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EE", + "is_reserved": true + }, + { + "id": "Reserved239", + "name": "Reserved 0xEF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00EF", + "is_reserved": true + }, + { + "id": "Reserved240", + "name": "Reserved 0xF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F0", + "is_reserved": true + }, + { + "id": "Reserved241", + "name": "Reserved 0xF1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F1", + "is_reserved": true + }, + { + "id": "Reserved242", + "name": "Reserved 0xF2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F2", + "is_reserved": true + }, + { + "id": "Reserved243", + "name": "Reserved 0xF3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F3", + "is_reserved": true + }, + { + "id": "Reserved244", + "name": "Reserved 0xF4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F4", + "is_reserved": true + }, + { + "id": "Reserved245", + "name": "Reserved 0xF5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F5", + "is_reserved": true + }, + { + "id": "Reserved246", + "name": "Reserved 0xF6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F6", + "is_reserved": true + }, + { + "id": "Reserved247", + "name": "Reserved 0xF7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F7", + "is_reserved": true + }, + { + "id": "Reserved248", + "name": "Reserved 0xF8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F8", + "is_reserved": true + }, + { + "id": "Reserved249", + "name": "Reserved 0xF9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00F9", + "is_reserved": true + }, + { + "id": "Reserved250", + "name": "Reserved 0xFA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FA", + "is_reserved": true + }, + { + "id": "Reserved251", + "name": "Reserved 0xFB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FB", + "is_reserved": true + }, + { + "id": "Reserved252", + "name": "Reserved 0xFC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FC", + "is_reserved": true + }, + { + "id": "Reserved253", + "name": "Reserved 0xFD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FD", + "is_reserved": true + }, + { + "id": "Reserved254", + "name": "Reserved 0xFE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FE", + "is_reserved": true + }, + { + "id": "Reserved255", + "name": "Reserved 0xFF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x00FF", + "is_reserved": true + }, + { + "id": "Reserved256", + "name": "Reserved 0x100", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0100", + "is_reserved": true + }, + { + "id": "Reserved257", + "name": "Reserved 0x101", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0101", + "is_reserved": true + }, + { + "id": "Reserved258", + "name": "Reserved 0x102", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0102", + "is_reserved": true + }, + { + "id": "Reserved259", + "name": "Reserved 0x103", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0103", + "is_reserved": true + }, + { + "id": "Reserved260", + "name": "Reserved 0x104", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0104", + "is_reserved": true + }, + { + "id": "Reserved261", + "name": "Reserved 0x105", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0105", + "is_reserved": true + }, + { + "id": "Reserved262", + "name": "Reserved 0x106", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0106", + "is_reserved": true + }, + { + "id": "Reserved263", + "name": "Reserved 0x107", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0107", + "is_reserved": true + }, + { + "id": "Reserved264", + "name": "Reserved 0x108", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0108", + "is_reserved": true + }, + { + "id": "Reserved265", + "name": "Reserved 0x109", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0109", + "is_reserved": true + }, + { + "id": "Reserved266", + "name": "Reserved 0x10A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010A", + "is_reserved": true + }, + { + "id": "Reserved267", + "name": "Reserved 0x10B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010B", + "is_reserved": true + }, + { + "id": "Reserved268", + "name": "Reserved 0x10C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010C", + "is_reserved": true + }, + { + "id": "Reserved269", + "name": "Reserved 0x10D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010D", + "is_reserved": true + }, + { + "id": "Reserved270", + "name": "Reserved 0x10E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010E", + "is_reserved": true + }, + { + "id": "Reserved271", + "name": "Reserved 0x10F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x010F", + "is_reserved": true + }, + { + "id": "Reserved272", + "name": "Reserved 0x110", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0110", + "is_reserved": true + }, + { + "id": "Reserved273", + "name": "Reserved 0x111", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0111", + "is_reserved": true + }, + { + "id": "Reserved274", + "name": "Reserved 0x112", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0112", + "is_reserved": true + }, + { + "id": "Reserved275", + "name": "Reserved 0x113", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0113", + "is_reserved": true + }, + { + "id": "Reserved276", + "name": "Reserved 0x114", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0114", + "is_reserved": true + }, + { + "id": "Reserved277", + "name": "Reserved 0x115", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0115", + "is_reserved": true + }, + { + "id": "Reserved278", + "name": "Reserved 0x116", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0116", + "is_reserved": true + }, + { + "id": "Reserved279", + "name": "Reserved 0x117", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0117", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "V2X_SHE_SECRET_KEY", + "description": "V2X SHE secret key" + }, + "registers": [ + { + "id": "fuse280", + "name": "V2X_SHE_SECRET_KEY0", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x0118" + }, + { + "id": "fuse281", + "name": "V2X_SHE_SECRET_KEY1", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x0119" + }, + { + "id": "fuse282", + "name": "V2X_SHE_SECRET_KEY2", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x011A" + }, + { + "id": "fuse283", + "name": "V2X_SHE_SECRET_KEY3", + "description": "V2X SHE secret key - used to export or import material to she, using key_update protocol", + "index_int": "0x011B" + } + ] + }, + { + "group": { + "name": "V2X_SHE_PRNG_KEY", + "description": "V2X SHE PRNG value" + }, + "registers": [ + { + "id": "fuse284", + "name": "V2X_SHE_PRNG_KEY0", + "description": "V2X SHE PRNG value", + "index_int": "0x011C" + }, + { + "id": "fuse285", + "name": "V2X_SHE_PRNG_KEY1", + "description": "V2X SHE PRNG value", + "index_int": "0x011D" + }, + { + "id": "fuse286", + "name": "V2X_SHE_PRNG_KEY2", + "description": "V2X SHE PRNG value", + "index_int": "0x011E" + }, + { + "id": "fuse287", + "name": "V2X_SHE_PRNG_KEY3", + "description": "V2X SHE PRNG value", + "index_int": "0x011F" + } + ] + }, + { + "group": { + "name": "Reserved 0x120-0x138", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved288", + "name": "Reserved 0x120", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0120", + "is_reserved": true + }, + { + "id": "Reserved289", + "name": "Reserved 0x121", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0121", + "is_reserved": true + }, + { + "id": "Reserved290", + "name": "Reserved 0x122", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0122", + "is_reserved": true + }, + { + "id": "Reserved291", + "name": "Reserved 0x123", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0123", + "is_reserved": true + }, + { + "id": "Reserved292", + "name": "Reserved 0x124", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0124", + "is_reserved": true + }, + { + "id": "Reserved293", + "name": "Reserved 0x125", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0125", + "is_reserved": true + }, + { + "id": "Reserved294", + "name": "Reserved 0x126", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0126", + "is_reserved": true + }, + { + "id": "Reserved295", + "name": "Reserved 0x127", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0127", + "is_reserved": true + }, + { + "id": "Reserved296", + "name": "Reserved 0x128", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0128", + "is_reserved": true + }, + { + "id": "Reserved297", + "name": "Reserved 0x129", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0129", + "is_reserved": true + }, + { + "id": "Reserved298", + "name": "Reserved 0x12A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012A", + "is_reserved": true + }, + { + "id": "Reserved299", + "name": "Reserved 0x12B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012B", + "is_reserved": true + }, + { + "id": "Reserved300", + "name": "Reserved 0x12C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012C", + "is_reserved": true + }, + { + "id": "Reserved301", + "name": "Reserved 0x12D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012D", + "is_reserved": true + }, + { + "id": "Reserved302", + "name": "Reserved 0x12E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012E", + "is_reserved": true + }, + { + "id": "Reserved303", + "name": "Reserved 0x12F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x012F", + "is_reserved": true + }, + { + "id": "Reserved304", + "name": "Reserved 0x130", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0130", + "is_reserved": true + }, + { + "id": "Reserved305", + "name": "Reserved 0x131", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0131", + "is_reserved": true + }, + { + "id": "Reserved306", + "name": "Reserved 0x132", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0132", + "is_reserved": true + }, + { + "id": "Reserved307", + "name": "Reserved 0x133", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0133", + "is_reserved": true + }, + { + "id": "Reserved308", + "name": "Reserved 0x134", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0134", + "is_reserved": true + }, + { + "id": "Reserved309", + "name": "Reserved 0x135", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0135", + "is_reserved": true + }, + { + "id": "Reserved310", + "name": "Reserved 0x136", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0136", + "is_reserved": true + }, + { + "id": "Reserved311", + "name": "Reserved 0x137", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0137", + "is_reserved": true + }, + { + "id": "Reserved312", + "name": "Reserved 0x138", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0138", + "is_reserved": true, + "bitfields": [ + { + "width": 12 + }, + { + "width": 20 + } + ] + } + ] + }, + { + "group": { + "name": "GPR2_CFG", + "description": "General purpose fuse 2" + }, + "registers": [ + { + "id": "fuse313", + "name": "GPR2_CFG0", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure EdgeLock Enclave API calls.", + "index_int": "0x0139", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse314", + "name": "GPR2_CFG1", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure EdgeLock Enclave API calls.", + "index_int": "0x013A" + }, + { + "id": "fuse315", + "name": "GPR2_CFG2", + "description": "Secure General Purpose Fuse for customer use, programmable in OEM OPEN lifecycle. Private fuse value available through secure EdgeLock Enclave API calls.", + "index_int": "0x013B" + } + ] + }, + { + "group": { + "name": "Reserved 0x13C-0x141", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved316", + "name": "Reserved 0x13C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013C", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved317", + "name": "Reserved 0x13D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013D", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved318", + "name": "Reserved 0x13E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013E", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 16 + } + ] + }, + { + "id": "Reserved319", + "name": "Reserved 0x13F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x013F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 1 + }, + { + "width": 15 + } + ] + }, + { + "id": "Reserved320", + "name": "Reserved 0x140", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0140", + "is_reserved": true + }, + { + "id": "Reserved321", + "name": "Reserved 0x141", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0141", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "COM_DEVICE_ID_CFG", + "description": "Device communication config" + }, + "registers": [ + { + "id": "fuse322", + "name": "COM_DEVICE_ID_CFG0", + "description": "COM_DEVICE_ID_CFG0", + "index_int": "0x0142", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse322-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse322-bits-16-31", + "name": "USB1_PID", + "description": "USB1 Product ID" + } + ] + }, + { + "id": "fuse323", + "name": "COM_DEVICE_ID_CFG1", + "description": "COM_DEVICE_ID_CFG1", + "index_int": "0x0143", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse323-bits-0-15", + "name": "USB2_PID", + "description": "USB2 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved324", + "name": "Reserved 0x144", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0144", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse325", + "name": "COM_DEVICE_ID_CFG3", + "description": "COM_DEVICE_ID_CFG3", + "index_int": "0x0145", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse325-bits-0-7", + "name": "MAC_ADDR_47_40", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits-8-15", + "name": "MAC_ADDR_39_32", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits-16-23", + "name": "MAC_ADDR_31_24", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse325-bits-24-31", + "name": "MAC_ADDR_23_16", + "description": "MAC Address. Reserved for customer SW" + } + ] + }, + { + "id": "fuse326", + "name": "COM_DEVICE_ID_CFG4", + "description": "COM_DEVICE_ID_CFG4", + "index_int": "0x0146", + "lock": { + "register_id": "fuse10", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse326-bits-0-7", + "name": "MAC_ADDR_15_8", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8, + "id": "fuse326-bits-8-15", + "name": "MAC_ADDR_7_0", + "description": "MAC Address. Reserved for customer SW" + }, + { + "width": 8 + }, + { + "width": 8, + "id": "fuse326-bits-24-31", + "name": "NUM_OF_MACS", + "description": "Max. Number of MACs supported. " + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x147-0x177", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved327", + "name": "Reserved 0x147", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0147", + "is_reserved": true, + "bitfields": [ + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 2 + } + ] + }, + { + "id": "Reserved328", + "name": "Reserved 0x148", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0148", + "is_reserved": true + }, + { + "id": "Reserved329", + "name": "Reserved 0x149", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0149", + "is_reserved": true + }, + { + "id": "Reserved330", + "name": "Reserved 0x14A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014A", + "is_reserved": true + }, + { + "id": "Reserved331", + "name": "Reserved 0x14B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014B", + "is_reserved": true + }, + { + "id": "Reserved332", + "name": "Reserved 0x14C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014C", + "is_reserved": true + }, + { + "id": "Reserved333", + "name": "Reserved 0x14D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014D", + "is_reserved": true + }, + { + "id": "Reserved334", + "name": "Reserved 0x14E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014E", + "is_reserved": true + }, + { + "id": "Reserved335", + "name": "Reserved 0x14F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x014F", + "is_reserved": true + }, + { + "id": "Reserved336", + "name": "Reserved 0x150", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0150", + "is_reserved": true + }, + { + "id": "Reserved337", + "name": "Reserved 0x151", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0151", + "is_reserved": true + }, + { + "id": "Reserved338", + "name": "Reserved 0x152", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0152", + "is_reserved": true + }, + { + "id": "Reserved339", + "name": "Reserved 0x153", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0153", + "is_reserved": true + }, + { + "id": "Reserved340", + "name": "Reserved 0x154", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0154", + "is_reserved": true + }, + { + "id": "Reserved341", + "name": "Reserved 0x155", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0155", + "is_reserved": true + }, + { + "id": "Reserved342", + "name": "Reserved 0x156", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0156", + "is_reserved": true + }, + { + "id": "Reserved343", + "name": "Reserved 0x157", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0157", + "is_reserved": true + }, + { + "id": "Reserved344", + "name": "Reserved 0x158", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0158", + "is_reserved": true + }, + { + "id": "Reserved345", + "name": "Reserved 0x159", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0159", + "is_reserved": true + }, + { + "id": "Reserved346", + "name": "Reserved 0x15A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015A", + "is_reserved": true + }, + { + "id": "Reserved347", + "name": "Reserved 0x15B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015B", + "is_reserved": true + }, + { + "id": "Reserved348", + "name": "Reserved 0x15C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015C", + "is_reserved": true + }, + { + "id": "Reserved349", + "name": "Reserved 0x15D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015D", + "is_reserved": true + }, + { + "id": "Reserved350", + "name": "Reserved 0x15E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015E", + "is_reserved": true + }, + { + "id": "Reserved351", + "name": "Reserved 0x15F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x015F", + "is_reserved": true + }, + { + "id": "Reserved352", + "name": "Reserved 0x160", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0160", + "is_reserved": true + }, + { + "id": "Reserved353", + "name": "Reserved 0x161", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0161", + "is_reserved": true + }, + { + "id": "Reserved354", + "name": "Reserved 0x162", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0162", + "is_reserved": true + }, + { + "id": "Reserved355", + "name": "Reserved 0x163", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0163", + "is_reserved": true + }, + { + "id": "Reserved356", + "name": "Reserved 0x164", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0164", + "is_reserved": true + }, + { + "id": "Reserved357", + "name": "Reserved 0x165", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0165", + "is_reserved": true + }, + { + "id": "Reserved358", + "name": "Reserved 0x166", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0166", + "is_reserved": true + }, + { + "id": "Reserved359", + "name": "Reserved 0x167", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0167", + "is_reserved": true + }, + { + "id": "Reserved360", + "name": "Reserved 0x168", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0168", + "is_reserved": true + }, + { + "id": "Reserved361", + "name": "Reserved 0x169", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0169", + "is_reserved": true + }, + { + "id": "Reserved362", + "name": "Reserved 0x16A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016A", + "is_reserved": true + }, + { + "id": "Reserved363", + "name": "Reserved 0x16B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016B", + "is_reserved": true + }, + { + "id": "Reserved364", + "name": "Reserved 0x16C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016C", + "is_reserved": true + }, + { + "id": "Reserved365", + "name": "Reserved 0x16D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016D", + "is_reserved": true + }, + { + "id": "Reserved366", + "name": "Reserved 0x16E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016E", + "is_reserved": true + }, + { + "id": "Reserved367", + "name": "Reserved 0x16F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x016F", + "is_reserved": true + }, + { + "id": "Reserved368", + "name": "Reserved 0x170", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0170", + "is_reserved": true + }, + { + "id": "Reserved369", + "name": "Reserved 0x171", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0171", + "is_reserved": true + }, + { + "id": "Reserved370", + "name": "Reserved 0x172", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0172", + "is_reserved": true + }, + { + "id": "Reserved371", + "name": "Reserved 0x173", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0173", + "is_reserved": true + }, + { + "id": "Reserved372", + "name": "Reserved 0x174", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0174", + "is_reserved": true + }, + { + "id": "Reserved373", + "name": "Reserved 0x175", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0175", + "is_reserved": true + }, + { + "id": "Reserved374", + "name": "Reserved 0x176", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0176", + "is_reserved": true + }, + { + "id": "Reserved375", + "name": "Reserved 0x177", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0177", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "GPR4_CFG", + "description": "General purpose fuse 4" + }, + "registers": [ + { + "id": "fuse376", + "name": "GPR4_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0178" + }, + { + "id": "fuse377", + "name": "GPR4_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0179" + }, + { + "id": "fuse378", + "name": "GPR4_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017A" + }, + { + "id": "fuse379", + "name": "GPR4_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017B" + }, + { + "id": "fuse380", + "name": "GPR4_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017C" + }, + { + "id": "fuse381", + "name": "GPR4_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017D", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse382", + "name": "GPR4_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017E" + }, + { + "id": "fuse383", + "name": "GPR4_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x017F", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse384", + "name": "GPR4_CFG8", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0180" + }, + { + "id": "fuse385", + "name": "GPR4_CFG9", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0181" + }, + { + "id": "fuse386", + "name": "GPR4_CFG10", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0182" + }, + { + "id": "fuse387", + "name": "GPR4_CFG11", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0183" + }, + { + "id": "fuse388", + "name": "GPR4_CFG12", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0184", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse389", + "name": "GPR4_CFG13", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0185" + }, + { + "id": "fuse390", + "name": "GPR4_CFG14", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0186" + }, + { + "id": "fuse391", + "name": "GPR4_CFG15", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0187" + } + ] + }, + { + "group": { + "name": "GPR5_CFG", + "description": "General purpose fuse 5" + }, + "registers": [ + { + "id": "fuse392", + "name": "GPR5_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0188" + }, + { + "id": "fuse393", + "name": "GPR5_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0189" + }, + { + "id": "fuse394", + "name": "GPR5_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018A" + }, + { + "id": "fuse395", + "name": "GPR5_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018B" + }, + { + "id": "fuse396", + "name": "GPR5_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018C" + }, + { + "id": "fuse397", + "name": "GPR5_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018D" + }, + { + "id": "fuse398", + "name": "GPR5_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018E" + }, + { + "id": "fuse399", + "name": "GPR5_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x018F" + }, + { + "id": "fuse400", + "name": "GPR5_CFG8", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0190" + }, + { + "id": "fuse401", + "name": "GPR5_CFG9", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0191" + }, + { + "id": "fuse402", + "name": "GPR5_CFG10", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0192" + }, + { + "id": "fuse403", + "name": "GPR5_CFG11", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0193" + }, + { + "id": "fuse404", + "name": "GPR5_CFG12", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0194" + }, + { + "id": "fuse405", + "name": "GPR5_CFG13", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0195" + }, + { + "id": "fuse406", + "name": "GPR5_CFG14", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0196" + }, + { + "id": "fuse407", + "name": "GPR5_CFG15", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0197" + } + ] + }, + { + "group": { + "name": "GPR6_CFG", + "description": "General purpose fuse 6" + }, + "registers": [ + { + "id": "fuse408", + "name": "GPR6_CFG0", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0198", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse409", + "name": "GPR6_CFG1", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x0199", + "reg_width": 16 + }, + { + "id": "fuse410", + "name": "GPR6_CFG2", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019A", + "reg_width": 16 + }, + { + "id": "fuse411", + "name": "GPR6_CFG3", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019B", + "reg_width": 16 + }, + { + "id": "fuse412", + "name": "GPR6_CFG4", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019C", + "reg_width": 16 + }, + { + "id": "fuse413", + "name": "GPR6_CFG5", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019D", + "reg_width": 16 + }, + { + "id": "fuse414", + "name": "GPR6_CFG6", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019E", + "reg_width": 16 + }, + { + "id": "fuse415", + "name": "GPR6_CFG7", + "description": "General Purpose fuse for customer use. Can be programmed in OEM OPEN or OEM closed.", + "index_int": "0x019F", + "lock": { + "register_id": "fuse11", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Reserved 0x1A0-0x1BF", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved416", + "name": "Reserved 0x1A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A0", + "is_reserved": true + }, + { + "id": "Reserved417", + "name": "Reserved 0x1A1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A1", + "is_reserved": true + }, + { + "id": "Reserved418", + "name": "Reserved 0x1A2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A2", + "is_reserved": true + }, + { + "id": "Reserved419", + "name": "Reserved 0x1A3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A3", + "is_reserved": true + }, + { + "id": "Reserved420", + "name": "Reserved 0x1A4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A4", + "is_reserved": true + }, + { + "id": "Reserved421", + "name": "Reserved 0x1A5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A5", + "is_reserved": true + }, + { + "id": "Reserved422", + "name": "Reserved 0x1A6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A6", + "is_reserved": true + }, + { + "id": "Reserved423", + "name": "Reserved 0x1A7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A7", + "is_reserved": true + }, + { + "id": "Reserved424", + "name": "Reserved 0x1A8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A8", + "is_reserved": true + }, + { + "id": "Reserved425", + "name": "Reserved 0x1A9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01A9", + "is_reserved": true + }, + { + "id": "Reserved426", + "name": "Reserved 0x1AA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AA", + "is_reserved": true + }, + { + "id": "Reserved427", + "name": "Reserved 0x1AB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AB", + "is_reserved": true + }, + { + "id": "Reserved428", + "name": "Reserved 0x1AC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AC", + "is_reserved": true + }, + { + "id": "Reserved429", + "name": "Reserved 0x1AD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AD", + "is_reserved": true + }, + { + "id": "Reserved430", + "name": "Reserved 0x1AE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AE", + "is_reserved": true + }, + { + "id": "Reserved431", + "name": "Reserved 0x1AF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01AF", + "is_reserved": true + }, + { + "id": "Reserved432", + "name": "Reserved 0x1B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B0", + "is_reserved": true + }, + { + "id": "Reserved433", + "name": "Reserved 0x1B1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B1", + "is_reserved": true + }, + { + "id": "Reserved434", + "name": "Reserved 0x1B2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B2", + "is_reserved": true + }, + { + "id": "Reserved435", + "name": "Reserved 0x1B3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B3", + "is_reserved": true + }, + { + "id": "Reserved436", + "name": "Reserved 0x1B4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B4", + "is_reserved": true + }, + { + "id": "Reserved437", + "name": "Reserved 0x1B5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B5", + "is_reserved": true + }, + { + "id": "Reserved438", + "name": "Reserved 0x1B6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B6", + "is_reserved": true + }, + { + "id": "Reserved439", + "name": "Reserved 0x1B7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B7", + "is_reserved": true + }, + { + "id": "Reserved440", + "name": "Reserved 0x1B8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B8", + "is_reserved": true + }, + { + "id": "Reserved441", + "name": "Reserved 0x1B9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01B9", + "is_reserved": true + }, + { + "id": "Reserved442", + "name": "Reserved 0x1BA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BA", + "is_reserved": true + }, + { + "id": "Reserved443", + "name": "Reserved 0x1BB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BB", + "is_reserved": true + }, + { + "id": "Reserved444", + "name": "Reserved 0x1BC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BC", + "is_reserved": true + }, + { + "id": "Reserved445", + "name": "Reserved 0x1BD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BD", + "is_reserved": true + }, + { + "id": "Reserved446", + "name": "Reserved 0x1BE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BE", + "is_reserved": true + }, + { + "id": "Reserved447", + "name": "Reserved 0x1BF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01BF", + "is_reserved": true + } + ] + }, + { + "group": { + "name": "OEM_PQC_SRKH", + "description": "OEM PQC SRK Hash" + }, + "registers": [ + { + "id": "fuse448", + "name": "OEM_PQC_SRKH0", + "description": "OEM_PQC_SRKH0", + "index_int": "0x01C0", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse449", + "name": "OEM_PQC_SRKH1", + "description": "OEM_PQC_SRKH1", + "index_int": "0x01C1", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse450", + "name": "OEM_PQC_SRKH2", + "description": "OEM_PQC_SRKH2", + "index_int": "0x01C2", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse451", + "name": "OEM_PQC_SRKH3", + "description": "OEM_PQC_SRKH3", + "index_int": "0x01C3", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse452", + "name": "OEM_PQC_SRKH4", + "description": "OEM_PQC_SRKH4", + "index_int": "0x01C4", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse453", + "name": "OEM_PQC_SRKH5", + "description": "OEM_PQC_SRKH5", + "index_int": "0x01C5", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse454", + "name": "OEM_PQC_SRKH6", + "description": "OEM_PQC_SRKH6", + "index_int": "0x01C6", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse455", + "name": "OEM_PQC_SRKH7", + "description": "OEM_PQC_SRKH7", + "index_int": "0x01C7", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse456", + "name": "OEM_PQC_SRKH8", + "description": "OEM_PQC_SRKH8", + "index_int": "0x01C8", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse457", + "name": "OEM_PQC_SRKH9", + "description": "OEM_PQC_SRKH9", + "index_int": "0x01C9", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse458", + "name": "OEM_PQC_SRKH10", + "description": "OEM_PQC_SRKH10", + "index_int": "0x01CA", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse459", + "name": "OEM_PQC_SRKH11", + "description": "OEM_PQC_SRKH11", + "index_int": "0x01CB", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse460", + "name": "OEM_PQC_SRKH12", + "description": "OEM_PQC_SRKH12", + "index_int": "0x01CC", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse461", + "name": "OEM_PQC_SRKH13", + "description": "OEM_PQC_SRKH13", + "index_int": "0x01CD", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse462", + "name": "OEM_PQC_SRKH14", + "description": "OEM_PQC_SRKH14", + "index_int": "0x01CE", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse463", + "name": "OEM_PQC_SRKH15", + "description": "OEM_PQC_SRKH15", + "index_int": "0x01CF", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "Reserved 0x1D0-0x20F", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved464", + "name": "Reserved 0x1D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D0", + "is_reserved": true + }, + { + "id": "Reserved465", + "name": "Reserved 0x1D1", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D1", + "is_reserved": true + }, + { + "id": "Reserved466", + "name": "Reserved 0x1D2", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D2", + "is_reserved": true + }, + { + "id": "Reserved467", + "name": "Reserved 0x1D3", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D3", + "is_reserved": true + }, + { + "id": "Reserved468", + "name": "Reserved 0x1D4", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D4", + "is_reserved": true + }, + { + "id": "Reserved469", + "name": "Reserved 0x1D5", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D5", + "is_reserved": true + }, + { + "id": "Reserved470", + "name": "Reserved 0x1D6", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D6", + "is_reserved": true + }, + { + "id": "Reserved471", + "name": "Reserved 0x1D7", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D7", + "is_reserved": true + }, + { + "id": "Reserved472", + "name": "Reserved 0x1D8", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D8", + "is_reserved": true + }, + { + "id": "Reserved473", + "name": "Reserved 0x1D9", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01D9", + "is_reserved": true + }, + { + "id": "Reserved474", + "name": "Reserved 0x1DA", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DA", + "is_reserved": true + }, + { + "id": "Reserved475", + "name": "Reserved 0x1DB", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DB", + "is_reserved": true + }, + { + "id": "Reserved476", + "name": "Reserved 0x1DC", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DC", + "is_reserved": true + }, + { + "id": "Reserved477", + "name": "Reserved 0x1DD", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DD", + "is_reserved": true + }, + { + "id": "Reserved478", + "name": "Reserved 0x1DE", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DE", + "is_reserved": true + }, + { + "id": "Reserved479", + "name": "Reserved 0x1DF", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x01DF", + "is_reserved": true + }, + { + "id": "Reserved480", + "name": "Reserved 0x1E0", + "description": "Reserved for future use. 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"name": "V2X_SHE_MONO_CNT3", + "description": "V2X_SHE_MONO_CNT3", + "index_int": "0x0213", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse532", + "name": "V2X_SHE_MONO_CNT4", + "description": "V2X_SHE_MONO_CNT4", + "index_int": "0x0214", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse533", + "name": "V2X_SHE_MONO_CNT5", + "description": "V2X_SHE_MONO_CNT5", + "index_int": "0x0215", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse534", + "name": "V2X_SHE_MONO_CNT6", + "description": "V2X_SHE_MONO_CNT6", + "index_int": "0x0216", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse535", + "name": "V2X_SHE_MONO_CNT7", + "description": "V2X_SHE_MONO_CNT7", + "index_int": "0x0217", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse536", + "name": "V2X_SHE_MONO_CNT8", + "description": "V2X_SHE_MONO_CNT8", + "index_int": "0x0218", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse537", + "name": "V2X_SHE_MONO_CNT9", + "description": "V2X_SHE_MONO_CNT9", + "index_int": "0x0219", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse538", + "name": "V2X_SHE_MONO_CNT10", + "description": "V2X_SHE_MONO_CNT10", + "index_int": "0x021A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse539", + "name": "V2X_SHE_MONO_CNT11", + "description": "V2X_SHE_MONO_CNT11", + "index_int": "0x021B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse540", + "name": "V2X_SHE_MONO_CNT12", + "description": "V2X_SHE_MONO_CNT12", + "index_int": "0x021C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse541", + "name": "V2X_SHE_MONO_CNT13", + "description": "V2X_SHE_MONO_CNT13", + "index_int": "0x021D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse542", + "name": "V2X_SHE_MONO_CNT14", + "description": "V2X_SHE_MONO_CNT14", + "index_int": "0x021E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse543", + "name": "V2X_SHE_MONO_CNT15", + "description": "V2X_SHE_MONO_CNT15", + "index_int": "0x021F", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse544", + "name": "V2X_SHE_MONO_CNT16", + "description": "V2X_SHE_MONO_CNT16", + "index_int": "0x0220", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse545", + "name": "V2X_SHE_MONO_CNT17", + "description": "V2X_SHE_MONO_CNT17", + "index_int": "0x0221", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse546", + "name": "V2X_SHE_MONO_CNT18", + "description": "V2X_SHE_MONO_CNT18", + "index_int": "0x0222", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse547", + "name": "V2X_SHE_MONO_CNT19", + "description": "V2X_SHE_MONO_CNT19", + "index_int": "0x0223", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse548", + "name": "V2X_SHE_MONO_CNT20", + "description": "V2X_SHE_MONO_CNT20", + "index_int": "0x0224", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse549", + "name": "V2X_SHE_MONO_CNT21", + "description": "V2X_SHE_MONO_CNT21", + "index_int": "0x0225", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse550", + "name": "V2X_SHE_MONO_CNT22", + "description": "V2X_SHE_MONO_CNT22", + "index_int": "0x0226", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse551", + "name": "V2X_SHE_MONO_CNT23", + "description": "V2X_SHE_MONO_CNT23", + "index_int": "0x0227", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse552", + "name": "V2X_SHE_MONO_CNT24", + "description": "V2X_SHE_MONO_CNT24", + "index_int": "0x0228", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse553", + "name": "V2X_SHE_MONO_CNT25", + "description": "V2X_SHE_MONO_CNT25", + "index_int": "0x0229", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse554", + "name": "V2X_SHE_MONO_CNT26", + "description": "V2X_SHE_MONO_CNT26", + "index_int": "0x022A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse555", + "name": "V2X_SHE_MONO_CNT27", + "description": "V2X_SHE_MONO_CNT27", + "index_int": "0x022B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse556", + "name": "V2X_SHE_MONO_CNT28", + "description": "V2X_SHE_MONO_CNT28", + "index_int": "0x022C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse557", + "name": "V2X_SHE_MONO_CNT29", + "description": "V2X_SHE_MONO_CNT29", + "index_int": "0x022D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse558", + "name": "V2X_SHE_MONO_CNT30", + "description": "V2X_SHE_MONO_CNT30", + "index_int": "0x022E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse559", + "name": "V2X_SHE_MONO_CNT31", + "description": "V2X_SHE_MONO_CNT31", + "index_int": "0x022F", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse560", + "name": "V2X_SHE_MONO_CNT32", + "description": "V2X_SHE_MONO_CNT32", + "index_int": "0x0230", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse561", + "name": "V2X_SHE_MONO_CNT33", + "description": "V2X_SHE_MONO_CNT33", + "index_int": "0x0231", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse562", + "name": "V2X_SHE_MONO_CNT34", + "description": "V2X_SHE_MONO_CNT34", + "index_int": "0x0232", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse563", + "name": "V2X_SHE_MONO_CNT35", + "description": "V2X_SHE_MONO_CNT35", + "index_int": "0x0233", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse564", + "name": "V2X_SHE_MONO_CNT36", + "description": "V2X_SHE_MONO_CNT36", + "index_int": "0x0234", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse565", + "name": "V2X_SHE_MONO_CNT37", + "description": "V2X_SHE_MONO_CNT37", + "index_int": "0x0235", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse566", + "name": "V2X_SHE_MONO_CNT38", + "description": "V2X_SHE_MONO_CNT38", + "index_int": "0x0236", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse567", + "name": "V2X_SHE_MONO_CNT39", + "description": "V2X_SHE_MONO_CNT39", + "index_int": "0x0237", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse568", + "name": "V2X_SHE_MONO_CNT40", + "description": "V2X_SHE_MONO_CNT40", + "index_int": "0x0238", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse569", + "name": "V2X_SHE_MONO_CNT41", + "description": "V2X_SHE_MONO_CNT41", + "index_int": "0x0239", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse570", + "name": "V2X_SHE_MONO_CNT42", + "description": "V2X_SHE_MONO_CNT42", + "index_int": "0x023A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse571", + "name": "V2X_SHE_MONO_CNT43", + "description": "V2X_SHE_MONO_CNT43", + "index_int": "0x023B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse572", + "name": "V2X_SHE_MONO_CNT44", + "description": "V2X_SHE_MONO_CNT44", + "index_int": "0x023C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse573", + "name": "V2X_SHE_MONO_CNT45", + "description": "V2X_SHE_MONO_CNT45", + "index_int": "0x023D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse574", + "name": "V2X_SHE_MONO_CNT46", + "description": "V2X_SHE_MONO_CNT46", + "index_int": "0x023E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse575", + "name": "V2X_SHE_MONO_CNT47", + "description": "V2X_SHE_MONO_CNT47", + "index_int": "0x023F", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse576", + "name": "V2X_SHE_MONO_CNT48", + "description": "V2X_SHE_MONO_CNT48", + "index_int": "0x0240", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse577", + "name": "V2X_SHE_MONO_CNT49", + "description": "V2X_SHE_MONO_CNT49", + "index_int": "0x0241", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse578", + "name": "V2X_SHE_MONO_CNT50", + "description": "V2X_SHE_MONO_CNT50", + "index_int": "0x0242", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse579", + "name": "V2X_SHE_MONO_CNT51", + "description": "V2X_SHE_MONO_CNT51", + "index_int": "0x0243", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse580", + "name": "V2X_SHE_MONO_CNT52", + "description": "V2X_SHE_MONO_CNT52", + "index_int": "0x0244", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse581", + "name": "V2X_SHE_MONO_CNT53", + "description": "V2X_SHE_MONO_CNT53", + "index_int": "0x0245", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse582", + "name": "V2X_SHE_MONO_CNT54", + "description": "V2X_SHE_MONO_CNT54", + "index_int": "0x0246", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse583", + "name": "V2X_SHE_MONO_CNT55", + "description": "V2X_SHE_MONO_CNT55", + "index_int": "0x0247", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse584", + "name": "V2X_SHE_MONO_CNT56", + "description": "V2X_SHE_MONO_CNT56", + "index_int": "0x0248", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse585", + "name": "V2X_SHE_MONO_CNT57", + "description": "V2X_SHE_MONO_CNT57", + "index_int": "0x0249", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse586", + "name": "V2X_SHE_MONO_CNT58", + "description": "V2X_SHE_MONO_CNT58", + "index_int": "0x024A", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse587", + "name": "V2X_SHE_MONO_CNT59", + "description": "V2X_SHE_MONO_CNT59", + "index_int": "0x024B", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse588", + "name": "V2X_SHE_MONO_CNT60", + "description": "V2X_SHE_MONO_CNT60", + "index_int": "0x024C", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse589", + "name": "V2X_SHE_MONO_CNT61", + "description": "V2X_SHE_MONO_CNT61", + "index_int": "0x024D", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse590", + "name": "V2X_SHE_MONO_CNT62", + "description": "V2X_SHE_MONO_CNT62", + "index_int": "0x024E", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse590-bits-0-15", + "name": "V2X_SHE_MONO_CNT", + "description": "V2X_SHE_MONO_CNT62" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x24F-0x261", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved591", + "name": "Reserved 0x24F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x024F", + "is_reserved": true, + "reg_width": 16, + "bitfields": [ + { + "width": 2 + }, + { + "width": 4 + }, + { + "width": 10 + } + ] + }, + { + "id": "Reserved592", + "name": "Reserved 0x250", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0250", + "is_reserved": true + }, + { + "id": "Reserved593", + "name": "Reserved 0x251", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0251", + "is_reserved": true + }, + { + "id": "Reserved594", + "name": "Reserved 0x252", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0252", + "is_reserved": true + }, + { + "id": "Reserved595", + "name": "Reserved 0x253", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0253", + "is_reserved": true + }, + { + "id": "Reserved596", + "name": "Reserved 0x254", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0254", + "is_reserved": true + }, + { + "id": "Reserved597", + "name": "Reserved 0x255", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0255", + "is_reserved": true + }, + { + "id": "Reserved598", + "name": "Reserved 0x256", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0256", + "is_reserved": true + }, + { + "id": "Reserved599", + "name": "Reserved 0x257", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0257", + "is_reserved": true + }, + { + "id": "Reserved600", + "name": "Reserved 0x258", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0258", + "is_reserved": true + }, + { + "id": "Reserved601", + "name": "Reserved 0x259", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0259", + "is_reserved": true + }, + { + "id": "Reserved602", + "name": "Reserved 0x25A", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025A", + "is_reserved": true + }, + { + "id": "Reserved603", + "name": "Reserved 0x25B", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025B", + "is_reserved": true + }, + { + "id": "Reserved604", + "name": "Reserved 0x25C", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025C", + "is_reserved": true + }, + { + "id": "Reserved605", + "name": "Reserved 0x25D", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025D", + "is_reserved": true + }, + { + "id": "Reserved606", + "name": "Reserved 0x25E", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025E", + "is_reserved": true + }, + { + "id": "Reserved607", + "name": "Reserved 0x25F", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x025F", + "is_reserved": true + }, + { + "id": "Reserved608", + "name": "Reserved 0x260", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0260", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved609", + "name": "Reserved 0x261", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "index_int": "0x0261", + "is_reserved": true + } + ] + } + ] +} \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/database.yaml new file mode 100644 index 0000000..dbcaa73 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/database.yaml @@ -0,0 +1,141 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt1010 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1010-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1010 + memory_map: + itcm: + start_int: "0x0" + size_int: "0x20000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x10000" + size_int: "0x10000" + warning_msg: RAM above 0x10000 is not initialized by default + dtcm: + start_int: "0x20000000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x20010000" + size_int: "0x10000" + warning_msg: RAM above 0x20010000 is not initialized by default + ocram: + start_int: "0x20200000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + flexspi: + start_int: "0x60000000" + size_int: "0x10000000" + external: true + non_xip_type: none + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x0145 + flashloader: + protocol: mboot + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + tool: blhost + no_verify: True + grouped_registers: + - uid: otfad_sw_gp2 + name: SW_GP2 + width: 128 + reversed: True + reverse_subregs_order: True + config_as_hexstring: true + description: General purpose SW key. + sub_regs: [fuse41, fuse42, fuse43, fuse44] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x0000_2000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_hab" + + # ======== HABv4 section ======== + hab: + mem_types: + flexspi_nor: + initial_load_size: 0x2000 + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 0 + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + additional_template: ["otfad_scramble"] + additional_template_text: | + When using OTFAD XIP, the core clock must operate at a higher frequency than the FlexSPI clock + otherwise, OTFAD operation may become unreliable. + + In case blank string is used, the output is not generated. If the filename contains directory, + the output folder will be ignored and the full path from filename will be used. + + fuses_1: + _name: Configuration of fuses for OTFAD1 + _no_verify: True + otfad_sw_gp2: __kek + fuse35: + fuse35-bit-8: 1 + fuse35-bit-10: __scramble_enabled + fuse35-bits-0-7: __key_scramble_align + fuse34: __key_scramble_mask + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + hab_container: 0x0 + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + hab_container: 0x1000 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + flexspi_nand: + instances: [0] + spi_nor: + instances: [0, 1] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fcb_flexspi_nor.json new file mode 100644 index 0000000..040c5ce --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fcb_flexspi_nor.json @@ -0,0 +1,25588 @@ +{ + "cpu": "MIMXRT1010", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010100" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "Reserved2_1", + "deprecated_names": ["reserve2_1"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "Reserved2_2", + "deprecated_names": ["reserve2_2"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "Reserved2_3", + "deprecated_names": ["reserve2_3"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "Reserved2_4", + "deprecated_names": ["reserve2_4"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "Reserved2_5", + "deprecated_names": ["reserve2_5"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "Reserved2_6", + "deprecated_names": ["reserve2_6"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "Reserved2_7", + "deprecated_names": ["reserve2_7"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "Reserved2_8", + "deprecated_names": ["reserve2_8"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "Reserved2_9", + "deprecated_names": ["reserve2_9"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "Reserved2_10", + "deprecated_names": ["reserve2_10"], + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fuses.json new file mode 100644 index 0000000..020d73d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1010/fuses.json @@ -0,0 +1,2350 @@ +{ + "cpu": "mimxrt1010", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-1", + "name": "SEC_CONFIG[0]", + "description": "Security Configuration Mode, and block of debugging of security HW, by JTAG" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2, + "id": "fuse4-bits-18-19", + "name": "PKGINFO[1:0]", + "description": "Burned by tester program, for indicating IC package type" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-1-3", + "name": "FLASH_TYPE", + "description": "FLASH type selection, depending on selected boot device.", + "values": [ + { + "name": "000", + "value": 0, + "description": "000-Device supports 3B read by default" + }, + { + "name": "001", + "value": 1, + "description": "001-Device supports 4B read by default" + }, + { + "name": "010", + "value": 2, + "description": "010-HyperFlash 1V8" + }, + { + "name": "011", + "value": 3, + "description": "011-HyperFlash 3V3" + }, + { + "name": "100", + "value": 4, + "description": "100-MXIC Octal DDR" + }, + { + "name": "101", + "value": 5, + "description": "101 - Micron Octal DDR" + }, + { + "name": "111", + "value": 7, + "description": "111 - QSPI device supports 3B read by default (on secondary pinmux option)" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG[1]", + "description": "Security Configuration (with SEC_CONFIG[0])", + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 432 / (Bus)144 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 508 / (Bus) 127 MHz" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 1, + "id": "fuse6-bit-12", + "name": "OTFAD_KEY_SEL0", + "description": "AES key selection for OTFAD", + "values": [ + { + "name": "0", + "value": 0, + "description": "Select [127:0] of key selected by FUSE_OTP_KEY_TO_DCP_DISABLE" + }, + { + "name": "1", + "value": 1, + "description": "Select [255:128] of key selected by FUSE_OTP_KEY_TO_DCP_DISABLE" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-13", + "name": "OTFAD_KEY_SEL1", + "description": "AES key selection for OTFAD", + "values": [ + { + "name": "OTFAD_KEY_SEL0", + "value": 0, + "description": "From Key selected by OTFAD_KEY_SEL0" + }, + { + "name": "FUSE_SW_GPR2[127:0]", + "value": 1, + "description": "From FUSE_SW_GPR2[127:0]" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller", + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + } + }, + { + "id": "fuse33", + "name": "SJC_RESP[63:32]", + "description": "Response reference value for the secure JTAG controller", + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + } + } + ] + }, + { + "group": { + "name": "OTFAD", + "description": "OTFAD encryption" + }, + "registers": [ + { + "id": "fuse34", + "name": "OTFAD_KEY_SCRAMBLE[31:0]", + "description": "Key scramble data value for key blob unwrap.", + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + } + }, + { + "id": "fuse35", + "name": "OTFAD_ENABLE", + "description": "Fuse OTFAD_ENABLE", + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse35-bits-0-7", + "name": "OTFAD_KEY_SCRAMBLE_ALIGN[7:0]", + "description": "4x 2-bit key scramble align select for key blob unwrap" + }, + { + "width": 1, + "id": "fuse35-bit-8", + "name": "OTFAD_ENABLE", + "description": "Reserved enable OTFAD description -- Move to GPR", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-9", + "name": "OTFAD_KEY_BLOB_EN", + "description": "enable key blob unwrap", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-10", + "name": "ENB_OTFAD_KEY_SCRAMBLE", + "description": "Enable KEK scramble during key blob processing", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse35-bit-11", + "name": "RESTRICT_OTFAD_IPS", + "description": "Restrict IPS access to CR, SR and CRC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse35-bit-13", + "name": "OTFAD_DISABLE_OVERRIDE", + "description": "disable otfad as if not present", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse36", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true + }, + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_SPEED", + "description": "LPSPI Speed select", + "values": [ + { + "name": "00", + "value": 0, + "description": "20 MHz (default)" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/database.yaml new file mode 100644 index 0000000..ed4583b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/database.yaml @@ -0,0 +1,127 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt1015 + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1015-crossover-mcu-with-arm-cortex-m7-core-operating-up-to-500-mhz:i.MX-RT1015 + memory_map: + itcm: + start_int: "0x0" + size_int: "0x20000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x10000" + size_int: "0x10000" + warning_msg: RAM above 0x10000 is not initialized by default + dtcm: + start_int: "0x20000000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x20010000" + size_int: "0x10000" + warning_msg: RAM above 0x20010000 is not initialized by default + ocram: + start_int: "0x20200000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + flexspi: + start_int: "0x60000000" + size_int: "0x10000000" + external: true + non_xip_type: none + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x0145 + flashloader: + protocol: mboot + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + tool: blhost + no_verify: True + grouped_registers: + - uid: otfad_sw_gp2 + name: SW_GP2 + width: 128 + reversed: True + reverse_subregs_order: True + config_as_hexstring: true + description: General purpose SW key. + sub_regs: [fuse41, fuse42, fuse43, fuse44] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x0000_2000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_hab" + + # ======== HABv4 section ======== + hab: + mem_types: + flexspi_nor: + initial_load_size: 0x2000 + flexspi_nand: + initial_load_size: 0x1000 + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== BEE section ======== + bee: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + hab_container: 0x0 + flexspi_nor: + segments: + fcb: 0x0000 + hab_container: 0x1000 + flexspi_nand: + segments: + hab_container: 0x400 + recovery_spi_hab: + segments: + hab_container: 0x400 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + flexspi_nand: + instances: [0] + spi_nor: + instances: [1, 2, 3, 4] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fcb_flexspi_nor.json new file mode 100644 index 0000000..1344741 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fcb_flexspi_nor.json @@ -0,0 +1,25568 @@ +{ + "cpu": "MIMXRT1015", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010100" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_10", + "description": " Reserved for future use", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fuses.json new file mode 100644 index 0000000..c95e7b4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1015/fuses.json @@ -0,0 +1,2568 @@ +{ + "cpu": "mimxrt1015", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2, + "id": "fuse4-bits-18-19", + "name": "PKGINFO[1:0]", + "description": "Burned by tester program, for indicating IC package type" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-1-3", + "name": "FLASH_TYPE", + "description": "FLASH type selection, depending on selected boot device.", + "values": [ + { + "name": "000", + "value": 0, + "description": "000-Device supports 3B read by default" + }, + { + "name": "001", + "value": 1, + "description": "001-Device supports 4B read by default" + }, + { + "name": "010", + "value": 2, + "description": "010-HyperFlash 1V8" + }, + { + "name": "011", + "value": 3, + "description": "011-HyperFlash 3V3" + }, + { + "name": "100", + "value": 4, + "description": "100-MXIC Octal DDR" + }, + { + "name": "101", + "value": 5, + "description": "101 - Micron Octal DDR" + }, + { + "name": "111", + "value": 7, + "description": "111 - QSPI device supports 3B read by default (on secondary pinmux option)" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG1", + "description": "Security Configuration", + "deprecated_names": [ + "SEC_CONFIG[1]" + ], + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 396 / (Bus)132 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 528 / (Bus) 132 MHz" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "BEE_KEY0_SEL", + "description": "AES key selection for BEE_KEY0", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "BEE_KEY1_SEL", + "description": "AES key selection for BEE_KEY1", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-24", + "name": "DLL_ENABLE", + "description": "Controls the enable/disable of the DLL for SD/eMMC boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-25", + "name": "NAND_ECC_DISABLE", + "description": "Indicate whether to enabled ECC (done by SW/Device HW) for Raw Nand device", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "NAND ECC is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "NAND ECC is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-29", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "Select Power Stable Cycle", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-3", + "name": "Disable SDMMC Manufacture mode", + "description": "The fuse bit is used to disable ROM feature “SD/MMC Manufacturing Mode”.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-5", + "name": "SD2 VOLTAGE SELECTION", + "description": "Fuse bit to change voltage selection for SD2 pads. When set ROM will select 1.8V for SD3 pads otherwise 3.3V", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-6", + "name": "SD1_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD1", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-7", + "name": "DLL Override", + "description": "Select the DLL mode for SD/eMMC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-8", + "name": "USDHC IOMUX SRE Enable", + "description": "The fuse bit is used for ROM to enable SRE bit for SD pads", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-9", + "name": "USDHC_IOMUX_SION_BIT_ENABLE", + "description": "The fuse bit is used for ROM to enable SION bit for MUX control register.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1, + "id": "fuse7-bit-11", + "name": "ENABLE_EMMC_22K_PULLUP", + "description": "The fuse bit is used for ROM to enable 22K pullup for SD pads.", + "values": [ + { + "name": "47K pullup", + "value": 0, + "description": "47K pullup" + }, + { + "name": "22K pullup", + "value": 1, + "description": "22K pullup" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "USDHC_PAD_PULL_DOWN", + "description": "The fuse bit is used for ROM to enable pull down bit for SD pads. ", + "values": [ + { + "name": "no action", + "value": 0, + "description": "no action" + }, + { + "name": "pull down", + "value": 1, + "description": "pull down" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "Override HYS bit for SD-MMC pads", + "description": "Once this fuse be blown, the [HYS] bit of IOMUXC_SW_PAD_CTL_PAD_SDx_CLK(x is the SD port which the ROM boot from), IOMUXC_SW_PAD_CTL_PAD_SDx_CMD, IOMUXC_SW_PAD_CTL_PAD_SDx_DAT0-n(n will be 0, 3, or 7, depends on the bus width selected) will be set. ", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "eMMC 4.4 - RESET TO PRE-IDLE STATE", + "description": "Once this fuse be blown, the CMD0 with argument 0xf0f0f0f0 will be sent to put the eMMC card into pre-IDLE state so that eMMC card’s fast boot can work properly.\nThis is useful for the warm boot, such as boot due to the WDOG reset.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-15", + "name": "SD2_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD2", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-20", + "name": "BT_LPB_POLARITY", + "description": "Define GPIO3 polarity, for determining LPB boot mode.", + "values": [ + { + "name": "Active High", + "value": 0, + "description": "Active High" + }, + { + "name": "Active Low", + "value": 1, + "description": "Active Low" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse7-bits-24-30", + "name": "MMC_DLL_DLY[6:0]", + "description": "eMMC 4.4 delay line default value (set by boot rom), used in conjunction with \"DLL Override\" = 1 (BOOT_CFG3[3])" + }, + { + "width": 1, + "id": "fuse7-bit-31", + "name": "Override NAND Pad Settings", + "description": "Override pad settings for NAND boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP0", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[31:0]" + ], + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller" + } + ] + }, + { + "id": "fuse33", + "name": "SJC_RESP1", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[55:32]" + ], + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 24, + "id": "fuse33-bits-0-23", + "name": "SJC_RESP[55:32]", + "description": "Response reference value for the secure JTAG controller" + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse34", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse35", + "name": "MAC1_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[15:0]" + ], + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse35-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse36", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_SPEED", + "description": "LPSPI Speed select", + "values": [ + { + "name": "00", + "value": 0, + "description": "20 MHz (default)" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-30-31", + "name": "SD_CALIBRATION_STEP", + "description": "SD Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + } + ] + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1020/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1020/database.yaml new file mode 100644 index 0000000..ed8b2c0 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1020/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1024 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/database.yaml new file mode 100644 index 0000000..64a4a93 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/database.yaml @@ -0,0 +1,161 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt102x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1020-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1020 + memory_map: + itcm: + start_int: 0x0 + size_int: 0x40000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x10000 + size_int: 0x30000 + warning_msg: RAM above 0x10000 is not initialized by default + dtcm: + start_int: 0x20000000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20010000 + size_int: 0x30000 + warning_msg: RAM above 0x20010000 is not initialized by default + ocram: + start_int: 0x20200000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20220000 + size_int: 0x20000 + warning_msg: RAM above 0x20220000 is not initialized by default + flexspi: + start_int: 0x60000000 + size_int: 0x10000000 + external: true + non_xip_type: none + sdram: + start_int: 0x80000000 + size_int: 0x60000000 + external: true + non_xip_type: ext_ram_semc + dcd_file: evkmimxrt1024_SDRAM_dcd.bin + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x0130 + flashloader: + protocol: mboot + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x0000_2000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: srk_table_hab + + # ======== HABv4 section ======== + hab: + mem_types: + serial_downloader: + initial_load_size: 0x400 + flexspi_nor: + initial_load_size: 0x2000 + flexspi_nand: + initial_load_size: 0x1000 + semc_nand: + initial_load_size: 0x1000 + sd: + initial_load_size: 0x1000 + mmc: + initial_load_size: 0x1000 + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== BEE section ======== + bee: {} + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + hab_container: 0x0 + flexspi_nor: + segments: + fcb: 0x0000 + bee_header_0: 0x0400 + bee_header_1: 0x0800 + hab_container: 0x1000 + flexspi_nand: + segments: + hab_container: 0x400 + semc_nor: + segments: + hab_container: 0x1000 + semc_nand: + segments: + hab_container: 0x400 + sd: + segments: + hab_container: 0x400 + mmc: + segments: + hab_container: 0x400 + emmc: + segments: + hab_container: 0x400 + recovery_spi_hab: + segments: + hab_container: 0x400 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + flexspi_nand: + instances: [0] + semc_nor: + instances: [0] # probably not supported in latest version of Flashloader + semc_nand: + instances: [0] # probably not supported in latest version of Flashloader + sd: + instances: [1, 2] + mmc: + instances: [1, 2] + emmc: + instances: [1, 2] + spi_nor: + instances: [1, 2, 3, 4] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fcb_flexspi_nor.json new file mode 100644 index 0000000..9f7594a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fcb_flexspi_nor.json @@ -0,0 +1,25568 @@ +{ + "cpu": "MIMXRT1024", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_10", + "description": " Reserved for future use", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fuses.json new file mode 100644 index 0000000..6772c25 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1024/fuses.json @@ -0,0 +1,2568 @@ +{ + "cpu": "mimxrt1024", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2, + "id": "fuse4-bits-18-19", + "name": "PKGINFO[1:0]", + "description": "Burned by tester program, for indicating IC package type" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-1-3", + "name": "FLASH_TYPE", + "description": "FLASH type selection, depending on selected boot device.", + "values": [ + { + "name": "000", + "value": 0, + "description": "000-Device supports 3B read by default" + }, + { + "name": "001", + "value": 1, + "description": "001-Device supports 4B read by default" + }, + { + "name": "010", + "value": 2, + "description": "010-HyperFlash 1V8" + }, + { + "name": "011", + "value": 3, + "description": "011-HyperFlash 3V3" + }, + { + "name": "100", + "value": 4, + "description": "100-MXIC Octal DDR" + }, + { + "name": "101", + "value": 5, + "description": "101 - Micron Octal DDR" + }, + { + "name": "111", + "value": 7, + "description": "111 - QSPI device supports 3B read by default (on secondary pinmux option)" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG1", + "description": "Security Configuration (with SEC_CONFIG[0])", + "deprecated_names": [ + "SEC_CONFIG[1]" + ], + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 396 / (Bus)132 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 528 / (Bus) 132 MHz" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "BEE_KEY0_SEL", + "description": "AES key selection for BEE_KEY0", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "BEE_KEY1_SEL", + "description": "AES key selection for BEE_KEY1", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-24", + "name": "DLL_ENABLE", + "description": "Controls the enable/disable of the DLL for SD/eMMC boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-25", + "name": "NAND_ECC_DISABLE", + "description": "Indicate whether to enabled ECC (done by SW/Device HW) for Raw Nand device", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "NAND ECC is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "NAND ECC is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-29", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "Select Power Stable Cycle", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-3", + "name": "Disable SDMMC Manufacture mode", + "description": "The fuse bit is used to disable ROM feature “SD/MMC Manufacturing Mode”.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-5", + "name": "SD2 VOLTAGE SELECTION", + "description": "Fuse bit to change voltage selection for SD2 pads. When set ROM will select 1.8V for SD3 pads otherwise 3.3V", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-6", + "name": "SD1_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD1", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-7", + "name": "DLL Override", + "description": "Select the DLL mode for SD/eMMC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-8", + "name": "USDHC IOMUX SRE Enable", + "description": "The fuse bit is used for ROM to enable SRE bit for SD pads", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-9", + "name": "USDHC_IOMUX_SION_BIT_ENABLE", + "description": "The fuse bit is used for ROM to enable SION bit for MUX control register.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1, + "id": "fuse7-bit-11", + "name": "ENABLE_EMMC_22K_PULLUP", + "description": "The fuse bit is used for ROM to enable 22K pullup for SD pads.", + "values": [ + { + "name": "47K pullup", + "value": 0, + "description": "47K pullup" + }, + { + "name": "22K pullup", + "value": 1, + "description": "22K pullup" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "USDHC_PAD_PULL_DOWN", + "description": "The fuse bit is used for ROM to enable pull down bit for SD pads. ", + "values": [ + { + "name": "no action", + "value": 0, + "description": "no action" + }, + { + "name": "pull down", + "value": 1, + "description": "pull down" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "Override HYS bit for SD-MMC pads", + "description": "Once this fuse be blown, the [HYS] bit of IOMUXC_SW_PAD_CTL_PAD_SDx_CLK(x is the SD port which the ROM boot from), IOMUXC_SW_PAD_CTL_PAD_SDx_CMD, IOMUXC_SW_PAD_CTL_PAD_SDx_DAT0-n(n will be 0, 3, or 7, depends on the bus width selected) will be set. ", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "eMMC 4.4 - RESET TO PRE-IDLE STATE", + "description": "Once this fuse be blown, the CMD0 with argument 0xf0f0f0f0 will be sent to put the eMMC card into pre-IDLE state so that eMMC card’s fast boot can work properly.\nThis is useful for the warm boot, such as boot due to the WDOG reset.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-15", + "name": "SD2_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD2", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-20", + "name": "BT_LPB_POLARITY", + "description": "Define GPIO3 polarity, for determining LPB boot mode.", + "values": [ + { + "name": "Active High", + "value": 0, + "description": "Active High" + }, + { + "name": "Active Low", + "value": 1, + "description": "Active Low" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse7-bits-24-30", + "name": "MMC_DLL_DLY[6:0]", + "description": "eMMC 4.4 delay line default value (set by boot rom), used in conjunction with \"DLL Override\" = 1 (BOOT_CFG3[3])" + }, + { + "width": 1, + "id": "fuse7-bit-31", + "name": "Override NAND Pad Settings", + "description": "Override pad settings for NAND boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP0", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[31:0]" + ], + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller" + } + ] + }, + { + "id": "fuse33", + "name": "SJC_RESP1", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[55:32]" + ], + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 24, + "id": "fuse33-bits-0-23", + "name": "SJC_RESP[55:32]", + "description": "Response reference value for the secure JTAG controller" + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse34", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse35", + "name": "MAC1_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[15:0]" + ], + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse35-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse36", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_SPEED", + "description": "LPSPI Speed select", + "values": [ + { + "name": "00", + "value": 0, + "description": "20 MHz (default)" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-30-31", + "name": "SD_CALIBRATION_STEP", + "description": "SD Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + } + ] + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/database.yaml new file mode 100644 index 0000000..b7bd28c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/database.yaml @@ -0,0 +1,55 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1024 + +# General MCU information +info: + spsdk_predecessor_name: rt104x + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT1040 + memory_map: + itcm: + start_int: 0x0 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20000 + size_int: 0x60000 + warning_msg: RAM above 0x20000 is not initialized by default + dtcm: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20020000 + size_int: 0x60000 + warning_msg: RAM above 0x20020000 is not initialized by default + ocram: + start_int: 0x20200000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20240000 + size_int: 0x40000 + warning_msg: RAM above 0x20240000 is not initialized by default + flexspi: + start_int: 0x60000000 + size_int: 0x10000000 + external: true + non_xip_type: none + sdram: + start_int: 0x80000000 + size_int: 0x60000000 + external: true + non_xip_type: ext_ram_semc + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x0135 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/fuses.json new file mode 100644 index 0000000..249f894 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1040/fuses.json @@ -0,0 +1,2868 @@ +{ + "cpu": "mimxrt1040", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-7", + "name": "GP4_RLOCK", + "description": "GP4 read lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-24-25", + "name": "GP4_LOCK", + "description": "Lock for GP4 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-1", + "name": "SEC_CONFIG[0]", + "description": "Security Configuration Mode, and block of debugging of security HW, by JTAG" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "FLASH_AUTO_PROBE_EN", + "description": "FLASH_AUTO_PROBE_EN", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse5-bit-1", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse5-bits-2-3", + "name": "FLASH PROBE TYPE", + "description": "FLASH PROBE TYPE (SPI mode after PoR)", + "values": [ + { + "name": "00", + "value": 0, + "description": "00 - QuadSPI NOR" + }, + { + "name": "01", + "value": 1, + "description": "01 - Macronix Octal FLASH" + }, + { + "name": "10", + "value": 2, + "description": "10 - Micron Octal FLASH" + }, + { + "name": "11", + "value": 3, + "description": "11 - Adesto Octal FLASH" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG[1]", + "description": "Security Configuration (with SEC_CONFIG[0])", + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 396 / (Bus)132 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 528 / (Bus) 132 MHz" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "BEE_KEY0_SEL", + "description": "AES key selection for BEE_KEY0", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "GP4[127:0]", + "value": 1, + "description": "GP4[127:0]" + }, + { + "name": "OTPMK[255:128]", + "value": 2, + "description": "From OTPMK[255:128]" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "BEE_KEY1_SEL", + "description": "AES key selection for BEE_KEY1", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "GP4[127:0]", + "value": 1, + "description": "GP4[127:0]" + }, + { + "name": "OTPMK[[255:128]", + "value": 2, + "description": "From OTPMK[[255:128]" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-24", + "name": "DLL_ENABLE", + "description": "Controls the enable/disable of the DLL for SD/eMMC boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-25", + "name": "NAND_ECC_DISABLE", + "description": "Indicate whether to enabled ECC (done by SW/Device HW) for Raw Nand device", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "NAND ECC is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "NAND ECC is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-29", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "Select Power Stable Cycle", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-3", + "name": "Disable SDMMC Manufacture mode", + "description": "The fuse bit is used to disable ROM feature “SD/MMC Manufacturing Mode”.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-5", + "name": "SD2 VOLTAGE SELECTION", + "description": "Fuse bit to change voltage selection for SD2 pads. When set ROM will select 1.8V for SD3 pads otherwise 3.3V", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-6", + "name": "SD1_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD1", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-7", + "name": "DLL Override", + "description": "Select the DLL mode for SD/eMMC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-8", + "name": "USDHC IOMUX SRE Enable", + "description": "The fuse bit is used for ROM to enable SRE bit for SD pads", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-9", + "name": "USDHC_IOMUX_SION_BIT_ENABLE", + "description": "The fuse bit is used for ROM to enable SION bit for MUX control register.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1, + "id": "fuse7-bit-11", + "name": "ENABLE_EMMC_22K_PULLUP", + "description": "The fuse bit is used for ROM to enable 22K pullup for SD pads.", + "values": [ + { + "name": "47K pullup", + "value": 0, + "description": "47K pullup" + }, + { + "name": "22K pullup", + "value": 1, + "description": "22K pullup" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "USDHC_PAD_PULL_DOWN", + "description": "The fuse bit is used for ROM to enable pull down bit for SD pads. ", + "values": [ + { + "name": "no action", + "value": 0, + "description": "no action" + }, + { + "name": "pull down", + "value": 1, + "description": "pull down" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "Override HYS bit for SD-MMC pads", + "description": "Once this fuse be blown, the [HYS] bit of IOMUXC_SW_PAD_CTL_PAD_SDx_CLK(x is the SD port which the ROM boot from), IOMUXC_SW_PAD_CTL_PAD_SDx_CMD, IOMUXC_SW_PAD_CTL_PAD_SDx_DAT0-n(n will be 0, 3, or 7, depends on the bus width selected) will be set. ", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "eMMC 4.4 - RESET TO PRE-IDLE STATE", + "description": "Once this fuse be blown, the CMD0 with argument 0xf0f0f0f0 will be sent to put the eMMC card into pre-IDLE state so that eMMC card’s fast boot can work properly.\nThis is useful for the warm boot, such as boot due to the WDOG reset.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-15", + "name": "SD2_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD2", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-20", + "name": "BT_LPB_POLARITY", + "description": "Define GPIO3 polarity, for determining LPB boot mode.", + "values": [ + { + "name": "Active High", + "value": 0, + "description": "Active High" + }, + { + "name": "Active Low", + "value": 1, + "description": "Active Low" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse7-bits-24-30", + "name": "MMC_DLL_DLY[6:0]", + "description": "eMMC 4.4 delay line default value (set by boot rom), used in conjunction with \"DLL Override\" = 1 (BOOT_CFG3[3])" + }, + { + "width": 1, + "id": "fuse7-bit-31", + "name": "Override NAND Pad Settings", + "description": "Override pad settings for NAND boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP0", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[31:0]" + ], + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller" + } + ] + }, + { + "id": "fuse33", + "name": "SJC_RESP1", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[55:32]" + ], + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 24, + "id": "fuse33-bits-0-23", + "name": "SJC_RESP[55:32]", + "description": "Response reference value for the secure JTAG controller" + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse34", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse35", + "name": "MAC1_ADDR0_MAC2_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[47:16]" + ], + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse35-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16, + "id": "fuse35-bits-16-31", + "name": "MAC2_ADDR[47:32]", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[47:16]" + ] + } + ] + }, + { + "id": "fuse36", + "name": "MAC2_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[31:0]" + ], + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse36-bits-0-31", + "name": "MAC2_ADDR[31:0]", + "description": "Ethernet MAC Address" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x650", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_SPEED", + "description": "LPSPI Speed select", + "values": [ + { + "name": "00", + "value": 0, + "description": "20 MHz (default)" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-30-31", + "name": "SD_CALIBRATION_STEP", + "description": "SD Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + } + ] + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x800-0x870", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved48", + "name": "Reserved 0x800", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0800", + "index_int": "0x0030", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved49", + "name": "Reserved 0x810", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0810", + "index_int": "0x0031", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved50", + "name": "Reserved 0x820", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0820", + "index_int": "0x0032", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved51", + "name": "Reserved 0x830", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0830", + "index_int": "0x0033", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved52", + "name": "Reserved 0x840", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0840", + "index_int": "0x0034", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved53", + "name": "Reserved 0x850", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0850", + "index_int": "0x0035", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved54", + "name": "Reserved 0x860", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0860", + "index_int": "0x0036", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved55", + "name": "Reserved 0x870", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0870", + "index_int": "0x0037", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "GP3", + "description": "General Purpose Fuse Register 3." + }, + "registers": [ + { + "id": "fuse56", + "name": "GP3[127:96]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0880", + "index_int": "0x0038", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse57", + "name": "GP3[95:64]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0890", + "index_int": "0x0039", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse58", + "name": "GP3[63:32]", + "description": "General Purpose fuse register #3", + "offset_int": "0x08A0", + "index_int": "0x003A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse59", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x08B0", + "index_int": "0x003B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + } + ] + }, + { + "group": { + "name": "GP4", + "description": "General Purpose Fuse Register 4." + }, + "registers": [ + { + "id": "fuse60", + "name": "GP4[127:96]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08C0", + "index_int": "0x003C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse61", + "name": "GP4[95:64]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08D0", + "index_int": "0x003D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse62", + "name": "GP4[63:32]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08E0", + "index_int": "0x003E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse63", + "name": "GP4[31:0]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08F0", + "index_int": "0x003F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1043/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1043/database.yaml new file mode 100644 index 0000000..731f7e4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1043/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1040 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1046/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1046/database.yaml new file mode 100644 index 0000000..731f7e4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1046/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1040 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/database.yaml new file mode 100644 index 0000000..0ab52ad --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/database.yaml @@ -0,0 +1,49 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1024 + +# General MCU information +info: + spsdk_predecessor_name: rt105x + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT1050 + memory_map: + itcm: + start_int: 0x0 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20000 + size_int: 0x60000 + warning_msg: RAM above 0x20000 is not initialized by default + dtcm: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20020000 + size_int: 0x60000 + warning_msg: RAM above 0x20020000 is not initialized by default + ocram: + start_int: 0x20200000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20240000 + size_int: 0x40000 + warning_msg: RAM above 0x20240000 is not initialized by default + flexspi: + start_int: 0x60000000 + size_int: 0x10000000 + external: true + non_xip_type: none + sdram: + start_int: 0x80000000 + size_int: 0x60000000 + external: true + non_xip_type: ext_ram_semc diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/fuses.json new file mode 100644 index 0000000..7156c3c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1050/fuses.json @@ -0,0 +1,2568 @@ +{ + "cpu": "mimxrt1050", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-1", + "name": "SEC_CONFIG[0]", + "description": "Security Configuration Mode, and block of debugging of security HW, by JTAG" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse5-bit-1", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse5-bits-2-3", + "name": "HOLD TIME", + "description": "HOLD TIME", + "values": [ + { + "name": "00", + "value": 0, + "description": "00 - 500us (NOR), 0us (NAND)" + }, + { + "name": "01", + "value": 1, + "description": "01 - 1ms (NOR), 500us (NAND)" + }, + { + "name": "10", + "value": 2, + "description": "10 - 3ms (NOR), 1ms (NAND)" + }, + { + "name": "11", + "value": 3, + "description": "11 - 10ms (NOR), 3ms (NAND)" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG[1]", + "description": "Security Configuration (with SEC_CONFIG[0])", + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 396 / (Bus)132 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 528 / (Bus) 132 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-3", + "name": "DIR_BT_DIS", + "description": "Direct External Memory Boot Disable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Direct boot from external memory is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Direct boot from external memory is not allowed" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "BEE_KEY0_SEL", + "description": "AES key selection for BEE_KEY0", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "BEE_KEY1_SEL", + "description": "AES key selection for BEE_KEY1", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "From OTPMK", + "value": 2, + "description": "From OTPMK" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-24", + "name": "DLL_ENABLE", + "description": "Controls the enable/disable of the DLL for SD/eMMC boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-25", + "name": "NAND_ECC_DISABLE", + "description": "Indicate whether to enabled ECC (done by SW/Device HW) for Raw Nand device", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "NAND ECC is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "NAND ECC is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-29", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "Select Power Stable Cycle", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-3", + "name": "Disable SDMMC Manufacture mode", + "description": "The fuse bit is used to disable ROM feature “SD/MMC Manufacturing Mode”.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-5", + "name": "SD2 VOLTAGE SELECTION", + "description": "Fuse bit to change voltage selection for SD2 pads. When set ROM will select 1.8V for SD3 pads otherwise 3.3V", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-6", + "name": "SD1_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD1", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-7", + "name": "DLL Override", + "description": "Select the DLL mode for SD/eMMC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-8", + "name": "USDHC IOMUX SRE Enable", + "description": "The fuse bit is used for ROM to enable SRE bit for SD pads", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-9", + "name": "USDHC_IOMUX_SION_BIT_ENABLE", + "description": "The fuse bit is used for ROM to enable SION bit for MUX control register.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1, + "id": "fuse7-bit-11", + "name": "ENABLE_EMMC_22K_PULLUP", + "description": "The fuse bit is used for ROM to enable 22K pullup for SD pads.", + "values": [ + { + "name": "47K pullup", + "value": 0, + "description": "47K pullup" + }, + { + "name": "22K pullup", + "value": 1, + "description": "22K pullup" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "USDHC_PAD_PULL_DOWN", + "description": "The fuse bit is used for ROM to enable pull down bit for SD pads. ", + "values": [ + { + "name": "no action", + "value": 0, + "description": "no action" + }, + { + "name": "pull down", + "value": 1, + "description": "pull down" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "Override HYS bit for SD-MMC pads", + "description": "Once this fuse be blown, the [HYS] bit of IOMUXC_SW_PAD_CTL_PAD_SDx_CLK(x is the SD port which the ROM boot from), IOMUXC_SW_PAD_CTL_PAD_SDx_CMD, IOMUXC_SW_PAD_CTL_PAD_SDx_DAT0-n(n will be 0, 3, or 7, depends on the bus width selected) will be set. ", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "eMMC 4.4 - RESET TO PRE-IDLE STATE", + "description": "Once this fuse be blown, the CMD0 with argument 0xf0f0f0f0 will be sent to put the eMMC card into pre-IDLE state so that eMMC card’s fast boot can work properly.\nThis is useful for the warm boot, such as boot due to the WDOG reset.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-15", + "name": "SD2_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD2", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-20", + "name": "BT_LPB_POLARITY", + "description": "Define GPIO3 polarity, for determining LPB boot mode.", + "values": [ + { + "name": "Active High", + "value": 0, + "description": "Active High" + }, + { + "name": "Active Low", + "value": 1, + "description": "Active Low" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse7-bits-24-30", + "name": "MMC_DLL_DLY[6:0]", + "description": "eMMC 4.4 delay line default value (set by boot rom), used in conjunction with \"DLL Override\" = 1 (BOOT_CFG3[3])" + }, + { + "width": 1, + "id": "fuse7-bit-31", + "name": "Override NAND Pad Settings", + "description": "Override pad settings for NAND boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP0", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[31:0]" + ], + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller" + } + ] + }, + { + "id": "fuse33", + "name": "SJC_RESP1", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[55:32]" + ], + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 24, + "id": "fuse33-bits-0-23", + "name": "SJC_RESP[55:32]", + "description": "Response reference value for the secure JTAG controller" + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse34", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse35", + "name": "MAC1_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[15:0]" + ], + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse35-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse36", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_CS_SEL", + "description": "LPSPI CS select", + "values": [ + { + "name": "00", + "value": 0, + "description": "CS#0 (default)" + }, + { + "name": "CS#1", + "value": 1, + "description": "CS#1" + }, + { + "name": "CS#2", + "value": 2, + "description": "CS#2" + }, + { + "name": "CS#3", + "value": 3, + "description": "CS#3" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-30-31", + "name": "SD_CALIBRATION_STEP", + "description": "SD Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + } + ] + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1060/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1060/database.yaml new file mode 100644 index 0000000..b2779fc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1060/database.yaml @@ -0,0 +1,58 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1064 + +# General MCU information +info: + memory_map: + itcm: + start_int: 0x0 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20000 + size_int: 0x60000 + warning_msg: RAM above 0x20000 is not initialized by default + dtcm: + start_int: 0x20000000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x20020000 + size_int: 0x60000 + warning_msg: RAM above 0x20020000 is not initialized by default + ocram: + start_int: 0x20200000 + size_int: 0x100000 + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: 0x202C0000 + size_int: 0x40000 + warning_msg: RAM above 0x202C0000 is not initialized by default + flexspi1: + start_int: 0x30000000 + size_int: 0x10000000 + external: true + non_xip_type: none + flexspi2: + start_int: 0x60000000 + size_int: 0x1f80_0000 + external: true + non_xip_type: none + sdram: + start_int: 0x80000000 + size_int: 0x60000000 + external: true + non_xip_type: ext_ram_semc + +features: + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [1, 2] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/database.yaml new file mode 100644 index 0000000..6fddb62 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/database.yaml @@ -0,0 +1,61 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1024 + +# General MCU information +info: + spsdk_predecessor_name: rt106x + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT1060 + memory_map: + itcm: + start_int: "0x0" + size_int: "0x80000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x20000" + size_int: "0x60000" + warning_msg: RAM above 0x20000 is not initialized by default + dtcm: + start_int: "0x20000000" + size_int: "0x80000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x20020000" + size_int: "0x60000" + warning_msg: RAM above 0x20020000 is not initialized by default + ocram: + start_int: "0x20200000" + size_int: "0x100000" + external: false + non_xip_type: int_ram + warning_ranges: + - start_int: "0x202C0000" + size_int: "0x40000" + warning_msg: RAM above 0x202C0000 is not initialized by default + flexspi: + start_int: "0x60000000" + size_int: "0x10000000" + external: true + non_xip_type: none + flexspi2: + start_int: "0x70000000" + size_int: "0x0f000000" + external: true + non_xip_type: none + sdram: + start_int: "0x80000000" + size_int: "0x60000000" + external: true + non_xip_type: ext_ram_semc + + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x0135 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/fuses.json new file mode 100644 index 0000000..8440f5e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1064/fuses.json @@ -0,0 +1,2868 @@ +{ + "cpu": "mimxrt1064", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS", + "description": "Fuse LOCKS", + "offset_int": "0x0400", + "index_int": "0", + "bitfields": [ + { + "width": 2, + "id": "fuse0-bits-0-1", + "name": "TESTER_LOCK", + "description": "Perform lock on Tester programed fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-2-3", + "name": "BOOT_CFG_LOCK", + "description": "Perform lock on BOOT related fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse0-bit-6", + "name": "SJC_RESP_LOCK", + "description": "SJC response lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read, sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-7", + "name": "GP4_RLOCK", + "description": "GP4 read lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-8-9", + "name": "MAC_ADDR_LOCK", + "description": "Lock MAC_ADDR fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-10-11", + "name": "GP1_LOCK", + "description": "Lock for General Purpose fuse register #1 (GP1)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-12-13", + "name": "GP2_LOCK", + "description": "Lock for General Purpose fuse register #2 (GP2)", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-16", + "name": "SW_GP1_LOCK", + "description": "Lock for SW_GP1 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse0-bits-18-19", + "name": "ANALOG_LOCK", + "description": "Lock for analog related fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-21", + "name": "SW_GP2_LOCK", + "description": "WP and OP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be sensed, burned or overridden in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-22", + "name": "MISC_CONF_LOCK", + "description": "RP Lock for MISC_CONF0, MISC_CONF1 fuses.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse0-bit-23", + "name": "SW_GP2_RLOCK", + "description": "RP Lock for SW_GP2 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-24-25", + "name": "GP4_LOCK", + "description": "Lock for GP4 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2, + "id": "fuse0-bits-26-27", + "name": "GP3_LOCK", + "description": "Lock for GP3 fuse.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded IIM register)" + }, + { + "name": "Write Lock", + "value": 1, + "description": "Write Lock (The controlled field can be read or sensed only)" + }, + { + "name": "Operation Lock", + "value": 2, + "description": "Operation Lock (The controlled field can't be overridden)" + }, + { + "name": "Full Lock", + "value": 3, + "description": "Write Lock + Operation Lock." + } + ] + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse0-bit-31", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1", + "value": 1, + "description": "Device is open for 'field-return' testing." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Different identifiers" + }, + "registers": [ + { + "id": "fuse1", + "name": "LOT_NO_ENC1", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0410", + "index_int": "0x0001", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse1-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse2", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0420", + "index_int": "0x0002", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 11, + "id": "fuse2-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "NXP-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID" + }, + { + "width": 5, + "id": "fuse2-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + }, + { + "width": 8, + "id": "fuse2-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID" + } + ] + }, + { + "id": "fuse3", + "name": "SI_REV", + "description": "Fuse SI_REV", + "deprecated_names": [ + "SI_REV[3:0]" + ], + "offset_int": "0x0430", + "index_int": "0x0003", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse3-bits-16-19", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse4", + "name": "TESTER_CFG", + "description": "Fuse TESTER_CFG", + "offset_int": "0x0440", + "index_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-1", + "name": "SEC_CONFIG[0]", + "description": "Security Configuration Mode, and block of debugging of security HW, by JTAG" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse4-bits-16-17", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating IC core speed" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "Boot config", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse5", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0450", + "index_int": "0x0005", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse5-bit-0", + "name": "FLASH_AUTO_PROBE_EN", + "description": "FLASH_AUTO_PROBE_EN", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse5-bit-1", + "name": "EncryptedXIP", + "description": "Support for the encrypted bootable image. It is applied only if BT_FUSE_SEL fuse bit is set. Otherwise the value is retrieved from the pins.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "0 - Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "1 - Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse5-bits-2-3", + "name": "FLASH PROBE TYPE", + "description": "FLASH PROBE TYPE (SPI mode after PoR)", + "values": [ + { + "name": "00", + "value": 0, + "description": "00 - QuadSPI NOR" + }, + { + "name": "01", + "value": 1, + "description": "01 - Macronix Octal FLASH" + }, + { + "name": "10", + "value": 2, + "description": "10 - Micron Octal FLASH" + }, + { + "name": "11", + "value": 3, + "description": "11 - Adesto Octal FLASH" + } + ] + }, + { + "width": 4, + "id": "fuse5-bits-4-7", + "name": "Boot_Device_Selection", + "description": "Boot device selection.", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "0000 - FlexSPI (Serial NOR)" + }, + { + "name": "SEMC (NOR)", + "value": 1, + "description": "0001 - SEMC (NOR)" + }, + { + "name": "SEMC (NAND)", + "value": 2, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SEMC (NAND)_1", + "value": 3, + "description": "001x - SEMC (NAND)" + }, + { + "name": "SD (SDR12)", + "value": 4, + "description": "0100 - SD/SDXC Speed (Normal/SDR12)" + }, + { + "name": "SD (SDR25)", + "value": 5, + "description": "0101 - SD/SDXC Speed (High/SDR25)" + }, + { + "name": "SD (SDR50)", + "value": 6, + "description": "0110 - SD/SDXC Speed (SDR50)" + }, + { + "name": "SD (SDR104)", + "value": 7, + "description": "0111 - SD/SDXC Speed (SDR104)" + }, + { + "name": "eMMC: Normal", + "value": 8, + "description": "1000 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: Normal/FB", + "value": 9, + "description": "1001 - MMC/eMMC (SD/MMC Speed Normal, Fast Boot Acknowledge Enabled)" + }, + { + "name": "eMMC: High", + "value": 10, + "description": "1010 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Disabled)" + }, + { + "name": "eMMC: High/FB", + "value": 11, + "description": "1011 - MMC/eMMC (SD/MMC Speed High, Fast Boot Acknowledge Enabled)" + }, + { + "name": "FlexSPI NAND 50MHz 12b", + "value": 12, + "description": "1100 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b", + "value": 13, + "description": "1101 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + }, + { + "name": "FlexSPI NAND 50MHz 12b 1", + "value": 14, + "description": "1110 - FlexSPI (Serial NAND), Default safe communication frequency High Speed (50 MHz), column address width 12bits" + }, + { + "name": "FlexSPI NAND 30MHz 13b 1", + "value": 15, + "description": "1111 - FlexSPI (Serial NAND), Default safe communication frequency Low Speed (30 MHz), column address width 13bits" + } + ] + }, + { + "width": 8, + "id": "fuse5-bits-8-15", + "name": "BOOT_CFG2", + "description": "BOOT configuration register #2, Usage varies, depending on selected boot device." + }, + { + "width": 8, + "id": "fuse5-bits-16-23", + "name": "BOOT_CFG3", + "description": "BOOT configuration register #3" + }, + { + "width": 8, + "id": "fuse5-bits-24-31", + "name": "BOOT_CFG4", + "description": "BOOT configuration register #4" + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0460", + "index_int": "0x0006", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-1", + "name": "SEC_CONFIG[1]", + "description": "Security Configuration (with SEC_CONFIG[0])", + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-2", + "name": "Boot Frequencies", + "description": "Determines, ARM Core and Bus frequencies during boot", + "values": [ + { + "name": "0", + "value": 0, + "description": "(ARM) 396 / (Bus)132 MHz" + }, + { + "name": "1", + "value": 1, + "description": "(ARM) 528 / (Bus) 132 MHz" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse6-bits-8-11", + "name": "SDRAM_CONFIG", + "description": "TBD (SDRAM config options)", + "deprecated_names": [ + "SDRAM_CONFIG[7:0]" + ] + }, + { + "width": 2, + "id": "fuse6-bits-12-13", + "name": "BEE_KEY0_SEL", + "description": "AES key selection for BEE_KEY0", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "GP4[127:0]", + "value": 1, + "description": "GP4[127:0]" + }, + { + "name": "OTPMK[255:128]", + "value": 2, + "description": "From OTPMK[255:128]" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-14-15", + "name": "BEE_KEY1_SEL", + "description": "AES key selection for BEE_KEY1", + "values": [ + { + "name": "From register", + "value": 0, + "description": "From register" + }, + { + "name": "GP4[127:0]", + "value": 1, + "description": "GP4[127:0]" + }, + { + "name": "OTPMK[[255:128]", + "value": 2, + "description": "From OTPMK[[255:128]" + }, + { + "name": "From SW-GP2", + "value": 3, + "description": "From SW-GP2" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-16", + "name": "FORCE_INTERNAL_BOOT", + "description": "Once been blown, the external BT_MODE[1:0] pins will be ignored, BootROM will take Boot Mode as “internal boot”.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot Mode from BT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "BT_MODE pins be ignored, Boot Mode forced to \"internal boot\"" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-17", + "name": "SDP_DISABLE", + "description": "Disable/Enable serial download support", + "values": [ + { + "name": "0", + "value": 0, + "description": "Serial download supported" + }, + { + "name": "1", + "value": 1, + "description": "No serial download support" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-18", + "name": "SDP_READ_DISABLE", + "description": "Disable/Enable serial download READ_REGISTER command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "SDP READ_REGISTER command is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "SDP READ_REGISTER is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-19", + "name": "DAP_SJC_SWD_SEL", + "description": "Control DAP works in JTAG or SWD mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DAP works in SWD mode" + }, + { + "name": "1", + "value": 1, + "description": "DAP works in JTAG mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-20", + "name": "SJC_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-21", + "name": "WDOG_ENABLE", + "description": "Watchdog Enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Watch-Dog is disabled." + }, + { + "name": "Enable", + "value": 1, + "description": "Watch-Dog is enabled." + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-22-23", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-24", + "name": "DLL_ENABLE", + "description": "Controls the enable/disable of the DLL for SD/eMMC boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable DLL for SD/eMMC" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable DLL for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-25", + "name": "NAND_ECC_DISABLE", + "description": "Indicate whether to enabled ECC (done by SW/Device HW) for Raw Nand device", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "NAND ECC is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "NAND ECC is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-26", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-27", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-29", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "Select Power Stable Cycle", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse6-bits-30-31", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "Select SD Power Cycle", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + } + ] + }, + { + "id": "fuse7", + "name": "BOOT_CFG2", + "description": "Fuse BOOT_CFG2", + "offset_int": "0x0470", + "index_int": "0x0007", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0004", + "operation_lock_int": "0x0008" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "Override SD Pad Settings", + "description": "Overrides ROM default value for SD PAD control register. When set ROM will override SD pad control register with value programmed into PAD_SETTINGS fuse bits.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "BT_MPU_DISABLE", + "description": "The fuse bit is used for ROM to not enable MMU", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "MPU is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "MPU is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-2", + "name": "L1 I-Cache DISABLE", + "description": "The fuse bit is used for ROM to not enable L1 I-Cache", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "L1 I-Cache is enabled during boot" + }, + { + "name": "Disable", + "value": 1, + "description": "L1 I-Cache is disabled during boot" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-3", + "name": "Disable SDMMC Manufacture mode", + "description": "The fuse bit is used to disable ROM feature “SD/MMC Manufacturing Mode”.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "UART Serial Download Disable", + "description": "Disable UART Serial Download", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-5", + "name": "SD2 VOLTAGE SELECTION", + "description": "Fuse bit to change voltage selection for SD2 pads. When set ROM will select 1.8V for SD3 pads otherwise 3.3V", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-6", + "name": "SD1_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD1", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-7", + "name": "DLL Override", + "description": "Select the DLL mode for SD/eMMC.", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-8", + "name": "USDHC IOMUX SRE Enable", + "description": "The fuse bit is used for ROM to enable SRE bit for SD pads", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-9", + "name": "USDHC_IOMUX_SION_BIT_ENABLE", + "description": "The fuse bit is used for ROM to enable SION bit for MUX control register.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-10", + "name": "Boot Failure Indicator Pin Select[4]", + "description": "Indicate Boot Failure" + }, + { + "width": 1, + "id": "fuse7-bit-11", + "name": "ENABLE_EMMC_22K_PULLUP", + "description": "The fuse bit is used for ROM to enable 22K pullup for SD pads.", + "values": [ + { + "name": "47K pullup", + "value": 0, + "description": "47K pullup" + }, + { + "name": "22K pullup", + "value": 1, + "description": "22K pullup" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-12", + "name": "USDHC_PAD_PULL_DOWN", + "description": "The fuse bit is used for ROM to enable pull down bit for SD pads. ", + "values": [ + { + "name": "no action", + "value": 0, + "description": "no action" + }, + { + "name": "pull down", + "value": 1, + "description": "pull down" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-13", + "name": "Override HYS bit for SD-MMC pads", + "description": "Once this fuse be blown, the [HYS] bit of IOMUXC_SW_PAD_CTL_PAD_SDx_CLK(x is the SD port which the ROM boot from), IOMUXC_SW_PAD_CTL_PAD_SDx_CMD, IOMUXC_SW_PAD_CTL_PAD_SDx_DAT0-n(n will be 0, 3, or 7, depends on the bus width selected) will be set. ", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-14", + "name": "eMMC 4.4 - RESET TO PRE-IDLE STATE", + "description": "Once this fuse be blown, the CMD0 with argument 0xf0f0f0f0 will be sent to put the eMMC card into pre-IDLE state so that eMMC card’s fast boot can work properly.\nThis is useful for the warm boot, such as boot due to the WDOG reset.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-15", + "name": "SD2_RST_POLARITY_SELECT", + "description": "Select reset polarity for SD2", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 4, + "id": "fuse7-bits-16-19", + "name": "Boot Failure Indicator Pin Select[3:0]", + "description": "Miscellaneous power management configuration bits.", + "values": [ + { + "name": "gpio1.IO00", + "value": 0, + "description": "gpio1.IO00" + }, + { + "name": "gpio1.IO01", + "value": 1, + "description": "gpio1.IO01" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-20", + "name": "BT_LPB_POLARITY", + "description": "Define GPIO3 polarity, for determining LPB boot mode.", + "values": [ + { + "name": "Active High", + "value": 0, + "description": "Active High" + }, + { + "name": "Active Low", + "value": 1, + "description": "Active Low" + } + ] + }, + { + "width": 2, + "id": "fuse7-bits-21-22", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1 + }, + { + "width": 7, + "id": "fuse7-bits-24-30", + "name": "MMC_DLL_DLY[6:0]", + "description": "eMMC 4.4 delay line default value (set by boot rom), used in conjunction with \"DLL Override\" = 1 (BOOT_CFG3[3])" + }, + { + "width": 1, + "id": "fuse7-bit-31", + "name": "Override NAND Pad Settings", + "description": "Override pad settings for NAND boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x480-0x4E0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved8", + "name": "Reserved 0x480", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0480", + "index_int": "0x0008", + "is_reserved": true, + "bitfields": [ + { + "width": 6 + }, + { + "width": 2 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 3 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + } + ] + }, + { + "id": "Reserved9", + "name": "Reserved 0x490", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0490", + "index_int": "0x0009", + "is_reserved": true, + "bitfields": [ + { + "width": 10 + }, + { + "width": 1 + }, + { + "width": 5 + }, + { + "width": 8 + }, + { + "width": 4 + }, + { + "width": 4 + } + ] + }, + { + "id": "Reserved10", + "name": "Reserved 0x4A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x4B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x4C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 20 + }, + { + "width": 12 + } + ] + }, + { + "id": "Reserved13", + "name": "Reserved 0x4D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04D0", + "index_int": "0x000D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved14", + "name": "Reserved 0x4E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x04E0", + "index_int": "0x000E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "USB VID and PID" + }, + "registers": [ + { + "id": "fuse15", + "name": "USB_ID", + "description": "Fuse USB_ID", + "offset_int": "0x04F0", + "index_int": "0x000F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00040000", + "operation_lock_int": "0x00080000" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse15-bits-0-15", + "name": "USB_VID", + "description": "USB VID", + "deprecated_names": [ + "USB_VID[31:0]" + ] + }, + { + "width": 16, + "id": "fuse15-bits-16-31", + "name": "USB_PID", + "description": "USB PID", + "deprecated_names": [ + "USB_PID[31:0]" + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x500-0x570", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved16", + "name": "Reserved 0x500", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0500", + "index_int": "0x0010", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved17", + "name": "Reserved 0x510", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0510", + "index_int": "0x0011", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved18", + "name": "Reserved 0x520", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0520", + "index_int": "0x0012", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved19", + "name": "Reserved 0x530", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0530", + "index_int": "0x0013", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved20", + "name": "Reserved 0x540", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0540", + "index_int": "0x0014", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved21", + "name": "Reserved 0x550", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0550", + "index_int": "0x0015", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved22", + "name": "Reserved 0x560", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0560", + "index_int": "0x0016", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved23", + "name": "Reserved 0x570", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0570", + "index_int": "0x0017", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "SRK Hash", + "description": "Super Root Keys Hash" + }, + "registers": [ + { + "id": "fuse24", + "name": "SRK_HASH[255:224]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0580", + "index_int": "0x0018" + }, + { + "id": "fuse25", + "name": "SRK_HASH[223:192]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0590", + "index_int": "0x0019" + }, + { + "id": "fuse26", + "name": "SRK_HASH[191:160]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05A0", + "index_int": "0x001A" + }, + { + "id": "fuse27", + "name": "SRK_HASH[159:128]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05B0", + "index_int": "0x001B" + }, + { + "id": "fuse28", + "name": "SRK_HASH[127:96]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05C0", + "index_int": "0x001C" + }, + { + "id": "fuse29", + "name": "SRK_HASH[95:64]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05D0", + "index_int": "0x001D" + }, + { + "id": "fuse30", + "name": "SRK_HASH[63:32]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05E0", + "index_int": "0x001E" + }, + { + "id": "fuse31", + "name": "SRK_HASH[31:0]", + "description": "SRK key, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x05F0", + "index_int": "0x001F" + } + ] + }, + { + "group": { + "name": "SJC", + "description": "Secure JTAG Controller" + }, + "registers": [ + { + "id": "fuse32", + "name": "SJC_RESP0", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[31:0]" + ], + "offset_int": "0x0600", + "index_int": "0x0020", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse32-bits-0-31", + "name": "SJC_RESP[31:0]", + "description": "Response reference value for the secure JTAG controller" + } + ] + }, + { + "id": "fuse33", + "name": "SJC_RESP1", + "description": "Response reference value for the secure JTAG controller", + "deprecated_names": [ + "SJC_RESP[55:32]" + ], + "offset_int": "0x0610", + "index_int": "0x0021", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0040", + "read_lock_int": "0x0040", + "operation_lock_int": "0x0040" + }, + "bitfields": [ + { + "width": 24, + "id": "fuse33-bits-0-23", + "name": "SJC_RESP[55:32]", + "description": "Response reference value for the secure JTAG controller" + }, + { + "width": 8 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse34", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0620", + "index_int": "0x0022", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse34-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse35", + "name": "MAC1_ADDR0_MAC2_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[47:16]" + ], + "offset_int": "0x0630", + "index_int": "0x0023", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse35-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16, + "id": "fuse35-bits-16-31", + "name": "MAC2_ADDR[47:32]", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[47:16]" + ] + } + ] + }, + { + "id": "fuse36", + "name": "MAC2_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[31:0]" + ], + "offset_int": "0x0640", + "index_int": "0x0024", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0100", + "operation_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse36-bits-0-31", + "name": "MAC2_ADDR[31:0]", + "description": "Ethernet MAC Address" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x650", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved37", + "name": "Reserved 0x650", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0650", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "General Purpose Fuse Registers." + }, + "registers": [ + { + "id": "fuse38", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x0660", + "index_int": "0x0026", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0400", + "operation_lock_int": "0x0800" + } + }, + { + "id": "fuse39", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x0670", + "index_int": "0x0027", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "SW_GPx", + "description": "SW general purpose keys." + }, + "registers": [ + { + "id": "fuse40", + "name": "SW_GP1[31:0]", + "description": "SW general purpose key", + "offset_int": "0x0680", + "index_int": "0x0028", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00010000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00010000" + } + }, + { + "id": "fuse41", + "name": "SW_GP2[127:96]", + "description": "SW general purpose key", + "offset_int": "0x0690", + "index_int": "0x0029", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse42", + "name": "SW_GP2[95:64]", + "description": "SW general purpose key", + "offset_int": "0x06A0", + "index_int": "0x002A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse43", + "name": "SW_GP2[63:32]", + "description": "SW general purpose key", + "offset_int": "0x06B0", + "index_int": "0x002B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + }, + { + "id": "fuse44", + "name": "SW_GP2[31:0]", + "description": "SW general purpose key", + "offset_int": "0x06C0", + "index_int": "0x002C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x00200000", + "read_lock_int": "0x00800000", + "operation_lock_int": "0x00200000" + } + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration." + }, + "registers": [ + { + "id": "fuse45", + "name": "MISC_CONF0", + "description": "Fuse MISC_CONF0", + "offset_int": "0x06D0", + "index_int": "0x002D", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse45-bits-0-5", + "name": "PAD_SETTINGS", + "description": "Used with conjunction of MMC/SD/Nand \"Override Pad Settings\" fuse value, as follow:\n'0' - Use IO default settings for boot device IO pads.\n'1' - Use \"Override\" value, as set by this register." + }, + { + "width": 1, + "id": "fuse45-bit-6", + "name": "USB_VBUS_EVENT_HANDLER_EN", + "description": "Rom handle USB VBUS attach/detach event", + "values": [ + { + "name": "0", + "value": 0, + "description": "ROM not handle USB VBUS attach/detach event" + }, + { + "name": "1", + "value": 1, + "description": "ROM handle USB VBUS attach/detach event" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-7", + "name": "Enable Boot Failure Indicator Pin", + "description": "Enable Boot Failure Indicator Pin", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-8-11", + "name": "READ_RETRY_SEQ_ID", + "description": "Choose Read Retry Sequence ", + "values": [ + { + "name": "0000", + "value": 0, + "description": "don't use read retry(RR) sequence embedded in ROM" + }, + { + "name": "0001", + "value": 1, + "description": "Micron 20nm RR sequence" + }, + { + "name": "0010", + "value": 2, + "description": "Toshiba A19nm RR sequence" + }, + { + "name": "0011", + "value": 3, + "description": "Toshiba 19nm RR sequence" + }, + { + "name": "0100", + "value": 4, + "description": "SanDisk 19nm RR sequence" + }, + { + "name": "0101", + "value": 5, + "description": "SanDisk 1ynmRR sequence" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse45-bits-13-15", + "name": "WDOG Timeout Select", + "description": "Select WDOG Timeout", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 4, + "id": "fuse45-bits-16-19", + "name": "Default_FlexRAM_Part", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse45-bit-24", + "name": "EEPROM_RECOVERY_EN", + "description": "EEPROM Recovery Enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-25-26", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI Port Select", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 1, + "id": "fuse45-bit-27", + "name": "LPSPI_ADDR", + "description": "SPI Addressing", + "values": [ + { + "name": "2-bytes", + "value": 0, + "description": "2-bytes (16-bit)" + }, + { + "name": "3-bytes", + "value": 1, + "description": "3-bytes (24-bit)" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-28-29", + "name": "LPSPI_SPEED", + "description": "LPSPI Speed select", + "values": [ + { + "name": "00", + "value": 0, + "description": "20 MHz (default)" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2, + "id": "fuse45-bits-30-31", + "name": "SD_CALIBRATION_STEP", + "description": "SD Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + } + ] + } + ] + }, + { + "id": "fuse46", + "name": "MISC_CONF1", + "description": "Fuse MISC_CONF1", + "offset_int": "0x06E0", + "index_int": "0x002E", + "lock": { + "register_id": "fuse0", + "read_lock_int": "0x00400000" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse46-bits-0-7", + "name": "BOOT_CONFIG_MISC0", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-8-15", + "name": "BOOT_CONFIG_MISC1", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-16-23", + "name": "BOOT_CONFIG_MISC2", + "description": "boot configuration misc " + }, + { + "width": 8, + "id": "fuse46-bits-24-31", + "name": "BOOT_CONFIG_MISC3", + "description": "boot configuration misc " + } + ] + }, + { + "id": "fuse47", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x06F0", + "index_int": "0x002F", + "bitfields": [ + { + "width": 1, + "id": "fuse47-bit-0", + "name": "SRK_REVOKE1", + "description": "SRK key 1 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-1", + "name": "SRK_REVOKE2", + "description": "SRK key 2 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-2", + "name": "SRK_REVOKE3", + "description": "SRK key 3 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse47-bit-3", + "name": "SRK_REVOKE4", + "description": "SRK key 4 revocation", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 4 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x800-0x870", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved48", + "name": "Reserved 0x800", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0800", + "index_int": "0x0030", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved49", + "name": "Reserved 0x810", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0810", + "index_int": "0x0031", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved50", + "name": "Reserved 0x820", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0820", + "index_int": "0x0032", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved51", + "name": "Reserved 0x830", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0830", + "index_int": "0x0033", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved52", + "name": "Reserved 0x840", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0840", + "index_int": "0x0034", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved53", + "name": "Reserved 0x850", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0850", + "index_int": "0x0035", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved54", + "name": "Reserved 0x860", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0860", + "index_int": "0x0036", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved55", + "name": "Reserved 0x870", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0870", + "index_int": "0x0037", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "GP3", + "description": "General Purpose Fuse Register 3." + }, + "registers": [ + { + "id": "fuse56", + "name": "GP3[127:96]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0880", + "index_int": "0x0038", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse57", + "name": "GP3[95:64]", + "description": "General Purpose fuse register #3", + "offset_int": "0x0890", + "index_int": "0x0039", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse58", + "name": "GP3[63:32]", + "description": "General Purpose fuse register #3", + "offset_int": "0x08A0", + "index_int": "0x003A", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + }, + { + "id": "fuse59", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x08B0", + "index_int": "0x003B", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x04000000", + "operation_lock_int": "0x08000000" + } + } + ] + }, + { + "group": { + "name": "GP4", + "description": "General Purpose Fuse Register 4." + }, + "registers": [ + { + "id": "fuse60", + "name": "GP4[127:96]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08C0", + "index_int": "0x003C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse61", + "name": "GP4[95:64]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08D0", + "index_int": "0x003D", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse62", + "name": "GP4[63:32]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08E0", + "index_int": "0x003E", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + }, + { + "id": "fuse63", + "name": "GP4[31:0]", + "description": "General Purpose fuse register #4", + "offset_int": "0x08F0", + "index_int": "0x003F", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x01000000", + "read_lock_int": "0x0080", + "operation_lock_int": "0x02000000" + } + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1165/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1165/database.yaml new file mode 100644 index 0000000..ca048ba --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1165/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1166 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/database.yaml new file mode 100644 index 0000000..1fa72d6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/database.yaml @@ -0,0 +1,277 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt116x + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-dual-core-arm-cortex-m7-and-cortex-m4:i.MX-RT1160 + memory_map: + itcm: + start_int: 0x0 + size_int: 0x40000 + external: false + non_xip_type: int_ram + cm4_itcm: + start_int: 0x1FFE0000 + size_int: 0x20000 + external: false + non_xip_type: int_ram + dtcm: + start_int: 0x20000000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + cm4_ocram: + start_int: 0x20200000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + ocram1: + start_int: 0x20240000 + size_int: 0x10000 + external: false + non_xip_type: int_ram + ocram2: + start_int: 0x202C0000 + size_int: 0x8000 + external: false + non_xip_type: int_ram + flexspi1: + start_int: 0x30000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_flexspi + flexspi2: + start_int: 0x60000000 + size_int: 0x1F800000 + external: true + non_xip_type: ext_ram_flexspi + sdram: + start_int: 0x80000000 + size_int: 0x4000000 + external: true + non_xip_type: ext_ram_semc + + isp: + rom: + protocol: sdp + usb: + - vid: 0x1FC9 + pid: 0x013D + flashloader: + protocol: mboot + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + grouped_registers: + - uid: iee_user_key1 + name: USER_KEY1 + width: 256 + reversed: True + config_as_hexstring: True + description: USER KEY 1 (IBKEK). + sub_regs: + [fuse96, fuse97, fuse98, fuse99, fuse100, fuse101, fuse102, fuse103] + - uid: iee_user_key2 + name: USER_KEY2 + width: 256 + reversed: True + config_as_hexstring: True + description: USER KEY 2 (IBKEK). + sub_regs: + [ + fuse104, + fuse105, + fuse106, + fuse107, + fuse108, + fuse109, + fuse110, + fuse111, + ] + - uid: otfad_key + name: OTFAD_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD Key known as KEK. + sub_regs: [fuse128, fuse129, fuse130, fuse131] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x0000_2000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: "srk_table_hab" + + # ======== HABv4 section ======== + hab: + mem_types: + flexspi_nor: + initial_load_size: 0x2000 + flexspi_nand: + initial_load_size: 0x1000 + semc_nand: + initial_load_size: 0x1000 + sd: + initial_load_size: 0x1000 + mmc: + initial_load_size: 0x1000 + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== XMCD section ======== + xmcd: + mem_types: + flexspi_ram: + simplified: + reg_spec: ../../common/xmcd/flexspi_ram_simplified.json + full: + reg_spec: ../../common/xmcd/flexspi_ram_full.json + semc_sdram: + simplified: + reg_spec: ../../common/xmcd/semc_sdram_simplified.json + full: + reg_spec: ../../common/xmcd/semc_sdram_full.json + fuses: + _name: "XMCD CRC" + fuse23: + fuse23-bit-14: 1 # XMC_CRC32_CHECK_EN + fuse73: "__crc" # XMC_CRC32_CHECK_SUM + + + # ======== IEE section ======== + iee: + has_kek_fuses: True + additional_template: ["ibkek", "key_blobs"] + additional_template_text: | + Refer to the Security Reference Manual for RT117x and Application Note 13250 for more information. + In case blank string is used, the output is not generated. If the filename contains directory, + the output folder will be ignored and the full path from filename will be used. + + fuses: + _name: Configuration of fuses for IEE + _desc: WARNING!! Check SRM and set all desired bitfields for boot configuration + _no_verify: True + iee_user_key1: __ibkek1 # USER KEY 1 (IEE KEK) + iee_user_key2: __ibkek2 # USER KEY 2 (IEE KEK) + fuse14: + fuse14-bit-8: 1 # Load IEE Key bitfield + fuse23: + fuse23-bit-12: 1 # Encrypt XIP engine + fuse9: + fuse9-bit-2: 1 + fuse9-bit-3: 1 + fuse20: 0x0000_0002 # BOOT CFG fuse! + + # ======== OTFAD section ======== + otfad: + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + + fuses_1: # Fuses for OTFAD1 + _name: Configuration of fuses for OTFAD1 + _no_verify: True + fuse71: # OTFAD CFG Fuse + fuse71-bit-0: __scramble_enabled # OTFAD enable scrambling + fuse133: __key_scramble_align # OTFAD scramble align + fuse132: __key_scramble_mask # OTFAD Scramble Key + otfad_key: __kek # OTFAD Key + + fuses_2: # Fuses for OTFAD2 + _name: Configuration of fuses for OTFAD2 + _no_verify: True + fuse71: # OTFAD CFG Fuse + fuse71-bit-4: __scramble_enabled # OTFAD enable scrambling + fuse135: __key_scramble_align # OTFAD scramble align + fuse134: __key_scramble_mask # OTFAD Scramble Key + otfad_key: __kek # OTFAD Key + + additional_template: ["otfad_scramble"] + additional_template_text: | + Is important to use physical addresses (non-secure) in settings of OTFAD to proper run the decryption on device. + + The fuse word 0x47 on address 0xC70 uses error-correcting codes. + The fuse word can only be written one time, so you must set all of the desired bits within the word at the same time. + Refer to the SRM to get familiar with the functionality of all bitfields. + The ENCRYPT_XIP_EN fuse is part of the BOOT_CFG1 fuse. If this bit is set, all BOOT_CFG fuses must be configured accordingly. + The encrypted XiP can be also enabled by the BOOT_CFG pin + + It is recommended to set the USER_KEY5_RLOCK and OTFAD1/2_KEY_SEL_LOCK fuses for production to protect sensitive data stored in the USER_KEY5 fuse (if used) and to prevent a modification of the OTFAD key selection by malicious software. + + In case blank string is used, the output is not generated. If the filename contains directory, + the output folder will be ignored and the full path from filename will be used. + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + hab_container: 0x0 + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + keystore: 0x0800 + hab_container: 0x1000 + flexspi_nand: + segments: + hab_container: 0x400 + semc_nand: + segments: + hab_container: 0x400 + sd: + segments: + hab_container: 0x400 + mmc: + segments: + hab_container: 0x400 + emmc: + segments: + hab_container: 0x400 + recovery_spi_hab: + segments: + hab_container: 0x400 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [1, 2] + flexspi_nand: + instances: [1, 2] + semc_nor: + instances: [0] # probably not supported in latest version of Flashloader + semc_nand: + instances: [0] # probably not supported in latest version of Flashloader + sd: + instances: [1, 2] + mmc: + instances: [1, 2] + emmc: + instances: [1, 2] + spi_nor: + instances: [1, 2, 3, 4] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fcb_flexspi_nor.json new file mode 100644 index 0000000..27770cf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fcb_flexspi_nor.json @@ -0,0 +1,25568 @@ +{ + "cpu": "MIMXRT1166", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_10", + "description": " Reserved for future use", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fuses.json new file mode 100644 index 0000000..e453f10 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1166/fuses.json @@ -0,0 +1,5393 @@ +{ + "cpu": "mimxrt1166", + "groups": [ + { + "group": { + "name": "Reserved 0x800-0x830", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved0", + "name": "Reserved 0x800", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0800", + "index_int": "0", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1", + "name": "Reserved 0x810", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0810", + "index_int": "0x0001", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved2", + "name": "Reserved 0x820", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0820", + "index_int": "0x0002", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved3", + "name": "Reserved 0x830", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0830", + "index_int": "0x0003", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_PARAM_CFG", + "description": "Fuses 0x840-0x860: Boot param config fuse registers" + }, + "registers": [ + { + "id": "fuse4", + "name": "BOOT_PARAM_CFG0", + "description": "Fuse BOOT_PARAM_CFG0", + "offset_int": "0x0840", + "index_int": "0x0004", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-2", + "name": "MECC_ENABLE", + "description": "Enable memory ECC", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1, + "id": "fuse4-bit-3", + "name": "XECC_ENABLE", + "description": "Enable external memory ECC", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse4-bit-15", + "name": "FLEXRAMECC_ENABLE", + "description": "Enable FlexRAM ECC", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved5", + "name": "Reserved 0x850", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0850", + "index_int": "0x0005", + "is_reserved": true, + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse6", + "name": "BOOT_PARAM_CFG1", + "description": "Fuse BOOT_PARAM_CFG1", + "offset_int": "0x0860", + "index_int": "0x0006", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse6-bit-6", + "name": "PUF_ENABLE", + "description": "Enable PUF IP", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1, + "id": "fuse6-bit-7", + "name": "UDF_ENABLE", + "description": "Enable UDF IP", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "DEBUG_CFG", + "description": "Fuse 0x870: Debug config fuse register" + }, + "registers": [ + { + "id": "fuse7", + "name": "DEBUG_CFG", + "description": "Fuse DEBUG_CFG", + "offset_int": "0x0870", + "index_int": "0x0007", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1, + "id": "fuse7-bit-0", + "name": "M7_DEBUG_DISABLE", + "description": "Disable ability to debug M7", + "values": [ + { + "name": "enabled", + "value": 0, + "description": "enabled" + }, + { + "name": "disabled", + "value": 1, + "description": "disabled" + } + ] + }, + { + "width": 1, + "id": "fuse7-bit-1", + "name": "M4_DEBUG_DISABLE", + "description": "Disable ability to debug M4", + "values": [ + { + "name": "enabled", + "value": 0, + "description": "enabled" + }, + { + "name": "disabled", + "value": 1, + "description": "disabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse7-bit-4", + "name": "FBB_DISABLE", + "description": "Disable FBB\n0 - FBB enable\n1 - FBB disable (for FF samples in RT1170 parts)", + "values": [ + { + "name": "enabled", + "value": 0, + "description": "enabled" + }, + { + "name": "disabled", + "value": 1, + "description": "disabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Locks", + "description": "Fuses 0x880-0x890: Lock bits allowing to lock access to specified fuse registers" + }, + "registers": [ + { + "id": "fuse8", + "name": "LOCK_CFG0", + "description": "Fuse LOCK_CFG0", + "offset_int": "0x0880", + "index_int": "0x0008", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4 + }, + { + "width": 4, + "id": "fuse8-bits-11-14", + "name": "JTAG_RESP_RLOCK[3:0]", + "description": "JTAG_RESP_RLOCK[0]: Read lock of JTAG_RESP[31:0]\nJTAG_RESP_RLOCK[1]: Read lock of JTAG_RESP[63:32]\nJTAG_RESP_RLOCK[2]: Read lock of JTAG_RESP[95:64]\nJTAG_RESP_RLOCK[3]: Read lock of JTAG_RESP[127:96]", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 15, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse9", + "name": "LOCK_CFG1", + "description": "Fuse LOCK_CFG1", + "offset_int": "0x0890", + "index_int": "0x0009", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse9-bit-2", + "name": "USER_KEY1_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-3", + "name": "USER_KEY2_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-4", + "name": "USER_KEY3_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-5", + "name": "USER_KEY4_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-6", + "name": "USER_KEY5_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse9-bit-10", + "name": "GP1_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-11", + "name": "GP2_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-12", + "name": "GP3_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-13", + "name": "GP4_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-14", + "name": "GP5_RLOCK", + "description": "Read Lock", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock (The controlled field can be read in the corresponded IIM register)" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock (The controlled field can't be read in the corresponded IIM register)" + } + ] + }, + { + "width": 1 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x8A0-0x8C0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved10", + "name": "Reserved 0x8A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x08A0", + "index_int": "0x000A", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved11", + "name": "Reserved 0x8B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x08B0", + "index_int": "0x000B", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved12", + "name": "Reserved 0x8C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x08C0", + "index_int": "0x000C", + "is_reserved": true, + "bitfields": [ + { + "width": 16 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Security config", + "description": "Fuses 0x8D0-0x8E0: Security config fuse registers" + }, + "registers": [ + { + "id": "fuse13", + "name": "SRK_REVOKE", + "description": "Fuse SRK_REVOKE", + "offset_int": "0x08D0", + "index_int": "0x000D", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 2 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse13-bits-4-7", + "name": "FIELD_RETURN", + "description": "Configure device for field return testing. Fuse burning is protected by CSF command, with proper parameter passed. Write / OP protected by FIELD_RETURN_LOCK bit in control register.", + "values": [ + { + "name": "0000", + "value": 0, + "description": "Device is in functional / secure mode." + }, + { + "name": "1010", + "value": 10, + "description": "Device is open for 'field-return' testing." + } + ] + }, + { + "width": 1, + "id": "fuse13-bit-8", + "name": "SRK_REVOKE[0]", + "description": "SRK key 1 revocation ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse13-bit-9", + "name": "SRK_REVOKE[1]", + "description": "SRK key 2 revocation ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse13-bit-10", + "name": "SRK_REVOKE[2]", + "description": "SRK key 3 revocation ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1, + "id": "fuse13-bit-11", + "name": "SRK_REVOKE[3]", + "description": "SRK key 4 revocation ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Revoke Key", + "value": 1, + "description": "Revoke Key" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse14", + "name": "SEC_BOOT_CFG0", + "description": "Fuse SEC_BOOT_CFG0", + "offset_int": "0x08E0", + "index_int": "0x000E", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse14-bit-1", + "name": "SEC_CONFIG[0]", + "description": "Security Configuration Mode, and block of debugging of security HW, by JTAG" + }, + { + "width": 1, + "id": "fuse14-bit-2", + "name": "MASTER_KEY_SEL", + "description": "Master Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "select scrambled OTPMK as master key" + }, + { + "name": "1", + "value": 1, + "description": "select PUF key[0] as master key" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-3", + "name": "MASTER_KEY_SEL_LOCK", + "description": "Lock Master Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "Software change Master Key selection allowed" + }, + { + "name": "1", + "value": 1, + "description": "Software change Master Key selection not allowed" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-4", + "name": "OTFAD1_KEY_SEL", + "description": "OTFAD1 Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "select USER_KEY5 as OTFAD1 Key" + }, + { + "name": "1", + "value": 1, + "description": "select PUF key[1] low 128 bt as OTFAD1 key" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-5", + "name": "OTFAD1_KEY_SEL_LOCK", + "description": "Lock OTFAD1 Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "Software change OTFAD1 Key selection allowed" + }, + { + "name": "1", + "value": 1, + "description": "Software change OTFAD1 Key selection not allowed" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-6", + "name": "OTFAD2_KEY_SEL", + "description": "OTFAD2 Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "select USER_KEY5 as OTFAD2 Key" + }, + { + "name": "1", + "value": 1, + "description": "select PUF key[1] low 128 bt as OTFAD2 key" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-7", + "name": "OTFAD2_KEY_SEL_LOCK", + "description": "Lock OTFAD2 Key selection", + "values": [ + { + "name": "0", + "value": 0, + "description": "Software change OTFAD2 Key selection allowed" + }, + { + "name": "1", + "value": 1, + "description": "Software change OTFAD2 Key selection not allowed" + } + ] + }, + { + "width": 1, + "id": "fuse14-bit-8", + "name": "LOAD_IEE_KEY", + "description": "Load IEE Key on start up", + "values": [ + { + "name": "0", + "value": 0, + "description": "not Load IEE key after reset" + }, + { + "name": "1", + "value": 1, + "description": "Load IEE key after reset" + } + ] + }, + { + "width": 1 + }, + { + "width": 6 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x8F0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved15", + "name": "Reserved 0x8F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x08F0", + "index_int": "0x000F", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "IDs", + "description": "Fuses 0x900-0x930: Different identifiers" + }, + "registers": [ + { + "id": "fuse16", + "name": "LOT_NO_ENC1", + "description": "FSL-wide unique, encoded LOT ID STD II/JTAG CHALLENGE/Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[42:11]" + ], + "offset_int": "0x0900", + "index_int": "0x0010", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse16-bits-0-31", + "name": "LOT_NO_ENC[42:11]", + "description": "FSL-wide unique, encoded LOT ID STD II/JTAG CHALLENGE/Unique ID" + } + ] + }, + { + "id": "fuse17", + "name": "LOT_NO_ENC0_WAFER_COORD", + "description": "FSL-wide unique, encoded LOT ID STD II/JTAG CHALLENGE/Unique ID", + "deprecated_names": [ + "LOT_NO_ENC[10:0]" + ], + "offset_int": "0x0910", + "index_int": "0x0011", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 11, + "id": "fuse17-bits-0-10", + "name": "LOT_NO_ENC[10:0]", + "description": "FSL-wide unique, encoded LOT ID STD II/JTAG CHALLENGE/Unique ID" + }, + { + "width": 5, + "id": "fuse17-bits-11-15", + "name": "WAFER_NO[4:0]", + "description": "The wafer number of the wafer on which the device was fabricated/JTAG CHALLENGE/Unique ID" + }, + { + "width": 8, + "id": "fuse17-bits-16-23", + "name": "DIE-Y-CORDINATE[7:0]", + "description": "The Y-coordinate of the die location on the wafer/JTAG CHALLENGE/Unique ID" + }, + { + "width": 8, + "id": "fuse17-bits-24-31", + "name": "DIE-X-CORDINATE[7:0]", + "description": "The X-coordinate of the die location on the wafer/JTAG CHALLENGE/Unique ID" + } + ] + }, + { + "id": "fuse18", + "name": "SI_REV", + "description": "Fuse SI_REV", + "offset_int": "0x0920", + "index_int": "0x0012", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse18-bits-24-27", + "name": "SI_REV[3:0]", + "description": "Silicon Revision number." + }, + { + "width": 4 + } + ] + }, + { + "id": "fuse19", + "name": "SPEED_GRADING", + "description": "Fuse SPEED_GRADING", + "offset_int": "0x0930", + "index_int": "0x0013", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 2, + "id": "fuse19-bits-0-1", + "name": "SPEED_GRADING[1:0]", + "description": "Burned by tester program, for indicating M7 core speed" + }, + { + "width": 2, + "id": "fuse19-bits-2-3", + "name": "SPEED_GRADING[3:2]", + "description": "Burned by tester program, for indicating M4 core speed" + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 24 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "Fuses 0x940-0x950: Boot config fuse registers" + }, + "registers": [ + { + "id": "fuse20", + "name": "BOOT_CFG0", + "description": "Fuse BOOT_CFG0", + "offset_int": "0x0940", + "index_int": "0x0014", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 8, + "id": "fuse20-bits-0-7", + "name": "BOOT_CFG1[7:0]", + "description": "See Boot sheet" + }, + { + "width": 8, + "id": "fuse20-bits-8-15", + "name": "BOOT_CFG2[7:0]", + "description": "See Boot sheet" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse21", + "name": "BOOT_CFG1", + "description": "Fuse BOOT_CFG1", + "offset_int": "0x0950", + "index_int": "0x0015", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 8, + "id": "fuse21-bits-0-7", + "name": "BOOT_CFG3[7:0]", + "description": "See Boot sheet" + }, + { + "width": 8, + "id": "fuse21-bits-8-15", + "name": "BOOT_CFG4[7:0]", + "description": "See Boot sheet" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "SEC_BOOT_CFG1", + "description": "Fuse 0x960: Security boot config 1 fuse register" + }, + "registers": [ + { + "id": "fuse22", + "name": "SEC_BOOT_CFG1", + "description": "Fuse SEC_BOOT_CFG1", + "offset_int": "0x0960", + "index_int": "0x0016", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "fuse22-bit-1", + "name": "SEC_CONFIG[1]", + "description": "Security Configuration (with SEC_CONFIG[0])", + "values": [ + { + "name": "Open", + "value": 0, + "description": "Open (allows any program image, even if the authentication fails)" + }, + { + "name": "Closed", + "value": 1, + "description": "Closed (The program image executes only if authenticated)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse22-bit-4", + "name": "BT_FUSE_SEL", + "description": "Determines, whether using fuses for boot configuration, or GPIO /Serial loader", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-5", + "name": "FORCE_COLD_BOOT", + "description": "Force cold boot when A9 core come out of reset. Reflected in SBMR reg of SRC", + "values": [ + { + "name": "0", + "value": 0, + "description": "Default behavior equivalent to the rest of the i.MX6 family allowing a fast recovery from low power modes. That is, the ROM is allowed to jump to the address previously programmed in the SRC persistent register." + }, + { + "name": "1", + "value": 1, + "description": "Fast recovery path in the ROM is not allowed and a cold boot is always performed. Customers wanting a higher level of security should burn this fuse." + } + ] + }, + { + "width": 2, + "id": "fuse22-bits-6-7", + "name": "JTAG_SMODE[1:0]", + "description": "JTAG Security Mode. Controls the security mode of the JTAG debug interface", + "values": [ + { + "name": "00", + "value": 0, + "description": "JTAG enable mode" + }, + { + "name": "01", + "value": 1, + "description": "Secure JTAG mode" + }, + { + "name": "11", + "value": 3, + "description": "No debug mode" + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-8", + "name": "KTE", + "description": "Kill Trace Enable. Enables tracing capability on ETM, and other modules", + "values": [ + { + "name": "0", + "value": 0, + "description": "Bus tracing is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)" + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-9", + "name": "JTAG_HEO", + "description": "JTAG HAB Enable Override. Disallows HAB JTAG enabling. The HAB may normally enable JTAG debugging by means of the HAB_JDE-bit in the OCOTP SCS register. The JTAG_HEO-bit can override this behavior", + "values": [ + { + "name": "0", + "value": 0, + "description": "HAB may enable JTAG debug access" + }, + { + "name": "1", + "value": 1, + "description": "HAB JTAG enable is overridden (HAB may not enable JTAG debug access)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse22-bit-11", + "name": "JTAG_DISABLE", + "description": "Disable/Enable the Secure JTAG Controller module. This fuse is used to create highest JTAG security level, where JTAG is totally blocked.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Secure JTAG Controller is enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "Secure JTAG Controller is disabled" + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-12", + "name": "BT_CORE_SEL", + "description": "Boot Core Selection.\nOnly applied to multi-core part.", + "values": [ + { + "name": "boot from M7", + "value": 0, + "description": "boot from M7" + }, + { + "name": "boot from M4", + "value": 1, + "description": "boot from M4" + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_PARAM", + "description": "Fuses 0x970-0x9B0: Boot parameters fuse registers" + }, + "registers": [ + { + "id": "fuse23", + "name": "BOOT_PARAM1", + "description": "Fuse BOOT_PARAM1", + "offset_int": "0x0970", + "index_int": "0x0017", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1, + "id": "fuse23-bit-0", + "name": "eMMC 5.0 - RESET TO PRE-IDLE STATE", + "description": "eMMC 5.0 - RESET TO PRE-IDLE STATE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-1", + "name": "SD2_RST_POLARITY_SELECTION", + "description": "SD2_RST_POLARITY_SELECTION", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-2", + "name": "SD1_RST_POLARITY_SELECTION", + "description": "SD1_RST_POLARITY_SELECTION", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-3", + "name": "SD1_VOLTAGE_SELECTION", + "description": "SD1_VOLTAGE_SELECTION", + "values": [ + { + "name": "3.3V", + "value": 0, + "description": "3.3V" + }, + { + "name": "1.8V", + "value": 1, + "description": "1.8V" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-4", + "name": "USDHC_CMD_IOMUX_SION_BIT_DISABLE", + "description": "USDHC_CMD_IOMUX_SION_BIT_DISABLE", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-5", + "name": "PWR_STABLE_CYCLE_SELECTION", + "description": "PWR_STABLE_CYCLE_SELECTION", + "values": [ + { + "name": "5 ms", + "value": 0, + "description": "5 ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse23-bits-6-7", + "name": "SD_PWR_CYCLE_SELECTION", + "description": "SD_PWR_CYCLE_SELECTION", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse23-bits-8-9", + "name": "SDMMC_DLL_DLY Calibration Step", + "description": "SDMMC_DLL_DLY Calibration Step", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + }, + { + "name": "2", + "value": 1, + "description": "2" + }, + { + "name": "4", + "value": 2, + "description": "4" + }, + { + "name": "6", + "value": 3, + "description": "6" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-10", + "name": "DLL_OVERRIDE", + "description": "DLL_OVERRIDE", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode for SD/eMMC (delay 10, step 2)" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode for SD/eMMC" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-11", + "name": "USB SDP DISABLE", + "description": "USB SDP DISABLE", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-12", + "name": "ENCRYPT_XIP_ENGINE", + "description": "ENCRYPT_XIP_ENGINE", + "values": [ + { + "name": "OTFAD", + "value": 0, + "description": "OTFAD (128bit AES-CTR)" + }, + { + "name": "IEE", + "value": 1, + "description": "IEE (128/256bit AES-CTR, 256/512bit AES-XTS)" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-13", + "name": "PUF Zeroize", + "description": "PUF Zeroize", + "values": [ + { + "name": "0", + "value": 0, + "description": "not zeroize PUF" + }, + { + "name": "1", + "value": 1, + "description": "zeroize PUF after boot" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-14", + "name": "XMC_CHK_EN", + "description": "XMC_CHK_EN", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "XMC Integrity check is not enabled" + }, + { + "name": "Enable", + "value": 1, + "description": "XMC Integrity Check is enabled" + } + ] + }, + { + "width": 1, + "id": "fuse23-bit-15", + "name": "SDMMC_MFG_MODE_DISABLE", + "description": "SDMMC_MFG_MODE_DISABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse24", + "name": "BOOT_PARAM2", + "description": "Fuse BOOT_PARAM2", + "offset_int": "0x0980", + "index_int": "0x0018", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse24-bits-0-15", + "name": "BOOT_PARM2", + "description": "Boot parameters. See Boot sheet." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_PARAM3", + "description": "Fuse BOOT_PARAM3", + "offset_int": "0x0990", + "index_int": "0x0019", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse25-bits-0-15", + "name": "BOOT_PARM3", + "description": "Boot parameters. See Boot sheet." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_PARAM4", + "description": "Fuse BOOT_PARAM4", + "offset_int": "0x09A0", + "index_int": "0x001A", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1, + "id": "fuse26-bit-0", + "name": "SDP_DISABLE", + "description": "SDP_DISABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-1", + "name": "UART_SDP_DISABLE", + "description": "UART_SDP_DISABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-2", + "name": "OSC_REF_FREQ", + "description": "OSC_REF_FREQ", + "values": [ + { + "name": "24MHz", + "value": 0, + "description": "24MHz" + }, + { + "name": "19.2MHz", + "value": 1, + "description": "19.2MHz" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-3", + "name": "BOOT_FREQ", + "description": "BOOT_FREQ", + "values": [ + { + "name": "0", + "value": 0, + "description": "M7: 400MHz (M4: 200MHz)" + }, + { + "name": "1", + "value": 1, + "description": "M7: 700MHz (M4: 240MHz)" + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-4-5", + "name": "LPB_BOOT", + "description": "Divide (Core / Bus) based on Boot Frequencies", + "values": [ + { + "name": "Div by 1", + "value": 0, + "description": "Div by 1" + }, + { + "name": "Div by 2", + "value": 1, + "description": "Div by 2" + }, + { + "name": "Div by 4", + "value": 2, + "description": "Div by 4" + }, + { + "name": "Div by 8", + "value": 3, + "description": "Div by 8" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-6", + "name": "D_CACHE_DISABLE", + "description": "D_CACHE_DISABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-7", + "name": "I_CACHE_DISABLE", + "description": "I_CACHE_DISABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2, + "id": "fuse26-bits-8-9", + "name": "FLASH_CONNECTION_SEL", + "description": "FLASH_CONNECTION_SEL", + "values": [ + { + "name": "0", + "value": 0, + "description": "Connected via PORTA" + }, + { + "name": "1", + "value": 1, + "description": "Parallel Mode" + }, + { + "name": "2", + "value": 2, + "description": "Connected via PORTB" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-10", + "name": "FLEXSPI_PIN_GROUP_SEL", + "description": "FLEXSPI_PIN_GROUP_SEL", + "values": [ + { + "name": "0", + "value": 0, + "description": "Primary Group" + }, + { + "name": "1", + "value": 1, + "description": "Secondary Group" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-11", + "name": "FLEXSPI_DQS_PIN_SEL", + "description": "FLEXSPI_DQS_PIN_SEL", + "values": [ + { + "name": "0", + "value": 0, + "description": "Primary DQS pin" + }, + { + "name": "1", + "value": 1, + "description": "Secondary DQS Pin" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-12", + "name": "Wipe Invalid Image", + "description": "Wipe Invalid Image", + "values": [ + { + "name": "Do not wipe", + "value": 0, + "description": "Do not wipe out invalid image from internal RAM" + }, + { + "name": "Wipe", + "value": 1, + "description": "Wipe" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-13", + "name": "ENABLE_SECURE_CPY", + "description": "ENABLE_SECURE_CPY", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-14", + "name": "FORCE_INTERNAL_BOOT", + "description": "FORCE_INTERNAL_BOOT", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-15", + "name": "WDOG_ENABLE", + "description": "WDOG_ENABLE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_PARAM5", + "description": "Fuse BOOT_PARAM5", + "offset_int": "0x09B0", + "index_int": "0x001B", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 3, + "id": "fuse27-bits-0-2", + "name": "WDOG Timeout Select", + "description": "WDOG Timeout Select", + "values": [ + { + "name": "64s", + "value": 0, + "description": "64s" + }, + { + "name": "32s", + "value": 1, + "description": "32s" + }, + { + "name": "16s", + "value": 2, + "description": "16s" + }, + { + "name": "8s", + "value": 3, + "description": "8s" + }, + { + "name": "4s", + "value": 4, + "description": "4s" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-3-4", + "name": "WDOG_B_PIN_SEL", + "description": "WDOG_B_PIN_SEL", + "values": [ + { + "name": "GPIO_DISP_B2_00", + "value": 0, + "description": "GPIO_DISP_B2_00" + }, + { + "name": "GPIO_DISP_B2_15", + "value": 1, + "description": "GPIO_DISP_B2_15" + }, + { + "name": "GPIO_AD_04", + "value": 2, + "description": "GPIO_AD_04" + }, + { + "name": "GPIO_EMC_B2_18", + "value": 3, + "description": "GPIO_EMC_B2_18" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-5", + "name": "WDOG_B_PIN_EN", + "description": "WDOG_B_PIN_EN", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse27-bits-8-9", + "name": "DICE_EN", + "description": "DICE_EN", + "values": [ + { + "name": "0", + "value": 0, + "description": "DICE Disabled - Do not perform DICE CDI calculation" + }, + { + "name": "1", + "value": 1, + "description": "DICE Enabled. DICE CDI is calculated." + }, + { + "name": "2", + "value": 2, + "description": "DICE Enabled. DICE CDI is calculated." + }, + { + "name": "3", + "value": 3, + "description": "DICE Enabled. DICE CDI is calculated." + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-10-11", + "name": "DICE_INC_NXP_CFG", + "description": "DICE_INC_NXP_CFG", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "Not included" + }, + { + "name": "1", + "value": 1, + "description": "NXP area included in CDI - 0x840-0x870 + 0x1100-12F0" + }, + { + "name": "2", + "value": 2, + "description": "NXP area included in CDI - 0x840-0x870 + 0x1100-12F0" + }, + { + "name": "3", + "value": 3, + "description": "NXP area included in CDI - 0x840-0x870 + 0x1100-12F0" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-12-13", + "name": "DICE_CUST_CFG", + "description": "DICE_CUST_CFG", + "values": [ + { + "name": "Not included", + "value": 0, + "description": "Not included" + }, + { + "name": "1", + "value": 1, + "description": "customer area included in CDI - 0x8E0 + 0x940-0x9B0 + 0xB00-0xB70" + }, + { + "name": "2", + "value": 2, + "description": "customer area included in CDI - 0x8E0 + 0x940-0x9B0 + 0xB00-0xB70" + }, + { + "name": "3", + "value": 3, + "description": "customer area included in CDI - 0x8E0 + 0x940-0x9B0 + 0xB00-0xB70" + } + ] + }, + { + "width": 1 + }, + { + "width": 1 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0x9C0-0xA70", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved28", + "name": "Reserved 0x9C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x09C0", + "index_int": "0x001C", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved29", + "name": "Reserved 0x9D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x09D0", + "index_int": "0x001D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved30", + "name": "Reserved 0x9E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x09E0", + "index_int": "0x001E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved31", + "name": "Reserved 0x9F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x09F0", + "index_int": "0x001F", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved32", + "name": "Reserved 0xA00", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A00", + "index_int": "0x0020", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved33", + "name": "Reserved 0xA10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A10", + "index_int": "0x0021", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved34", + "name": "Reserved 0xA20", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A20", + "index_int": "0x0022", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved35", + "name": "Reserved 0xA30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A30", + "index_int": "0x0023", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved36", + "name": "Reserved 0xA40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A40", + "index_int": "0x0024", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved37", + "name": "Reserved 0xA50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A50", + "index_int": "0x0025", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved38", + "name": "Reserved 0xA60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A60", + "index_int": "0x0026", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved39", + "name": "Reserved 0xA70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0A70", + "index_int": "0x0027", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "MAC", + "description": "Fuses 0xA80-0xAD0: Ethernet MAC Address" + }, + "registers": [ + { + "id": "fuse40", + "name": "MAC1_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[47:16]" + ], + "offset_int": "0x0A80", + "index_int": "0x0028", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse40-bits-0-31", + "name": "MAC1_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse41", + "name": "MAC1_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC1_ADDR[15:0]" + ], + "offset_int": "0x0A90", + "index_int": "0x0029", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse41-bits-0-15", + "name": "MAC1_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse42", + "name": "MAC2_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[47:16]" + ], + "offset_int": "0x0AA0", + "index_int": "0x002A", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse42-bits-0-31", + "name": "MAC2_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse43", + "name": "MAC2_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC2_ADDR[15:0]" + ], + "offset_int": "0x0AB0", + "index_int": "0x002B", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse43-bits-0-15", + "name": "MAC2_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse44", + "name": "MAC3_ADDR1", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC3_ADDR[47:16]" + ], + "offset_int": "0x0AC0", + "index_int": "0x002C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse44-bits-0-31", + "name": "MAC3_ADDR[47:16]", + "description": "Ethernet MAC Address" + } + ] + }, + { + "id": "fuse45", + "name": "MAC3_ADDR0", + "description": "Ethernet MAC Address", + "deprecated_names": [ + "MAC3_ADDR[15:0]" + ], + "offset_int": "0x0AD0", + "index_int": "0x002D", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse45-bits-0-15", + "name": "MAC3_ADDR[15:0]", + "description": "Ethernet MAC Address" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "USB", + "description": "Fuse 0xAE0: USB fuse register" + }, + "registers": [ + { + "id": "fuse46", + "name": "USB", + "description": "Fuse USB", + "offset_int": "0x0AE0", + "index_int": "0x002E", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse46-bits-0-15", + "name": "USB_VID[15:0]", + "description": "USB VID" + }, + { + "width": 16, + "id": "fuse46-bits-16-31", + "name": "USB_PID[15:0]", + "description": "USB PID" + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 0xAF0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved47", + "name": "Reserved 0xAF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0AF0", + "index_int": "0x002F", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 24 + } + ] + } + ] + }, + { + "group": { + "name": "M7_SRK_HASH", + "description": "Fuses 0xB00-0xB70: SRK key for M7 fuse registers" + }, + "registers": [ + { + "id": "fuse48", + "name": "M7_SRK_HASH[255:224]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B00", + "index_int": "0x0030", + "individual_write_lock": "implicit" + }, + { + "id": "fuse49", + "name": "M7_SRK_HASH[223:192]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B10", + "index_int": "0x0031", + "individual_write_lock": "implicit" + }, + { + "id": "fuse50", + "name": "M7_SRK_HASH[191:160]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B20", + "index_int": "0x0032", + "individual_write_lock": "implicit" + }, + { + "id": "fuse51", + "name": "M7_SRK_HASH[159:128]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B30", + "index_int": "0x0033", + "individual_write_lock": "implicit" + }, + { + "id": "fuse52", + "name": "M7_SRK_HASH[127:96]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B40", + "index_int": "0x0034", + "individual_write_lock": "implicit" + }, + { + "id": "fuse53", + "name": "M7_SRK_HASH[95:64]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B50", + "index_int": "0x0035", + "individual_write_lock": "implicit" + }, + { + "id": "fuse54", + "name": "M7_SRK_HASH[63:32]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B60", + "index_int": "0x0036", + "individual_write_lock": "implicit" + }, + { + "id": "fuse55", + "name": "M7_SRK_HASH[31:0]", + "description": "SRK key for M7, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B70", + "index_int": "0x0037", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "M4_SRK_HASH", + "description": "Fuses 0xB80-0xBF0: SRK Key for M4 fuse registers" + }, + "registers": [ + { + "id": "fuse56", + "name": "M4_SRK_HASH[255:224]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B80", + "index_int": "0x0038", + "individual_write_lock": "implicit" + }, + { + "id": "fuse57", + "name": "M4_SRK_HASH[223:192]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0B90", + "index_int": "0x0039", + "individual_write_lock": "implicit" + }, + { + "id": "fuse58", + "name": "M4_SRK_HASH[191:160]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BA0", + "index_int": "0x003A", + "individual_write_lock": "implicit" + }, + { + "id": "fuse59", + "name": "M4_SRK_HASH[159:128]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BB0", + "index_int": "0x003B", + "individual_write_lock": "implicit" + }, + { + "id": "fuse60", + "name": "M4_SRK_HASH[127:96]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BC0", + "index_int": "0x003C", + "individual_write_lock": "implicit" + }, + { + "id": "fuse61", + "name": "M4_SRK_HASH[95:64]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BD0", + "index_int": "0x003D", + "individual_write_lock": "implicit" + }, + { + "id": "fuse62", + "name": "M4_SRK_HASH[63:32]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BE0", + "index_int": "0x003E", + "individual_write_lock": "implicit" + }, + { + "id": "fuse63", + "name": "M4_SRK_HASH[31:0]", + "description": "SRK key for M4, no HW visible lines. NO HW Visible signals available", + "offset_int": "0x0BF0", + "index_int": "0x003F", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "Reserved 0xC00-0xC60", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved64", + "name": "Reserved 0xC00", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C00", + "index_int": "0x0040", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved65", + "name": "Reserved 0xC10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C10", + "index_int": "0x0041", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved66", + "name": "Reserved 0xC20", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C20", + "index_int": "0x0042", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved67", + "name": "Reserved 0xC30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C30", + "index_int": "0x0043", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved68", + "name": "Reserved 0xC40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C40", + "index_int": "0x0044", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved69", + "name": "Reserved 0xC50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C50", + "index_int": "0x0045", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved70", + "name": "Reserved 0xC60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0C60", + "index_int": "0x0046", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_CONFIG_MISC", + "description": "Fuses 0xC70-0xCA0: Boot config misc fuse registers" + }, + "registers": [ + { + "id": "fuse71", + "name": "BOOT_CONFIG_MISC1", + "description": "Fuse BOOT_CONFIG_MISC1", + "offset_int": "0x0C70", + "index_int": "0x0047", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 1, + "id": "fuse71-bit-0", + "name": "OTFAD1_SCRAMBLE_EN", + "description": "Enable OTFAD1's kek scramble", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse71-bit-2", + "name": "OTFAD1_RESTRICT_IPS", + "description": "Restrict OTFAD1's IPS bus", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse71-bit-4", + "name": "OTFAD2_SCRAMBLE_EN", + "description": "Enable OTFAD2's kek scramble", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse71-bit-6", + "name": "OTFAD2_RESTRICT_IPS", + "description": "Restrict OTFAD2's IPS bus", + "values": [ + { + "name": "disabled", + "value": 0, + "description": "disabled" + }, + { + "name": "enabled", + "value": 1, + "description": "enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 8, + "id": "fuse71-bits-8-15", + "name": "BOOT_CONFIG_MISC1[7:0]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "deprecated_names": [ + "BOOT_CONFIG_MISC1[15:8]" + ] + }, + { + "width": 6, + "id": "fuse71-bits-16-21", + "name": "Default_FlexRAM_Part[5:0]", + "description": "Default FlexRAM RAM bank partitioning" + }, + { + "width": 10, + "id": "fuse71-bits-22-31", + "name": "BOOT_CONFIG_MISC1[17:8]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "deprecated_names": [ + "BOOT_CONFIG_MISC1[31:22]" + ] + } + ] + }, + { + "id": "fuse72", + "name": "BOOT_CONFIG_MISC2[31:0]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x0C80", + "index_int": "0x0048", + "individual_write_lock": "implicit" + }, + { + "id": "fuse73", + "name": "BOOT_CONFIG_MISC3[31:0]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x0C90", + "index_int": "0x0049", + "individual_write_lock": "implicit" + }, + { + "id": "fuse74", + "name": "BOOT_CONFIG_MISC4[31:0]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x0CA0", + "index_int": "0x004A", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "JTAG_RESP", + "description": "Fuses 0xCB0-0xCE0: JTAG Response fuse registers" + }, + "registers": [ + { + "id": "fuse75", + "name": "JTAG_RESP[127:96]", + "description": "JTAG Response", + "offset_int": "0x0CB0", + "index_int": "0x004B", + "individual_write_lock": "implicit" + }, + { + "id": "fuse76", + "name": "JTAG_RESP[95:64]", + "description": "JTAG Response", + "offset_int": "0x0CC0", + "index_int": "0x004C", + "individual_write_lock": "implicit" + }, + { + "id": "fuse77", + "name": "JTAG_RESP[63:32]", + "description": "JTAG Response", + "offset_int": "0x0CD0", + "index_int": "0x004D", + "individual_write_lock": "implicit" + }, + { + "id": "fuse78", + "name": "JTAG_RESP[31:0]", + "description": "JTAG Response", + "offset_int": "0x0CE0", + "index_int": "0x004E", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "Reserved 0xCF0-0xDF0", + "description": "Reserved for future use." + }, + "registers": [ + { + "id": "Reserved79", + "name": "Reserved 0xCF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0CF0", + "index_int": "0x004F", + "is_reserved": true, + "bitfields": [ + { + "width": 8 + }, + { + "width": 8 + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved80", + "name": "Reserved 0xD00", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D00", + "index_int": "0x0050", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved81", + "name": "Reserved 0xD10", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D10", + "index_int": "0x0051", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved82", + "name": "Reserved 0xD20", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D20", + "index_int": "0x0052", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved83", + "name": "Reserved 0xD30", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D30", + "index_int": "0x0053", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved84", + "name": "Reserved 0xD40", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D40", + "index_int": "0x0054", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved85", + "name": "Reserved 0xD50", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D50", + "index_int": "0x0055", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved86", + "name": "Reserved 0xD60", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D60", + "index_int": "0x0056", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved87", + "name": "Reserved 0xD70", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D70", + "index_int": "0x0057", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved88", + "name": "Reserved 0xD80", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D80", + "index_int": "0x0058", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved89", + "name": "Reserved 0xD90", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0D90", + "index_int": "0x0059", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved90", + "name": "Reserved 0xDA0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DA0", + "index_int": "0x005A", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved91", + "name": "Reserved 0xDB0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DB0", + "index_int": "0x005B", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved92", + "name": "Reserved 0xDC0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DC0", + "index_int": "0x005C", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved93", + "name": "Reserved 0xDD0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DD0", + "index_int": "0x005D", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved94", + "name": "Reserved 0xDE0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DE0", + "index_int": "0x005E", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved95", + "name": "Reserved 0xDF0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x0DF0", + "index_int": "0x005F", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "USER_KEYx", + "description": "Fuses 0xE00-0x1070: User keys fuse registers" + }, + "registers": [ + { + "id": "fuse96", + "name": "USER_KEY1[255:224]", + "description": "User Key #1", + "offset_int": "0x0E00", + "index_int": "0x0060", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0004" + } + }, + { + "id": "fuse97", + "name": "USER_KEY1[223:192]", + "description": "User Key #1", + "offset_int": "0x0E10", + "index_int": "0x0061", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0004" + } + }, + { + "id": "fuse98", + "name": "USER_KEY1[191:160]", + "description": "User Key #1", + "offset_int": "0x0E20", + "index_int": "0x0062", + "individual_write_lock": "implicit", + "lock": { + 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Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x1290", + "index_int": "0x00A9", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved170", + "name": "Reserved 0x12A0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12A0", + "index_int": "0x00AA", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved171", + "name": "Reserved 0x12B0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12B0", + "index_int": "0x00AB", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved172", + "name": "Reserved 0x12C0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12C0", + "index_int": "0x00AC", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved173", + "name": "Reserved 0x12D0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12D0", + "index_int": "0x00AD", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved174", + "name": "Reserved 0x12E0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12E0", + "index_int": "0x00AE", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + }, + { + "id": "Reserved175", + "name": "Reserved 0x12F0", + "description": "Reserved for future use. Modification may result in unpredictable system behavior. Software should not rely on the value.", + "offset_int": "0x12F0", + "index_int": "0x00AF", + "is_reserved": true, + "bitfields": [ + { + "width": 32 + } + ] + } + ] + }, + { + "group": { + "name": "GPx", + "description": "Fuses 0x1300-0x17F0: General purpose fuse registers" + }, + "registers": [ + { + "id": "fuse176", + "name": "GP1[511:480]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1300", + "index_int": "0x00B0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse177", + "name": "GP1[479:448]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1310", + "index_int": "0x00B1", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse178", + "name": "GP1[447:416]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1320", + "index_int": "0x00B2", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse179", + "name": "GP1[415:384]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1330", + "index_int": "0x00B3", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse180", + "name": "GP1[383:352]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1340", + "index_int": "0x00B4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse181", + "name": "GP1[351:320]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1350", + "index_int": "0x00B5", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse182", + "name": "GP1[319:288]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1360", + "index_int": "0x00B6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse183", + "name": "GP1[287:256]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1370", + "index_int": "0x00B7", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse184", + "name": "GP1[255:224]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1380", + "index_int": "0x00B8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse185", + "name": "GP1[223:192]", + "description": "General Purpose fuse register #1", + "offset_int": "0x1390", + "index_int": "0x00B9", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse186", + "name": "GP1[191:160]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13A0", + "index_int": "0x00BA", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse187", + "name": "GP1[159:128]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13B0", + "index_int": "0x00BB", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse188", + "name": "GP1[127:96]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13C0", + "index_int": "0x00BC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse189", + "name": "GP1[95:64]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13D0", + "index_int": "0x00BD", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse190", + "name": "GP1[63:32]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13E0", + "index_int": "0x00BE", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse191", + "name": "GP1[31:0]", + "description": "General Purpose fuse register #1", + "offset_int": "0x13F0", + "index_int": "0x00BF", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0400" + } + }, + { + "id": "fuse192", + "name": "GP2[511:480]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1400", + "index_int": "0x00C0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse193", + "name": "GP2[479:448]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1410", + "index_int": "0x00C1", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse194", + "name": "GP2[447:416]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1420", + "index_int": "0x00C2", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse195", + "name": "GP2[415:384]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1430", + "index_int": "0x00C3", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse196", + "name": "GP2[383:352]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1440", + "index_int": "0x00C4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse197", + "name": "GP2[351:320]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1450", + "index_int": "0x00C5", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse198", + "name": "GP2[319:288]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1460", + "index_int": "0x00C6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse199", + "name": "GP2[287:256]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1470", + "index_int": "0x00C7", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse200", + "name": "GP2[255:224]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1480", + "index_int": "0x00C8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse201", + "name": "GP2[223:192]", + "description": "General Purpose fuse register #2", + "offset_int": "0x1490", + "index_int": "0x00C9", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse202", + "name": "GP2[191:160]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14A0", + "index_int": "0x00CA", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse203", + "name": "GP2[159:128]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14B0", + "index_int": "0x00CB", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse204", + "name": "GP2[127:96]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14C0", + "index_int": "0x00CC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse205", + "name": "GP2[95:64]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14D0", + "index_int": "0x00CD", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse206", + "name": "GP2[63:32]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14E0", + "index_int": "0x00CE", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse207", + "name": "GP2[31:0]", + "description": "General Purpose fuse register #2", + "offset_int": "0x14F0", + "index_int": "0x00CF", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x0800" + } + }, + { + "id": "fuse208", + "name": "GP3[511:480]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1500", + "index_int": "0x00D0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse209", + "name": "GP3[479:448]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1510", + "index_int": "0x00D1", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse210", + "name": "GP3[447:416]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1520", + "index_int": "0x00D2", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse211", + "name": "GP3[415:384]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1530", + "index_int": "0x00D3", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse212", + "name": "GP3[383:352]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1540", + "index_int": "0x00D4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse213", + "name": "GP3[351:320]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1550", + "index_int": "0x00D5", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse214", + "name": "GP3[319:288]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1560", + "index_int": "0x00D6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse215", + "name": "GP3[287:256]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1570", + "index_int": "0x00D7", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse216", + "name": "GP3[255:224]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1580", + "index_int": "0x00D8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse217", + "name": "GP3[223:192]", + "description": "General Purpose fuse register #3", + "offset_int": "0x1590", + "index_int": "0x00D9", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse218", + "name": "GP3[191:160]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15A0", + "index_int": "0x00DA", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse219", + "name": "GP3[159:128]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15B0", + "index_int": "0x00DB", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse220", + "name": "GP3[127:96]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15C0", + "index_int": "0x00DC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse221", + "name": "GP3[95:64]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15D0", + "index_int": "0x00DD", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse222", + "name": "GP3[63:32]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15E0", + "index_int": "0x00DE", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse223", + "name": "GP3[31:0]", + "description": "General Purpose fuse register #3", + "offset_int": "0x15F0", + "index_int": "0x00DF", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x1000" + } + }, + { + "id": "fuse224", + "name": "GP4[511:480]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1600", + "index_int": "0x00E0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse225", + "name": "GP4[479:448]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1610", + "index_int": "0x00E1", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse226", + "name": "GP4[447:416]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1620", + "index_int": "0x00E2", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse227", + "name": "GP4[415:384]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1630", + "index_int": "0x00E3", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse228", + "name": "GP4[383:352]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1640", + "index_int": "0x00E4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse229", + "name": "GP4[351:320]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1650", + "index_int": "0x00E5", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse230", + "name": "GP4[319:288]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1660", + "index_int": "0x00E6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse231", + "name": "GP4[287:256]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1670", + "index_int": "0x00E7", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse232", + "name": "GP4[255:224]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1680", + "index_int": "0x00E8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse233", + "name": "GP4[223:192]", + "description": "General Purpose fuse register #4", + "offset_int": "0x1690", + "index_int": "0x00E9", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse234", + "name": "GP4[191:160]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16A0", + "index_int": "0x00EA", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse235", + "name": "GP4[159:128]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16B0", + "index_int": "0x00EB", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse236", + "name": "GP4[127:96]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16C0", + "index_int": "0x00EC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse237", + "name": "GP4[95:64]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16D0", + "index_int": "0x00ED", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse238", + "name": "GP4[63:32]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16E0", + "index_int": "0x00EE", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse239", + "name": "GP4[31:0]", + "description": "General Purpose fuse register #4", + "offset_int": "0x16F0", + "index_int": "0x00EF", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x2000" + } + }, + { + "id": "fuse240", + "name": "GP5[511:480]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1700", + "index_int": "0x00F0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse241", + "name": "GP5[479:448]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1710", + "index_int": "0x00F1", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse242", + "name": "GP5[447:416]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1720", + "index_int": "0x00F2", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse243", + "name": "GP5[415:384]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1730", + "index_int": "0x00F3", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse244", + "name": "GP5[383:352]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1740", + "index_int": "0x00F4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse245", + "name": "GP5[351:320]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1750", + "index_int": "0x00F5", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse246", + "name": "GP5[319:288]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1760", + "index_int": "0x00F6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse247", + "name": "GP5[287:256]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1770", + "index_int": "0x00F7", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse248", + "name": "GP5[255:224]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1780", + "index_int": "0x00F8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse249", + "name": "GP5[223:192]", + "description": "General Purpose fuse register #5", + "offset_int": "0x1790", + "index_int": "0x00F9", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse250", + "name": "GP5[191:160]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17A0", + "index_int": "0x00FA", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse251", + "name": "GP5[159:128]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17B0", + "index_int": "0x00FB", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse252", + "name": "GP5[127:96]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17C0", + "index_int": "0x00FC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse253", + "name": "GP5[95:64]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17D0", + "index_int": "0x00FD", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse254", + "name": "GP5[63:32]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17E0", + "index_int": "0x00FE", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + }, + { + "id": "fuse255", + "name": "GP5[31:0]", + "description": "General Purpose fuse register #5", + "offset_int": "0x17F0", + "index_int": "0x00FF", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse9", + "read_lock_int": "0x4000" + } + } + ] + }, + { + "group": { + "name": "BOOT_CONFIG_MISC5", + "description": "Fuses 0x1800-0x18F0: Boot config misc fuse registers" + }, + "registers": [ + { + "id": "fuse256", + "name": "BOOT_CONFIG_MISC5[511:480]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1800", + "index_int": "0x0100", + "individual_write_lock": "implicit" + }, + { + "id": "fuse257", + "name": "BOOT_CONFIG_MISC5[479:448]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1810", + "index_int": "0x0101", + "individual_write_lock": "implicit" + }, + { + "id": "fuse258", + "name": "BOOT_CONFIG_MISC5[447:416]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1820", + "index_int": "0x0102", + "individual_write_lock": "implicit" + }, + { + "id": "fuse259", + "name": "BOOT_CONFIG_MISC5[415:384]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1830", + "index_int": "0x0103", + "individual_write_lock": "implicit" + }, + { + "id": "fuse260", + "name": "BOOT_CONFIG_MISC5[383:352]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1840", + "index_int": "0x0104", + "individual_write_lock": "implicit" + }, + { + "id": "fuse261", + "name": "BOOT_CONFIG_MISC5[351:320]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1850", + "index_int": "0x0105", + "individual_write_lock": "implicit" + }, + { + "id": "fuse262", + "name": "BOOT_CONFIG_MISC5[319:288]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1860", + "index_int": "0x0106", + "individual_write_lock": "implicit" + }, + { + "id": "fuse263", + "name": "BOOT_CONFIG_MISC5[287:256]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1870", + "index_int": "0x0107", + "individual_write_lock": "implicit" + }, + { + "id": "fuse264", + "name": "BOOT_CONFIG_MISC5[255:224]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1880", + "index_int": "0x0108", + "individual_write_lock": "implicit" + }, + { + "id": "fuse265", + "name": "BOOT_CONFIG_MISC5[223:192]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x1890", + "index_int": "0x0109", + "individual_write_lock": "implicit" + }, + { + "id": "fuse266", + "name": "BOOT_CONFIG_MISC5[191:160]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18A0", + "index_int": "0x010A", + "individual_write_lock": "implicit" + }, + { + "id": "fuse267", + "name": "BOOT_CONFIG_MISC5[159:128]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18B0", + "index_int": "0x010B", + "individual_write_lock": "implicit" + }, + { + "id": "fuse268", + "name": "BOOT_CONFIG_MISC5[127:96]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18C0", + "index_int": "0x010C", + "individual_write_lock": "implicit" + }, + { + "id": "fuse269", + "name": "BOOT_CONFIG_MISC5[95:64]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18D0", + "index_int": "0x010D", + "individual_write_lock": "implicit" + }, + { + "id": "fuse270", + "name": "BOOT_CONFIG_MISC5[63:32]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18E0", + "index_int": "0x010E", + "individual_write_lock": "implicit" + }, + { + "id": "fuse271", + "name": "BOOT_CONFIG_MISC5[31:0]", + "description": "Boot configuration misc fields are boot device dependent. See the reference manual for details.", + "offset_int": "0x18F0", + "index_int": "0x010F", + "individual_write_lock": "implicit" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1171/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1171/database.yaml new file mode 100644 index 0000000..b84ee23 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1171/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1172 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1172/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1172/database.yaml new file mode 100644 index 0000000..d46777f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1172/database.yaml @@ -0,0 +1,54 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1176 + +# General MCU information +info: + memory_map: + itcm: + start_int: "0x0" + size_int: "0x40000" + external: false + non_xip_type: int_ram + dtcm: + start_int: "0x20000000" + size_int: "0x40000" + external: false + non_xip_type: int_ram + ocram1: + start_int: "0x20240000" + size_int: "0x80000" + external: false + non_xip_type: int_ram + ocram2: + start_int: "0x202C0000" + size_int: "0x80000" + external: false + non_xip_type: int_ram + ocram-ecc1: + start_int: "0x20340000" + size_int: "0x10000" + external: false + non_xip_type: none + ocram-ecc2: + start_int: "0x20350000" + size_int: "0x10000" + external: false + non_xip_type: none + flexspi1: + start_int: "0x30000000" + size_int: "0x10000000" + external: true + non_xip_type: ext_ram_flexspi + flexspi2: + start_int: "0x60000000" + size_int: "0x1F800000" + external: true + non_xip_type: ext_ram_flexspi + sdram: + start_int: "0x80000000" + size_int: "0x4000000" + external: true + non_xip_type: ext_ram_semc diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1173/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1173/database.yaml new file mode 100644 index 0000000..1b0dff9 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1173/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1176 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1175/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1175/database.yaml new file mode 100644 index 0000000..1b0dff9 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1175/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1176 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1176/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1176/database.yaml new file mode 100644 index 0000000..17a0954 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1176/database.yaml @@ -0,0 +1,68 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1166 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt117x + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT1170 + memory_map: + itcm: + start_int: "0x0" + size_int: "0x40000" + external: false + non_xip_type: int_ram + cm4_itcm: + start_int: "0x1FFE0000" + size_int: "0x20000" + external: false + non_xip_type: int_ram + dtcm: + start_int: "0x20000000" + size_int: "0x40000" + external: false + non_xip_type: int_ram + cm4_ocram: + start_int: "0x20200000" + size_int: "0x40000" + external: false + non_xip_type: int_ram + ocram1: + start_int: "0x20240000" + size_int: "0x80000" + external: false + non_xip_type: int_ram + ocram2: + start_int: "0x202C0000" + size_int: "0x80000" + external: false + non_xip_type: int_ram + ocram-ecc1: + start_int: "0x20340000" + size_int: "0x10000" + external: false + non_xip_type: none + ocram-ecc2: + start_int: "0x20350000" + size_int: "0x10000" + external: false + non_xip_type: none + flexspi1: + start_int: "0x30000000" + size_int: "0x10000000" + external: true + non_xip_type: ext_ram_flexspi + flexspi2: + start_int: "0x60000000" + size_int: "0x1F800000" + external: true + non_xip_type: ext_ram_flexspi + sdram: + start_int: "0x80000000" + size_int: "0x4000000" + external: true + non_xip_type: ext_ram_semc diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1181/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1181/database.yaml new file mode 100644 index 0000000..311f978 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1181/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1182 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1182/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1182/database.yaml new file mode 100644 index 0000000..23d1227 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1182/database.yaml @@ -0,0 +1,69 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1189 + +# General MCU information +info: + memory_map: + code-tcm: + start_int: 0x0FFE0000 + size_int: 0x20000 + external: false + non_xip_type: int_ram + system-tcm: + start_int: 0x20000000 + size_int: 0x20000 + external: false + non_xip_type: int_ram + ocram1_ns: + start_int: 0x20480000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram1_s: + start_int: 0x30480000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram2_ns: + start_int: 0x20500000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + ocram2_s: + start_int: 0x30500000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + flexspi2_ns: + start_int: 0x04000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi2_s + evk_default: true + flexspi2_s: + start_int: 0x14000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + isp: + rom: + protocol: mboot + interfaces: [uart] + flashloader: + protocol: mboot + interfaces: [uart] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1186/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1186/database.yaml new file mode 100644 index 0000000..a508bca --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1186/database.yaml @@ -0,0 +1,13 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1189 + +revisions: + a0: {} +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1187/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1187/database.yaml new file mode 100644 index 0000000..509474a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1187/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt1189 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/database.yaml new file mode 100644 index 0000000..0479881 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/database.yaml @@ -0,0 +1,315 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + b0: {} +latest: b0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt118x + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT1180 + memory_map: + code-tcm: + start_int: 0x0FFE0000 + size_int: 0x20000 + external: false + non_xip_type: int_ram + system-tcm: + start_int: 0x20000000 + size_int: 0x20000 + external: false + non_xip_type: int_ram + cm7_itcm_ns: + start_int: 0x20380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_itcm_s: + start_int: 0x30380000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_ns: + start_int: 0x20400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + cm7_dtcm_s: + start_int: 0x30400000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram1_ns: + start_int: 0x20480000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram1_s: + start_int: 0x30480000 + size_int: 0x80000 + external: false + non_xip_type: int_ram + ocram2_ns: + start_int: 0x20500000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + ocram2_s: + start_int: 0x30500000 + size_int: 0x40000 + external: false + non_xip_type: int_ram + flexspi1_ns: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi1_s + flexspi1_s: + start_int: 0x38000000 + size_int: 0x08000000 + external: true + non_xip_type: ext_ram_flexspi + flexspi2_ns: + start_int: 0x04000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + mirror_of: flexspi2_s + evk_default: true + flexspi2_s: + start_int: 0x14000000 + size_int: 0x04000000 + external: true + non_xip_type: ext_ram_flexspi + sdram: + start_int: 0x80000000 + size_int: 0x10000000 + external: true + non_xip_type: ext_ram_semc + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x014C + flashloader: + protocol: mboot + interfaces: [uart, usb, spi] + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + tool: blhost + grouped_registers: + - uid: otfad1_key + name: OTFAD1_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD1 Key known as KEK. + sub_regs: [fuse184, fuse185, fuse186, fuse187] + - uid: otfad2_key + name: OTFAD2_KEY + width: 128 + reverse_subregs_order: True + reversed: True + config_as_hexstring: true + description: OTFAD2 Key known as KEK. + sub_regs: [fuse178, fuse179, fuse180, fuse181] + - uid: srkh + name: SRKH + width: 256 + reversed: True + config_as_hexstring: True + description: "SHA256 hash digest of hash of four SRK keys" + sub_regs: + [ + "fuse128", + "fuse129", + "fuse130", + "fuse131", + "fuse132", + "fuse133", + "fuse134", + "fuse135", + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x1ffe_0000 + size: 0xc000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_srk] + rot_type: srk_table_ahab + + # ======== DAT section ======== + dat: + socc: 0x5254049C # SOCC identification + based_on_ele: True # Flag if the implementation of DAT is based on EdgeLock Enclave + dat_is_using_sha256_always: True + dmbox_ap_ix: 0 + + # ======== AHAB section ======== + ahab: + container_types: [1] # Supported container types + core_ids: + CORTEX_M33: [1, "cortex-m33", "Cortex M33"] + CORTEX_M7: [2, "cortex-m7", "Cortex M7"] + ELE: [6, "ele", "EdgeLock Enclave"] + image_types: + application: + EXECUTABLE: [0x03, executable, Executable Image] + DATA: [0x04, data, Data Image] + PROVISIONING_IMAGE: [0x07, provisioning_image, Provisioning Image] + PROVISIONING_DATA: [0x09, provisioning_data, Provisioning data Image] + ele: + ELE: [0x06, ele, EdgeLock Enclave Image] + + image_types_mapping: + ele: [6] + + allow_empty_hash: True + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== XMCD section ======== + xmcd: + mem_types: + flexspi_ram: + simplified: + reg_spec: ../../common/xmcd/flexspi_ram_simplified.json + full: + reg_spec: ../../common/xmcd/flexspi_ram_full.json + semc_sdram: + simplified: + reg_spec: ../../common/xmcd/semc_sdram_simplified.json + full: + reg_spec: ../../common/xmcd/semc_sdram_full.json + fuses: + _name: "XMCD CRC" + fuse31: + fuse31-bit-20: 1 # XMC_CRC32_CHECK_EN + fuse32: "__crc" # XMC_CRC32_CHECK_SUM + + # ======== IEE section ======== + iee: + generate_keyblob: False + has_kek_fuses: False + additional_template: ["key_blobs_with_ele"] + + # ======== OTFAD section ======== + otfad: + keyblob_byte_swap_cnt: 8 + sb_21_supported: False + has_kek_fuses: True + supports_key_scrambling: True + reversed_scramble_key: True + + fuses_1: # Fuses for OTFAD1 + _name: Configuration of fuses for OTFAD1 + _no_verify: True + fuse188: # OTFAD CFG Fuse + fuse188-bit-3: 1 # OTFAD Enable + fuse188-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse188-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse189: __key_scramble_mask # OTFAD Scramble Key + otfad1_key: __kek # OTFAD Key + + fuses_2: # Fuses for OTFAD2 + _name: Configuration of fuses for OTFAD2 + _no_verify: True + fuse182: # OTFAD CFG Fuse + fuse182-bit-3: 1 # OTFAD Enable + fuse182-bit-7: __scramble_enabled # OTFAD enable scrambling + fuse182-bits-8-15: __key_scramble_align # OTFAD scramble align + fuse183: __key_scramble_mask # OTFAD Scramble Key + otfad2_key: __kek # OTFAD Key + + additional_template: ["otfad_scramble"] + additional_template_text: | + Is important to use physical addresses (non-secure) in settings of OTFAD to proper run the decryption on device. + For example: + In case of using FlexSPI2 the secure base address address is 0x1400_0000. But in setting of the OTFAD use 0x0400_0000 as a base address. + The code must be still linked on secure base address 0x1400_0000 to proper run of OTFAD hardware. + + Same is for FlexSPI1, but instead of 0x3800_0000 base address, the 0x2800_0000 must be used in OTFAD configuration. + + # ======== Bootable image section ======== + bootable_image: + mem_types: + serial_downloader: + segments: + xmcd: 0x00 + ahab_container: 0x400 + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + xmcd: 0x0800 + ahab_container: 0x1000 + flexspi_nand: + segments: + xmcd: 0x00 + ahab_container: 0x400 + semc_nand: + segments: + xmcd: 0x00 + ahab_container: 0x400 + emmc: + segments: + #secondary_image_table: 0x200 (not used) + xmcd: 0x400 + ahab_container: 0x800 + sd: + segments: + #secondary_image_table: 0x200 (not used) + xmcd: 0x400 + ahab_container: 0x800 + + # ======== EdgeLock Enclave section ======== + ele: + ele_device: mboot + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [1, 2] + flexspi_nand: + instances: [1, 2] + semc_nor: + instances: [0] # probably not supported in latest version of Flashloader + semc_nand: + instances: [0] # probably not supported in latest version of Flashloader + sd: + instances: [1, 2] + emmc: + instances: [1, 2] + spi_nor: + instances: [1, 2, 4, 5] + + # ======== Misc signing section ======== + signing: + pss_padding: true + + # ===== TLV ===== + tlv_blob: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fcb_flexspi_nor.json new file mode 100644 index 0000000..f61849c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fcb_flexspi_nor.json @@ -0,0 +1,25685 @@ +{ + "cpu": "MIMXRT1189", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix", + "default_value_int": "0x56010000", + "bitfields": [ + { + "id": "field004-bits0-7", + "width": 8, + "name": "bugfix", + "access": "RW", + "description": "[07:00] Bugfix - 0" + }, + { + "id": "field004-bits8-15", + "width": 8, + "name": "minor", + "access": "RW", + "description": "[15:08] Minor" + }, + { + "id": "field004-bits16-23", + "width": 8, + "name": "major", + "access": "RW", + "description": "[23:16] Major - 1" + }, + { + "width": 8 + } + ] + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type: 0 - Generic, 1 - Quad Enable, 2 - SPI-to-xSPI, 3 - xSPI-to-SPI", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration. effective only when deviceModeCfgEnable = 1", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable", + "default_value_int": "0x0" + }, + { + "id": "Reserved01D", + "offset_int": "0x1d", + "reg_width": 24, + "name": "reserved1", + "description": " [0x01d-0x019] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x02c-0x02f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved3", + "description": " [0x03c-0x03f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 64, + "name": "reserved4", + "description": " [0x048-0x04f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 8, + "name": "csPadSettingOverrideEn", + "description": " [0x060-0x060] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field061", + "offset_int": "0x61", + "reg_width": 8, + "name": "csPadSettingOverride", + "description": " [0x061-0x061] Overriding pad setting of CS", + "default_value_int": "0x0" + }, + { + "id": "Reserved062", + "offset_int": "0x62", + "reg_width": 16, + "name": "reserved5", + "description": " [0x062-0x063] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 8, + "name": "sclkPadSettingOverrideEn", + "description": " [0x064-0x064] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field065", + "offset_int": "0x65", + "reg_width": 8, + "name": "sclkPadSettingOverride", + "description": " [0x065-0x065] Overriding pad setting of SCLK", + "default_value_int": "0x0" + }, + { + "id": "Reserved066", + "offset_int": "0x66", + "reg_width": 16, + "name": "reserved6", + "description": " [0x066-0x067] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 8, + "name": "dataPadSettingOverrideEn", + "description": " [0x068-0x068] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field069", + "offset_int": "0x69", + "reg_width": 8, + "name": "dataPadSettingOverride", + "description": " [0x069-0x069] Overriding pad setting of data signals", + "default_value_int": "0x0" + }, + { + "id": "Reserved06A", + "offset_int": "0x6a", + "reg_width": 16, + "name": "reserved7", + "description": " [0x06a-0x06b] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 8, + "name": "dqsPadSettingOverrideEn", + "description": " [0x06c-0x06c] Set to 0 if it is not supported", + "default_value_int": "0x0" + }, + { + "id": "field06D", + "offset_int": "0x6d", + "reg_width": 8, + "name": "dqsPadSettingOverride", + "description": " [0x06d-0x06d] Overriding pad setting of DQS", + "default_value_int": "0x0" + }, + { + "id": "Reserved06E", + "offset_int": "0x6e", + "reg_width": 16, + "name": "reserved8", + "description": " [0x06e-0x06f] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "dataValidTime", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-15", + "width": 16, + "name": "dllAValidTime", + "access": "RW", + "description": " Data valid time for DLLA in terms of 0.1 ns" + }, + { + "id": "field078-bits16-31", + "width": 16, + "name": "dllBValidTime", + "access": "RW", + "description": " Data valid time for DLLB in terms of 0.1 ns" + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15" + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved9_0", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved9_1", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved9_2", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved9_3", + "description": " [0x1b0-0x1bf] Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " The data order is swapped in OPI DDR mode", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved10_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "reserved10_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "reserved10_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "reserved10_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "reserved10_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context after being configured", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D4-bits0-7", + "width": 8, + "name": "flashPorMode", + "access": "RW", + "description": " Flash POR Mode" + }, + { + "id": "field1D4-bits8-15", + "width": 8, + "name": "flashCurrentMode", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + }, + { + "width": 8 + }, + { + "id": "field1D4-bits24-31", + "width": 8, + "name": "flashRestoringSequence", + "access": "RW", + "description": " Sequence Number, valid number: 1-16" + } + ] + }, + { + "id": "Reserved1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserved11_0", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserved11_1", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserved11_2", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserved11_3", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserved11_4", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserved11_5", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserved11_6", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserved11_7", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserved11_8", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserved11_9", + "description": " Reserved for future use", + "default_value_int": "0x0", + "is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fuses.json new file mode 100644 index 0000000..9e3eddc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt1189/fuses.json @@ -0,0 +1,3592 @@ +{ + "cpu": "mimxrt1189", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Write/Read/Override Protection" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCKS0", + "description": "Fuse 0", + "index_int": "0", + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG_LOCK", + "description": "Boot Configuration Lock;\n000 - Unlocked (fuses can be read, sensed, burned or overridden in the corresponding \nOTP shadow register);\nxx1 - WP (Write Protect, the controlled field can not be burned);\nx1x - OP (Over-ride Protect, the controlled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from \nshadow registers)", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 9 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits;\n000 - Unlocked (fuses can be read, sensed, burned or overridden in the corresponding OTP shadow register);\nxx1 - WP (Write Protect, the controlled field can not be burned); x1x - OP (Over-ride Protect, the \ncontrolled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from \nshadow registers)", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 17 + } + ] + }, + { + "id": "fuse1", + "name": "COM_DEVICE_ID_LOCKS", + "description": "Fuse 1", + "index_int": "0x0001", + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "COM_DEVICE_ID0_LOCK", + "description": "Communication Device ID0 Lock - Ethernet;\n000 - Unlocked (fuses can be read, sensed, burned or overridden in the corresponding OTP shadow register);\nxx1 - WP (Write Protect, the controlled field can not be burned); x1x - OP (Over-ride Protect, the \ncontrolled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from \nshadow registers)", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "COM_DEVICE_ID1_LOCK", + "description": "Communication Device ID1 Lock - USB, Ethernet;\n000 - Unlocked (fuses can be read, sensed, burned or overridden in the corresponding OTP shadow register);\nxx1 - WP (Write Protect, the controlled field can not be burned); x1x - OP (Over-ride Protect, the \ncontrolled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from \nshadow registers)", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 23 + } + ] + }, + { + "id": "fuse2", + "name": "ELE_OTFAD1_KEY_LOCK", + "description": "Fuse 2", + "index_int": "0x0002", + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-3-5", + "name": "ELE_OTFAD1_KEY_LOCK", + "description": "ELE OTFAD1 Key Lock;\nxx1 - WP (Write Protect, the controlled field can not be burned);\nx1x - OP (Over-ride Protect, the controlled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers);", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 26 + } + ] + }, + { + "id": "fuse4", + "name": "ELE_OEM_SRKH_LOCK", + "description": "Fuse 4", + "index_int": "0x0004", + "bitfields": [ + { + "width": 12 + }, + { + "width": 3, + "id": "fuse4-bits-12-14", + "name": "ELE_OEM_SRKH_LOCK", + "description": "ELE OEM SRK Hash Lock;\nxx1 - WP (Write Protect, the controlled field can not be burned);\nx1x - OP (Over-ride Protect, the controlled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers);", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 17 + } + ] + }, + { + "id": "fuse6", + "name": "ELE_OTFAD2_KEY_LOCK", + "description": "Fuse 6", + "index_int": "0x0006", + "bitfields": [ + { + "width": 12 + }, + { + "width": 3, + "id": "fuse6-bits-12-14", + "name": "ELE_OTFAD2_KEY_LOCK", + "description": "ELE OTFAD Key Lock;\nxx1 - WP (Write Protect, the controlled field can not be burned);\nx1x - OP (Over-ride Protect, the controlled field shadow registers can not be over-written);\n1xx - RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers);", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WP", + "value": 1, + "description": "WP" + }, + { + "name": "OP", + "value": 2, + "description": "OP" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP+WP" + }, + { + "name": "RP", + "value": 4, + "description": "RP" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP" + }, + { + "name": "RP+OP+WP", + "value": 7, + "description": "RP+OP+WP" + } + ] + }, + { + "width": 17 + } + ] + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse24", + "name": "BOOT_CFG0", + "description": "Fuse 24 [799:792]", + "index_int": "0x0018", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse24-bits-0-2", + "name": "BOOT_MODE_FROM_FUSE", + "description": "BOOT_MODE_FROM_FUSE\n0-FlexSPI NOR\n1-FlexSPI NAND\n2-eMMC\n3-SD\n4-SEMC SLC raw NAND\n5-Serial Boot", + "values": [ + { + "name": "FlexSPI NOR", + "value": 0, + "description": "FlexSPI NOR" + }, + { + "name": "FlexSPI NAND", + "value": 1, + "description": "FlexSPI NAND" + }, + { + "name": "eMMC", + "value": 2, + "description": "eMMC" + }, + { + "name": "SD", + "value": 3, + "description": "SD" + }, + { + "name": "4", + "value": 4, + "description": "SEMC SLC raw NAND" + }, + { + "name": "Serial Boot", + "value": 5, + "description": "Serial Boot" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse24-bit-4", + "name": "RECOVERY_BOOT_EN", + "description": "RECOVERY_BOOT_EN\n0-Recovery boot is disabled\n1-Recovery boot is enabled", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Recovery boot is disabled" + }, + { + "name": "Enable", + "value": 1, + "description": "Recovery boot is enabled" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-5", + "name": "DIS_SDMMC_MFG_BOOT", + "description": "DIS_SDMMC_MFG_BOOT\n0-Enable\n1-Disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-6", + "name": "BT_FUSE_SEL", + "description": "BT_FUSE_SEL\n0-BOOT_MODE_FROM_FUSE is invalid\n1-BOOT_MODE_FROM_FUSE is valid", + "values": [ + { + "name": "0", + "value": 0, + "description": "BOOT_MODE_FROM_FUSE is invalid" + }, + { + "name": "1", + "value": 1, + "description": "BOOT_MODE_FROM_FUSE is valid" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-7", + "name": "FORCE_BT_FROM_FUSE", + "description": "FORCE_BT_FROM_FUSE\n0-Boot mode determined by BOOT_MODE pins \n1-Boot mode determined by BOOT_MODE_FROM_FUSE", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot mode determined by BOOT_MODE pins" + }, + { + "name": "1", + "value": 1, + "description": "Boot mode determined by BOOT_MODE_FROM_FUSE" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse24-bit-10", + "name": "DIS_UART_DWNLD", + "description": "DIS_UART_DWNLD\n0-Enable UART in Serial Downloader\n1-Disable UART in Serial Downloader", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable UART in Serial Downloader" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable UART in Serial Downloader" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-11", + "name": "DIS_SPI_DWNLD", + "description": "DIS_SPI_DWNLD\n0-Enable SPI in Serial Downloader\n1-Disable SPI in Serial Downloader", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable SPI in Serial Downloader" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable SPI in Serial Downloader" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-12", + "name": "DIS_USB_HID_DWNLD", + "description": "DIS_USB_HID_DWNLD\n0-Enable USB in Serial Downloader\n1-Disable USB in Serial Downloader", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable USB in Serial Downloader" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable USB in Serial Downloader" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-13", + "name": "DIS_INFINITE_LOOP", + "description": "DIS_INFINITE_LOOP\n0-Infinite loop is allowed\n1-Infinite Loop is forbidden", + "values": [ + { + "name": "0", + "value": 0, + "description": "Infinite loop is allowed" + }, + { + "name": "1", + "value": 1, + "description": "Infinite Loop is forbidden" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-14", + "name": "DIS_BT_MODE_API", + "description": "DIS_BT_MODE_API\n0-Allow boot from ROM API call\n1-Disallow boot from ROM API call", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow boot from ROM API call" + }, + { + "name": "Disallow", + "value": 1, + "description": "Disallow boot from ROM API call" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-15", + "name": "DIS_SERIAL_DWNLD", + "description": "DIS_SERIAL_DWNLD\n0-Allow Serial downloader mode\n1-Disable Serial Downloader mode", + "values": [ + { + "name": "Allow", + "value": 0, + "description": "Allow Serial downloader mode" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable Serial Downloader mode" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-16-17", + "name": "LPSPI_PORT_SEL", + "description": "LPSPI_PORT_SEL\n0-LPSPI1\n1-LPSPI2\n2-LPSPI3\n3-LPSPI4", + "values": [ + { + "name": "LPSPI1", + "value": 0, + "description": "LPSPI1" + }, + { + "name": "LPSPI2", + "value": 1, + "description": "LPSPI2" + }, + { + "name": "LPSPI3", + "value": 2, + "description": "LPSPI3" + }, + { + "name": "LPSPI4", + "value": 3, + "description": "LPSPI4" + } + ] + }, + { + "width": 2, + "id": "fuse24-bits-18-19", + "name": "LPSPI_SPEED", + "description": "LPSPI_SPEED\n0-30MHz\n1-10MHz\n2-30MHz Dual Read\n3-30MHz Quad Read", + "values": [ + { + "name": "30MHz", + "value": 0, + "description": "30MHz" + }, + { + "name": "10MHz", + "value": 1, + "description": "10MHz" + }, + { + "name": "2", + "value": 2, + "description": "30MHz Dual Read" + }, + { + "name": "3", + "value": 3, + "description": "30MHz Quad Read" + } + ] + }, + { + "width": 3, + "id": "fuse24-bits-20-22", + "name": "LPSPI_DUMMY_BYTES", + "description": "LPSPI_DUMMY_BYTES\n0-Default (4 cycles for dual/6 cycles for quad)\nn (non-zero) - 4n cycles for dual/2n cycles for quad", + "values": [ + { + "name": "Default", + "value": 0, + "description": "Default (4 cycles for dual/6 cycles for quad)" + } + ] + }, + { + "width": 1, + "id": "fuse24-bit-23", + "name": "LPSPI_INTERNAL_PULL", + "description": "LPSPI_INTERNAL_PULL\n0-No internal pull-up\n1-Internal pull-up enabled", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "No internal pull-up" + }, + { + "name": "Enable", + "value": 1, + "description": "Internal pull-up enabled" + } + ] + }, + { + "width": 4, + "id": "fuse24-bits-24-27", + "name": "BOOT_FAIL_IND_PIN", + "description": "BOOT_FAIL_IND_PIN\nn - GPIO4_IOn/GPIO_AD_n selected" + }, + { + "width": 3 + }, + { + "width": 1, + "id": "fuse24-bit-31", + "name": "BOOT_FAIL_IND_EN", + "description": "BOOT_FAIL_IND_EN\n0-Boot failure indicator pin is disabled \n1-Boot failure indicator pin is enabled", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Boot failure indicator pin is disabled" + }, + { + "name": "Enable", + "value": 1, + "description": "Boot failure indicator pin is enabled" + } + ] + } + ] + }, + { + "id": "fuse25", + "name": "BOOT_CFG1", + "description": "Fuse 25 [823:816]", + "index_int": "0x0019", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse25-bits-0-1", + "name": "xSPI_NOR_PROBE_TYPE", + "description": "xSPI_NOR_PROBE_TYPE (Non-0 only when xSPI_NOR_TYPE is 0)\n0-JESD216\n1-MXIC Octal\n2-Micron Octal\n3-Adesto Octal", + "values": [ + { + "name": "JESD216", + "value": 0, + "description": "JESD216" + }, + { + "name": "MXIC Octal", + "value": 1, + "description": "MXIC Octal" + }, + { + "name": "Micron Octal", + "value": 2, + "description": "Micron Octal" + }, + { + "name": "Adesto Octal", + "value": 3, + "description": "Adesto Octal" + } + ] + }, + { + "width": 2, + "id": "fuse25-bits-2-3", + "name": "xSPI_NOR_HOLD_TIME", + "description": "xSPI_NOR_HOLD_TIME\n0-500us\n1-1ms\n2-3ms\n3-10ms", + "values": [ + { + "name": "500us", + "value": 0, + "description": "500us" + }, + { + "name": "1ms", + "value": 1, + "description": "1ms" + }, + { + "name": "3ms", + "value": 2, + "description": "3ms" + }, + { + "name": "10ms", + "value": 3, + "description": "10ms" + } + ] + }, + { + "width": 3, + "id": "fuse25-bits-4-6", + "name": "xSPI_NOR_FREQ", + "description": "xSPI_NOR_FREQ\n0-100MHz\n1-120MHz\n2-133MHz\n3-166MHz\n4-200MHz\n5-80MHz\n6-60MHz\n7-50MHz", + "values": [ + { + "name": "100MHz", + "value": 0, + "description": "100MHz" + }, + { + "name": "120MHz", + "value": 1, + "description": "120MHz" + }, + { + "name": "133MHz", + "value": 2, + "description": "133MHz" + }, + { + "name": "166MHz", + "value": 3, + "description": "166MHz" + }, + { + "name": "200MHz", + "value": 4, + "description": "200MHz" + }, + { + "name": "80MHz", + "value": 5, + "description": "80MHz" + }, + { + "name": "60MHz", + "value": 6, + "description": "60MHz" + }, + { + "name": "50MHz", + "value": 7, + "description": "50MHz" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-7", + "name": "xSPI_NOR_CONNECTION_SEL", + "description": "xSPI_NOR_CONNECTION_SEL\n0-Connected via PORTA CS0\n1-Connected via PORTB CS0", + "values": [ + { + "name": "0", + "value": 0, + "description": "Connected via PORTA CS0" + }, + { + "name": "1", + "value": 1, + "description": "Connected via PORTB CS0" + } + ] + }, + { + "width": 3, + "id": "fuse25-bits-8-10", + "name": "xSPI_NOR_TYPE", + "description": "xSPI_NOR_TYPE\n0-Boot with default 0x03 Read\n1-Reserved\n2-HyperFLASH 1V8\n3-HyperFLASH 3V0\n4-MXIC Octal Read\n5-Micron Octal DDR ReadOthers - Reserved", + "values": [ + { + "name": "0", + "value": 0, + "description": "Boot with default 0x03 Read" + }, + { + "name": "2", + "value": 2, + "description": "HyperFLASH 1V8" + }, + { + "name": "3", + "value": 3, + "description": "HyperFLASH 3V0" + }, + { + "name": "4", + "value": 4, + "description": "MXIC Octal Read" + }, + { + "name": "5", + "value": 5, + "description": "Micron Octal DDR ReadOthers - Reserved" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-11", + "name": "RST_REQUIRED", + "description": "RST_REQUIRED\nReset required after boot failure. Set if xSPI_NOR_ ENCRYPT_XIP_EN is 1" + }, + { + "width": 2, + "id": "fuse25-bits-12-13", + "name": "xSPI_NOR_RESET_TYPE", + "description": "xSPI_NOR_RESET_TYPE (Non-0 only when xSPI_NOR_TYPE is 0)\n0-Reset sequence is specified in FLASH_STATE_CTX Register\n1-Reset FLASH by Reset Pin before access\n2-Reset FLASH by JEDEC Hardware Reset flow\n3-Typical Reset Sequence (0x66, 0x99)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset sequence is specified in FLASH_STATE_CTX Register" + }, + { + "name": "1", + "value": 1, + "description": "Reset FLASH by Reset Pin before access" + }, + { + "name": "2", + "value": 2, + "description": "Reset FLASH by JEDEC Hardware Reset flow" + }, + { + "name": "3", + "value": 3, + "description": "Typical Reset Sequence (0x66, 0x99)" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse25-bit-16", + "name": "xSPI_NOR_ENCRYPT_XIP_EN", + "description": "xSPI_NOR_ENCRYPT_XIP_EN\n0-Encrypted XIP is disabled\n1-Encrypted XIP is enabled", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Encrypted XIP is disabled" + }, + { + "name": "Enable", + "value": 1, + "description": "Encrypted XIP is enabled" + } + ] + }, + { + "width": 1, + "id": "fuse25-bit-17", + "name": "XSPI_NOR_ENCRYPT_ENG", + "description": "XSPI_NOR_ENCRYPT_ENG\n0-OTFAD\n1-IEE", + "values": [ + { + "name": "OTFAD", + "value": 0, + "description": "OTFAD" + }, + { + "name": "IEE", + "value": 1, + "description": "IEE" + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse25-bit-20", + "name": "DIS_xSPI_NOR_FCB", + "description": "DIS_xSPI_NOR_FCB\n0-Enable FLASH CFG Block\n1-Disable FLASH CFG Block", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable FLASH CFG Block" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable FLASH CFG Block" + } + ] + }, + { + "width": 3 + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse26", + "name": "BOOT_CFG2", + "description": "Fuse 26 [847:840]", + "index_int": "0x001A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse26-bits-0-2", + "name": "FLEXSPI_PAD_SETTING_OVERRIDE", + "description": "FLEXSPI_PAD_SETTING_OVERRIDE\n0-Slew rate , 0: slow slew rate, 1: fast slew rate bit\n1-Drive Strength, 0: normal driver, 1 : high driver bit\n2-Pull selection, 0: pull off, 1 - Pull on", + "values": [ + { + "name": "0", + "value": 0, + "description": "Slew rate , 0: slow slew rate, 1: fast slew rate bit" + }, + { + "name": "1", + "value": 1, + "description": "Drive Strength, 0: normal driver, 1 : high driver bit" + }, + { + "name": "2", + "value": 2, + "description": "Pull selection, 0: pull off, 1 - Pull on" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-3", + "name": "FLEXSPI_PAD_OVERRIDE_EN", + "description": "FLEXSPI_PAD_OVERRIDE_EN\n0-Use default pad setting\n1-Use the pad setting specified by FLEXSPI_PAD_SETTING_OVERRIDE FUSE field", + "values": [ + { + "name": "0", + "value": 0, + "description": "Use default pad setting" + }, + { + "name": "1", + "value": 1, + "description": "Use the pad setting specified by FLEXSPI_PAD_SETTING_OVERRIDE FUSE field" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-4", + "name": "FLEXSPI_RESET_PIN_SEL", + "description": "FLEXSPI_RESET_PIN_SEL\nSelect the Reset Pin\n0-Reset Pin 0\n1-Reset Pin 1", + "values": [ + { + "name": "Reset Pin 0", + "value": 0, + "description": "Reset Pin 0" + }, + { + "name": "Reset Pin 1", + "value": 1, + "description": "Reset Pin 1" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-5", + "name": "xSPI_LOOPBACK_DQS_PIN_SEL", + "description": "xSPI_LOOPBACK_DQS_PIN_SEL\n0-Secondary (dummy) DQS pin\n1-Standard DQS pin", + "values": [ + { + "name": "Secondary", + "value": 0, + "description": "Secondary (dummy) DQS pin" + }, + { + "name": "1", + "value": 1, + "description": "Standard DQS pin" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-6", + "name": "FLEXSPI_PIN_GROUP_SEL", + "description": "FLEXSPI_PIN_GROUP_SEL\n0-Primary group\n1-Secondary group", + "values": [ + { + "name": "0", + "value": 0, + "description": "Primary group" + }, + { + "name": "1", + "value": 1, + "description": "Secondary group" + } + ] + }, + { + "width": 1, + "id": "fuse26-bit-7", + "name": "FLEXSPI_INSTANCE", + "description": "FLEXSPI_INSTANCE\n0-FLEXSPI1\n1-FLEXSPI2", + "values": [ + { + "name": "FLEXSPI1", + "value": 0, + "description": "FLEXSPI1" + }, + { + "name": "FLEXSPI2", + "value": 1, + "description": "FLEXSPI2" + } + ] + }, + { + "width": 5, + "id": "fuse26-bits-8-12", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "FLEXSPI_DELAY_CELL_NUM\nZero - Use the Delay cell value calculated by ROM\nOthers - Use the Delay cell value in terms of 100ps" + }, + { + "width": 3 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse27", + "name": "BOOT_CFG3", + "description": "Fuse 27 [887:880]", + "index_int": "0x001B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse27-bit-0", + "name": "xSPI_NAND_SEARCH_COUNT", + "description": "xSPI_NAND_SEARCH_COUNT\n0-1\n1-2", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + }, + { + "name": "2", + "value": 1, + "description": "2" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-1", + "name": "xSPI_NAND_COL_ADDR_WIDTH", + "description": "xSPI_NAND_COL_ADDR_WIDTH\n0-12 bits\n1-13bits", + "values": [ + { + "name": "12 bits", + "value": 0, + "description": "12 bits" + }, + { + "name": "13bits", + "value": 1, + "description": "13bits" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-2-3", + "name": "xSPI_NAND_CS_INTERVAL", + "description": "xSPI_NAND_CS_INTERVAL\n CS de-asserted interval between two commands\n0-100ns\n1-200ns\n2-400ns\n3-50ns", + "values": [ + { + "name": "100ns", + "value": 0, + "description": "100ns" + }, + { + "name": "200ns", + "value": 1, + "description": "200ns" + }, + { + "name": "400ns", + "value": 2, + "description": "400ns" + }, + { + "name": "50ns", + "value": 3, + "description": "50ns" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-4-5", + "name": "xSPI_NAND_SEARCH_STRIDE", + "description": "xSPI_NAND_SEARCH_STRIDE\n0-64 pages\n1-128 pages\n2-256 pages\n3-32 pages", + "values": [ + { + "name": "64 pages", + "value": 0, + "description": "64 pages" + }, + { + "name": "128 pages", + "value": 1, + "description": "128 pages" + }, + { + "name": "256 pages", + "value": 2, + "description": "256 pages" + }, + { + "name": "32 pages", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 2, + "id": "fuse27-bits-6-7", + "name": "xSPI_NAND_HOLD_TIME", + "description": "xSPI_NAND_HOLD_TIME\nHold Time before issuing Command to FLASH\n0-Wait until FLASH is idle by polling status register in the FLASH\n1-500us \n2-1ms \n3-3ms", + "values": [ + { + "name": "0", + "value": 0, + "description": "Wait until FLASH is idle by polling status register in the FLASH" + }, + { + "name": "500us", + "value": 1, + "description": "500us" + }, + { + "name": "1ms", + "value": 2, + "description": "1ms" + }, + { + "name": "3ms", + "value": 3, + "description": "3ms" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse27-bits-10-11", + "name": "xSPI_NAND_RESET_TYPE", + "description": "xSPI_NAND_RESET_TYPE\n0-No reset\n1-Reset the FLASH by 0xFF\n2-Reset the FLASH by 0x66, 0x99\n3-Reset the FLASH by dedicated Reset Pin", + "values": [ + { + "name": "No reset", + "value": 0, + "description": "No reset" + }, + { + "name": "1", + "value": 1, + "description": "Reset the FLASH by 0xFF" + }, + { + "name": "2", + "value": 2, + "description": "Reset the FLASH by 0x66, 0x99" + }, + { + "name": "3", + "value": 3, + "description": "Reset the FLASH by dedicated Reset Pin" + } + ] + }, + { + "width": 1, + "id": "fuse27-bit-12", + "name": "xSPI_NAND_CONNECTION_SEL", + "description": "xSPI_NAND_CONNECTION_SEL\n0-Connected via PORTA CS0\n1-Connected via PORTB CS0", + "values": [ + { + "name": "0", + "value": 0, + "description": "Connected via PORTA CS0" + }, + { + "name": "1", + "value": 1, + "description": "Connected via PORTB CS0" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse27-bits-16-18", + "name": "xSPI_NAND_FREQ", + "description": "xSPI_NAND_FREQ\n0-80MHz \n1-100MHz \n2-120MHz \n3-133MHz \n4-166MHz \n5-200MHz \n6-60MHz \n7-30MHz", + "values": [ + { + "name": "80MHz", + "value": 0, + "description": "80MHz" + }, + { + "name": "100MHz", + "value": 1, + "description": "100MHz" + }, + { + "name": "120MHz", + "value": 2, + "description": "120MHz" + }, + { + "name": "133MHz", + "value": 3, + "description": "133MHz" + }, + { + "name": "166MHz", + "value": 4, + "description": "166MHz" + }, + { + "name": "200MHz", + "value": 5, + "description": "200MHz" + }, + { + "name": "60MHz", + "value": 6, + "description": "60MHz" + }, + { + "name": "30MHz", + "value": 7, + "description": "30MHz" + } + ] + }, + { + "width": 5 + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse28", + "name": "BOOT_CFG4", + "description": "Fuse 28 [911:904]", + "index_int": "0x001C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse28-bit-0", + "name": "USDHC_PORT", + "description": "USDHC_PORT\n0-USDHC1\n1-USDHC2", + "values": [ + { + "name": "USDHC1", + "value": 0, + "description": "USDHC1" + }, + { + "name": "USDHC2", + "value": 1, + "description": "USDHC2" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-1", + "name": "SION_DISABLE", + "description": "SION_DISABLE\n0-Enable\n1-Disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-2", + "name": "USDHC1_RST_POLARITY", + "description": "USDHC1_RST_POLARITY\n0-Reset active low\n1-Reset active high", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-3", + "name": "USDHC2_RST_POLARITY", + "description": "USDHC2_RST_POLARITY\n0-Reset active low\n1-Reset active high", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 2, + "id": "fuse28-bits-4-5", + "name": "PWR_CYCLE", + "description": "PWR_CYCLE\n0-20ms\n1-10ms\n2-5ms\n3-2.5ms", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-6", + "name": "PWR_CYCLE_EN", + "description": "PWR_CYCLE_EN\n0-No power cycle\n1-Enabled via SD_RST", + "values": [ + { + "name": "0", + "value": 0, + "description": "No power cycle" + }, + { + "name": "1", + "value": 1, + "description": "Enabled via SD_RST" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-7", + "name": "PWR_STABLE_CYCLE", + "description": "PWR_STABLE_CYCLE\n0-5ms\n1-2.5ms", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-8", + "name": "MMC_SPEED", + "description": "MMC_SPEED\n0-Normal\n1-High speed", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal" + }, + { + "name": "High speed", + "value": 1, + "description": "High speed" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-9", + "name": "NO_PREIDLE_STATE", + "description": "NO_PREIDLE_STATE\n0-Issue pre-idle command\n1-Do not issue", + "values": [ + { + "name": "0", + "value": 0, + "description": "Issue pre-idle command" + }, + { + "name": "Do not issue", + "value": 1, + "description": "Do not issue" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-10", + "name": "USDHC1_VSEL", + "description": "USDHC1_VSEL\n0-3v3\n1-1v8", + "values": [ + { + "name": "3v3", + "value": 0, + "description": "3v3" + }, + { + "name": "1v8", + "value": 1, + "description": "1v8" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-11", + "name": "USDHC2_VSEL", + "description": "USDHC2_VSEL\n0-3v3\n1-1v8", + "values": [ + { + "name": "3v3", + "value": 0, + "description": "3v3" + }, + { + "name": "1v8", + "value": 1, + "description": "1v8" + } + ] + }, + { + "width": 2, + "id": "fuse28-bits-12-13", + "name": "MMC_BUS_WIDTH", + "description": "MMC_BUS_WIDTH\n0-4-bit\n1-8-bit\n2-4-bit DDR\n3-8-bit DDR", + "values": [ + { + "name": "4-bit", + "value": 0, + "description": "4-bit" + }, + { + "name": "8-bit", + "value": 1, + "description": "8-bit" + }, + { + "name": "4-bit DDR", + "value": 2, + "description": "4-bit DDR" + }, + { + "name": "8-bit DDR", + "value": 3, + "description": "8-bit DDR" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-14", + "name": "MMC_FAST_BOOT_EN", + "description": "MMC_FAST_BOOT_EN\n0-Normal boot\n1-Fast boot", + "values": [ + { + "name": "Normal boot", + "value": 0, + "description": "Normal boot" + }, + { + "name": "Fast boot", + "value": 1, + "description": "Fast boot" + } + ] + }, + { + "width": 1, + "id": "fuse28-bit-15", + "name": "MMC_FAST_BOOT_ACK_EN", + "description": "MMC_FAST_BOOT_ACK_EN\n0-Disabled\n1-Enabled", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse29", + "name": "BOOT_CFG5", + "description": "Fuse 29 [959:952]", + "index_int": "0x001D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse29-bit-0", + "name": "SEARCH_COUNT", + "description": "SEARCH_COUNT\n0-1\n1-2", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + }, + { + "name": "2", + "value": 1, + "description": "2" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-1", + "name": "PORT_WIDTH", + "description": "PORT_WIDTH\n0-8-bit\n1-16-bit", + "values": [ + { + "name": "8-bit", + "value": 0, + "description": "8-bit" + }, + { + "name": "16-bit", + "value": 1, + "description": "16-bit" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-2", + "name": "ECC_SEL", + "description": "ECC_SEL\n0-NAND device ECC\n1-SEMC built-in ECC", + "values": [ + { + "name": "0", + "value": 0, + "description": "NAND device ECC" + }, + { + "name": "1", + "value": 1, + "description": "SEMC built-in ECC" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-3", + "name": "SEMC_ECC_MODE", + "description": "SEMC_ECC_MODE\n0-BCH4\n1-BCH8", + "values": [ + { + "name": "BCH4", + "value": 0, + "description": "BCH4" + }, + { + "name": "BCH8", + "value": 1, + "description": "BCH8" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-4", + "name": "EDO_MODE", + "description": "EDO_MODE\n0-EDO mode\n1-Non-EDO mode", + "values": [ + { + "name": "EDO mode", + "value": 0, + "description": "EDO mode" + }, + { + "name": "Non", + "value": 1, + "description": "Non-EDO mode" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-5", + "name": "ACCESS_CMD", + "description": "ACCESS_CMD\n0-IP read\n1-AHB read", + "values": [ + { + "name": "IP read", + "value": 0, + "description": "IP read" + }, + { + "name": "AHB read", + "value": 1, + "description": "AHB read" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-6", + "name": "RDY_POLARITY", + "description": "RDY_POLARITY\n0-High active\n1-Low active", + "values": [ + { + "name": "High active", + "value": 0, + "description": "High active" + }, + { + "name": "Low active", + "value": 1, + "description": "Low active" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-7", + "name": "RDY_CHECK_TYPE", + "description": "RDY_CHECK_TYPE\n0-Via status register\n1-Via R/B# pin", + "values": [ + { + "name": "0", + "value": 0, + "description": "Via status register" + }, + { + "name": "Via R/B# pin", + "value": 1, + "description": "Via R/B# pin" + } + ] + }, + { + "width": 3, + "id": "fuse29-bits-8-10", + "name": "TIMING_MODE", + "description": "TIMING_MODE\n000-Mode0: 10MHz \n001-Mode1: 20MHz \n010-Mode2: 28MHz \n011-Mode3: 33MHz \n100-Mode4: 40MHz \n101-Mode5: 50MHz \n11x-Fastest Mode", + "values": [ + { + "name": "10MHz", + "value": 0, + "description": "Mode0: 10MHz" + }, + { + "name": "20MHz", + "value": 1, + "description": "Mode1: 20MHz" + }, + { + "name": "28MHz", + "value": 2, + "description": "Mode2: 28MHz" + }, + { + "name": "33MHz", + "value": 3, + "description": "Mode3: 33MHz" + }, + { + "name": "40MHz", + "value": 4, + "description": "Mode4: 40MHz" + }, + { + "name": "50MHz", + "value": 5, + "description": "Mode5: 50MHz" + }, + { + "name": "Fastest Mode", + "value": 6, + "description": "Fastest Mode" + } + ] + }, + { + "width": 1 + }, + { + "width": 3, + "id": "fuse29-bits-12-14", + "name": "PCS_SEL", + "description": "PCS_SEL\n000-CSX0\n001-CSX1\n010-CSX2\n011-CSX3\n100-A8\nOthers-CSX0", + "values": [ + { + "name": "CSX0", + "value": 0, + "description": "CSX0" + }, + { + "name": "CSX1", + "value": 1, + "description": "CSX1" + }, + { + "name": "CSX2", + "value": 2, + "description": "CSX2" + }, + { + "name": "CSX3", + "value": 3, + "description": "CSX3" + }, + { + "name": "A8", + "value": 4, + "description": "A8" + } + ] + }, + { + "width": 1 + }, + { + "width": 4, + "id": "fuse29-bits-16-19", + "name": "BOOT_SEARCH_STRIDE", + "description": "BOOT_SEARCH_STRIDE\n Search Stride for FCB and DBBT Search strides in terms of page\nzero: 64 \nother: Value = 2^(BOOT_SEARCH_STRIDE)" + }, + { + "width": 3, + "id": "fuse29-bits-20-22", + "name": "ROW_COL_ADDR_MODE", + "description": "ROW_COL_ADDR_MODE\n Applicable only for non-ONFI devices\n00x-5 bytes (CA2+RA3) \n010-4 bytes (CA2+RA2) \n011-3 bytes (CA2+RA1) \n10x-4 bytes (CA1+RA3) \n110-3 bytes (CA1+RA2) \n111-2 bytes (CA1+RA1)", + "values": [ + { + "name": "00x", + "value": 0, + "description": "5 bytes (CA2+RA3)" + }, + { + "name": "010", + "value": 2, + "description": "4 bytes (CA2+RA2)" + }, + { + "name": "011", + "value": 3, + "description": "3 bytes (CA2+RA1)" + }, + { + "name": "10x", + "value": 4, + "description": "4 bytes (CA1+RA3)" + }, + { + "name": "110", + "value": 6, + "description": "3 bytes (CA1+RA2)" + }, + { + "name": "111", + "value": 7, + "description": "2 bytes (CA1+RA1)" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-23", + "name": "STATUS_CMD_TYPE", + "description": "STATUS_CMD_TYPE\nApplicable only fornon-ONFI devices\n0-Common (0x70)\n1-Enhanced (0x78)", + "values": [ + { + "name": "Common", + "value": 0, + "description": "Common (0x70)" + }, + { + "name": "Enhanced", + "value": 1, + "description": "Enhanced (0x78)" + } + ] + }, + { + "width": 3, + "id": "fuse29-bits-24-26", + "name": "COL_ADDRESS_WIDTH", + "description": "COL_ADDRESS_WIDTH\n000-12bits \n001-09bits \n010-10bits \n011-11bits \n100-13bits \n101-14bits \n110-15bits \n111-16bits", + "values": [ + { + "name": "12bits", + "value": 0, + "description": "12bits" + }, + { + "name": "09bits", + "value": 1, + "description": "09bits" + }, + { + "name": "10bits", + "value": 2, + "description": "10bits" + }, + { + "name": "11bits", + "value": 3, + "description": "11bits" + }, + { + "name": "13bits", + "value": 4, + "description": "13bits" + }, + { + "name": "14bits", + "value": 5, + "description": "14bits" + }, + { + "name": "15bits", + "value": 6, + "description": "15bits" + }, + { + "name": "16bits", + "value": 7, + "description": "16bits" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-27", + "name": "DEV_ECC_INIT_STATUS", + "description": "DEV_ECC_INIT_STATUS (Applicable only for non-ONFI devices)\n0-Enabled\n1-Disabled", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 3, + "id": "fuse29-bits-28-30", + "name": "Pages_In_Block", + "description": "Pages_In_Block\n000-128 \n001-8 \n010-16 \n011-32 \n100-64 \n101-256 \n110-512 \n111-1024", + "values": [ + { + "name": "128", + "value": 0, + "description": "128" + }, + { + "name": "8", + "value": 1, + "description": "8" + }, + { + "name": "16", + "value": 2, + "description": "16" + }, + { + "name": "32", + "value": 3, + "description": "32" + }, + { + "name": "64", + "value": 4, + "description": "64" + }, + { + "name": "256", + "value": 5, + "description": "256" + }, + { + "name": "512", + "value": 6, + "description": "512" + }, + { + "name": "1024", + "value": 7, + "description": "1024" + } + ] + }, + { + "width": 1, + "id": "fuse29-bit-31", + "name": "ONFI_COMPLIANCE_SEL", + "description": "ONFI_COMPLIANCE_SEL\n0-ONFI 1.0\n1-Non-ONFI", + "values": [ + { + "name": "ONFI 1.0", + "value": 0, + "description": "ONFI 1.0" + }, + { + "name": "Non-ONFI", + "value": 1, + "description": "Non-ONFI" + } + ] + } + ] + }, + { + "id": "fuse30", + "name": "BOOT_CFG6", + "description": "Fuse 30 [991:984]", + "index_int": "0x001E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse30-bit-0", + "name": "USDHC_PORT", + "description": "USDHC_PORT\n0-USDHC1\n1-USDHC2", + "values": [ + { + "name": "USDHC1", + "value": 0, + "description": "USDHC1" + }, + { + "name": "USDHC2", + "value": 1, + "description": "USDHC2" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-1", + "name": "SION_DISABLE", + "description": "SION_DISABLE\n0-Enable\n1-Disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-2", + "name": "USDHC1_RST_POLARITY", + "description": "USDHC1_RST_POLARITY\n0-Reset active low\n1-Reset active high", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-3", + "name": "USDHC2_RST_POLARITY", + "description": "USDHC2_RST_POLARITY\n0-Reset active low\n1-Reset active high", + "values": [ + { + "name": "0", + "value": 0, + "description": "Reset active low" + }, + { + "name": "1", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 2, + "id": "fuse30-bits-4-5", + "name": "PWR_CYCLE", + "description": "PWR_CYCLE\n0-20ms\n1-10ms\n2-5ms\n3-2.5ms", + "values": [ + { + "name": "20ms", + "value": 0, + "description": "20ms" + }, + { + "name": "10ms", + "value": 1, + "description": "10ms" + }, + { + "name": "5ms", + "value": 2, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 3, + "description": "2.5ms" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-6", + "name": "PWR_CYCLE_EN", + "description": "PWR_CYCLE_EN\n0-No power cycle\n1-Enabled via SD_RST", + "values": [ + { + "name": "0", + "value": 0, + "description": "No power cycle" + }, + { + "name": "1", + "value": 1, + "description": "Enabled via SD_RST" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-7", + "name": "PWR_STABLE_CYCLE", + "description": "PWR_STABLE_CYCLE\n0-5ms\n1-2.5ms", + "values": [ + { + "name": "5ms", + "value": 0, + "description": "5ms" + }, + { + "name": "2.5ms", + "value": 1, + "description": "2.5ms" + } + ] + }, + { + "width": 2, + "id": "fuse30-bits-8-9", + "name": "SD_SPEED", + "description": "SD_SPEED\n0-Normal (SDR12)\n1-High (SDR25)\n2-SDR50\n3-SDR104", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal (SDR12)" + }, + { + "name": "High", + "value": 1, + "description": "High (SDR25)" + }, + { + "name": "SDR50", + "value": 2, + "description": "SDR50" + }, + { + "name": "SDR104", + "value": 3, + "description": "SDR104" + } + ] + }, + { + "width": 1, + "id": "fuse30-bit-10", + "name": "SD_BUS_WIDTH", + "description": "SD_BUS_WIDTH\n0-1-bit\n1-4-bit", + "values": [ + { + "name": "1-bit", + "value": 0, + "description": "1-bit" + }, + { + "name": "4-bit", + "value": 1, + "description": "4-bit" + } + ] + }, + { + "width": 11 + }, + { + "width": 2, + "id": "fuse30-bits-22-23", + "name": "DLL_DELAY_CALIB_STEP", + "description": "DLL_DELAY_CALIB_STEP\n00-1 \n01-2 \n10-4 \n11-6", + "values": [ + { + "name": "1", + "value": 0, + "description": "1" + }, + { + "name": "2", + "value": 1, + "description": "2" + }, + { + "name": "4", + "value": 2, + "description": "4" + }, + { + "name": "6", + "value": 3, + "description": "6" + } + ] + }, + { + "width": 7, + "id": "fuse30-bits-24-30", + "name": "DLL_DELAY_CALIB_START", + "description": "DLL_DELAY_CALIB_START\n DLL tuning start" + }, + { + "width": 1, + "id": "fuse30-bit-31", + "name": "DLL_DELAY_OVERRIDE", + "description": "DLL_DELAY_OVERRIDE\n0-DLL Slave Mode\n1-DLL Override Mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "DLL Slave Mode" + }, + { + "name": "1", + "value": 1, + "description": "DLL Override Mode" + } + ] + } + ] + }, + { + "id": "fuse31", + "name": "BOOT_CFG7", + "description": "Fuse 31 [1023:1016]", + "index_int": "0x001F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 6, + "id": "fuse31-bits-0-5", + "name": "2ND_IMG_OFFSET", + "description": "2ND_IMG_OFFSET\nzero - No 2nd physical image present\nOtherwise - 2nd physical image located at 2ND_IMG_SIZE_UNIT* 2ND_IMG_OFFSET" + }, + { + "width": 2, + "id": "fuse31-bits-6-7", + "name": "2ND_IMG_SIZE_UNIT", + "description": "2ND_IMG_SIZE_UNIT\n0-256KB \n1-1MB \n2-4MB \n3-16MB", + "values": [ + { + "name": "256KB", + "value": 0, + "description": "256KB" + }, + { + "name": "1MB", + "value": 1, + "description": "1MB" + }, + { + "name": "4MB", + "value": 2, + "description": "4MB" + }, + { + "name": "16MB", + "value": 3, + "description": "16MB" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-8", + "name": "WDOG_EN", + "description": "WDOG_EN\n0-Disable all WDOGs during boot\n1-Keep WDOG1 enabled during boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable all WDOGs during boot" + }, + { + "name": "Enable", + "value": 1, + "description": "Keep WDOG1 enabled during boot" + } + ] + }, + { + "width": 3, + "id": "fuse31-bits-9-11", + "name": "WDOG_TIMEOUT_SEL", + "description": "WDOG_TIMEOUT_SEL\n0-128s \n1-64s \n2-32s \n3-16s \n4-8s \nOthers-4s", + "values": [ + { + "name": "128s", + "value": 0, + "description": "128s" + }, + { + "name": "64s", + "value": 1, + "description": "64s" + }, + { + "name": "32s", + "value": 2, + "description": "32s" + }, + { + "name": "16s", + "value": 3, + "description": "16s" + }, + { + "name": "8s", + "value": 4, + "description": "8s" + } + ] + }, + { + "width": 4 + }, + { + "width": 1, + "id": "fuse31-bit-16", + "name": "POR_PRELOAD_CM33_TCM_ECC", + "description": "POR_PRELOAD_CM33_TCM_ECC\n0-Not load\n1-load", + "values": [ + { + "name": "Not load", + "value": 0, + "description": "Not load" + }, + { + "name": "load", + "value": 1, + "description": "load" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-17", + "name": "POR_PRELOAD_CM7_TCM_ECC", + "description": "POR_PRELOAD_CM7_TCM_ECC\n0-Not load\n1-load", + "values": [ + { + "name": "Not load", + "value": 0, + "description": "Not load" + }, + { + "name": "load", + "value": 1, + "description": "load" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-18", + "name": "Release_M7_RST_STAT", + "description": "Release_M7_RST_STAT\n0-RST assert\n1-RST release (Required to access M7TCM)", + "values": [ + { + "name": "RST assert", + "value": 0, + "description": "RST assert" + }, + { + "name": "1", + "value": 1, + "description": "RST release (Required to access M7TCM)" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-19", + "name": "BOOT_FREQ", + "description": "BOOT_FREQ\n0-200MHz derived from RC400M\n1-240MHz derived from PLL480MHz", + "values": [ + { + "name": "0", + "value": 0, + "description": "200MHz derived from RC400M" + }, + { + "name": "1", + "value": 1, + "description": "240MHz derived from PLL480MHz" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-20", + "name": "XMC_CRC32_CHECK_EN", + "description": "XMC_CRC32_CHECK_EN\n0-Disabled\n1-Enabled", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 6 + }, + { + "width": 1, + "id": "fuse31-bit-30", + "name": "INVERT_CM33_PRELOAD", + "description": "INVERT_CM33_PRELOAD\n(impacts POR_PRELOAD_CM33_TCM_ECC)\n0-no invert\n1-invert", + "values": [ + { + "name": "no invert", + "value": 0, + "description": "no invert" + }, + { + "name": "invert", + "value": 1, + "description": "invert" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse32", + "name": "BOOT_CFG8", + "description": "XMCD CRC32 sum value", + "index_int": "0x0020", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + } + ] + }, + { + "group": { + "name": "OEM_SRKH", + "description": "OEM SRK Hash" + }, + "registers": [ + { + "id": "fuse128", + "name": "OEM_SRKH7", + "description": "OEM SRK HASH7", + "index_int": "0x0080", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse129", + "name": "OEM_SRKH6", + "description": "OEM SRK HASH6", + "index_int": "0x0081", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse130", + "name": "OEM_SRKH5", + "description": "OEM SRK HASH5", + "index_int": "0x0082", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse131", + "name": "OEM_SRKH4", + "description": "OEM SRK HASH4", + "index_int": "0x0083", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse132", + "name": "OEM_SRKH3", + "description": "OEM SRK HASH3", + "index_int": "0x0084", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse133", + "name": "OEM_SRKH2", + "description": "OEM SRK HASH2", + "index_int": "0x0085", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse134", + "name": "OEM_SRKH1", + "description": "OEM SRK HASH1", + "index_int": "0x0086", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse135", + "name": "OEM_SRKH0", + "description": "OEM SRK HASH0", + "index_int": "0x0087", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse4", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + } + ] + }, + { + "group": { + "name": "OTFAD", + "description": "OTFAD configuration" + }, + "registers": [ + { + "id": "fuse178", + "name": "OTFAD2_KEY3", + "description": "OTFAD2 key 3", + "index_int": "0x00B2", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse179", + "name": "OTFAD2_KEY2", + "description": "OTFAD2 key 2", + "index_int": "0x00B3", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse180", + "name": "OTFAD2_KEY1", + "description": "OTFAD2 key 1", + "index_int": "0x00B4", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse181", + "name": "OTFAD2_KEY0", + "description": "OTFAD2 key 0", + "index_int": "0x00B5", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse182", + "name": "OTFAD2_CFG", + "description": "Fuse 182", + "index_int": "0x00B6", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 3, + "access": "none" + }, + { + "width": 1, + "id": "fuse182-bit-3", + "name": "OTFAD2_ENABLE", + "description": "OTFAD2 enable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse182-bit-4", + "name": "OTFAD2_DISABLE_OVERRIDE", + "description": "OTFAD2 disable override", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse182-bit-5", + "name": "OTFAD2_KEY_BLOB_EN", + "description": "OTFAD2 key blob enable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse182-bit-6", + "name": "OTFAD2_KEY_SCRAMBLE_CRC_EN", + "description": "OTFAD2 key scramble CRC enable, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse182-bit-7", + "name": "OTFAD2_KEY_SCRAMBLE_EN", + "description": "OTFAD2 key scramble enable, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8, + "id": "fuse182-bits-8-15", + "name": "OTFAD2_KEY_SCRAMBLE_ALIGN", + "description": "OTFAD2 key scramble align, write-only", + "access": "WO" + }, + { + "width": 1, + "id": "fuse182-bit-16", + "name": "OTFAD2_RESTRICT_OTFAD_IPS", + "description": "OTFAD2 restrictOTFAD IPS, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 15, + "access": "none" + } + ] + }, + { + "id": "fuse183", + "name": "OTFAD2_KEY_SCRAMBLE", + "description": "OTFAD2 key scramble", + "index_int": "0x00B7", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse6", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse184", + "name": "OTFAD1_KEY3", + "description": "OTFAD1 key 3", + "index_int": "0x00B8", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse185", + "name": "OTFAD1_KEY2", + "description": "OTFAD1 key 2", + "index_int": "0x00B9", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse186", + "name": "OTFAD1_KEY1", + "description": "OTFAD1 key 1", + "index_int": "0x00BA", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse187", + "name": "OTFAD1_KEY0", + "description": "OTFAD1 key 0", + "index_int": "0x00BB", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse188", + "name": "OTFAD1_CFG", + "description": "Fuse 188", + "index_int": "0x00BC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 3, + "access": "none" + }, + { + "width": 1, + "id": "fuse188-bit-3", + "name": "OTFAD1_ENABLE", + "description": "OTFAD1 enable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse188-bit-4", + "name": "OTFAD1_DISABLE_OVERRIDE", + "description": "OTFAD1 disable override", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse188-bit-5", + "name": "OTFAD1_KEY_BLOB_EN", + "description": "OTFAD1 key blob enable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse188-bit-6", + "name": "OTFAD1_KEY_SCRAMBLE_CRC_EN", + "description": "OTFAD1 key scramble CRC enable, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse188-bit-7", + "name": "OTFAD1_KEY_SCRAMBLE_EN", + "description": "OTFAD1 key scramble enable, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8, + "id": "fuse188-bits-8-15", + "name": "OTFAD1_KEY_SCRAMBLE_ALIGN", + "description": "OTFAD1 key scramble align, write-only", + "access": "WO" + }, + { + "width": 1, + "id": "fuse188-bit-16", + "name": "OTFAD1_RESTRICT_OTFAD_IPS", + "description": "OTFAD1RESTRICT OTFAD IPS, write-only", + "access": "WO", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 15, + "access": "none" + } + ] + }, + { + "id": "fuse189", + "name": "OTFAD1_KEY_SCRAMBLE", + "description": "OTFAD1 key scramble", + "index_int": "0x00BD", + "access": "WO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + } + ] + }, + { + "group": { + "name": "MISC", + "description": "MISC configuration" + }, + "registers": [ + { + "id": "fuse312", + "name": "USB1", + "description": "Fuse 312", + "index_int": "0x0138", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse312-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse312-bits-16-31", + "name": "USB1_PID", + "description": "USB0 Product ID" + } + ] + }, + { + "id": "fuse313", + "name": "USB2", + "description": "Fuse 313", + "index_int": "0x0139", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse313-bits-0-15", + "name": "USB2_PID", + "description": "USB1 Product ID" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse315", + "name": "MAC1_ADDR_31_0", + "description": "MAC_0 Address", + "index_int": "0x013B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse316", + "name": "MAC1_MAC2", + "description": "Fuse 316", + "index_int": "0x013C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse316-bits-0-15", + "name": "MAC1_ADDR_47_32", + "description": "MAC_0 Address" + }, + { + "width": 16, + "id": "fuse316-bits-16-31", + "name": "MAC2_ADDR_47_32", + "description": "MAC_1 Address" + } + ] + }, + { + "id": "fuse317", + "name": "MAC2_ADDR_31_0", + "description": "MAC_1 Address", + "index_int": "0x013D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse318", + "name": "MAC3_ADDR_31_0", + "description": "MAC_2 Address", + "index_int": "0x013E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse319", + "name": "MAC3_MAC4", + "description": "Fuse 319", + "index_int": "0x013F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse319-bits-0-15", + "name": "MAC3_ADDR_47_32", + "description": "MAC_2 Address" + }, + { + "width": 16, + "id": "fuse319-bits-16-31", + "name": "MAC4_ADDR_47_32", + "description": "MAC_3 Address" + } + ] + }, + { + "id": "fuse320", + "name": "MAC4_ADDR_31_0", + "description": "MAC_3 Address", + "index_int": "0x0140", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse321", + "name": "MAC5_ADDR_31_0", + "description": "MAC_4 Address", + "index_int": "0x0141", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + } + }, + { + "id": "fuse322", + "name": "MAC5_MAC6", + "description": "Fuse 322", + "index_int": "0x0142", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse322-bits-0-15", + "name": "MAC5_ADDR_47_32", + "description": "MAC_4 Address" + }, + { + "width": 16, + "id": "fuse322-bits-16-31", + "name": "MAC6_ADDR_47_32", + "description": "MAC_5 Address" + } + ] + }, + { + "id": "fuse323", + "name": "MAC6_ADDR_31_0", + "description": "MAC_5 Address", + "index_int": "0x0143", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse324", + "name": "MAC7_ADDR_31_0", + "description": "MAC_6 Address", + "index_int": "0x0144", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse325", + "name": "MAC7_MAC8", + "description": "Fuse 325", + "index_int": "0x0145", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse325-bits-0-15", + "name": "MAC7_ADDR_47_32", + "description": "MAC_6 Address" + }, + { + "width": 16, + "id": "fuse325-bits-16-31", + "name": "MAC8_ADDR_47_32", + "description": "MAC_7 Address" + } + ] + }, + { + "id": "fuse326", + "name": "MAC8_ADDR_31_0", + "description": "MAC_7 Address", + "index_int": "0x0146", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse327", + "name": "MISC", + "description": "Fuse 327", + "index_int": "0x0147", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse327-bit-0", + "name": "MAC_ADDR_DISABLE", + "description": "MAC ADDR Disable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse327-bit-1", + "name": "USB_ADDR_DISABLE", + "description": "USB ADDR Disable", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2, + "id": "fuse327-bits-2-3", + "name": "CM33_TCM_CFG", + "description": "CM33 TCM configuration", + "values": [ + { + "name": "REGULAR_TCM", + "value": 0, + "description": "REGULAR_TCM (128 kB Code TCM, 128 kB Sys TCM);" + }, + { + "name": "DOUBLE_CODE_TCM", + "value": 1, + "description": "DOUBLE_CODE_TCM (256 kB Code TCM);" + }, + { + "name": "DOUBLE_SYS_TCM", + "value": 2, + "description": "DOUBLE_SYS_TCM (256 kB Sys TCM);" + } + ] + }, + { + "width": 3, + "id": "fuse327-bits-4-6", + "name": "CM7_TCM_CFG", + "description": "CM7 TCM configuration", + "values": [ + { + "name": "REGULAR_TCM", + "value": 0, + "description": "REGULAR_TCM (256 kB ITCM, 256 kB DTCM)" + }, + { + "name": "DOUBLE_ITCM", + "value": 1, + "description": "DOUBLE_ITCM (512 kB ITCM)" + }, + { + "name": "DOUBLE_DTCM", + "value": 2, + "description": "DOUBLE_DTCM (512 kB DTCM)" + }, + { + "name": "HALF_ITCM", + "value": 4, + "description": "HALF_ITCM (128 kB ITCM, 384 kB DTCM)" + }, + { + "name": "HALF_DTCM", + "value": 5, + "description": "HALF_DTCM (384 kB ITCM, 128 kB DTCM)" + } + ] + }, + { + "width": 2, + "id": "fuse327-bits-7-8", + "name": "FORCE_EWMOUT", + "description": "EWM_FORCE_OUT", + "values": [ + { + "name": "00", + "value": 0, + "description": "No EWM_OUT output is forced to GPIO, user should use IOMUXC to configure pinmux and select GPIO to output EWM_OUT" + }, + { + "name": "01", + "value": 1, + "description": "EWM_OUT output is forced to GPIO_AON_27 (ALT7), GPIO_AON_27 IOMUXC control register is override and no longer works." + }, + { + "name": "10", + "value": 2, + "description": "EWM_OUT output is forced to GPIO_AD_12 (ALT7), GPIO_AD_12 IOMUXC control register is override and no longer works." + }, + { + "name": "11", + "value": 3, + "description": "EWM_OUT output is forced to GPIO_AD_29 (ALT7), GPIO_AD_29 IOMUXC control register is" + } + ] + }, + { + "width": 23 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/database.yaml new file mode 100644 index 0000000..af61bc3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/database.yaml @@ -0,0 +1,37 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt595s + +# General MCU information +info: + memory_map: + flexspi0_ns: + start_int: "0x08000000" + size_int: "0x04000000" + external: true + flexspi0_s: + start_int: "0x18000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi0_ns + flexspi1_ns: + start_int: "0x28000000" + size_int: "0x04000000" + external: true + flexspi1_s: + start_int: "0x38000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi1_ns + sram: + start_int: 0x20080000 + size_int: 0x280000 + external: false + non_xip_type: int_ram + usb-ram: + start_int: 0x40140000 + size_int: 0x4000 + external: false + non_xip_type: int_ram diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/tz.json new file mode 100644 index 0000000..2c622db --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt533s/tz.json @@ -0,0 +1,2293 @@ +{ + "cpu": "mimxrt533s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Secure vector table address (vtor_addr)", + "description": "TrustZone register - Secure vector table address (vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Non-secure vector table address (vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (sau_ctrl)", + "description": "TrustZone register - SAU Control Register (sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "description": "TrustZone register - ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 0 (qospi4_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 0 (qospi4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 1 (qospi4_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 1 (qospi4_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 2 (qospi4_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 2 (qospi4_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 3 (qospi4_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 3 (qospi4_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "description": "TrustZone register - RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "description": "TrustZone register - RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "description": "TrustZone register - RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "description": "TrustZone register - RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "description": "TrustZone register - RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "description": "TrustZone register - RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "description": "TrustZone register - RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "description": "TrustZone register - RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "description": "TrustZone register - RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "description": "TrustZone register - RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "description": "TrustZone register - RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "description": "TrustZone register - RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "description": "TrustZone register - RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "description": "TrustZone register - RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "description": "TrustZone register - RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "description": "TrustZone register - RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "description": "TrustZone register - RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "description": "TrustZone register - RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "description": "TrustZone register - RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "description": "TrustZone register - RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "description": "TrustZone register - RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "description": "TrustZone register - RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "description": "TrustZone register - RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "description": "TrustZone register - RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "description": "TrustZone register - RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "description": "TrustZone register - RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "description": "TrustZone register - RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "description": "TrustZone register - RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "description": "TrustZone register - RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "description": "TrustZone register - RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "description": "TrustZone register - RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "description": "TrustZone register - RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "description": "TrustZone register - RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "description": "TrustZone register - RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "description": "TrustZone register - RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "description": "TrustZone register - RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "description": "TrustZone register - RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "description": "TrustZone register - RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "description": "TrustZone register - RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "description": "TrustZone register - RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "description": "TrustZone register - RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "description": "TrustZone register - RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "description": "TrustZone register - RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "description": "TrustZone register - RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "description": "TrustZone register - RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "description": "TrustZone register - RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "description": "TrustZone register - RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "description": "TrustZone register - RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "description": "TrustZone register - RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "description": "TrustZone register - RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "description": "TrustZone register - RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "description": "TrustZone register - RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "description": "TrustZone register - RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "description": "TrustZone register - RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "description": "TrustZone register - RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "description": "TrustZone register - RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "description": "TrustZone register - RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "description": "TrustZone register - RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "description": "TrustZone register - RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "description": "TrustZone register - RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "description": "TrustZone register - RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "description": "TrustZone register - RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "description": "TrustZone register - RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "description": "TrustZone register - RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "RAM5 Slave Rule Register (ram5_slave_rule)", + "description": "TrustZone register - RAM5 Slave Rule Register (ram5_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "description": "TrustZone register - RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "description": "TrustZone register - RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "description": "TrustZone register - RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "description": "TrustZone register - RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "description": "TrustZone register - RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "description": "TrustZone register - RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "description": "TrustZone register - RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "description": "TrustZone register - RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "description": "TrustZone register - RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "description": "TrustZone register - RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "description": "TrustZone register - RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "description": "TrustZone register - RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "description": "TrustZone register - RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "description": "TrustZone register - RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "description": "TrustZone register - RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "description": "TrustZone register - RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "RAM6 Slave Rule Register (ram6_slave_rule)", + "description": "TrustZone register - RAM6 Slave Rule Register (ram6_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "description": "TrustZone register - RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "description": "TrustZone register - RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "description": "TrustZone register - RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "description": "TrustZone register - RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "description": "TrustZone register - RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "description": "TrustZone register - RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "description": "TrustZone register - RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "description": "TrustZone register - RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "description": "TrustZone register - RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "description": "TrustZone register - RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "description": "TrustZone register - RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "description": "TrustZone register - RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "description": "TrustZone register - RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "description": "TrustZone register - RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "description": "TrustZone register - RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "description": "TrustZone register - RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "RAM7 Slave Rule Register (ram7_slave_rule)", + "description": "TrustZone register - RAM7 Slave Rule Register (ram7_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "description": "TrustZone register - RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "description": "TrustZone register - RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "description": "TrustZone register - RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "description": "TrustZone register - RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "description": "TrustZone register - RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "description": "TrustZone register - RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "description": "TrustZone register - RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "description": "TrustZone register - RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "description": "TrustZone register - RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "description": "TrustZone register - RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "description": "TrustZone register - RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "description": "TrustZone register - RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "description": "TrustZone register - RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "description": "TrustZone register - RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "description": "TrustZone register - RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "description": "TrustZone register - RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "RAM8 Slave Rule Register (ram8_slave_rule)", + "description": "TrustZone register - RAM8 Slave Rule Register (ram8_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "description": "TrustZone register - RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "description": "TrustZone register - RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "description": "TrustZone register - RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "description": "TrustZone register - RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram82_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram82_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram82_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram82_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram82_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram82_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram82_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram82_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram83_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram83_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram83_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram83_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram83_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram83_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram83_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram83_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "(ezh_ram_slave_rule)", + "description": "TrustZone register - (ezh_ram_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule0)", + "description": "TrustZone register - (ezh_ram0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule1)", + "description": "TrustZone register - (ezh_ram0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule2)", + "description": "TrustZone register - (ezh_ram0_slave_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule3)", + "description": "TrustZone register - (ezh_ram0_slave_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qospi1_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qospi1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qospi10_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qospi10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qospi10_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qospi10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qospi10_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qospi10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qospi10_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qospi10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qospi11_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qospi11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qospi11_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qospi11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qospi11_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qospi11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qospi11_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qospi11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qospi12_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qospi12_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qospi12_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qospi12_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qospi12_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qospi12_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qospi12_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qospi12_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qospi13_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qospi13_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qospi13_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qospi13_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qospi13_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qospi13_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qospi13_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qospi13_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 0 (qospi14_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 0 (qospi14_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 1 (qospi14_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 1 (qospi14_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 2 (qospi14_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 2 (qospi14_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 3 (qospi14_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 3 (qospi14_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "AIPS Bridge Slave Rule Register (aips_bridge_slave_rule0)", + "description": "TrustZone register - AIPS Bridge Slave Rule Register (aips_bridge_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field41C", + "offset_int": "0x41c", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field420", + "offset_int": "0x420", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field424", + "offset_int": "0x424", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field428", + "offset_int": "0x428", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (security_ctrl_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (security_ctrl_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field42C", + "offset_int": "0x42c", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field430", + "offset_int": "0x430", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field434", + "offset_int": "0x434", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field438", + "offset_int": "0x438", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field43C", + "offset_int": "0x43c", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field440", + "offset_int": "0x440", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field444", + "offset_int": "0x444", + "reg_width": 32, + "name": "Secure GPIO Register 4 (sec_gp_reg4)", + "description": "TrustZone register - Secure GPIO Register 4 (sec_gp_reg4)", + "default_value_int": "0xffffffff" + }, + { + "id": "field448", + "offset_int": "0x448", + "reg_width": 32, + "name": "Secure GPIO Register 5 (sec_gp_reg5)", + "description": "TrustZone register - Secure GPIO Register 5 (sec_gp_reg5)", + "default_value_int": "0xffffffff" + }, + { + "id": "field44C", + "offset_int": "0x44c", + "reg_width": 32, + "name": "Secure GPIO Register 6 (sec_gp_reg6)", + "description": "TrustZone register - Secure GPIO Register 6 (sec_gp_reg6)", + "default_value_int": "0xffffffff" + }, + { + "id": "field450", + "offset_int": "0x450", + "reg_width": 32, + "name": "Secure GPIO Register 7 (sec_gp_reg7)", + "description": "TrustZone register - Secure GPIO Register 7 (sec_gp_reg7)", + "default_value_int": "0xffffffff" + }, + { + "id": "field454", + "offset_int": "0x454", + "reg_width": 32, + "name": "Secure GPIO Register 8 for DSP (sec_gp_reg8)", + "description": "TrustZone register - Secure GPIO Register 8 for DSP (sec_gp_reg8)", + "default_value_int": "0xffffffff" + }, + { + "id": "field458", + "offset_int": "0x458", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaaaa" + }, + { + "id": "field45C", + "offset_int": "0x45c", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field460", + "offset_int": "0x460", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field464", + "offset_int": "0x464", + "reg_width": 32, + "name": "M33 Lock Control Register (m33_lock_reg)", + "description": "TrustZone register - M33 Lock Control Register (m33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field468", + "offset_int": "0x468", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field46C", + "offset_int": "0x46c", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field470", + "offset_int": "0x470", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt555s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt555s/database.yaml new file mode 100644 index 0000000..cb18346 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt555s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt595s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/database.yaml new file mode 100644 index 0000000..35bbcc1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/database.yaml @@ -0,0 +1,322 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + b0: {} +latest: b0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt5xx + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT500 + memory_map: + flexspi0_ns: + start_int: "0x08000000" + size_int: "0x04000000" + external: true + flexspi0_s: + start_int: "0x18000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi0_ns + flexspi1_ns: + start_int: "0x28000000" + size_int: "0x04000000" + external: true + flexspi1_s: + start_int: "0x38000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi1_ns + sram: + start_int: "0x20080000" + size_int: "0x480000" + external: false + non_xip_type: int_ram + usb-ram: + start_int: "0x40140000" + size_int: "0x4000" + external: false + non_xip_type: int_ram + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0023 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + grouped_registers: + - uid: otfad_kek_seed + name: OTFAD_KEK_SEED + width: 128 + reversed: True + config_as_hexstring: True + description: + "When OTP key store is used (USE_PUF = 0), this 128-bit user + programmed value is used to derive OTFAD_KEK.\n\nOTFAD_KEK[127:0] = + AES_ENCRYPT (OTP_MASTER_KEK, OTFAD_KEK_SEED[127:0])" + sub_regs: ["fuse108", "fuse109", "fuse110", "fuse111"] + - uid: otp_master_key + name: OTP_MASTER_KEY + width: 256 + config_as_hexstring: True + description: "Master Key used to derive different usage keys (HMAC_KEY, + ENC_IMAGE_KEY, SB2_KEK, OTFAD_KEK). \n- ENC_BOOT_HMAC_KEY[127:0] = + AES_ENCRYPT (OTP_MASTER_KEK, 0x00000000000000000000000000000000)\n- + ENC_BOOT_AES_KEY[256:0] = AES_ENCRYPT (OTP_MASTER_KEK, + 0x00000000000000000000000000000001) || AES_ENCRYPT (OTP_MASTER_KEK, + 0x00000000000000000000000000000002)\n- SB_KEK[256:0] = AES_ENCRYPT + (OTP_MASTER_KEK, 0x00000000000000000000000000000003) || AES_ENCRYPT + (OTP_MASTER_KEK, 0x00000000000000000000000000000004) OR if + SBKEK_SEED != 0 then SB_KEK[255:0] = AES_ENCRYPT (OTP_MASTER_KEK, + SBKEK_SEED[255:0])\n- OTFAD_KEK[127:0] = AES_ENCRYPT + (OTP_MASTER_KEK, OTFAD_KEK_SEED[127:0])" + sub_regs: + [ + "fuse112", + "fuse113", + "fuse114", + "fuse115", + "fuse116", + "fuse117", + "fuse118", + "fuse119", + ] + - uid: rkth + name: RKTH + width: 256 + reversed: True + config_as_hexstring: True + description: + "SHA256 hash digest of hash of four Root Of Trust Keys (modulus || + exponent).\nFor i in 0..3:\n Let M[i] = BE(Modulus i)\n Let + E[i] = BE(Exponent i)\n Let RKH[i] = SHA256( M[i] || E[i] )\n Let + RKTH = SHA256( RKH[0] || RKH[1] || RKH[2] || RKH[3] )\nNote: + Documentation update needed when using blhost due to endianness issue." + sub_regs: + [ + "fuse120", + "fuse121", + "fuse122", + "fuse123", + "fuse124", + "fuse125", + "fuse126", + "fuse127", + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x0010_C000 + size: 0x1000 + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 0 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + signed_ram: + image_type: SIGNED_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinRelocTable + - Mbi_MixinLoadAddress + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinCertBlockV1 + - Mbi_MixinHmacMandatory + - Mbi_MixinKeyStore + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + - Mbi_ExportMixinHmacKeyStoreFinalize + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinRelocTable + - Mbi_MixinLoadAddress + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + encrypted_signed_ram: + image_type: ENCRYPTED_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinRelocTable + - Mbi_MixinLoadAddress + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_MixinKeyStore + - Mbi_MixinHmacMandatory + - Mbi_MixinCtrInitVector + - Mbi_ExportMixinAppTrustZoneCertBlockEncrypt + - Mbi_ExportMixinRsaSign + - Mbi_ExportMixinHmacKeyStoreFinalize + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + signed: signed_ram + encrypted: encrypted_signed_ram + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== Bootable image section ======== + bootable_image: + mem_types: + flexspi_nor: + segments: + keyblob: 0x0000 + fcb: 0x0400 + image_version: 0x0600 + keystore: 0x0800 + mbi: 0x1000 + remap_align: 0x40000 # 256 KB + sd: + segments: + mbi: 0x1000 + emmc: + segments: + mbi: 0x1000 + recovery_spi_sb21: + segments: + sb21: 0x1000 + recovery_spi_mbi: + segments: + mbi: 0x1000 + # ======== Secure binary v2.1 section ======== + sb21: + keyblobs: true + supported_commands: + [ + erase, + load, + enable, + keywrap, + encrypt, + fill, + jump, + version_check, + keystore_to_nv, + keystore_from_nv, + programFuses, + ] + + # ======== Shadow registers section ======== + shadow_regs: + inverted_regs: + fuse95: fuse104 # DCFG_CC_SOCU -> DCFG_CC_SOCU_AP + computed_fields: + fuse95: # DCFG_CC_SOCU + fuse95-bit-31: comalg_dcfg_cc_socu_test_en # DEV_TEST_EN + fuse95-bits-0-7: comalg_dcfg_cc_socu_crc8 # CRC8 + fuse100: # DCFG_CC_SOCU_NS + fuse100-bits-0-7: comalg_dcfg_cc_socu_crc8 # CRC8 + + # ======== Trust Zone section ======== + tz: + reg_spec: tz.json + + # ======== OTFAD section ======== + otfad: + key_blob_rec_size: 64 + key_blob_max_cnt: 4 + key_blob_min_cnt: 4 + byte_swap: false + keyblob_byte_swap_cnt: 0 + sb_21_supported: True + has_kek_fuses: False + additional_template: [] + additional_template_text: "" + + fuses: + _no_verify: True + otp_master_key: __otp_master_key + otfad_kek_seed: __otfad_kek_seed + fuse106: + fuse106-bit-12: 1 + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0, 1] + flexspi_nand: + instances: [0, 1] + sd: + instances: [0, 1] + emmc: + instances: [0, 1] + spi_nor: + reg_spec: ../../common/memcfg/opt_word_spi_nor_legacy.json + instances: [0, 1, 2, 3, 4, 5, 6, 7] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fcb_flexspi_nor.json new file mode 100644 index 0000000..4fe6446 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fcb_flexspi_nor.json @@ -0,0 +1,25599 @@ +{ + "cpu": "MIMXRT595S", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details ", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same ", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3 ", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false ", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution ", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size ", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context ", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use ", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fuses.json new file mode 100644 index 0000000..dc3ee69 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/fuses.json @@ -0,0 +1,3975 @@ +{ + "cpu": "MIMXRT595S", + "shadow_reg_base_addr_int": "0x40130000", + "groups": [ + { + "group": { + "name": "SHADOW_LOCK", + "description": "Fuses used to define read/write access permissions to shadows registers of Customer configured OTP words." + }, + "registers": [ + { + "id": "fuse8", + "name": "CUST_WR_RD_LOCK0", + "description": "Fuses used to define read/write access permissions to shadows registers of Customer configured OTP words. This is a redundant OTP word hence only 16 bits defined.", + "index_int": "0x0008", + "shadow_reg_offset_int": "0x0020", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1, + "id": "fuse8-bit-0", + "name": "DCFG_CC_SOCU_WR", + "description": "When set locks APB write access to DCFG_CC_SOCU and DCFG_CC_SOCU_AP shadow registers. (Fuse 256)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-1", + "name": "DCFG_CC_SOCU_NS_WR", + "description": "When set locks APB write access to DCFG_CC_SOCU_NS shadow registers. (Fuse 257)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-2", + "name": "OTFAD_CFG_WR_LOCK", + "description": "When set locks APB write access to OTFAD_CFG shadow register. (Fuse 258)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse8-bit-4", + "name": "KEY_SCRAMBLE_SEED_WR_LOCK", + "description": "When set locks APB write access to KEY_SCRAMBLE_SEED shadow register. (Fuse 260)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-5", + "name": "KEY_SCRAMBLE_SEED_RD_LOCK", + "description": "When set locks APB read access to KEY_SCRAMBLE_SEED shadow register. (Fuse 261)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-6", + "name": "OTFAD_KEK_SEED_WR_LOCK", + "description": "When set locks APB write access to OTFAD_KEK_SEED shadow registers. (Fuse 262)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse8-bit-8", + "name": "OTP_MASTER_KEY_WR_LOCK", + "description": "When set locks APB write access to OTP_MASTER_KEY shadow registers. (Fuse 264)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-9", + "name": "SEC_BOOT_CFG5_WR_LOCK", + "description": "When set locks APB write access to SEC_BOOT_CFG5 shadow registers. (Fuse 265)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse9", + "name": "CUST_WR_RD_LOCK1", + "description": "Fuses used to define read/write access permissions to shadows registers of customer configured OTP words. This is a redundant OTP word hence only 16 bits defined.", + "index_int": "0x0009", + "shadow_reg_offset_int": "0x0024", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 4 + }, + { + "width": 1, + "id": "fuse9-bit-4", + "name": "CRC4_WR_LOCK", + "description": "When set locks APB write access to CRC4 shadow register. (Fuse 292)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-5", + "name": "CRC4_RD_LOCK", + "description": "When set locks APB read access to CRC4 shadow register. (Fuse 293)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-6", + "name": "CRC5_WR_LOCK", + "description": "When set locks APB write access to CRC5 shadow register. (Fuse 294)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-7", + "name": "CRC5_RD_LOCK", + "description": "When set locks APB read access to CRC5 shadow register. (Fuse 295)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-8", + "name": "CRC6_WR_LOCK", + "description": "When set locks APB write access to CRC6 shadow register. (Fuse 296)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-9", + "name": "CRC6_RD_LOCK", + "description": "When set locks APB read access to CRC6 shadow register. (Fuse 297)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-10", + "name": "CRC7_WR_LOCK", + "description": "When set locks APB write access to CRC7 shadow register. (Fuse 298)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-11", + "name": "CRC7_RD_LOCK", + "description": "When set locks APB read access to CRC7 shadow register. (Fuse 299)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-12", + "name": "BOOT_CFG0_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG0 and RKTH shadow register. (Fuse 300)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-13", + "name": "BOOT_CFG1_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG1 shadow register. (Fuse 301)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-14", + "name": "BOOT_CFG2_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG2 shadow register. (Fuse 302)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-15", + "name": "BOOT_CFG3_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG3 shadow register. (Fuse 303)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "DEBUG_CFG", + "description": "DEBUG_CFG group" + }, + "registers": [ + { + "id": "fuse95", + "name": "DCFG_CC_SOCU", + "description": "Debug Configuration word (tier-1 developer). Use DCFG_CC_SOCU_WR to write lock this OTP word.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x005F", + "shadow_reg_offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0001" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse95-bits-0-7", + "name": "CRC8", + "description": "CRC-8/ITU of upper 3 bytes of this register. Polynomial=0x07, initial value= 0x00, XorOut=0x55.", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse95-bit-8", + "name": "DFLT_NIDEN", + "description": "Fixed state of Non-secure non-invasive debug enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-9", + "name": "DFLT_DBGEN", + "description": "Fixed state of Non-secure invasive debug enable, when PINNED_DBGEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Fixed state of secure non-invasive debug enable, when PINNED_SPNIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-11", + "name": "DFLT_SPIDEN", + "description": "Fixed state of secure invasive debug enable, when PINNED_SPIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-12", + "name": "DFLT_TAPEN", + "description": "Fixed state of Test Access Port enable, when PINNED_TAPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-13", + "name": "DFLT_DSPEN", + "description": "Fixed state of DSP invasive debug enable, when PINNED_DSPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-14", + "name": "DFLT_ISPCMDEN", + "description": "Fixed state of ISP boot flow commands enable, when PINNED_ISPCMDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-15", + "name": "DFLT_PMCMDEN", + "description": "Fixed state of permanent modification commands (set Fault analysis mode) enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-16", + "name": "PINNED_NIDEN", + "description": "Fix the state of Non-secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-17", + "name": "PINNED_DBGEN", + "description": "Fix the state of Non-secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-18", + "name": "PINNED_SPNIDEN", + "description": "Fix the state of secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-19", + "name": "PINNED_SPIDEN", + "description": "Fix the state of secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-20", + "name": "PINNED_TAPEN", + "description": "Fix the state of Test Access Port enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-21", + "name": "PINNED_DSPEN", + "description": "Fix the state of DSP invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-22", + "name": "PINNED_ISPCMDEN", + "description": "Fix the state of ISP boot flow commands enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-23", + "name": "PINNED_PMCMDEN", + "description": "Fix the state of permanent modification commands (set Fault analysis mode) enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-24", + "name": "FORCE_UUID_MATCH", + "description": "When set, debug authentication protocol only accepts \"Debug Credential\" certificates (DC) with matching UUID.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "fuse95-bit-31", + "name": "DEV_TEST_EN", + "description": "Enable test mode.\nThis bit should be clear in OTP words. But during development to test different\nDCFG_CC_SOCU settings without programming OTP words, developers can write the\nvalues to shadow registers corresponding to OTP words (95 & 104) with this bit set.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + }, + { + "id": "fuse100", + "name": "DCFG_CC_SOCU_NS", + "description": "Debug Configuration word (tier-2 developer). Use DCFG_CC_SOCU_NS_WR to write lock this OTP word.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0064", + "shadow_reg_offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse100-bits-0-7", + "name": "CRC8", + "description": "CRC-8/ITU of upper 3 bytes of this register. Polynomial=0x07, initial value= 0x00, XorOut=0x55.", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse100-bit-8", + "name": "DFLT_NIDEN", + "description": "Fixed state of Non-secure non-invasive debug enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-9", + "name": "DFLT_DBGEN", + "description": "Fixed state of Non-secure invasive debug enable, when PINNED_DBGEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Fixed state of secure non-invasive debug enable, when PINNED_SPNIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-11", + "name": "DFLT_SPIDEN", + "description": "Fixed state of secure invasive debug enable, when PINNED_SPIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-12", + "name": "DFLT_TAPEN", + "description": "Fixed state of Test Access Port enable, when PINNED_TAPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-13", + "name": "DFLT_DSPEN", + "description": "Fixed state of DSP invasive debug enable, when PINNED_DSPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-14", + "name": "DFLT_ISPCMDEN", + "description": "Fixed state of ISP boot flow commands enable, when PINNED_ISPCMDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-15", + "name": "DFLT_PMCMDEN", + "description": "Fixed state of permanent modification commands (set Fault analysis mode) enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-16", + "name": "PINNED_NIDEN", + "description": "Fix the state of Non-secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-17", + "name": "PINNED_DBGEN", + "description": "Fix the state of Non-secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-18", + "name": "PINNED_SPNIDEN", + "description": "Fix the state of secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-19", + "name": "PINNED_SPIDEN", + "description": "Fix the state of secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-20", + "name": "PINNED_TAPEN", + "description": "Fix the state of Test Access Port enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-21", + "name": "PINNED_DSPEN", + "description": "Fix the state of DSP invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-22", + "name": "PINNED_ISPCMDEN", + "description": "Fix the state of ISP boot flow commands enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-23", + "name": "PINNED_PMCMDEN", + "description": "Fix the state of permanent modification commands (set Fault analysis mode) enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-24", + "name": "FORCE_UUID_MATCH", + "description": "When set, debug authentication protocol only accepts \"Debug Credential\" certificates (DC) with matching UUID.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "fuse100-bit-31", + "name": "DEV_TEST_EN", + "description": "Enable test mode.\nThis bit should be clear in OTP words. But during development to test different\nDCFG_CC_SOCU settings without programming OTP words, developers can write the\nvalues to shadow registers corresponding to OTP words (95 & 104) with this bit set.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + }, + { + "id": "fuse104", + "name": "DCFG_CC_SOCU_AP", + "description": "Anti-pole (inverse) value of Debug Configuration word(DCFG_CC_SOCU). Use DCFG_CC_SOCU_WR to write lock this OTP word.", + "index_int": "0x0068", + "shadow_reg_offset_int": "0x01A0", + "individual_write_lock": "always_lock", + "calculated": { + "method": "inverse", + "src_register_id": "fuse95" + }, + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0001" + } + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "BOOT_CFG group" + }, + "registers": [ + { + "id": "fuse96", + "name": "BOOT_CFG0", + "description": "Boot configuration word0. Shadow register is present for this word thus SW could access the register directly to read contents.", + "deprecated_names": [ + "BOOT_CFG[0]" + ], + "index_int": "0x0060", + "shadow_reg_offset_int": "0x0180", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse96-bits-0-3", + "name": "PRIMARY_BOOT_SRC", + "description": "Primary boot Source. (a.k.a. Master boot source)", + "values": [ + { + "name": "ISP_PIN_BOOT", + "value": 0, + "description": "ISP pins will determine boot source." + }, + { + "name": "QSPI_BOOT", + "value": 1, + "description": "Boot from Octal/Quad SPI flash device using FlexSpi channel A interface pins." + }, + { + "name": "SDHC0_BOOT", + "value": 2, + "description": "Boot from eMMC device or SD card connected to SDHC0 port." + }, + { + "name": "SDHC1_BOOT", + "value": 3, + "description": "Boot from eMMC device or SD card connected to SDHC1 port." + }, + { + "name": "SPI_SLV_BOOT", + "value": 4, + "description": "Boot using SPI slave interface using master boot mode." + }, + { + "name": "UART_BOOT", + "value": 6, + "description": "Boot using UART interface using master boot mode." + }, + { + "name": "SPI_FC_BOOT", + "value": 7, + "description": "Boot from 1-bit SPI flash device from FlexCom interface pins selected by REDUNDANT_SPI_PORT field. Only load-to-RAM images are supported in this mode." + }, + { + "name": "ISP_MODE", + "value": 9, + "description": "Always enter ISP mode. DEFAULT_ISP_MODE field will determine the ISP interface." + }, + { + "name": "QSPI_REC_BOOT", + "value": 12, + "description": "Boot from Octal/Quad SPI flash device using FlexSPI channel A interface pins. If image is not found check recovery boot using SPI-flash device through FlexComm." + }, + { + "name": "SDHC0_REC_BOOT", + "value": 13, + "description": "Boot from SDHC0 port device. If image is not found check recovery boot using SPI-flash device through FlexComm." + }, + { + "name": "SDHC1_REC_BOOT", + "value": 14, + "description": "Boot from SDHC1 port device. If image is not found check recovery boot using SPI-flash device through FlexComm." + } + ] + }, + { + "width": 3, + "id": "fuse96-bits-4-6", + "name": "DEFAULT_ISP_MODE", + "description": "When a valid image is not available to master boot, ROM switches to ISP mode for programming primary boot devices. This field determines the default ISP mode.", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto detect ISP mode. ROM monitors USB, UART, SPI and I2C interfaces for any activity." + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "Support ISP command interface using USB HID class only." + }, + { + "name": "UART_ISP", + "value": 2, + "description": "Support ISP command interface on UART port only." + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "Support ISP command interface on SPI port only." + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "Support ISP command interface on I2C port only." + }, + { + "name": "DISABLE_ISP", + "value": 7, + "description": "Disable ISP fall through when proper image is not found on primary boot device." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-7", + "name": "BOOT_CLK_SPEED", + "description": "Defines clock speeds during boot.", + "values": [ + { + "name": "NORMAL_CLK", + "value": 0, + "description": "Normal boot. All clocks are set to 48MHz using IRC48M, except USB block. USB block will use external XTAL clock." + }, + { + "name": "HISPEED_CLK", + "value": 1, + "description": "High-speed boot.\n o Core clock is set to 198MHz using main_pll with IRC48M as input\n o UART, I2C : 48MHz (IRC48M)\n o SPI, SDHC: 198MHz (main_pll)\n o USB: external XTAL\n o OSPI: Set to different speed using aux0_pll. Speed of OSPI interface is obtained from Boot Configuration Block present on OSPI-flash device.\n \u00b7 SDR: 30/50/60/72/80/90/100 MHz\n \u00b7 DDR: 30/50/60/72/80 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-8", + "name": "RSA4K_EN", + "description": "Use 4096 bit RSA keys only for certificate validations. By default the ROM assume 2048-bit keys.", + "values": [ + { + "name": "RSA2K", + "value": 0, + "description": "Use RSA2K or higher key length operations to validate certificates, image and debug credentials." + }, + { + "name": "RSA4K", + "value": 1, + "description": "Use RSA4K operations to validate certificates, image and debug credentials." + } + ] + }, + { + "width": 2, + "id": "fuse96-bits-9-10", + "name": "WDT_WAIT", + "description": "Refresh time period for Watchdog timer. IF configured boot ROM starts watchdog timer for the specified refresh period. If the timer is not refreshed or halted SoC reset is issued. This feature is used for detecting denial of service attacks during secure boot.", + "values": [ + { + "name": "WDT_DISABLE", + "value": 0, + "description": "Watchdog timer is disabled." + }, + { + "name": "WDT_250_MS", + "value": 1, + "description": "Refresh timer is set to 250 milliseconds." + }, + { + "name": "WDT_500_MS", + "value": 2, + "description": "Refresh timer is set to 500 milliseconds." + }, + { + "name": "WDT_1000_MS", + "value": 3, + "description": "Refresh timer is set to 500 milliseconds." + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse96-bits-13-14", + "name": "TZM_IMAGE_TYPE", + "description": "TZM_IMAGE_TYPE bit-field", + "values": [ + { + "name": "TZM_NORMAL", + "value": 0, + "description": "TrustZone-M mode is determined by the image header." + }, + { + "name": "TZM_DISABLE", + "value": 1, + "description": "Disable TrustZone-M features. ROM will always boot to a non-secure code and all TZ-M features are disabled." + }, + { + "name": "TZM_ENABLE", + "value": 2, + "description": "TrustZone-M features are enabled. ROM will always boot to secure code." + }, + { + "name": "TZM_PRESET", + "value": 3, + "description": "TrustZone-M features are enabled and setting are loaded from image header and locked before branching to user code." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-15", + "name": "PSA_BSTATE_SKIP", + "description": "If set, ROM skips computation of boot state defined by PSA specification. As part of boot state computation ROM includes OTP words \n- Shadow register values of 95 to 104 \n- Fuse values of words 128 to 147.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-16", + "name": "PSA_BSTATE_INC_KEYS", + "description": "If set, boot state computation includes OTP shadow register values of words 106 to 127.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 3, + "id": "fuse96-bits-17-19", + "name": "REDUNDANT_SPI_PORT", + "description": "FlexComm port to use for redundant SPI flash boot.", + "values": [ + { + "name": "FC0", + "value": 0, + "description": "Use FlexCom0 pins P0_0 (SCK), P0_1 (MISO), P0_2 (MOSI), P0_3 (SEL)" + }, + { + "name": "FC1", + "value": 1, + "description": "Use FlexCom1 pins P0_7 (SCK), P0_8 (MISO), P0_9 (MOSI), P0_10 (SEL)" + }, + { + "name": "FC2", + "value": 2, + "description": "Use FlexCom2 pins P0_14 (SCK), P0_15 (MISO), P0_16 (MOSI), P0_17 (SEL)" + }, + { + "name": "FC3", + "value": 3, + "description": "Use FlexCom3 pins P0_21 (SCK), P0_22 (MISO), P0_23 (MOSI), P0_24 (SEL)" + }, + { + "name": "FC4", + "value": 4, + "description": "Use FlexCom4 pins P0_28 (SCK), P0_29 (MISO), P0_30 (MOSI), P0_31 (SEL)" + }, + { + "name": "FC5", + "value": 5, + "description": "Use FlexCom5 pins P1_3 (SCK), P1_4 (MISO), P1_5 (MOSI), P1_6 (SEL)" + }, + { + "name": "FC6", + "value": 6, + "description": "Use FlexCom6 pins P3_25 (SCK), P3_26 (MISO), P3_27 (MOSI), P3_28 (SEL)" + }, + { + "name": "FC7", + "value": 7, + "description": "Use FlexCom7 pins P4_0 (SCK), P4_1 (MISO), P4_2 (MOSI), P4_3 (SEL)" + } + ] + }, + { + "width": 2, + "id": "fuse96-bits-20-21", + "name": "SECURE_BOOT_EN", + "description": "Force secure image only.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Allow non-secure images with and without CRC. Used during development." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Secure boot is enabled. The images have to be signed and optionally AES-CTR encrypted using pre-shared key. ROM does signature checking first and then does decryption of authenticated image." + }, + { + "name": "ENABLED_2", + "value": 2, + "description": "Secure boot is enabled." + }, + { + "name": "ENABLED_3", + "value": 3, + "description": "Secure boot is enabled." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-22", + "name": "DICE_INC_OTP", + "description": "Include non-field updatable OTP Fields in DICE computation. OTP values in shadow registers are used in computation for words 95, 96, 98, 99, 104, 120 - 127.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-23", + "name": "DICE_SKIP", + "description": "If set, ROM skips computation of Composite Device Identifier (CDI) defined in DICE specification. But ROM will continue to hide UDS source in OTP and PUF (index 15) before passing control to user code.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8, + "id": "fuse96-bits-24-31", + "name": "BOOT_FAIL_PIN", + "description": "GPIO port and pin number to use for indicating boot failure. Boot ROM will drive this pin high before locking the chip on error conditions. Applications can use this pin to power cycle the system.\n[2:0] - Defines GPIO port\n[7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "fuse97", + "name": "BOOT_CFG1", + "description": "Boot configuration word specifying Quad/Octal-SPI flash devices settings.", + "deprecated_names": [ + "BOOT_CFG[1]" + ], + "index_int": "0x0061", + "shadow_reg_offset_int": "0x0184", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse97-bit-0", + "name": "QSPI_AUTO_PROBE_EN", + "description": "Octal/Quad SPI flash auto probe feature enable.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-1-3", + "name": "QSPI_PROBE_TYPE", + "description": "Octal/Quad SPI flash probe type.", + "values": [ + { + "name": "QSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MICRON_OCTAL", + "value": 1, + "description": "Micron Octal FLASH" + }, + { + "name": "MACRONIX_OCTAL", + "value": 2, + "description": "Macronix Octal FLASH" + }, + { + "name": "ADESTO_OCTAL", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-4-6", + "name": "QSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "Use 3byte (24-bit) address read (0x03) by default" + }, + { + "name": "QSPI_ADDR_4B", + "value": 1, + "description": "Use 4byte (32-bit) address read (0x13) by default" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HyperFlash 1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HyperFlash 3V3" + }, + { + "name": "OSPI_DDR_MXIC", + "value": 4, + "description": "MXIC Octal DDR" + }, + { + "name": "OSPI_DDR_MICRON", + "value": 5, + "description": "Micron Octal DDR" + } + ] + }, + { + "width": 4, + "id": "fuse97-bits-7-10", + "name": "QSPI_DUMMY_CYCLES", + "description": "Octal/Quad SPI flash dummy cycles for read command." + }, + { + "width": 3, + "id": "fuse97-bits-11-13", + "name": "QSPI_FREQUENCY", + "description": "Octal/Quad SPI flash interface frequency.", + "values": [ + { + "name": "QSPI_60MHZ", + "value": 0, + "description": "60MHz" + }, + { + "name": "QSPI_80MHZ", + "value": 1, + "description": "80MHz" + }, + { + "name": "QSPI_90MHZ", + "value": 2, + "description": "90MHz" + }, + { + "name": "QSPI_100MHZ", + "value": 3, + "description": "100MHz" + }, + { + "name": "QSPI_120MHZ", + "value": 4, + "description": "120MHz" + }, + { + "name": "QSPI_133MHZ", + "value": 5, + "description": "133MHz" + }, + { + "name": "QSPI_166MHZ", + "value": 6, + "description": "166MHz" + }, + { + "name": "QSPI_200MHZ", + "value": 7, + "description": "200MHz" + } + ] + }, + { + "width": 1, + "id": "fuse97-bit-14", + "name": "QSPI_RESET_PIN_ENABLE", + "description": "Use QSPI_RESET_PIN to reset the flash device.", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "Octal/Quad SPI flash device reset pin is not connected or available." + }, + { + "name": "EN_RESET", + "value": 1, + "description": "Octal/Quad SPI flash device reset pin is connected to a GPIO (QSPI_RESET_PIN)." + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-15-17", + "name": "QSPI_RESET_PIN_GPIO_PORT", + "description": "GPIO port and pin number to use for Octal/Quad SPI flash reset function.\nDefines GPIO port." + }, + { + "width": 5, + "id": "fuse97-bits-18-22", + "name": "QSPI_RESET_PIN_GPIO_PIN_NUM", + "description": "GPIO port and pin number to use for Octal/Quad SPI flash reset function.\nDefines GPIO pin number." + }, + { + "width": 2, + "id": "fuse97-bits-23-24", + "name": "QSPI_HOLD TIME", + "description": "Wait time before access to Serial Flash.", + "values": [ + { + "name": "WAIT_500_US", + "value": 0, + "description": "Wait for 500 micro seconds." + }, + { + "name": "WAIT_1_MS", + "value": 1, + "description": "Wait for 1 milliseconds." + }, + { + "name": "WAIT_3_MS", + "value": 2, + "description": "Wait for 3 milliseconds." + }, + { + "name": "WAIT_10_MS", + "value": 3, + "description": "Wait for 10 milliseconds." + } + ] + }, + { + "width": 4, + "id": "fuse97-bits-25-28", + "name": "QSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by QSPI_HOLD TIME field.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "100US_DELAY", + "value": 1, + "description": "Waits additional 100 micro-seconds." + }, + { + "name": "500US_DELAY", + "value": 2, + "description": "Waits additional 500 micro-seconds." + }, + { + "name": "1MS_DELAY", + "value": 3, + "description": "Waits additional 1 milli-seconds." + }, + { + "name": "10MS_DELAY", + "value": 4, + "description": "Waits additional 10 milli-seconds." + }, + { + "name": "20MS_DELAY", + "value": 5, + "description": "Waits additional 20 milli-seconds." + }, + { + "name": "40MS_DELAY", + "value": 6, + "description": "Waits additional 40 milli-seconds." + }, + { + "name": "60MS_DELAY", + "value": 7, + "description": "Waits additional 60 milli-seconds." + }, + { + "name": "80MS_DELAY", + "value": 8, + "description": "Waits additional 80 milli-seconds." + }, + { + "name": "100MS_DELAY", + "value": 9, + "description": "Waits additional 100 milli-seconds." + }, + { + "name": "120MS_DELAY", + "value": 10, + "description": "Waits additional 120 milli-seconds." + }, + { + "name": "140MS_DELAY", + "value": 11, + "description": "Waits additional 140 milli-seconds." + }, + { + "name": "160MS_DELAY", + "value": 12, + "description": "Waits additional 160 milli-seconds." + }, + { + "name": "180MS_DELAY", + "value": 13, + "description": "Waits additional 180 milli-seconds." + }, + { + "name": "200MS_DELAY", + "value": 14, + "description": "Waits additional 200 milli-seconds." + }, + { + "name": "220MS_DELAY", + "value": 15, + "description": "Waits additional 220 milli-seconds." + } + ] + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse97-bit-31", + "name": "QSPI_ISP_AUTO_PROBE_EN", + "description": "Enable auto probing of Octal/Quad SPI flash device on SP mode entry. \nSet this bit when using secure update (receive-sb ISP command) feature with PUF keystore. So that ROM auto-detects the flash device and loads the PUF key store prior to receiving ISP commands.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + }, + { + "id": "fuse98", + "name": "BOOT_CFG2", + "description": "Boot configuration word specifying settings for SD card and eMMC boot interface.", + "deprecated_names": [ + "BOOT_CFG[2]" + ], + "index_int": "0x0062", + "shadow_reg_offset_int": "0x0188", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse98-bit-0", + "name": "SDHC_DEVICE_TYPE", + "description": "Device type connected to SDHC port.", + "values": [ + { + "name": "eMMC_DEV", + "value": 0, + "description": "eMMC device" + }, + { + "name": "SD_DEV", + "value": 1, + "description": "SD card device" + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-1-2", + "name": "SDHC_BUS_WIDTH", + "description": "Bus width of the device connected to SDHC.", + "values": [ + { + "name": "SD_1B_MMC_4B", + "value": 0, + "description": "For SD cards use 1-bit data bus. \nFor eMMC use 4-bit data bus." + }, + { + "name": "SD_4B_MMC_8B", + "value": 1, + "description": "For SD cards use 4-bit data bus. \nFor eMMC use 8-bit data bus." + }, + { + "name": "MMC_4B_DDR", + "value": 2, + "description": "For eMMC use 4-bit bus in DDR mode." + }, + { + "name": "MMC_8B_DDR", + "value": 3, + "description": "For eMMC use 8-bit bus in DDR mode." + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-3-4", + "name": "SDHC_SPEED", + "description": "Speed ratings of eMMC devices and SD card devices.", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal speed for eMMC devices. SDR12 speeds for SD." + }, + { + "name": "HIGH", + "value": 1, + "description": "High speed for eMMC devices. SDR25 speeds for SD." + }, + { + "name": "SDR50", + "value": 2, + "description": "SDR50 speeds for SD card." + }, + { + "name": "SDR104", + "value": 3, + "description": "SDR104" + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-5", + "name": "SDHC_PWR_CYCLE_EN", + "description": "Enable SDHC power cycle via USDHC_RST pad.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-6", + "name": "SDHC0_PWR_POL", + "description": "Polarity of power enable signal for SDHC0 port.", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high signal." + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low signal." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-7", + "name": "SDHC1_PWR_POL", + "description": "Polarity of power enable signal for SDHC1 port.", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high signal." + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low signal." + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-8-9", + "name": "SDHC_PWR_CYCLE_WAIT", + "description": "Wait time after powering down the SDHC devices.", + "values": [ + { + "name": "WAIT_20_MS", + "value": 0, + "description": "Wait 20 milliseconds." + }, + { + "name": "WAIT_10_MS", + "value": 1, + "description": "Wait 10 milliseconds." + }, + { + "name": "WAIT_05_MS", + "value": 2, + "description": "Wait 5 milliseconds." + }, + { + "name": "WAIT_2_5_MS", + "value": 3, + "description": "Wait 2.5 milliseconds." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-10", + "name": "SDHC_PWR_STABLE_WAIT", + "description": "Wait time for power to stabilize after enabling power to SDHC devices.", + "values": [ + { + "name": "WAIT_5_MS", + "value": 0, + "description": "Wait 5 milliseconds." + }, + { + "name": "WAIT_2_5_MS", + "value": 1, + "description": "Wait 2.5 milliseconds." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-11", + "name": "SDHC0_CARD_VOLTAGE", + "description": "SD Voltage selection for SDHC0 port.", + "values": [ + { + "name": "3V3", + "value": 0, + "description": "Uses 3v3 rail." + }, + { + "name": "1V8", + "value": 1, + "description": "Uses 1v8 rail." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-12", + "name": "SDHC1_CARD_VOLTAGE", + "description": "SD Voltage selection for SDHC1 port.", + "values": [ + { + "name": "3V3", + "value": 0, + "description": "Uses 3v3 rail." + }, + { + "name": "1V8", + "value": 1, + "description": "Uses 1v8 rail." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-13", + "name": "MMC_RESET_PRE_IDLE_STATE", + "description": "Reset the MMC to Pre-Idle state before starting boot mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-14", + "name": "SDHC_FASTBOOT_MODE", + "description": "Specifies if the boot mode is enabled in Extended CSD register of the eMMC device.", + "values": [ + { + "name": "NORMAL_MODE", + "value": 0, + "description": "eMMC operates in transfer mode after power-up." + }, + { + "name": "BOOT_MODE", + "value": 1, + "description": "eMMC operates in boot mode after power-up." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-15", + "name": "SDHC_FASTBOOT_ACK_EN", + "description": "Specifies if the eMMC device sends boot acknowledge pattern during boot operation.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-16", + "name": "SDHC_PAD_CTL_FREEZE", + "description": "When using SDHC interface in high speed modes, the auto pad compensation control logic could cause interference due to modifications in IO drive strength. Hence it is recommended to freeze the compensated value and enable auto compensation periodically in application code by putting the pad back to normal mode. When this field is set ROM freezes the auto compensation circuit during boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-17", + "name": "SDHC_PAD_CTL_FAST_FREEZE", + "description": "Same as SDHC_PAD_CTL_FREEZE, but in this mode the time taken for switching the compensation from Fast Freeze mode to Normal mode is considerably smaller than the delay incurred in switching from Freeze mode to Normal mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-18", + "name": "QSPI_PAD_CTL_FREEZE", + "description": "When using QSPI interface in high speed modes, the auto pad compensation control logic could cause interference due to modifications in IO drive strength. Hence it is recommended to freeze the compensated value and enable auto compensation periodically in application code by putting the pad back to normal mode. When this field is set ROM freezes the auto compensation circuit during boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-19", + "name": "QSPI_PAD_CTL_FAST_FREEZE", + "description": "Same as QSPI_PAD_CTL_FREEZE, but in this mode the time taken for switching the compensation from Fast Freeze mode to Normal mode is considerably smaller than the delay incurred in switching from Freeze mode to Normal mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse98-bits-28-31", + "name": "QSPI_IMAGE_SIZE", + "description": "Any offset in memory mapped FlexSPI area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "Size of the remapped area (aka second half) is same as first half. It is determined by QSPI_IMAGE_OFFSET Field. \n Remap size = QSPI_IMAGE_OFFSET * 256KByte;" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "Size of remapped area is 768KByte." + } + ] + } + ] + }, + { + "id": "fuse99", + "name": "BOOT_CFG3", + "description": "Boot configuration word specifying delay lines settings for SDHC and QSPI interfaces.", + "deprecated_names": [ + "BOOT_CFG[3]" + ], + "index_int": "0x0063", + "shadow_reg_offset_int": "0x018C", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x8000" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse99-bits-0-6", + "name": "QSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS)" + }, + { + "width": 1, + "id": "fuse99-bit-7", + "name": "SDHC_DLL_TUNING_OVERRIDE_ENABLE", + "description": "SDHC_DLL_TUNING_OVERRIDE_ENABLE bit-field", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Default\uff1a DLL delay tuning start 10, DLL delay tuning step 2 ( this config can cover most of user cases.)" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override by SDHC_DLL_SETTING" + } + ] + }, + { + "width": 8, + "id": "fuse99-bits-8-15", + "name": "SDHC_DLL_TUNING_START", + "description": "DLL delay tuning start." + }, + { + "width": 3, + "id": "fuse99-bits-16-18", + "name": "SDHC_DLL_TUNING_STEP", + "description": "DLL delay tuning step." + }, + { + "width": 3, + "id": "fuse99-bits-19-21", + "name": "USB_PLL_DIV_SEL", + "description": "USB PLL divider value. Used for configuring USB PLL during USB ISP and DFU boot modes. The value corresponds to the PLL_DIV_SEL field of the USBPHY_PLL_SIC register." + }, + { + "width": 10, + "id": "fuse99-bits-22-31", + "name": "QSPI_IMAGE_OFFSET", + "description": "Any offset within memory mapped FlexSPI area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which can be programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. \nIf this field is left blank boot ROM assumes that application intends to not use dual image boot feature. The physical flash offset is computed as below:\n physical offset = QSPI_IMAGE_OFFSET * 256KByte;" + } + ] + } + ] + }, + { + "group": { + "name": "SECURITY_EPOCH", + "description": "OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different lifecycle stages of the device." + }, + "registers": [ + { + "id": "fuse101", + "name": "SEC_BOOT_CFG5", + "description": "Boot configuration word5. \n- This word is set in redundant mode. Thus individual bits can be programmed separately at different lifecycle stages of the device.", + "deprecated_names": [ + "SEC_BOOT_CFG[5]" + ], + "index_int": "0x0065", + "shadow_reg_offset_int": "0x0194", + "individual_write_lock": "user", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse101-bits-0-3", + "name": "REVOKE_ROOTKEY", + "description": "Revoke up to 4 root keys. When a bit is set corresponding root key is revoked." + }, + { + "width": 1, + "id": "fuse101-bit-4", + "name": "FA_MODE_EN", + "description": "Enable Fault Analysis mode.\n- When set ROM checks and erases customer sensitive assets (AES keys or key codes) stored in IFR/OTP. \n- Issues zeroized command to PUF (disables key decoding until POR)\n- Blocks all HW routed OTP keys and set lock bits on those registers\n- Enables all debug ports and waits in loop for tester.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2, + "id": "fuse101-bits-5-6", + "name": "ENABLE_CRC_CHECK", + "description": "Enable CRC checking of OTP words.", + "values": [ + { + "name": "CRC_DISABLE", + "value": 0, + "description": "CRC checking of OTP words is disabled." + }, + { + "name": "CRC_ENABLE", + "value": 1, + "description": "CRC check of all OTP words is enabled." + }, + { + "name": "CRC_NXPONLY", + "value": 2, + "description": "CRC check is enabled only for NXP programmed OTP words." + }, + { + "name": "CRC_ENABLE2", + "value": 3, + "description": "CRC check of all OTP words is enabled." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-7", + "name": "USE_PUF", + "description": "Use PUF to store AES keys and UDS.", + "values": [ + { + "name": "KEY_IN_OTP", + "value": 0, + "description": "AES keys and UDS are read from OTP." + }, + { + "name": "KEY_IN_PUF", + "value": 1, + "description": "AES keys and UDS are read from PUF." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-8", + "name": "PUF_BLOCK_ENROLL", + "description": "Block further enrollment of PUF block. When this bit is set ROM blocks generation of new activation codes.", + "values": [ + { + "name": "ENROLL_EN", + "value": 0, + "description": "Enable generation of new activation code." + }, + { + "name": "ENROLL_DIS", + "value": 1, + "description": "Disable generation of new activation code." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-9", + "name": "PUF_BLOCK_SET_KEY", + "description": "Block further enrollment of PUF block. When this bit is set ROM blocks generation of new key codes.", + "values": [ + { + "name": "KEY_GEN_EN", + "value": 0, + "description": "Enable generation of new key codes." + }, + { + "name": "KEY_GEN_DIS", + "value": 1, + "description": "Disable generation of new key codes." + } + ] + }, + { + "width": 6 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse102", + "name": "REVOKE_IMG_KEY", + "description": "Image keys revocation identifier.", + "index_int": "0x0066", + "shadow_reg_offset_int": "0x0198", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse102-bits-0-15", + "name": "REVOKE_IMG_KEY", + "description": "To implement anti-rollback feature, the image key certificate should be revoked using this field. The in-field FW update process should blow the least unblown bit. During image key certificate validation this field is compare with the certificate content (upper 2 bytes of serial number field in X.509 certificate)." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse103", + "name": "SEC_BOOT_CFG7", + "description": "Boot configuration word7. \n- This word is set in redundant mode. Thus individual bits can be programmed separately at different lifecycle stages of the device.", + "deprecated_names": [ + "SEC_BOOT_CFG[7]" + ], + "index_int": "0x0067", + "shadow_reg_offset_int": "0x019C", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse103-bits-0-15", + "name": "DAP_VENDOR_USAGE", + "description": "Lower 16-bits of Vendor Usage field in Debug Credentials defined in NXP's Debug Authentication Protocol specifications Version 1.0." + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "USB_CFG", + "description": "USB_CFG group" + }, + "registers": [ + { + "id": "fuse105", + "name": "USB_ID", + "description": "Override default USB ID's used by ROM during USB master boot and ISP modes.", + "index_int": "0x0069", + "individual_write_lock": "always_lock", + "bitfields": [ + { + "width": 16, + "id": "fuse105-bits-0-15", + "name": "USB_VID", + "description": "USB vendor ID." + }, + { + "width": 16, + "id": "fuse105-bits-16-31", + "name": "USB_PID", + "description": "USB product ID." + } + ] + } + ] + }, + { + "group": { + "name": "OTFAD_CFG", + "description": "OTFAD_CFG group" + }, + "registers": [ + { + "id": "fuse106", + "name": "OTFAD_CFG", + "description": "Configuration word to control OTFAD key blob loading during boot process.", + "index_int": "0x006A", + "shadow_reg_offset_int": "0x01A8", + "individual_write_lock": "user", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0004" + }, + "bitfields": [ + { + "width": 12 + }, + { + "width": 1, + "id": "fuse106-bit-12", + "name": "OTFAD_ENABLE", + "description": "When this field is set, it indicates to ROM that OTFAD feature is enabled and should initialize the OTFAD engine before accessing the memory mapped QSPI flash buffer area.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse106-bit-13", + "name": "KEYBLOB_RESTRICT_REG", + "description": "ROM after loading OTFAD registers restricts read access before jumping to user code. Only CTR registers are writable in this mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "KEY_STORE", + "description": "KEY_STORE group" + }, + "registers": [ + { + "id": "fuse107", + "name": "KEY_SCRAMBLE_SEED", + "description": "Key scramble data used as input to scramble master key stored in OTP.", + "index_int": "0x006B", + "shadow_reg_offset_int": "0x01AC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0010", + "read_lock_int": "0x0020" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse107-bits-0-31", + "name": "SCRAMBLE_INPUT", + "description": "32-bit random value programmed by user which will be used as one of the two inputs to scramble OTP_MASTER_KEY key." + } + ] + }, + { + "id": "fuse108", + "name": "OTFAD_KEK_SEED_31_0", + "description": "When OTP key store is used (USE_PUF = 0), this 128-bit user programmed value is used to derive OTFAD_KEK.\n\nOTFAD_KEK[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, OTFAD_KEK_SEED[127:0]);", + "index_int": "0x006C", + "shadow_reg_offset_int": "0x01B0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse109", + "name": "OTFAD_KEK_SEED_63_32", + "description": "OTFAD_KEK_SEED_63_32 register", + "index_int": "0x006D", + "shadow_reg_offset_int": "0x01B4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse110", + "name": "OTFAD_KEK_SEED_95_64", + "description": "OTFAD_KEK_SEED_95_64 register", + "index_int": "0x006E", + "shadow_reg_offset_int": "0x01B8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse111", + "name": "OTFAD_KEK_SEED_127_96", + "description": "OTFAD_KEK_SEED_127_96 register", + "index_int": "0x006F", + "shadow_reg_offset_int": "0x01BC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse112", + "name": "OTP_MASTER_KEY[31:0]", + "description": "Master Key used to derive different usage keys (HMAC_KEY, ENC_IMAGE_KEY, SB2_KEK, OTFAD_KEK). \n\n- ENC_BOOT_HMAC_KEY[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000000);\n- ENC_BOOT_AES_KEY[255:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000001) || AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000002);\n- SB_KEK[255:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000003) || AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000004); \n- OTFAD_KEK[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, OTFAD_KEK_SEED[127:0]);", + "index_int": "0x0070", + "shadow_reg_offset_int": "0x01C0", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse113", + "name": "OTP_MASTER_KEY[63:32]", + "description": "OTP_MASTER_KEY[63:32] register", + "index_int": "0x0071", + "shadow_reg_offset_int": "0x01C4", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse114", + "name": "OTP_MASTER_KEY[95:64]", + "description": "OTP_MASTER_KEY[95:64] register", + "index_int": "0x0072", + "shadow_reg_offset_int": "0x01C8", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse115", + "name": "OTP_MASTER_KEY[127:96]", + "description": "OTP_MASTER_KEY[127:96] register", + "index_int": "0x0073", + "shadow_reg_offset_int": "0x01CC", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse116", + "name": "OTP_MASTER_KEY[159:128]", + "description": "OTP_MASTER_KEY[159:128] register", + "index_int": "0x0074", + "shadow_reg_offset_int": "0x01D0", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse117", + "name": "OTP_MASTER_KEY[191:160]", + "description": "OTP_MASTER_KEY[191:160] register", + "index_int": "0x0075", + "shadow_reg_offset_int": "0x01D4", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse118", + "name": "OTP_MASTER_KEY[223:192]", + "description": "OTP_MASTER_KEY[223:192] register", + "index_int": "0x0076", + "shadow_reg_offset_int": "0x01D8", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse119", + "name": "OTP_MASTER_KEY[255:224]", + "description": "OTP_MASTER_KEY[255:224] register", + "index_int": "0x0077", + "shadow_reg_offset_int": "0x01DC", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse120", + "name": "RKTH_255_224", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys (modulus || exponent).\nFor i in 0..3:\n Let M[i] = BE(Modulus i)\n Let E[i] = BE(Exponent i)\n Let RKH[i] = SHA256( M[i] || E[i] )\n Let RKTH = SHA256( RKH[0] || RKH[1] || RKH[2] || RKH[3] )\nNote: Documentation update needed when using blhost due to endianness issue.", + "index_int": "0x0078", + "shadow_reg_offset_int": "0x01E0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse121", + "name": "RKTH_223_192", + "description": "RKTH_223_192 register", + "index_int": "0x0079", + "shadow_reg_offset_int": "0x01E4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse122", + "name": "RKTH_191_160", + "description": "RKTH_191_160 register", + "index_int": "0x007A", + "shadow_reg_offset_int": "0x01E8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse123", + "name": "RKTH_159_128", + "description": "RKTH_159_128 register", + "index_int": "0x007B", + "shadow_reg_offset_int": "0x01EC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse124", + "name": "RKTH_127_96", + "description": "RKTH_127_96 register", + "index_int": "0x007C", + "shadow_reg_offset_int": "0x01F0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse125", + "name": "RKTH_95_64", + "description": "RKTH_95_64 register", + "index_int": "0x007D", + "shadow_reg_offset_int": "0x01F4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse126", + "name": "RKTH_63_32", + "description": "RKTH_63_32 register", + "index_int": "0x007E", + "shadow_reg_offset_int": "0x01F8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse127", + "name": "RKTH_31_0", + "description": "RKTH_31_0 register", + "index_int": "0x007F", + "shadow_reg_offset_int": "0x01FC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + } + ] + }, + { + "group": { + "name": "NT_FW_VERSION", + "description": "NT_FW_VERSION group" + }, + "registers": [ + { + "id": "fuse128", + "name": "NT_FW_VER_15_0", + "description": "Non-trusted firmware version counter (0 - 255). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0080", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse128-bits-0-15", + "name": "NT_FW_VER_15_0", + "description": "Non-trusted firmware version counter (0 - 255). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse129", + "name": "NT_FW_VER_31_16", + "description": "NT_FW_VER_31_16 register", + "index_int": "0x0081", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse129-bits-0-15", + "name": "NT_FW_VER_31_16", + "description": "NT_FW_VER_31_16 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse130", + "name": "NT_FW_VER_47_32", + "description": "NT_FW_VER_47_32 register", + "index_int": "0x0082", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse130-bits-0-15", + "name": "NT_FW_VER_47_32", + "description": "NT_FW_VER_47_32 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse131", + "name": "NT_FW_VER_63_48", + "description": "NT_FW_VER_63_48 register", + "index_int": "0x0083", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse131-bits-0-15", + "name": "NT_FW_VER_63_48", + "description": "NT_FW_VER_63_48 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse132", + "name": "NT_FW_VER_79_64", + "description": "NT_FW_VER_79_64 register", + "index_int": "0x0084", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse132-bits-0-15", + "name": "NT_FW_VER_79_64", + "description": "NT_FW_VER_79_64 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse133", + "name": "NT_FW_VER_95_80", + "description": "NT_FW_VER_95_80 register", + "index_int": "0x0085", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse133-bits-0-15", + "name": "NT_FW_VER_95_80", + "description": "NT_FW_VER_95_80 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse134", + "name": "NT_FW_VER_111_96", + "description": "NT_FW_VER_111_96 register", + "index_int": "0x0086", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse134-bits-0-15", + "name": "NT_FW_VER_111_96", + "description": "NT_FW_VER_111_96 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse135", + "name": "NT_FW_VER_127_112", + "description": "NT_FW_VER_127_112 register", + "index_int": "0x0087", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse135-bits-0-15", + "name": "NT_FW_VER_127_112", + "description": "NT_FW_VER_127_112 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse136", + "name": "NT_FW_VER_143_128", + "description": "NT_FW_VER_143_128 register", + "index_int": "0x0088", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse136-bits-0-15", + "name": "NT_FW_VER_143_128", + "description": "NT_FW_VER_143_128 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse137", + "name": "NT_FW_VER_159_144", + "description": "NT_FW_VER_159_144 register", + "index_int": "0x0089", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse137-bits-0-15", + "name": "NT_FW_VER_159_144", + "description": "NT_FW_VER_159_144 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse138", + "name": "NT_FW_VER_175_160", + "description": "NT_FW_VER_175_160 register", + "index_int": "0x008A", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse138-bits-0-15", + "name": "NT_FW_VER_175_160", + "description": "NT_FW_VER_175_160 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse139", + "name": "NT_FW_VER_191_176", + "description": "NT_FW_VER_191_176 register", + "index_int": "0x008B", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse139-bits-0-15", + "name": "NT_FW_VER_191_176", + "description": "NT_FW_VER_191_176 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse140", + "name": "NT_FW_VER_207_192", + "description": "NT_FW_VER_207_192 register", + "index_int": "0x008C", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse140-bits-0-15", + "name": "NT_FW_VER_207_192", + "description": "NT_FW_VER_207_192 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse141", + "name": "NT_FW_VER_223_208", + "description": "NT_FW_VER_223_208 register", + "index_int": "0x008D", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse141-bits-0-15", + "name": "NT_FW_VER_223_208", + "description": "NT_FW_VER_223_208 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse142", + "name": "NT_FW_VER_239_224", + "description": "NT_FW_VER_239_224 register", + "index_int": "0x008E", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse142-bits-0-15", + "name": "NT_FW_VER_239_224", + "description": "NT_FW_VER_239_224 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse143", + "name": "NT_FW_VER_255_240", + "description": "NT_FW_VER_255_240 register", + "index_int": "0x008F", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse143-bits-0-15", + "name": "NT_FW_VER_255_240", + "description": "NT_FW_VER_255_240 register" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "TZ_FW_VERSION", + "description": "TZ_FW_VERSION group" + }, + "registers": [ + { + "id": "fuse144", + "name": "TZ_FW_VER_15_0", + "description": "Trusted firmware version counter (0 - 63). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0090", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse144-bits-0-15", + "name": "TZ_FW_VER_15_0", + "description": "Trusted firmware version counter (0 - 63). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse145", + "name": "TZ_FW_VER_31_16", + "description": "TZ_FW_VER_31_16 register", + "index_int": "0x0091", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse145-bits-0-15", + "name": "TZ_FW_VER_31_16", + "description": "TZ_FW_VER_31_16 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse146", + "name": "TZ_FW_VER_47_32", + "description": "TZ_FW_VER_47_32 register", + "index_int": "0x0092", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse146-bits-0-15", + "name": "TZ_FW_VER_47_32", + "description": "TZ_FW_VER_47_32 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse147", + "name": "TZ_FW_VER_63_48", + "description": "TZ_FW_VER_63_48 register", + "index_int": "0x0093", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse147-bits-0-15", + "name": "TZ_FW_VER_63_48", + "description": "TZ_FW_VER_63_48 register" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "USER_DATA", + "description": "USER_DATA group" + }, + "registers": [ + { + "id": "fuse148", + "name": "USER_RED_0", + "description": "Customer defined data.OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0094", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse148-bits-0-15", + "name": "USER_RED_0", + "description": "Customer defined data.OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse149", + "name": "USER_RED_1", + "description": "USER_RED_1 register", + "index_int": "0x0095", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse149-bits-0-15", + "name": "USER_RED_1", + "description": "USER_RED_1 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse150", + "name": "USER_RED_2", + "description": "USER_RED_2 register", + "index_int": "0x0096", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse150-bits-0-15", + "name": "USER_RED_2", + "description": "USER_RED_2 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse151", + "name": "USER_RED_3", + "description": "USER_RED_3 register", + "index_int": "0x0097", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse151-bits-0-15", + "name": "USER_RED_3", + "description": "USER_RED_3 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse152", + "name": "USER_ECC_0", + "description": "Customer defined data.OTP words in this block are ECC fuse words. Thus all bits in these words can be programmed at one shot.", + "index_int": "0x0098", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse153", + "name": "USER_ECC_1", + "description": "USER_ECC_1 register", + "index_int": "0x0099", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse154", + "name": "USER_ECC_2", + "description": "USER_ECC_2 register", + "index_int": "0x009A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse155", + "name": "USER_ECC_3", + "description": "USER_ECC_3 register", + "index_int": "0x009B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse156", + "name": "USER_ECC_4", + "description": "USER_ECC_4 register", + "index_int": "0x009C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse157", + "name": "USER_ECC_5", + "description": "USER_ECC_5 register", + "index_int": "0x009D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse158", + "name": "USER_ECC_6", + "description": "USER_ECC_6 register", + "index_int": "0x009E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse159", + "name": "USER_ECC_7", + "description": "USER_ECC_7 register", + "index_int": "0x009F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK1", + "description": "USER_BANK1 group" + }, + "registers": [ + { + "id": "fuse392", + "name": "USER_BANK1_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0188", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse393", + "name": "USER_BANK1_1", + "description": "USER_BANK1_1 register", + "index_int": "0x0189", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse394", + "name": "USER_BANK1_2", + "description": "USER_BANK1_2 register", + "index_int": "0x018A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse395", + "name": "USER_BANK1_3", + "description": "USER_BANK1_3 register", + "index_int": "0x018B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse396", + "name": "USER_BANK1_4", + "description": "USER_BANK1_4 register", + "index_int": "0x018C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse397", + "name": "USER_BANK1_5", + "description": "USER_BANK1_5 register", + "index_int": "0x018D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse398", + "name": "USER_BANK1_6", + "description": "USER_BANK1_6 register", + "index_int": "0x018E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse399", + "name": "USER_BANK1_7", + "description": "USER_BANK1_7 register", + "index_int": "0x018F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK2", + "description": "USER_BANK2 group" + }, + "registers": [ + { + "id": "fuse400", + "name": "USER_BANK2_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0190", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse401", + "name": "USER_BANK2_1", + "description": "USER_BANK2_1 register", + "index_int": "0x0191", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse402", + "name": "USER_BANK2_2", + "description": "USER_BANK2_2 register", + "index_int": "0x0192", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse403", + "name": "USER_BANK2_3", + "description": "USER_BANK2_3 register", + "index_int": "0x0193", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse404", + "name": "USER_BANK2_4", + "description": "USER_BANK2_4 register", + "index_int": "0x0194", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse405", + "name": "USER_BANK2_5", + "description": "USER_BANK2_5 register", + "index_int": "0x0195", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse406", + "name": "USER_BANK2_6", + "description": "USER_BANK2_6 register", + "index_int": "0x0196", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse407", + "name": "USER_BANK2_7", + "description": "USER_BANK2_7 register", + "index_int": "0x0197", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK3", + "description": "USER_BANK3 group" + }, + "registers": [ + { + "id": "fuse408", + "name": "USER_BANK3_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0198", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse409", + "name": "USER_BANK3_1", + "description": "USER_BANK3_1 register", + "index_int": "0x0199", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse410", + "name": "USER_BANK3_2", + "description": "USER_BANK3_2 register", + "index_int": "0x019A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse411", + "name": "USER_BANK3_3", + "description": "USER_BANK3_3 register", + "index_int": "0x019B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse412", + "name": "USER_BANK3_4", + "description": "USER_BANK3_4 register", + "index_int": "0x019C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse413", + "name": "USER_BANK3_5", + "description": "USER_BANK3_5 register", + "index_int": "0x019D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse414", + "name": "USER_BANK3_6", + "description": "USER_BANK3_6 register", + "index_int": "0x019E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse415", + "name": "USER_BANK3_7", + "description": "USER_BANK3_7 register", + "index_int": "0x019F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK4", + "description": "USER_BANK4 group" + }, + "registers": [ + { + "id": "fuse416", + "name": "USER_BANK4_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01A0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse417", + "name": "USER_BANK4_1", + "description": "USER_BANK4_1 register", + "index_int": "0x01A1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse418", + "name": "USER_BANK4_2", + "description": "USER_BANK4_2 register", + "index_int": "0x01A2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse419", + "name": "USER_BANK4_3", + "description": "USER_BANK4_3 register", + "index_int": "0x01A3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse420", + "name": "USER_BANK4_4", + "description": "USER_BANK4_4 register", + "index_int": "0x01A4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse421", + "name": "USER_BANK4_5", + "description": "USER_BANK4_5 register", + "index_int": "0x01A5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse422", + "name": "USER_BANK4_6", + "description": "USER_BANK4_6 register", + "index_int": "0x01A6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse423", + "name": "USER_BANK4_7", + "description": "USER_BANK4_7 register", + "index_int": "0x01A7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK5", + "description": "USER_BANK5 group" + }, + "registers": [ + { + "id": "fuse424", + "name": "USER_BANK5_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01A8", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse425", + "name": "USER_BANK5_1", + "description": "USER_BANK5_1 register", + "index_int": "0x01A9", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse426", + "name": "USER_BANK5_2", + "description": "USER_BANK5_2 register", + "index_int": "0x01AA", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse427", + "name": "USER_BANK5_3", + "description": "USER_BANK5_3 register", + "index_int": "0x01AB", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse428", + "name": "USER_BANK5_4", + "description": "USER_BANK5_4 register", + "index_int": "0x01AC", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse429", + "name": "USER_BANK5_5", + "description": "USER_BANK5_5 register", + "index_int": "0x01AD", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse430", + "name": "USER_BANK5_6", + "description": "USER_BANK5_6 register", + "index_int": "0x01AE", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse431", + "name": "USER_BANK5_7", + "description": "USER_BANK5_7 register", + "index_int": "0x01AF", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK6", + "description": "USER_BANK6 group" + }, + "registers": [ + { + "id": "fuse432", + "name": "USER_BANK6_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01B0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse433", + "name": "USER_BANK6_1", + "description": "USER_BANK6_1 register", + "index_int": "0x01B1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse434", + "name": "USER_BANK6_2", + "description": "USER_BANK6_2 register", + "index_int": "0x01B2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse435", + "name": "USER_BANK6_3", + "description": "USER_BANK6_3 register", + "index_int": "0x01B3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse436", + "name": "USER_BANK6_4", + "description": "USER_BANK6_4 register", + "index_int": "0x01B4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse437", + "name": "USER_BANK6_5", + "description": "USER_BANK6_5 register", + "index_int": "0x01B5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse438", + "name": "USER_BANK6_6", + "description": "USER_BANK6_6 register", + "index_int": "0x01B6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse439", + "name": "USER_BANK6_7", + "description": "USER_BANK6_7 register", + "index_int": "0x01B7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK7", + "description": "USER_BANK7 group" + }, + "registers": [ + { + "id": "fuse440", + "name": "USER_BANK7_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01B8", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse441", + "name": "USER_BANK7_1", + "description": "USER_BANK7_1 register", + "index_int": "0x01B9", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse442", + "name": "USER_BANK7_2", + "description": "USER_BANK7_2 register", + "index_int": "0x01BA", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse443", + "name": "USER_BANK7_3", + "description": "USER_BANK7_3 register", + "index_int": "0x01BB", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse444", + "name": "USER_BANK7_4", + "description": "USER_BANK7_4 register", + "index_int": "0x01BC", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse445", + "name": "USER_BANK7_5", + "description": "USER_BANK7_5 register", + "index_int": "0x01BD", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse446", + "name": "USER_BANK7_6", + "description": "USER_BANK7_6 register", + "index_int": "0x01BE", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse447", + "name": "USER_BANK7_7", + "description": "USER_BANK7_7 register", + "index_int": "0x01BF", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK8", + "description": "USER_BANK8 group" + }, + "registers": [ + { + "id": "fuse448", + "name": "USER_BANK8_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01C0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse449", + "name": "USER_BANK8_1", + "description": "USER_BANK8_1 register", + "index_int": "0x01C1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse450", + "name": "USER_BANK8_2", + "description": "USER_BANK8_2 register", + "index_int": "0x01C2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse451", + "name": "USER_BANK8_3", + "description": "USER_BANK8_3 register", + "index_int": "0x01C3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse452", + "name": "USER_BANK8_4", + "description": "USER_BANK8_4 register", + "index_int": "0x01C4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse453", + "name": "USER_BANK8_5", + "description": "USER_BANK8_5 register", + "index_int": "0x01C5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse454", + "name": "USER_BANK8_6", + "description": "USER_BANK8_6 register", + "index_int": "0x01C6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse455", + "name": "USER_BANK8_7", + "description": "USER_BANK8_7 register", + "index_int": "0x01C7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "CRC_BANK", + "description": "CRC_BANK group" + }, + "registers": [ + { + "id": "fuse492", + "name": "CRC4", + "description": "CRC of BOOT_CFG configuration data. Word 96 to 100 (0x180 - 0x18F).", + "index_int": "0x01EC", + "shadow_reg_offset_int": "0x07B0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0010", + "read_lock_int": "0x0020" + } + }, + { + "id": "fuse493", + "name": "CRC5", + "description": "CRC of SECURE_CFG configuration data. Word 107 to 127 (0x1A4 - 0x200).", + "index_int": "0x01ED", + "shadow_reg_offset_int": "0x07B4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0080" + } + }, + { + "id": "fuse494", + "name": "CRC6", + "description": "CRC of customer programmed mode fuse (Word 8 and 9).", + "index_int": "0x01EE", + "shadow_reg_offset_int": "0x07B8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0100", + "read_lock_int": "0x0200" + } + }, + { + "id": "fuse495", + "name": "CRC7", + "description": "Customer defined.", + "index_int": "0x01EF", + "shadow_reg_offset_int": "0x07BC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0400", + "read_lock_int": "0x0800" + } + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/tz.json new file mode 100644 index 0000000..34c96bb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt595s/tz.json @@ -0,0 +1,2293 @@ +{ + "cpu": "mimxrt595s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Secure vector table address (vtor_addr)", + "description": "TrustZone register - Secure vector table address (vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Non-secure vector table address (vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (sau_ctrl)", + "description": "TrustZone register - SAU Control Register (sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "description": "TrustZone register - ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 0 (qospi4_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 0 (qospi4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 1 (qospi4_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 1 (qospi4_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 2 (qospi4_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 2 (qospi4_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 3 (qospi4_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 3 (qospi4_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "description": "TrustZone register - RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "description": "TrustZone register - RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "description": "TrustZone register - RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "description": "TrustZone register - RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "description": "TrustZone register - RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "description": "TrustZone register - RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "description": "TrustZone register - RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "description": "TrustZone register - RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "description": "TrustZone register - RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "description": "TrustZone register - RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "description": "TrustZone register - RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "description": "TrustZone register - RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "description": "TrustZone register - RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "description": "TrustZone register - RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "description": "TrustZone register - RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "description": "TrustZone register - RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "description": "TrustZone register - RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "description": "TrustZone register - RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "description": "TrustZone register - RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "description": "TrustZone register - RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "description": "TrustZone register - RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "description": "TrustZone register - RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "description": "TrustZone register - RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "description": "TrustZone register - RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "description": "TrustZone register - RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "description": "TrustZone register - RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "description": "TrustZone register - RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "description": "TrustZone register - RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "description": "TrustZone register - RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "description": "TrustZone register - RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "description": "TrustZone register - RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "description": "TrustZone register - RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "description": "TrustZone register - RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "description": "TrustZone register - RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "description": "TrustZone register - RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "description": "TrustZone register - RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "description": "TrustZone register - RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "description": "TrustZone register - RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "description": "TrustZone register - RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "description": "TrustZone register - RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "description": "TrustZone register - RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "description": "TrustZone register - RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "description": "TrustZone register - RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "description": "TrustZone register - RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "description": "TrustZone register - RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "description": "TrustZone register - RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "description": "TrustZone register - RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "description": "TrustZone register - RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "description": "TrustZone register - RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "description": "TrustZone register - RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "description": "TrustZone register - RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "description": "TrustZone register - RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "description": "TrustZone register - RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "description": "TrustZone register - RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "description": "TrustZone register - RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "description": "TrustZone register - RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "description": "TrustZone register - RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "description": "TrustZone register - RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "description": "TrustZone register - RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "description": "TrustZone register - RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "description": "TrustZone register - RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "description": "TrustZone register - RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "description": "TrustZone register - RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "description": "TrustZone register - RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "RAM5 Slave Rule Register (ram5_slave_rule)", + "description": "TrustZone register - RAM5 Slave Rule Register (ram5_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "description": "TrustZone register - RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "description": "TrustZone register - RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "description": "TrustZone register - RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "description": "TrustZone register - RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "description": "TrustZone register - RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "description": "TrustZone register - RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "description": "TrustZone register - RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "description": "TrustZone register - RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "description": "TrustZone register - RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "description": "TrustZone register - RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "description": "TrustZone register - RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "description": "TrustZone register - RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "description": "TrustZone register - RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "description": "TrustZone register - RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "description": "TrustZone register - RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "description": "TrustZone register - RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "RAM6 Slave Rule Register (ram6_slave_rule)", + "description": "TrustZone register - RAM6 Slave Rule Register (ram6_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "description": "TrustZone register - RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "description": "TrustZone register - RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "description": "TrustZone register - RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "description": "TrustZone register - RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "description": "TrustZone register - RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "description": "TrustZone register - RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "description": "TrustZone register - RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "description": "TrustZone register - RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "description": "TrustZone register - RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "description": "TrustZone register - RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "description": "TrustZone register - RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "description": "TrustZone register - RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "description": "TrustZone register - RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "description": "TrustZone register - RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "description": "TrustZone register - RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "description": "TrustZone register - RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "RAM7 Slave Rule Register (ram7_slave_rule)", + "description": "TrustZone register - RAM7 Slave Rule Register (ram7_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "description": "TrustZone register - RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "description": "TrustZone register - RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "description": "TrustZone register - RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "description": "TrustZone register - RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "description": "TrustZone register - RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "description": "TrustZone register - RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "description": "TrustZone register - RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "description": "TrustZone register - RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "description": "TrustZone register - RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "description": "TrustZone register - RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "description": "TrustZone register - RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "description": "TrustZone register - RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "description": "TrustZone register - RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "description": "TrustZone register - RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "description": "TrustZone register - RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "description": "TrustZone register - RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "RAM8 Slave Rule Register (ram8_slave_rule)", + "description": "TrustZone register - RAM8 Slave Rule Register (ram8_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "description": "TrustZone register - RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "description": "TrustZone register - RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "description": "TrustZone register - RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "description": "TrustZone register - RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram82_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram82_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram82_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram82_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram82_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram82_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram82_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram82_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram83_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram83_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram83_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram83_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram83_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram83_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram83_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram83_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "(ezh_ram_slave_rule)", + "description": "TrustZone register - (ezh_ram_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule0)", + "description": "TrustZone register - (ezh_ram0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule1)", + "description": "TrustZone register - (ezh_ram0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule2)", + "description": "TrustZone register - (ezh_ram0_slave_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "(ezh_ram0_slave_rule3)", + "description": "TrustZone register - (ezh_ram0_slave_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qospi1_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qospi1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qospi10_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qospi10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qospi10_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qospi10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qospi10_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qospi10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qospi10_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qospi10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qospi11_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qospi11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qospi11_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qospi11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qospi11_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qospi11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qospi11_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qospi11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qospi12_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qospi12_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qospi12_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qospi12_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qospi12_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qospi12_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qospi12_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qospi12_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qospi13_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qospi13_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qospi13_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qospi13_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qospi13_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qospi13_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qospi13_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qospi13_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 0 (qospi14_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 0 (qospi14_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 1 (qospi14_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 1 (qospi14_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 2 (qospi14_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 2 (qospi14_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 3 (qospi14_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 3 (qospi14_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "AIPS Bridge Slave Rule Register (aips_bridge_slave_rule0)", + "description": "TrustZone register - AIPS Bridge Slave Rule Register (aips_bridge_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field41C", + "offset_int": "0x41c", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field420", + "offset_int": "0x420", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field424", + "offset_int": "0x424", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field428", + "offset_int": "0x428", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (security_ctrl_mem_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (security_ctrl_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field42C", + "offset_int": "0x42c", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field430", + "offset_int": "0x430", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field434", + "offset_int": "0x434", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field438", + "offset_int": "0x438", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field43C", + "offset_int": "0x43c", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field440", + "offset_int": "0x440", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field444", + "offset_int": "0x444", + "reg_width": 32, + "name": "Secure GPIO Register 4 (sec_gp_reg4)", + "description": "TrustZone register - Secure GPIO Register 4 (sec_gp_reg4)", + "default_value_int": "0xffffffff" + }, + { + "id": "field448", + "offset_int": "0x448", + "reg_width": 32, + "name": "Secure GPIO Register 5 (sec_gp_reg5)", + "description": "TrustZone register - Secure GPIO Register 5 (sec_gp_reg5)", + "default_value_int": "0xffffffff" + }, + { + "id": "field44C", + "offset_int": "0x44c", + "reg_width": 32, + "name": "Secure GPIO Register 6 (sec_gp_reg6)", + "description": "TrustZone register - Secure GPIO Register 6 (sec_gp_reg6)", + "default_value_int": "0xffffffff" + }, + { + "id": "field450", + "offset_int": "0x450", + "reg_width": 32, + "name": "Secure GPIO Register 7 (sec_gp_reg7)", + "description": "TrustZone register - Secure GPIO Register 7 (sec_gp_reg7)", + "default_value_int": "0xffffffff" + }, + { + "id": "field454", + "offset_int": "0x454", + "reg_width": 32, + "name": "Secure GPIO Register 8 for DSP (sec_gp_reg8)", + "description": "TrustZone register - Secure GPIO Register 8 for DSP (sec_gp_reg8)", + "default_value_int": "0xffffffff" + }, + { + "id": "field458", + "offset_int": "0x458", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaaaa" + }, + { + "id": "field45C", + "offset_int": "0x45c", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field460", + "offset_int": "0x460", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field464", + "offset_int": "0x464", + "reg_width": 32, + "name": "M33 Lock Control Register (m33_lock_reg)", + "description": "TrustZone register - M33 Lock Control Register (m33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field468", + "offset_int": "0x468", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field46C", + "offset_int": "0x46c", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field470", + "offset_int": "0x470", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/database.yaml new file mode 100644 index 0000000..5d12abc --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/database.yaml @@ -0,0 +1,57 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt595s + +revisions: + a0: + features: + tz: + reg_spec: tz_a0.json + + b0: + features: + tz: + reg_spec: tz_b0.json + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt6xx + # Web page of MCU representative + web: https://www.nxp.com/products/i.MX-RT600 + memory_map: + flexspi0_ns: + start_int: "0x08000000" + size_int: "0x04000000" + external: true + flexspi0_s: + start_int: "0x18000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi0_ns + flexspi1_ns: + start_int: "0x28000000" + size_int: "0x04000000" + external: true + flexspi1_s: + start_int: "0x38000000" + size_int: "0x04000000" + external: true + mirror_of: flexspi1_ns + sram: + start_int: "0x20000" + size_int: "0x460000" + external: false + non_xip_type: int_ram + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0020 + +features: + otfad: + byte_swap: true diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fcb_flexspi_nor.json new file mode 100644 index 0000000..df7004e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fcb_flexspi_nor.json @@ -0,0 +1,25599 @@ +{ + "cpu": "MIMXRT685S", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x56020000" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details ", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same ", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3 ", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false ", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution ", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size ", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context ", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use ", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fuses.json new file mode 100644 index 0000000..95a0373 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/fuses.json @@ -0,0 +1,3939 @@ +{ + "cpu": "MIMXRT685S", + "shadow_reg_base_addr_int": "0x40130000", + "groups": [ + { + "group": { + "name": "SHADOW_LOCK", + "description": "Fuses used to define read/write access permissions to shadows registers of Customer configured OTP words." + }, + "registers": [ + { + "id": "fuse8", + "name": "CUST_WR_RD_LOCK0", + "description": "Fuses used to define read/write access permissions to shadows registers of Customer configured OTP words. This is a redundant OTP word hence only 16 bits defined.", + "index_int": "0x0008", + "shadow_reg_offset_int": "0x0020", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 1, + "id": "fuse8-bit-0", + "name": "DCFG_CC_SOCU_WR", + "description": "When set locks APB write access to DCFG_CC_SOCU and DCFG_CC_SOCU_AP shadow registers. (Fuse 256)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-1", + "name": "DCFG_CC_SOCU_NS_WR", + "description": "When set locks APB write access to DCFG_CC_SOCU_NS shadow registers. (Fuse 257)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-2", + "name": "OTFAD_CFG_WR_LOCK", + "description": "When set locks APB write access to OTFAD_CFG shadow register. (Fuse 258)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse8-bit-4", + "name": "KEY_SCRAMBLE_SEED_WR_LOCK", + "description": "When set locks APB write access to KEY_SCRAMBLE_SEED shadow register. (Fuse 260)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-5", + "name": "KEY_SCRAMBLE_SEED_RD_LOCK", + "description": "When set locks APB read access to KEY_SCRAMBLE_SEED shadow register. (Fuse 261)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-6", + "name": "OTFAD_KEK_SEED_WR_LOCK", + "description": "When set locks APB write access to OTFAD_KEK_SEED shadow registers. (Fuse 262)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse8-bit-8", + "name": "OTP_MASTER_KEY_WR_LOCK", + "description": "When set locks APB write access to OTP_MASTER_KEY shadow registers. (Fuse 264)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse8-bit-9", + "name": "SEC_BOOT_CFG5_WR_LOCK", + "description": "When set locks APB write access to SEC_BOOT_CFG5 shadow registers. (Fuse 265)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse9", + "name": "CUST_WR_RD_LOCK1", + "description": "Fuses used to define read/write access permissions to shadows registers of customer configured OTP words. This is a redundant OTP word hence only 16 bits defined.", + "index_int": "0x0009", + "shadow_reg_offset_int": "0x0024", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 4 + }, + { + "width": 1, + "id": "fuse9-bit-4", + "name": "CRC4_WR_LOCK", + "description": "When set locks APB write access to CRC4 shadow register. (Fuse 292)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-5", + "name": "CRC4_RD_LOCK", + "description": "When set locks APB read access to CRC4 shadow register. (Fuse 293)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-6", + "name": "CRC5_WR_LOCK", + "description": "When set locks APB write access to CRC5 shadow register. (Fuse 294)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-7", + "name": "CRC5_RD_LOCK", + "description": "When set locks APB read access to CRC5 shadow register. (Fuse 295)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-8", + "name": "CRC6_WR_LOCK", + "description": "When set locks APB write access to CRC6 shadow register. (Fuse 296)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-9", + "name": "CRC6_RD_LOCK", + "description": "When set locks APB read access to CRC6 shadow register. (Fuse 297)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-10", + "name": "CRC7_WR_LOCK", + "description": "When set locks APB write access to CRC7 shadow register. (Fuse 298)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-11", + "name": "CRC7_RD_LOCK", + "description": "When set locks APB read access to CRC7 shadow register. (Fuse 299)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-12", + "name": "BOOT_CFG0_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG0 and RKTH shadow register. (Fuse 300)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-13", + "name": "BOOT_CFG1_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG1 shadow register. (Fuse 301)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-14", + "name": "BOOT_CFG2_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG2 shadow register. (Fuse 302)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse9-bit-15", + "name": "BOOT_CFG3_WR_LOCK", + "description": "When set locks APB write access to BOOT_CFG3 shadow register. (Fuse 303)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "DEBUG_CFG", + "description": "DEBUG_CFG group" + }, + "registers": [ + { + "id": "fuse95", + "name": "DCFG_CC_SOCU", + "description": "Debug Configuration word (tier-1 developer). Use DCFG_CC_SOCU_WR to write lock this OTP word.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x005F", + "shadow_reg_offset_int": "0x017C", + "default_value_int": "0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0001" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse95-bits-0-7", + "name": "CRC8", + "description": "CRC-8/ITU of upper 3 bytes of this register. Polynomial=0x07, initial value= 0x00, XorOut=0x55.", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse95-bit-8", + "name": "DFLT_NIDEN", + "description": "Fixed state of Non-secure non-invasive debug enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-9", + "name": "DFLT_DBGEN", + "description": "Fixed state of Non-secure invasive debug enable, when PINNED_DBGEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Fixed state of secure non-invasive debug enable, when PINNED_SPNIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-11", + "name": "DFLT_SPIDEN", + "description": "Fixed state of secure invasive debug enable, when PINNED_SPIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-12", + "name": "DFLT_TAPEN", + "description": "Fixed state of Test Access Port enable, when PINNED_TAPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-13", + "name": "DFLT_HIFI4EN", + "description": "Fixed state of HiFi4 invasive debug enable, when PINNED_HIFI4EN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-14", + "name": "DFLT_ISPCMDEN", + "description": "Fixed state of ISP boot flow commands enable, when PINNED_ISPCMDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-15", + "name": "DFLT_PMCMDEN", + "description": "Fixed state of permanent modification commands (set Fault analysis mode) enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-16", + "name": "PINNED_NIDEN", + "description": "Fix the state of Non-secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-17", + "name": "PINNED_DBGEN", + "description": "Fix the state of Non-secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-18", + "name": "PINNED_SPNIDEN", + "description": "Fix the state of secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-19", + "name": "PINNED_SPIDEN", + "description": "Fix the state of secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-20", + "name": "PINNED_TAPEN", + "description": "Fix the state of Test Access Port enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-21", + "name": "PINNED_HIFI4EN", + "description": "Fix the state of HiFi4 invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-22", + "name": "PINNED_ISPCMDEN", + "description": "Fix the state of ISP boot flow commands enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-23", + "name": "PINNED_PMCMDEN", + "description": "Fix the state of permanent modification commands (set Fault analysis mode) enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse95-bit-24", + "name": "FORCE_UUID_MATCH", + "description": "When set, debug authentication protocol only accepts \"Debug Credential\" certificates (DC) with matching UUID.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "fuse95-bit-31", + "name": "DEV_TEST_EN", + "description": "Enable test mode.\nThis bit should be clear in OTP words. But during development to test different\nDCFG_CC_SOCU settings without programming OTP words, developers can write the\nvalues to shadow registers corresponding to OTP words (95 & 104) with this bit set.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + }, + { + "id": "fuse100", + "name": "DCFG_CC_SOCU_NS", + "description": "Debug Configuration word (tier-2 developer). Use DCFG_CC_SOCU_NS_WR to write lock this OTP word.\nCombinations of PIN and DFLT bits and resulting restriction level:\n- PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n- PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at start up. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate.\n- PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected.\n- PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0064", + "shadow_reg_offset_int": "0x0190", + "default_value_int": "0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse100-bits-0-7", + "name": "CRC8", + "description": "CRC-8/ITU of upper 3 bytes of this register. Polynomial=0x07, initial value= 0x00, XorOut=0x55.", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse100-bit-8", + "name": "DFLT_NIDEN", + "description": "Fixed state of Non-secure non-invasive debug enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-9", + "name": "DFLT_DBGEN", + "description": "Fixed state of Non-secure invasive debug enable, when PINNED_DBGEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Fixed state of secure non-invasive debug enable, when PINNED_SPNIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-11", + "name": "DFLT_SPIDEN", + "description": "Fixed state of secure invasive debug enable, when PINNED_SPIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-12", + "name": "DFLT_TAPEN", + "description": "Fixed state of Test Access Port enable, when PINNED_TAPEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-13", + "name": "DFLT_HIFI4EN", + "description": "Fixed state of HiFi4 invasive debug enable, when PINNED_HIFI4EN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-14", + "name": "DFLT_ISPCMDEN", + "description": "Fixed state of ISP boot flow commands enable, when PINNED_ISPCMDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-15", + "name": "DFLT_PMCMDEN", + "description": "Fixed state of permanent modification commands (set Fault analysis mode) enable, when PINNED_NIDEN is set.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-16", + "name": "PINNED_NIDEN", + "description": "Fix the state of Non-secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-17", + "name": "PINNED_DBGEN", + "description": "Fix the state of Non-secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-18", + "name": "PINNED_SPNIDEN", + "description": "Fix the state of secure non-invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-19", + "name": "PINNED_SPIDEN", + "description": "Fix the state of secure invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-20", + "name": "PINNED_TAPEN", + "description": "Fix the state of Test Access Port enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "State of the field is fixed." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-21", + "name": "PINNED_HIFI4EN", + "description": "Fix the state of HiFi4 invasive debug enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-22", + "name": "PINNED_ISPCMDEN", + "description": "Fix the state of ISP boot flow commands enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-23", + "name": "PINNED_PMCMDEN", + "description": "Fix the state of permanent modification commands (set Fault analysis mode) enable.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse100-bit-24", + "name": "FORCE_UUID_MATCH", + "description": "When set, debug authentication protocol only accepts \"Debug Credential\" certificates (DC) with matching UUID.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 6 + }, + { + "width": 1, + "id": "fuse100-bit-31", + "name": "DEV_TEST_EN", + "description": "Enable test mode.\nThis bit should be clear in OTP words. But during development to test different\nDCFG_CC_SOCU settings without programming OTP words, developers can write the\nvalues to shadow registers corresponding to OTP words (95 & 104) with this bit set.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + } + ] + }, + { + "id": "fuse104", + "name": "DCFG_CC_SOCU_AP", + "description": "Anti-pole (inverse) value of Debug Configuration word(DCFG_CC_SOCU). Use DCFG_CC_SOCU_WR to write lock this OTP word.", + "index_int": "0x0068", + "shadow_reg_offset_int": "0x01A0", + "individual_write_lock": "always_lock", + "calculated": { + "method": "inverse", + "src_register_id": "fuse95" + }, + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0001" + } + } + ] + }, + { + "group": { + "name": "BOOT_CFG", + "description": "BOOT_CFG group" + }, + "registers": [ + { + "id": "fuse96", + "name": "BOOT_CFG0", + "description": "Boot configuration word0. Shadow register is present for this word thus SW could access the register directly to read contents.", + "deprecated_names": [ + "BOOT_CFG[0]" + ], + "index_int": "0x0060", + "shadow_reg_offset_int": "0x0180", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse96-bits-0-3", + "name": "PRIMARY_BOOT_SRC", + "description": "Primary boot Source. (a.k.a. Master boot source)", + "values": [ + { + "name": "ISP_PIN_BOOT", + "value": 0, + "description": "ISP pins will determine boot source." + }, + { + "name": "QSPI_A_BOOT", + "value": 1, + "description": "Boot from Octal/Quad SPI flash device using FlexSpi channel A interface pins." + }, + { + "name": "SDHC0_BOOT", + "value": 2, + "description": "Boot from eMMC device or SD card connected to SDHC0 port." + }, + { + "name": "SDHC1_BOOT", + "value": 3, + "description": "Boot from eMMC device or SD card connected to SDHC1 port." + }, + { + "name": "SPI_SLV_BOOT", + "value": 4, + "description": "Boot using SPI slave interface using master boot mode." + }, + { + "name": "QSPI_B_BOOT", + "value": 5, + "description": "Boot from Octal/Quad SPI flash device using FlexSpi channel B interface pins. Only load-to-RAM image are supported in this mode." + }, + { + "name": "UART_BOOT", + "value": 6, + "description": "Boot using UART interface using master boot mode." + }, + { + "name": "SPI_FC_BOOT", + "value": 7, + "description": "Boot from 1-bit SPI flash device from FlexCom interface pins selected by REDUNDANT_SPI_PORT field. Only load-to-RAM images are supported in this mode." + }, + { + "name": "ISP_MODE", + "value": 9, + "description": "Always enter ISP mode. DEFAULT_ISP_MODE field will determine the ISP interface." + }, + { + "name": "QSPI_B_REC_BOOT", + "value": 11, + "description": "Boot from Octal/Quad SPI flash device using FlexSPI channel B interface pins. If image is not found check recovery boot using SPI-flash device through FlexComm." + }, + { + "name": "QSPI_A_REC_BOOT", + "value": 12, + "description": "Boot from Octal/Quad SPI flash device using FlexSPI channel A interface pins. If image is not found check recovery boot using SPI-flash device through FlexComm." + }, + { + "name": "SDHC0_REC_BOOT", + "value": 13, + "description": "Boot from SDHC0 port device. If image is not found check recovery boot using SPI-flash device through FlexComm." + }, + { + "name": "SDHC1_REC_BOOT", + "value": 14, + "description": "Boot from SDHC1 port device. If image is not found check recovery boot using SPI-flash device through FlexComm." + } + ] + }, + { + "width": 3, + "id": "fuse96-bits-4-6", + "name": "DEFAULT_ISP_MODE", + "description": "When a valid image is not available to master boot, ROM switches to ISP mode for programming primary boot devices. This field determines the default ISP mode.", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto detect ISP mode. ROM monitors USB, UART, SPI and I2C interfaces for any activity." + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "Support ISP command interface using USB HID class only." + }, + { + "name": "UART_ISP", + "value": 2, + "description": "Support ISP command interface on UART port only." + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "Support ISP command interface on SPI port only." + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "Support ISP command interface on I2C port only." + }, + { + "name": "DISABLE_ISP", + "value": 7, + "description": "Disable ISP fall through when proper image is not found on primary boot device." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-7", + "name": "BOOT_CLK_SPEED", + "description": "Defines clock speeds during boot.", + "values": [ + { + "name": "NORMAL_CLK", + "value": 0, + "description": "Normal boot. All clocks are set to 48MHz using IRC48M, except USB block. USB block will use external XTAL clock." + }, + { + "name": "HISPEED_CLK", + "value": 1, + "description": "High-speed boot.\n o Core clock is set to 198MHz using main_pll with IRC48M as input\n o UART, I2C : 48MHz (IRC48M)\n o SPI, SDHC: 198MHz (main_pll)\n o USB: external XTAL\n o OSPI: Set to different speed using aux0_pll. Speed of OSPI interface is obtained from Boot Configuration Block present on OSPI-flash device.\n \u00b7 SDR: 30/50/60/72/80/90/100 MHz\n \u00b7 DDR: 30/50/60/72/80 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-8", + "name": "RSA4K_EN", + "description": "Use 4096 bit RSA keys only for certificate validations. By default the ROM assume 2048-bit keys.", + "values": [ + { + "name": "RSA2K", + "value": 0, + "description": "Use RSA2K or higher key length operations to validate certificates, image and debug credentials." + }, + { + "name": "RSA4K", + "value": 1, + "description": "Use RSA4K operations to validate certificates, image and debug credentials." + } + ] + }, + { + "width": 4 + }, + { + "width": 2, + "id": "fuse96-bits-13-14", + "name": "TZM_IMAGE_TYPE", + "description": "TZM_IMAGE_TYPE bit-field", + "values": [ + { + "name": "TZM_NORMAL", + "value": 0, + "description": "TrustZone-M mode is determined by the image header." + }, + { + "name": "TZM_DISABLE", + "value": 1, + "description": "Disable TrustZone-M features. ROM will always boot to a non-secure code and all TZ-M features are disabled." + }, + { + "name": "TZM_ENABLE", + "value": 2, + "description": "TrustZone-M features are enabled. ROM will always boot to secure code." + }, + { + "name": "TZM_PRESET", + "value": 3, + "description": "TrustZone-M features are enabled and setting are loaded from image header and locked before branching to user code." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-15", + "name": "PSA_BSTATE_SKIP", + "description": "If set, ROM skips computation of boot state defined by PSA specification. As part of boot state computation ROM includes OTP words \n- Shadow register values of 95 to 104 \n- Fuse values of words 128 to 147.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-16", + "name": "PSA_BSTATE_INC_KEYS", + "description": "If set, boot state computation includes OTP shadow register values of words 106 to 127.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 3, + "id": "fuse96-bits-17-19", + "name": "REDUNDANT_SPI_PORT", + "description": "FlexComm port to use for redundant SPI flash boot.", + "values": [ + { + "name": "FC0", + "value": 0, + "description": "Use FlexCom0 pins P0_0 (SCK), P0_1 (MISO), P0_2 (MOSI), P0_3 (SEL)" + }, + { + "name": "FC1", + "value": 1, + "description": "Use FlexCom1 pins P0_7 (SCK), P0_8 (MISO), P0_9 (MOSI), P0_10 (SEL)" + }, + { + "name": "FC2", + "value": 2, + "description": "Use FlexCom2 pins P0_14 (SCK), P0_15 (MISO), P0_16 (MOSI), P0_17 (SEL)" + }, + { + "name": "FC3", + "value": 3, + "description": "Use FlexCom3 pins P0_21 (SCK), P0_22 (MISO), P0_23 (MOSI), P0_24 (SEL)" + }, + { + "name": "FC4", + "value": 4, + "description": "Use FlexCom4 pins P0_28 (SCK), P0_29 (MISO), P0_30 (MOSI), P0_31 (SEL)" + }, + { + "name": "FC5", + "value": 5, + "description": "Use FlexCom5 pins P1_3 (SCK), P1_4 (MISO), P1_5 (MOSI), P1_6 (SEL)" + }, + { + "name": "FC6", + "value": 6, + "description": "Use FlexCom6 pins P3_25 (SCK), P3_26 (MISO), P3_27 (MOSI), P3_28 (SEL)" + }, + { + "name": "FC7", + "value": 7, + "description": "Use FlexCom7 pins P4_0 (SCK), P4_1 (MISO), P4_2 (MOSI), P4_3 (SEL)" + } + ] + }, + { + "width": 2, + "id": "fuse96-bits-20-21", + "name": "SECURE_BOOT_EN", + "description": "Force secure image only.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Allow non-secure images with and without CRC. Used during development." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Secure boot is enabled. The images have to be signed and optionally AES-CTR encrypted using pre-shared key. ROM does signature checking first and then does decryption of authenticated image." + }, + { + "name": "ENABLED_2", + "value": 2, + "description": "Secure boot is enabled." + }, + { + "name": "ENABLED_3", + "value": 3, + "description": "Secure boot is enabled." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-22", + "name": "DICE_INC_OTP", + "description": "Include non-field updatable OTP Fields in DICE computation. OTP values in shadow registers are used in computation for words 95, 96, 98, 99, 104, 120 - 127.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse96-bit-23", + "name": "DICE_SKIP", + "description": "If set, ROM skips computation of Composite Device Identifier (CDI) defined in DICE specification. But ROM will continue to hide UDS source in OTP and PUF (index 15) before passing control to user code.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8, + "id": "fuse96-bits-24-31", + "name": "BOOT_FAIL_PIN", + "description": "GPIO port and pin number to use for indicating boot failure. Boot ROM will drive this pin high before locking the chip on error conditions. Applications can use this pin to power cycle the system.\n[2:0] - Defines GPIO port\n[7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "fuse97", + "name": "BOOT_CFG1", + "description": "Boot configuration word specifying Quad/Octal-SPI flash devices settings.", + "deprecated_names": [ + "BOOT_CFG[1]" + ], + "index_int": "0x0061", + "shadow_reg_offset_int": "0x0184", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse97-bit-0", + "name": "QSPI_AUTO_PROBE_EN", + "description": "Quad/Octal-SPI flash auto probe feature enable.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-1-3", + "name": "QSPI_PROBE_TYPE", + "description": "Quad/Octal-SPI flash probe type.", + "values": [ + { + "name": "QSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + }, + { + "name": "MICRON_OCTAL", + "value": 1, + "description": "Micron Octal FLASH" + }, + { + "name": "MACRONIX_OCTAL", + "value": 2, + "description": "Macronix Octal FLASH" + }, + { + "name": "ADESTO_OCTAL", + "value": 3, + "description": "Adesto Octal FLASH" + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-4-6", + "name": "QSPI_FLASH_TYPE", + "description": "Define typical Serial NOR Flash types", + "values": [ + { + "name": "QSPI_ADDR_3B", + "value": 0, + "description": "Use 3byte (24-bit) address read (0x03) by default" + }, + { + "name": "QSPI_ADDR_4B", + "value": 1, + "description": "Use 4byte (32-bit) address read (0x13) by default" + }, + { + "name": "HYPER_1V8", + "value": 2, + "description": "HyperFlash 1V8" + }, + { + "name": "HYPER_3V3", + "value": 3, + "description": "HyperFlash 3V3" + }, + { + "name": "OSPI_DDR_MXIC", + "value": 4, + "description": "MXIC Octal DDR" + }, + { + "name": "OSPI_DDR_MICRON", + "value": 5, + "description": "Micron Octal DDR" + } + ] + }, + { + "width": 4, + "id": "fuse97-bits-7-10", + "name": "QSPI_DUMMY_CYCLES", + "description": "Quad/Octal-SPI dummy cycles for read command." + }, + { + "width": 3, + "id": "fuse97-bits-11-13", + "name": "QSPI_FREQUENCY", + "description": "Quad/Octal-SPI flash interface frequency.", + "values": [ + { + "name": "QSPI_60MHZ", + "value": 0, + "description": "60MHz" + }, + { + "name": "QSPI_80MHZ", + "value": 1, + "description": "80MHz" + }, + { + "name": "QSPI_90MHZ", + "value": 2, + "description": "90MHz" + }, + { + "name": "QSPI_100MHZ", + "value": 3, + "description": "100MHz" + }, + { + "name": "QSPI_120MHZ", + "value": 4, + "description": "120MHz" + }, + { + "name": "QSPI_133MHZ", + "value": 5, + "description": "133MHz" + }, + { + "name": "QSPI_166MHZ", + "value": 6, + "description": "166MHz" + }, + { + "name": "QSPI_200MHZ", + "value": 7, + "description": "200MHz" + } + ] + }, + { + "width": 1, + "id": "fuse97-bit-14", + "name": "QSPI_RESET_PIN_ENABLE", + "description": "Use QSPI_RESET_PIN to reset the flash device.", + "values": [ + { + "name": "NO_RESET", + "value": 0, + "description": "Octal/QSPI device reset pin is not connected or available." + }, + { + "name": "EN_RESET", + "value": 1, + "description": "Octal/QSPI device reset pin is connected to a GPIO (QSPI_RESET_PIN)." + } + ] + }, + { + "width": 3, + "id": "fuse97-bits-15-17", + "name": "QSPI_RESET_PIN_GPIO_PORT", + "description": "GPIO port and pin number to use for O/QSPI reset function.\nDefines GPIO port." + }, + { + "width": 5, + "id": "fuse97-bits-18-22", + "name": "QSPI_RESET_PIN_GPIO_PIN_NUM", + "description": "GPIO port and pin number to use for O/QSPI reset function.\nDefines GPIO pin number." + }, + { + "width": 2, + "id": "fuse97-bits-23-24", + "name": "QSPI_HOLD TIME", + "description": "Wait time before access to Serial Flash.", + "values": [ + { + "name": "WAIT_500_US", + "value": 0, + "description": "Wait for 500 micro seconds." + }, + { + "name": "WAIT_1_MS", + "value": 1, + "description": "Wait for 1 milliseconds." + }, + { + "name": "WAIT_3_MS", + "value": 2, + "description": "Wait for 3 milliseconds." + }, + { + "name": "WAIT_10_MS", + "value": 3, + "description": "Wait for 10 milliseconds." + } + ] + }, + { + "width": 4, + "id": "fuse97-bits-25-28", + "name": "QSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by QSPI_HOLD TIME field.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No delay" + }, + { + "name": "100US_DELAY", + "value": 1, + "description": "Waits additional 100 micro-seconds." + }, + { + "name": "500US_DELAY", + "value": 2, + "description": "Waits additional 500 micro-seconds." + }, + { + "name": "1MS_DELAY", + "value": 3, + "description": "Waits additional 1 milli-seconds." + }, + { + "name": "10MS_DELAY", + "value": 4, + "description": "Waits additional 10 milli-seconds." + }, + { + "name": "20MS_DELAY", + "value": 5, + "description": "Waits additional 20 milli-seconds." + }, + { + "name": "40MS_DELAY", + "value": 6, + "description": "Waits additional 40 milli-seconds." + }, + { + "name": "60MS_DELAY", + "value": 7, + "description": "Waits additional 60 milli-seconds." + }, + { + "name": "80MS_DELAY", + "value": 8, + "description": "Waits additional 80 milli-seconds." + }, + { + "name": "100MS_DELAY", + "value": 9, + "description": "Waits additional 100 milli-seconds." + }, + { + "name": "120MS_DELAY", + "value": 10, + "description": "Waits additional 120 milli-seconds." + }, + { + "name": "140MS_DELAY", + "value": 11, + "description": "Waits additional 140 milli-seconds." + }, + { + "name": "160MS_DELAY", + "value": 12, + "description": "Waits additional 160 milli-seconds." + }, + { + "name": "180MS_DELAY", + "value": 13, + "description": "Waits additional 180 milli-seconds." + }, + { + "name": "200MS_DELAY", + "value": 14, + "description": "Waits additional 200 milli-seconds." + }, + { + "name": "220MS_DELAY", + "value": 15, + "description": "Waits additional 220 milli-seconds." + } + ] + }, + { + "width": 3 + } + ] + }, + { + "id": "fuse98", + "name": "BOOT_CFG2", + "description": "Boot configuration word specifying settings for SD card and eMMC boot interface.", + "deprecated_names": [ + "BOOT_CFG[2]" + ], + "index_int": "0x0062", + "shadow_reg_offset_int": "0x0188", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x4000" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse98-bit-0", + "name": "SDHC_DEVICE_TYPE", + "description": "Device type connected to SDHC port.", + "values": [ + { + "name": "eMMC_DEV", + "value": 0, + "description": "eMMC device" + }, + { + "name": "SD_DEV", + "value": 1, + "description": "SD card device" + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-1-2", + "name": "SDHC_BUS_WIDTH", + "description": "Bus width of the device connected to SDHC.", + "values": [ + { + "name": "SD_1B_MMC_4B", + "value": 0, + "description": "For SD cards use 1-bit data bus. \nFor eMMC use 4-bit data bus." + }, + { + "name": "SD_4B_MMC_8B", + "value": 1, + "description": "For SD cards use 4-bit data bus. \nFor eMMC use 8-bit data bus." + }, + { + "name": "MMC_4B_DDR", + "value": 2, + "description": "For eMMC use 4-bit bus in DDR mode." + }, + { + "name": "MMC_8B_DDR", + "value": 3, + "description": "For eMMC use 8-bit bus in DDR mode." + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-3-4", + "name": "SDHC_SPEED", + "description": "Speed ratings of eMMC devices and SD card devices.", + "values": [ + { + "name": "NORMAL", + "value": 0, + "description": "Normal speed for eMMC devices. SDR12 speeds for SD." + }, + { + "name": "HIGH", + "value": 1, + "description": "High speed for eMMC devices. SDR25 speeds for SD." + }, + { + "name": "SDR50", + "value": 2, + "description": "SDR50 speeds for SD card." + }, + { + "name": "SDR104", + "value": 3, + "description": "SDR104" + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-5", + "name": "SDHC_PWR_CYCLE_EN", + "description": "Enable SDHC power cycle via USDHC_RST pad.", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disabled." + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enabled." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-6", + "name": "SDHC0_PWR_POL", + "description": "Polarity of power enable signal for SDHC0 port.", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high signal." + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low signal." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-7", + "name": "SDHC1_PWR_POL", + "description": "Polarity of power enable signal for SDHC1 port.", + "values": [ + { + "name": "ACTIVE_HIGH", + "value": 0, + "description": "Active high signal." + }, + { + "name": "ACTIVE_LOW", + "value": 1, + "description": "Active low signal." + } + ] + }, + { + "width": 2, + "id": "fuse98-bits-8-9", + "name": "SDHC_PWR_CYCLE_WAIT", + "description": "Wait time after powering down the SDHC devices.", + "values": [ + { + "name": "WAIT_20_MS", + "value": 0, + "description": "Wait 20 milliseconds." + }, + { + "name": "WAIT_10_MS", + "value": 1, + "description": "Wait 10 milliseconds." + }, + { + "name": "WAIT_05_MS", + "value": 2, + "description": "Wait 5 milliseconds." + }, + { + "name": "WAIT_2_5_MS", + "value": 3, + "description": "Wait 2.5 milliseconds." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-10", + "name": "SDHC_PWR_STABLE_WAIT", + "description": "Wait time for power to stabilize after enabling power to SDHC devices.", + "values": [ + { + "name": "WAIT_5_MS", + "value": 0, + "description": "Wait 5 milliseconds." + }, + { + "name": "WAIT_2_5_MS", + "value": 1, + "description": "Wait 2.5 milliseconds." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-11", + "name": "SDHC0_CARD_VOLTAGE", + "description": "SD Voltage selection for SDHC0 port.", + "values": [ + { + "name": "3V3", + "value": 0, + "description": "Uses 3v3 rail." + }, + { + "name": "1V8", + "value": 1, + "description": "Uses 1v8 rail." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-12", + "name": "SDHC1_CARD_VOLTAGE", + "description": "SD Voltage selection for SDHC1 port.", + "values": [ + { + "name": "3V3", + "value": 0, + "description": "Uses 3v3 rail." + }, + { + "name": "1V8", + "value": 1, + "description": "Uses 1v8 rail." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-13", + "name": "MMC_RESET_PRE_IDLE_STATE", + "description": "Reset the MMC to Pre-Idle state before starting boot mode", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-14", + "name": "SDHC_FASTBOOT_MODE", + "description": "Specifies if the boot mode is enabled in Extended CSD register of the eMMC device.", + "values": [ + { + "name": "NORMAL_MODE", + "value": 0, + "description": "eMMC operates in transfer mode after power-up." + }, + { + "name": "BOOT_MODE", + "value": 1, + "description": "eMMC operates in boot mode after power-up." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-15", + "name": "SDHC_FASTBOOT_ACK_EN", + "description": "Specifies if the eMMC device sends boot acknowledge pattern during boot operation.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-16", + "name": "SDHC_PAD_CTL_FREEZE", + "description": "When using SDHC interface in high speed modes, the auto pad compensation control logic could cause interference due to modifications in IO drive strength. Hence it is recommended to freeze the compensated value and enable auto compensation periodically in application code by putting the pad back to normal mode. When this field is set ROM freezes the auto compensation circuit during boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-17", + "name": "SDHC_PAD_CTL_FAST_FREEZE", + "description": "Same as SDHC_PAD_CTL_FREEZE, but in this mode the time taken for switching the compensation from Fast Freeze mode to Normal mode is considerably smaller than the delay incurred in switching from Freeze mode to Normal mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-18", + "name": "QSPI_PAD_CTL_FREEZE", + "description": "When using QSPI interface in high speed modes, the auto pad compensation control logic could cause interference due to modifications in IO drive strength. Hence it is recommended to freeze the compensated value and enable auto compensation periodically in application code by putting the pad back to normal mode. When this field is set ROM freezes the auto compensation circuit during boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse98-bit-19", + "name": "QSPI_PAD_CTL_FAST_FREEZE", + "description": "Same as QSPI_PAD_CTL_FREEZE, but in this mode the time taken for switching the compensation from Fast Freeze mode to Normal mode is considerably smaller than the delay incurred in switching from Freeze mode to Normal mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 8 + }, + { + "width": 4, + "id": "fuse98-bits-28-31", + "name": "QSPI_IMAGE_SIZE", + "description": "Any offset in memory mapped FlexSPI area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which are programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped.", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "Size of the remapped area (aka second half) is same as first half. It is determined by QSPI_IMAGE_OFFSET Field. \n Remap size = QSPI_IMAGE_OFFSET * 256KByte;" + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "Size of remapped area is 768KByte." + } + ] + } + ] + }, + { + "id": "fuse99", + "name": "BOOT_CFG3", + "description": "Boot configuration word specifying delay lines settings for SDHC and QSPI interfaces.", + "deprecated_names": [ + "BOOT_CFG[3]" + ], + "index_int": "0x0063", + "shadow_reg_offset_int": "0x018C", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x8000" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse99-bits-0-6", + "name": "QSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via DQS (either internal loopback or external DQS)" + }, + { + "width": 1, + "id": "fuse99-bit-7", + "name": "SDHC_DLL_TUNING_OVERRIDE_ENABLE", + "description": "SDHC_DLL_TUNING_OVERRIDE_ENABLE bit-field", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Default\uff1a DLL delay tuning start 10, DLL delay tuning step 2 ( this config can cover most of user cases.)" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Override by SDHC_DLL_SETTING" + } + ] + }, + { + "width": 8, + "id": "fuse99-bits-8-15", + "name": "SDHC_DLL_TUNING_START", + "description": "DLL delay tuning start." + }, + { + "width": 3, + "id": "fuse99-bits-16-18", + "name": "SDHC_DLL_TUNING_STEP", + "description": "DLL delay tuning step." + }, + { + "width": 3, + "id": "fuse99-bits-19-21", + "name": "USB_PLL_DIV_SEL", + "description": "USB PLL divider value. Used for configuring USB PLL during USB ISP and DFU boot modes. The value corresponds to the PLL_DIV_SEL field of the USBPHY_PLL_SIC register." + }, + { + "width": 10, + "id": "fuse99-bits-22-31", + "name": "QSPI_IMAGE_OFFSET", + "description": "Any offset within memory mapped FlexSPI area could be remapped to offset zero to support eXecute In Place (XIP) of image programmed at different offset. This allows to build all update images with same RO base address, which can be programmed at offset 0 or higher offset. QSPI_IMAGE_OFFSET field specifies the offset location of second image. QSPI_IMAGE_SIZE field specifies the size multiple to determine the size of area to be remapped. \nIf this field is left blank boot ROM assumes that application intends to not use dual image boot feature. The physical flash offset is computed as below:\n physical offset = QSPI_IMAGE_OFFSET * 256KByte;" + } + ] + } + ] + }, + { + "group": { + "name": "SECURITY_EPOCH", + "description": "OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different lifecycle stages of the device." + }, + "registers": [ + { + "id": "fuse101", + "name": "SEC_BOOT_CFG5", + "description": "Boot configuration word5. \n- This word is set in redundant mode. Thus individual bits can be programmed separately at different lifecycle stages of the device.", + "deprecated_names": [ + "SEC_BOOT_CFG[5]" + ], + "index_int": "0x0065", + "shadow_reg_offset_int": "0x0194", + "individual_write_lock": "user", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0200" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse101-bits-0-3", + "name": "REVOKE_ROOTKEY", + "description": "Revoke up to 4 root keys. When a bit is set corresponding root key is revoked." + }, + { + "width": 1, + "id": "fuse101-bit-4", + "name": "FA_MODE_EN", + "description": "Enable Fault Analysis mode.\n- When set ROM checks and erases customer sensitive assets (AES keys or key codes) stored in IFR/OTP. \n- Issues zeroized command to PUF (disables key decoding until POR)\n- Blocks all HW routed OTP keys and set lock bits on those registers\n- Enables all debug ports and waits in loop for tester.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2, + "id": "fuse101-bits-5-6", + "name": "ENABLE_CRC_CHECK", + "description": "Enable CRC checking of OTP words.", + "values": [ + { + "name": "CRC_DISABLE", + "value": 0, + "description": "CRC checking of OTP words is disabled." + }, + { + "name": "CRC_ENABLE", + "value": 1, + "description": "CRC check of all OTP words is enabled." + }, + { + "name": "CRC_NXPONLY", + "value": 2, + "description": "CRC check is enabled only for NXP programmed OTP words." + }, + { + "name": "CRC_ENABLE2", + "value": 3, + "description": "CRC check of all OTP words is enabled." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-7", + "name": "USE_PUF", + "description": "Use PUF to store AES keys and UDS.", + "values": [ + { + "name": "KEY_IN_OTP", + "value": 0, + "description": "AES keys and UDS are read from OTP." + }, + { + "name": "KEY_IN_PUF", + "value": 1, + "description": "AES keys and UDS are read from PUF." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-8", + "name": "PUF_BLOCK_ENROLL", + "description": "Block further enrollment of PUF block. When this bit is set ROM blocks generation of new activation codes.", + "values": [ + { + "name": "ENROLL_EN", + "value": 0, + "description": "Enable generation of new activation code." + }, + { + "name": "ENROLL_DIS", + "value": 1, + "description": "Disable generation of new activation code." + } + ] + }, + { + "width": 1, + "id": "fuse101-bit-9", + "name": "PUF_BLOCK_SET_KEY", + "description": "Block further enrollment of PUF block. When this bit is set ROM blocks generation of new key codes.", + "values": [ + { + "name": "KEY_GEN_EN", + "value": 0, + "description": "Enable generation of new key codes." + }, + { + "name": "KEY_GEN_DIS", + "value": 1, + "description": "Disable generation of new key codes." + } + ] + }, + { + "width": 6 + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse102", + "name": "REVOKE_IMG_KEY", + "description": "Image keys revocation identifier.", + "index_int": "0x0066", + "shadow_reg_offset_int": "0x0198", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse102-bits-0-15", + "name": "REVOKE_IMG_KEY", + "description": "To implement anti-rollback feature, the image key certificate should be revoked using this field. The in-field FW update process should blow the least unblown bit. During image key certificate validation this field is compare with the certificate content (upper 2 bytes of serial number field in X.509 certificate)." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse103", + "name": "SEC_BOOT_CFG7", + "description": "Boot configuration word7. \n- This word is set in redundant mode. Thus individual bits can be programmed separately at different lifecycle stages of the device.", + "deprecated_names": [ + "SEC_BOOT_CFG[7]" + ], + "index_int": "0x0067", + "shadow_reg_offset_int": "0x019C", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse103-bits-0-15", + "name": "DAP_VENDOR_USAGE", + "description": "Lower 16-bits of Vendor Usage field in Debug Credentials defined in NXP's Debug Authentication Protocol specifications Version 1.0." + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "USB_CFG", + "description": "USB_CFG group" + }, + "registers": [ + { + "id": "fuse105", + "name": "USB_ID", + "description": "Override default USB ID's used by ROM during USB master boot and ISP modes.", + "index_int": "0x0069", + "individual_write_lock": "always_lock", + "bitfields": [ + { + "width": 16, + "id": "fuse105-bits-0-15", + "name": "USB_VID", + "description": "USB vendor ID." + }, + { + "width": 16, + "id": "fuse105-bits-16-31", + "name": "USB_PID", + "description": "USB product ID." + } + ] + } + ] + }, + { + "group": { + "name": "OTFAD_CFG", + "description": "OTFAD_CFG group" + }, + "registers": [ + { + "id": "fuse106", + "name": "OTFAD_CFG", + "description": "Configuration word to control OTFAD key blob loading during boot process.", + "index_int": "0x006A", + "shadow_reg_offset_int": "0x01A8", + "individual_write_lock": "user", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0004" + }, + "bitfields": [ + { + "width": 12 + }, + { + "width": 1, + "id": "fuse106-bit-12", + "name": "OTFAD_ENABLE", + "description": "When this field is set, it indicates to ROM that OTFAD feature is enabled and should initialize the OTFAD engine before accessing the memory mapped QSPI flash buffer area.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 1, + "id": "fuse106-bit-13", + "name": "KEYBLOB_RESTRICT_REG", + "description": "ROM after loading OTFAD registers restricts read access before jumping to user code. Only CTR registers are writable in this mode.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Value 0." + }, + { + "name": "1", + "value": 1, + "description": "Value 1." + } + ] + }, + { + "width": 2 + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "KEY_STORE", + "description": "KEY_STORE group" + }, + "registers": [ + { + "id": "fuse107", + "name": "KEY_SCRAMBLE_SEED", + "description": "Key scramble data used as input to scramble master key stored in OTP.", + "index_int": "0x006B", + "shadow_reg_offset_int": "0x01AC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0010", + "read_lock_int": "0x0020" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse107-bits-0-31", + "name": "SCRAMBLE_INPUT", + "description": "32-bit random value programmed by user which will be used as one of the two inputs to scramble OTP_MASTER_KEY key." + } + ] + }, + { + "id": "fuse108", + "name": "OTFAD_KEK_SEED_31_0", + "description": "When OTP key store is used (USE_PUF = 0), this 128-bit user programmed value is used to derive OTFAD_KEK.\n\nOTFAD_KEK[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, OTFAD_KEK_SEED[127:0]);", + "index_int": "0x006C", + "shadow_reg_offset_int": "0x01B0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse109", + "name": "OTFAD_KEK_SEED_63_32", + "description": "OTFAD_KEK_SEED_63_32 register", + "index_int": "0x006D", + "shadow_reg_offset_int": "0x01B4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse110", + "name": "OTFAD_KEK_SEED_95_64", + "description": "OTFAD_KEK_SEED_95_64 register", + "index_int": "0x006E", + "shadow_reg_offset_int": "0x01B8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse111", + "name": "OTFAD_KEK_SEED_127_96", + "description": "OTFAD_KEK_SEED_127_96 register", + "index_int": "0x006F", + "shadow_reg_offset_int": "0x01BC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0040" + } + }, + { + "id": "fuse112", + "name": "OTP_MASTER_KEY[31:0]", + "description": "Master Key used to derive different usage keys (HMAC_KEY, ENC_IMAGE_KEY, SB2_KEK, OTFAD_KEK). \n\n- ENC_BOOT_HMAC_KEY[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000000);\n- ENC_BOOT_AES_KEY[255:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000001) || AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000002);\n- SB_KEK[255:0] = AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000003) || AES_ENCRYPT (OTP_MASTER_KEY, 0x00000000000000000000000000000004); \n- OTFAD_KEK[127:0] = AES_ENCRYPT (OTP_MASTER_KEY, OTFAD_KEK_SEED[127:0]);", + "index_int": "0x0070", + "shadow_reg_offset_int": "0x01C0", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse113", + "name": "OTP_MASTER_KEY[63:32]", + "description": "OTP_MASTER_KEY[63:32] register", + "index_int": "0x0071", + "shadow_reg_offset_int": "0x01C4", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse114", + "name": "OTP_MASTER_KEY[95:64]", + "description": "OTP_MASTER_KEY[95:64] register", + "index_int": "0x0072", + "shadow_reg_offset_int": "0x01C8", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse115", + "name": "OTP_MASTER_KEY[127:96]", + "description": "OTP_MASTER_KEY[127:96] register", + "index_int": "0x0073", + "shadow_reg_offset_int": "0x01CC", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse116", + "name": "OTP_MASTER_KEY[159:128]", + "description": "OTP_MASTER_KEY[159:128] register", + "index_int": "0x0074", + "shadow_reg_offset_int": "0x01D0", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse117", + "name": "OTP_MASTER_KEY[191:160]", + "description": "OTP_MASTER_KEY[191:160] register", + "index_int": "0x0075", + "shadow_reg_offset_int": "0x01D4", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse118", + "name": "OTP_MASTER_KEY[223:192]", + "description": "OTP_MASTER_KEY[223:192] register", + "index_int": "0x0076", + "shadow_reg_offset_int": "0x01D8", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse119", + "name": "OTP_MASTER_KEY[255:224]", + "description": "OTP_MASTER_KEY[255:224] register", + "index_int": "0x0077", + "shadow_reg_offset_int": "0x01DC", + "access": "WO", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse8", + "write_lock_int": "0x0100" + } + }, + { + "id": "fuse120", + "name": "RKTH_255_224", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys (modulus || exponent).\nFor i in 0..3:\n Let M[i] = BE(Modulus i)\n Let E[i] = BE(Exponent i)\n Let RKH[i] = SHA256( M[i] || E[i] )\n Let RKTH = SHA256( RKH[0] || RKH[1] || RKH[2] || RKH[3] )\nNote: Documentation update needed when using blhost due to endianness issue.", + "index_int": "0x0078", + "shadow_reg_offset_int": "0x01E0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse121", + "name": "RKTH_223_192", + "description": "RKTH_223_192 register", + "index_int": "0x0079", + "shadow_reg_offset_int": "0x01E4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse122", + "name": "RKTH_191_160", + "description": "RKTH_191_160 register", + "index_int": "0x007A", + "shadow_reg_offset_int": "0x01E8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse123", + "name": "RKTH_159_128", + "description": "RKTH_159_128 register", + "index_int": "0x007B", + "shadow_reg_offset_int": "0x01EC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse124", + "name": "RKTH_127_96", + "description": "RKTH_127_96 register", + "index_int": "0x007C", + "shadow_reg_offset_int": "0x01F0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse125", + "name": "RKTH_95_64", + "description": "RKTH_95_64 register", + "index_int": "0x007D", + "shadow_reg_offset_int": "0x01F4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse126", + "name": "RKTH_63_32", + "description": "RKTH_63_32 register", + "index_int": "0x007E", + "shadow_reg_offset_int": "0x01F8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + }, + { + "id": "fuse127", + "name": "RKTH_31_0", + "description": "RKTH_31_0 register", + "index_int": "0x007F", + "shadow_reg_offset_int": "0x01FC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x1000" + } + } + ] + }, + { + "group": { + "name": "NT_FW_VERSION", + "description": "NT_FW_VERSION group" + }, + "registers": [ + { + "id": "fuse128", + "name": "NT_FW_VER_15_0", + "description": "Non-trusted firmware version counter (0 - 255). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0080", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse128-bits-0-15", + "name": "NT_FW_VER_15_0", + "description": "Non-trusted firmware version counter (0 - 255). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse129", + "name": "NT_FW_VER_31_16", + "description": "NT_FW_VER_31_16 register", + "index_int": "0x0081", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse129-bits-0-15", + "name": "NT_FW_VER_31_16", + "description": "NT_FW_VER_31_16 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse130", + "name": "NT_FW_VER_47_32", + "description": "NT_FW_VER_47_32 register", + "index_int": "0x0082", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse130-bits-0-15", + "name": "NT_FW_VER_47_32", + "description": "NT_FW_VER_47_32 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse131", + "name": "NT_FW_VER_63_48", + "description": "NT_FW_VER_63_48 register", + "index_int": "0x0083", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse131-bits-0-15", + "name": "NT_FW_VER_63_48", + "description": "NT_FW_VER_63_48 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse132", + "name": "NT_FW_VER_79_64", + "description": "NT_FW_VER_79_64 register", + "index_int": "0x0084", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse132-bits-0-15", + "name": "NT_FW_VER_79_64", + "description": "NT_FW_VER_79_64 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse133", + "name": "NT_FW_VER_95_80", + "description": "NT_FW_VER_95_80 register", + "index_int": "0x0085", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse133-bits-0-15", + "name": "NT_FW_VER_95_80", + "description": "NT_FW_VER_95_80 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse134", + "name": "NT_FW_VER_111_96", + "description": "NT_FW_VER_111_96 register", + "index_int": "0x0086", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse134-bits-0-15", + "name": "NT_FW_VER_111_96", + "description": "NT_FW_VER_111_96 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse135", + "name": "NT_FW_VER_127_112", + "description": "NT_FW_VER_127_112 register", + "index_int": "0x0087", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse135-bits-0-15", + "name": "NT_FW_VER_127_112", + "description": "NT_FW_VER_127_112 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse136", + "name": "NT_FW_VER_143_128", + "description": "NT_FW_VER_143_128 register", + "index_int": "0x0088", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse136-bits-0-15", + "name": "NT_FW_VER_143_128", + "description": "NT_FW_VER_143_128 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse137", + "name": "NT_FW_VER_159_144", + "description": "NT_FW_VER_159_144 register", + "index_int": "0x0089", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse137-bits-0-15", + "name": "NT_FW_VER_159_144", + "description": "NT_FW_VER_159_144 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse138", + "name": "NT_FW_VER_175_160", + "description": "NT_FW_VER_175_160 register", + "index_int": "0x008A", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse138-bits-0-15", + "name": "NT_FW_VER_175_160", + "description": "NT_FW_VER_175_160 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse139", + "name": "NT_FW_VER_191_176", + "description": "NT_FW_VER_191_176 register", + "index_int": "0x008B", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse139-bits-0-15", + "name": "NT_FW_VER_191_176", + "description": "NT_FW_VER_191_176 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse140", + "name": "NT_FW_VER_207_192", + "description": "NT_FW_VER_207_192 register", + "index_int": "0x008C", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse140-bits-0-15", + "name": "NT_FW_VER_207_192", + "description": "NT_FW_VER_207_192 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse141", + "name": "NT_FW_VER_223_208", + "description": "NT_FW_VER_223_208 register", + "index_int": "0x008D", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse141-bits-0-15", + "name": "NT_FW_VER_223_208", + "description": "NT_FW_VER_223_208 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse142", + "name": "NT_FW_VER_239_224", + "description": "NT_FW_VER_239_224 register", + "index_int": "0x008E", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse142-bits-0-15", + "name": "NT_FW_VER_239_224", + "description": "NT_FW_VER_239_224 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse143", + "name": "NT_FW_VER_255_240", + "description": "NT_FW_VER_255_240 register", + "index_int": "0x008F", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse143-bits-0-15", + "name": "NT_FW_VER_255_240", + "description": "NT_FW_VER_255_240 register" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "TZ_FW_VERSION", + "description": "TZ_FW_VERSION group" + }, + "registers": [ + { + "id": "fuse144", + "name": "TZ_FW_VER_15_0", + "description": "Trusted firmware version counter (0 - 63). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0090", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse144-bits-0-15", + "name": "TZ_FW_VER_15_0", + "description": "Trusted firmware version counter (0 - 63). OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse145", + "name": "TZ_FW_VER_31_16", + "description": "TZ_FW_VER_31_16 register", + "index_int": "0x0091", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse145-bits-0-15", + "name": "TZ_FW_VER_31_16", + "description": "TZ_FW_VER_31_16 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse146", + "name": "TZ_FW_VER_47_32", + "description": "TZ_FW_VER_47_32 register", + "index_int": "0x0092", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse146-bits-0-15", + "name": "TZ_FW_VER_47_32", + "description": "TZ_FW_VER_47_32 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse147", + "name": "TZ_FW_VER_63_48", + "description": "TZ_FW_VER_63_48 register", + "index_int": "0x0093", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse147-bits-0-15", + "name": "TZ_FW_VER_63_48", + "description": "TZ_FW_VER_63_48 register" + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "USER_DATA", + "description": "USER_DATA group" + }, + "registers": [ + { + "id": "fuse148", + "name": "USER_RED_0", + "description": "Customer defined data.OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device.", + "index_int": "0x0094", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse148-bits-0-15", + "name": "USER_RED_0", + "description": "Customer defined data.OTP words in this block are redundant fuse words. Thus individual bits can be programmed separately at different point in time throughout the life of device." + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse149", + "name": "USER_RED_1", + "description": "USER_RED_1 register", + "index_int": "0x0095", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse149-bits-0-15", + "name": "USER_RED_1", + "description": "USER_RED_1 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse150", + "name": "USER_RED_2", + "description": "USER_RED_2 register", + "index_int": "0x0096", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse150-bits-0-15", + "name": "USER_RED_2", + "description": "USER_RED_2 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse151", + "name": "USER_RED_3", + "description": "USER_RED_3 register", + "index_int": "0x0097", + "individual_write_lock": "user", + "bitfields": [ + { + "width": 16, + "id": "fuse151-bits-0-15", + "name": "USER_RED_3", + "description": "USER_RED_3 register" + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse152", + "name": "USER_ECC_0", + "description": "Customer defined data.OTP words in this block are ECC fuse words. Thus all bits in these words can be programmed at one shot.", + "index_int": "0x0098", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse153", + "name": "USER_ECC_1", + "description": "USER_ECC_1 register", + "index_int": "0x0099", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse154", + "name": "USER_ECC_2", + "description": "USER_ECC_2 register", + "index_int": "0x009A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse155", + "name": "USER_ECC_3", + "description": "USER_ECC_3 register", + "index_int": "0x009B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse156", + "name": "USER_ECC_4", + "description": "USER_ECC_4 register", + "index_int": "0x009C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse157", + "name": "USER_ECC_5", + "description": "USER_ECC_5 register", + "index_int": "0x009D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse158", + "name": "USER_ECC_6", + "description": "USER_ECC_6 register", + "index_int": "0x009E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse159", + "name": "USER_ECC_7", + "description": "USER_ECC_7 register", + "index_int": "0x009F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK1", + "description": "USER_BANK1 group" + }, + "registers": [ + { + "id": "fuse392", + "name": "USER_BANK1_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0188", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse393", + "name": "USER_BANK1_1", + "description": "USER_BANK1_1 register", + "index_int": "0x0189", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse394", + "name": "USER_BANK1_2", + "description": "USER_BANK1_2 register", + "index_int": "0x018A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse395", + "name": "USER_BANK1_3", + "description": "USER_BANK1_3 register", + "index_int": "0x018B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse396", + "name": "USER_BANK1_4", + "description": "USER_BANK1_4 register", + "index_int": "0x018C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse397", + "name": "USER_BANK1_5", + "description": "USER_BANK1_5 register", + "index_int": "0x018D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse398", + "name": "USER_BANK1_6", + "description": "USER_BANK1_6 register", + "index_int": "0x018E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse399", + "name": "USER_BANK1_7", + "description": "USER_BANK1_7 register", + "index_int": "0x018F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK2", + "description": "USER_BANK2 group" + }, + "registers": [ + { + "id": "fuse400", + "name": "USER_BANK2_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0190", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse401", + "name": "USER_BANK2_1", + "description": "USER_BANK2_1 register", + "index_int": "0x0191", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse402", + "name": "USER_BANK2_2", + "description": "USER_BANK2_2 register", + "index_int": "0x0192", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse403", + "name": "USER_BANK2_3", + "description": "USER_BANK2_3 register", + "index_int": "0x0193", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse404", + "name": "USER_BANK2_4", + "description": "USER_BANK2_4 register", + "index_int": "0x0194", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse405", + "name": "USER_BANK2_5", + "description": "USER_BANK2_5 register", + "index_int": "0x0195", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse406", + "name": "USER_BANK2_6", + "description": "USER_BANK2_6 register", + "index_int": "0x0196", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse407", + "name": "USER_BANK2_7", + "description": "USER_BANK2_7 register", + "index_int": "0x0197", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK3", + "description": "USER_BANK3 group" + }, + "registers": [ + { + "id": "fuse408", + "name": "USER_BANK3_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x0198", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse409", + "name": "USER_BANK3_1", + "description": "USER_BANK3_1 register", + "index_int": "0x0199", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse410", + "name": "USER_BANK3_2", + "description": "USER_BANK3_2 register", + "index_int": "0x019A", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse411", + "name": "USER_BANK3_3", + "description": "USER_BANK3_3 register", + "index_int": "0x019B", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse412", + "name": "USER_BANK3_4", + "description": "USER_BANK3_4 register", + "index_int": "0x019C", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse413", + "name": "USER_BANK3_5", + "description": "USER_BANK3_5 register", + "index_int": "0x019D", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse414", + "name": "USER_BANK3_6", + "description": "USER_BANK3_6 register", + "index_int": "0x019E", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse415", + "name": "USER_BANK3_7", + "description": "USER_BANK3_7 register", + "index_int": "0x019F", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK4", + "description": "USER_BANK4 group" + }, + "registers": [ + { + "id": "fuse416", + "name": "USER_BANK4_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01A0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse417", + "name": "USER_BANK4_1", + "description": "USER_BANK4_1 register", + "index_int": "0x01A1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse418", + "name": "USER_BANK4_2", + "description": "USER_BANK4_2 register", + "index_int": "0x01A2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse419", + "name": "USER_BANK4_3", + "description": "USER_BANK4_3 register", + "index_int": "0x01A3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse420", + "name": "USER_BANK4_4", + "description": "USER_BANK4_4 register", + "index_int": "0x01A4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse421", + "name": "USER_BANK4_5", + "description": "USER_BANK4_5 register", + "index_int": "0x01A5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse422", + "name": "USER_BANK4_6", + "description": "USER_BANK4_6 register", + "index_int": "0x01A6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse423", + "name": "USER_BANK4_7", + "description": "USER_BANK4_7 register", + "index_int": "0x01A7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK5", + "description": "USER_BANK5 group" + }, + "registers": [ + { + "id": "fuse424", + "name": "USER_BANK5_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01A8", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse425", + "name": "USER_BANK5_1", + "description": "USER_BANK5_1 register", + "index_int": "0x01A9", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse426", + "name": "USER_BANK5_2", + "description": "USER_BANK5_2 register", + "index_int": "0x01AA", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse427", + "name": "USER_BANK5_3", + "description": "USER_BANK5_3 register", + "index_int": "0x01AB", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse428", + "name": "USER_BANK5_4", + "description": "USER_BANK5_4 register", + "index_int": "0x01AC", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse429", + "name": "USER_BANK5_5", + "description": "USER_BANK5_5 register", + "index_int": "0x01AD", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse430", + "name": "USER_BANK5_6", + "description": "USER_BANK5_6 register", + "index_int": "0x01AE", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse431", + "name": "USER_BANK5_7", + "description": "USER_BANK5_7 register", + "index_int": "0x01AF", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK6", + "description": "USER_BANK6 group" + }, + "registers": [ + { + "id": "fuse432", + "name": "USER_BANK6_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01B0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse433", + "name": "USER_BANK6_1", + "description": "USER_BANK6_1 register", + "index_int": "0x01B1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse434", + "name": "USER_BANK6_2", + "description": "USER_BANK6_2 register", + "index_int": "0x01B2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse435", + "name": "USER_BANK6_3", + "description": "USER_BANK6_3 register", + "index_int": "0x01B3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse436", + "name": "USER_BANK6_4", + "description": "USER_BANK6_4 register", + "index_int": "0x01B4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse437", + "name": "USER_BANK6_5", + "description": "USER_BANK6_5 register", + "index_int": "0x01B5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse438", + "name": "USER_BANK6_6", + "description": "USER_BANK6_6 register", + "index_int": "0x01B6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse439", + "name": "USER_BANK6_7", + "description": "USER_BANK6_7 register", + "index_int": "0x01B7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK7", + "description": "USER_BANK7 group" + }, + "registers": [ + { + "id": "fuse440", + "name": "USER_BANK7_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01B8", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse441", + "name": "USER_BANK7_1", + "description": "USER_BANK7_1 register", + "index_int": "0x01B9", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse442", + "name": "USER_BANK7_2", + "description": "USER_BANK7_2 register", + "index_int": "0x01BA", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse443", + "name": "USER_BANK7_3", + "description": "USER_BANK7_3 register", + "index_int": "0x01BB", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse444", + "name": "USER_BANK7_4", + "description": "USER_BANK7_4 register", + "index_int": "0x01BC", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse445", + "name": "USER_BANK7_5", + "description": "USER_BANK7_5 register", + "index_int": "0x01BD", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse446", + "name": "USER_BANK7_6", + "description": "USER_BANK7_6 register", + "index_int": "0x01BE", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse447", + "name": "USER_BANK7_7", + "description": "USER_BANK7_7 register", + "index_int": "0x01BF", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "USER_BANK8", + "description": "USER_BANK8 group" + }, + "registers": [ + { + "id": "fuse448", + "name": "USER_BANK8_0", + "description": "Customer programmable fuse bank containing 8 independent 32-bit fuse words. Each OTP word in this block are ECC protected. Thus all 32-bits in a word should be programmed at once.", + "index_int": "0x01C0", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse449", + "name": "USER_BANK8_1", + "description": "USER_BANK8_1 register", + "index_int": "0x01C1", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse450", + "name": "USER_BANK8_2", + "description": "USER_BANK8_2 register", + "index_int": "0x01C2", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse451", + "name": "USER_BANK8_3", + "description": "USER_BANK8_3 register", + "index_int": "0x01C3", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse452", + "name": "USER_BANK8_4", + "description": "USER_BANK8_4 register", + "index_int": "0x01C4", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse453", + "name": "USER_BANK8_5", + "description": "USER_BANK8_5 register", + "index_int": "0x01C5", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse454", + "name": "USER_BANK8_6", + "description": "USER_BANK8_6 register", + "index_int": "0x01C6", + "individual_write_lock": "always_lock" + }, + { + "id": "fuse455", + "name": "USER_BANK8_7", + "description": "USER_BANK8_7 register", + "index_int": "0x01C7", + "individual_write_lock": "always_lock" + } + ] + }, + { + "group": { + "name": "CRC_BANK", + "description": "CRC_BANK group" + }, + "registers": [ + { + "id": "fuse492", + "name": "CRC4", + "description": "CRC of BOOT_CFG configuration data. Word 96 to 100 (0x180 - 0x18F).", + "index_int": "0x01EC", + "shadow_reg_offset_int": "0x07B0", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0010", + "read_lock_int": "0x0020" + } + }, + { + "id": "fuse493", + "name": "CRC5", + "description": "CRC of SECURE_CFG configuration data. Word 107 to 127 (0x1A4 - 0x200).", + "index_int": "0x01ED", + "shadow_reg_offset_int": "0x07B4", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0040", + "read_lock_int": "0x0080" + } + }, + { + "id": "fuse494", + "name": "CRC6", + "description": "CRC of customer programmed mode fuse (Word 8 and 9).", + "index_int": "0x01EE", + "shadow_reg_offset_int": "0x07B8", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0100", + "read_lock_int": "0x0200" + } + }, + { + "id": "fuse495", + "name": "CRC7", + "description": "Customer defined.", + "index_int": "0x01EF", + "shadow_reg_offset_int": "0x07BC", + "individual_write_lock": "always_lock", + "lock": { + "register_id": "fuse9", + "write_lock_int": "0x0400", + "read_lock_int": "0x0800" + } + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_a0.json new file mode 100644 index 0000000..35956b6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_a0.json @@ -0,0 +1,2005 @@ +{ + "cpu": "mimxrt685s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Secure vector table address (vtor_addr)", + "description": "TrustZone register - Secure vector table address (vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Non-secure vector table address (vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register(mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register(mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register.(sau_ctrl)", + "description": "TrustZone register - SAU Control Register.(sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "description": "TrustZone register - ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qospi_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qospi0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qospi0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qospi0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qospi0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qospi1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qospi1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qospi1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qospi1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qospi2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qospi2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qospi2_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qospi2_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qospi3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qospi3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qospi3_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qospi3_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "description": "TrustZone register - RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "description": "TrustZone register - RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "description": "TrustZone register - RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "description": "TrustZone register - RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "description": "TrustZone register - RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "description": "TrustZone register - RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "description": "TrustZone register - RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "description": "TrustZone register - RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "description": "TrustZone register - RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "description": "TrustZone register - RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "description": "TrustZone register - RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "description": "TrustZone register - RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "description": "TrustZone register - RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "description": "TrustZone register - RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "description": "TrustZone register - RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "description": "TrustZone register - RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "description": "TrustZone register - RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "description": "TrustZone register - RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "description": "TrustZone register - RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "description": "TrustZone register - RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "description": "TrustZone register - RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "description": "TrustZone register - RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "description": "TrustZone register - RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "description": "TrustZone register - RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "description": "TrustZone register - RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "description": "TrustZone register - RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "description": "TrustZone register - RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "description": "TrustZone register - RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "description": "TrustZone register - RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "description": "TrustZone register - RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "description": "TrustZone register - RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "description": "TrustZone register - RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "description": "TrustZone register - RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "description": "TrustZone register - RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "description": "TrustZone register - RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "description": "TrustZone register - RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "description": "TrustZone register - RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "description": "TrustZone register - RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "description": "TrustZone register - RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "description": "TrustZone register - RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "description": "TrustZone register - RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "description": "TrustZone register - RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "description": "TrustZone register - RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "description": "TrustZone register - RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "description": "TrustZone register - RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "description": "TrustZone register - RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "description": "TrustZone register - RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "description": "TrustZone register - RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "description": "TrustZone register - RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "description": "TrustZone register - RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "description": "TrustZone register - RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "description": "TrustZone register - RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "description": "TrustZone register - RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "description": "TrustZone register - RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "description": "TrustZone register - RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "description": "TrustZone register - RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "description": "TrustZone register - RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "description": "TrustZone register - RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "description": "TrustZone register - RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "description": "TrustZone register - RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "description": "TrustZone register - RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "description": "TrustZone register - RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "description": "TrustZone register - RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "description": "TrustZone register - RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "RAM5 Slave Rule Register (ram5_slave_rule)", + "description": "TrustZone register - RAM5 Slave Rule Register (ram5_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "description": "TrustZone register - RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "description": "TrustZone register - RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "description": "TrustZone register - RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "description": "TrustZone register - RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "description": "TrustZone register - RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "description": "TrustZone register - RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "description": "TrustZone register - RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "description": "TrustZone register - RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "description": "TrustZone register - RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "description": "TrustZone register - RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "description": "TrustZone register - RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "description": "TrustZone register - RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "description": "TrustZone register - RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "description": "TrustZone register - RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "description": "TrustZone register - RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "description": "TrustZone register - RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "RAM6 Slave Rule Register (ram6_slave_rule)", + "description": "TrustZone register - RAM6 Slave Rule Register (ram6_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "description": "TrustZone register - RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "description": "TrustZone register - RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "description": "TrustZone register - RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "description": "TrustZone register - RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "description": "TrustZone register - RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "description": "TrustZone register - RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "description": "TrustZone register - RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "description": "TrustZone register - RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "description": "TrustZone register - RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "description": "TrustZone register - RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "description": "TrustZone register - RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "description": "TrustZone register - RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "description": "TrustZone register - RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "description": "TrustZone register - RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "description": "TrustZone register - RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "description": "TrustZone register - RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "RAM7 Slave Rule Register (ram7_slave_rule)", + "description": "TrustZone register - RAM7 Slave Rule Register (ram7_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "description": "TrustZone register - RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "description": "TrustZone register - RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "description": "TrustZone register - RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "description": "TrustZone register - RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "description": "TrustZone register - RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "description": "TrustZone register - RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "description": "TrustZone register - RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "description": "TrustZone register - RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "description": "TrustZone register - RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "description": "TrustZone register - RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "description": "TrustZone register - RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "description": "TrustZone register - RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "description": "TrustZone register - RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "description": "TrustZone register - RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "description": "TrustZone register - RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "description": "TrustZone register - RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "RAM8 Slave Rule Register (ram8_slave_rule)", + "description": "TrustZone register - RAM8 Slave Rule Register (ram8_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "description": "TrustZone register - RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "description": "TrustZone register - RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "description": "TrustZone register - RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "description": "TrustZone register - RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "HiFi4 DSP Slave Rule Register (pif_hifi4_x_slave_rule0)", + "description": "TrustZone register - HiFi4 DSP Slave Rule Register (pif_hifi4_x_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 0 (pif_hifi4_x_mem_rule0)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 0 (pif_hifi4_x_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 1 (pif_hifi4_x_mem_rule1)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 1 (pif_hifi4_x_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 2 (pif_hifi4_x_mem_rule2)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 2 (pif_hifi4_x_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 3 (pif_hifi4_x_mem_rule3)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 3 (pif_hifi4_x_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 0 (ahb_periph0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register 1 (ahb_periph0_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 0 (aips_bridge0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register 1 (aips_bridge0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "AIPS bridge 1 Slave Rule Register (aips_bridge1_slave_rule0)", + "description": "TrustZone register - AIPS bridge 1 Slave Rule Register (aips_bridge1_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register 0 (ahb_periph2_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register 0 (ahb_periph3_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "Secure GPIO Register 1 (sec_gp_reg1)", + "description": "TrustZone register - Secure GPIO Register 1 (sec_gp_reg1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "Secure GPIO Register 2 (sec_gp_reg2)", + "description": "TrustZone register - Secure GPIO Register 2 (sec_gp_reg2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "Secure GPIO Register 3 (sec_gp_reg3)", + "description": "TrustZone register - Secure GPIO Register 3 (sec_gp_reg3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "Secure GPIO Register 4 (sec_gp_reg4)", + "description": "TrustZone register - Secure GPIO Register 4 (sec_gp_reg4)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "Secure GPIO Register 5 (sec_gp_reg5)", + "description": "TrustZone register - Secure GPIO Register 5 (sec_gp_reg5)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "Secure GPIO Register 6 (sec_gp_reg6)", + "description": "TrustZone register - Secure GPIO Register 6 (sec_gp_reg6)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "Secure GPIO Register 7 (sec_gp_reg7)", + "description": "TrustZone register - Secure GPIO Register 7 (sec_gp_reg7)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "Secure GPIO Register 8 for DSP(sec_gp_reg8)", + "description": "TrustZone register - Secure GPIO Register 8 for DSP(sec_gp_reg8)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0xaaaa" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "M33 Lock Control Register (m33_lock_reg)", + "description": "TrustZone register - M33 Lock Control Register (m33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_b0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_b0.json new file mode 100644 index 0000000..ae9499c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt685s/tz_b0.json @@ -0,0 +1,2117 @@ +{ + "cpu": "mimxrt685s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Secure vector table address (vtor_addr)", + "description": "TrustZone register - Secure vector table address (vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "Non-secure vector table address (vtor_ns_addr)", + "description": "TrustZone register - Non-secure vector table address (vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "Interrupt target non-secure register 0 (nvic_itns0)", + "description": "TrustZone register - Interrupt target non-secure register 0 (nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "Interrupt target non-secure register 1 (nvic_itns1)", + "description": "TrustZone register - Interrupt target non-secure register 1 (nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register. (mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register. (mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (sau_ctrl)", + "description": "TrustZone register - SAU Control Register (sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "description": "TrustZone register - ROM Slave Rule Register 0 (bootrom0_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (bootrom0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (bootrom0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (bootrom0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (bootrom0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "Quad/Octal SPI Slave Rule Register 0 (qspi_slave_rule0)", + "description": "TrustZone register - Quad/Octal SPI Slave Rule Register 0 (qspi_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 0 (qspi0_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 0 (qspi0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 1 (qspi0_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 1 (qspi0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 2 (qspi0_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 2 (qspi0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "Quad/Octal SPI 0 Memory Rule Register 3 (qspi0_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 0 Memory Rule Register 3 (qspi0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 0 (qspi1_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 0 (qspi1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 1 (qspi1_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 1 (qspi1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 2 (qspi1_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 2 (qspi1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "Quad/Octal SPI 1 Memory Rule Register 3 (qspi1_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 1 Memory Rule Register 3 (qspi1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 0 (qspi2_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 0 (qspi2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 1 (qspi2_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 1 (qspi2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 2 (qspi2_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 2 (qspi2_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "Quad/Octal SPI 2 Memory Rule Register 3 (qspi2_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 2 Memory Rule Register 3 (qspi2_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 0 (qspi3_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 0 (qspi3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 1 (qspi3_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 1 (qspi3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 2 (qspi3_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 2 (qspi3_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "Quad/Octal SPI 3 Memory Rule Register 3 (qspi3_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 3 Memory Rule Register 3 (qspi3_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 0 (qspi4_mem_rule0)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 0 (qspi4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 1 (qspi4_mem_rule1)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 1 (qspi4_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 2 (qspi4_mem_rule2)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 2 (qspi4_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "Quad/Octal SPI 4 Memory Rule Register 3 (qspi4_mem_rule3)", + "description": "TrustZone register - Quad/Octal SPI 4 Memory Rule Register 3 (qspi4_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "description": "TrustZone register - RAM00 Memory Rule Register 0 (ram00_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "description": "TrustZone register - RAM00 Memory Rule Register 1 (ram00_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "description": "TrustZone register - RAM00 Memory Rule Register 2 (ram00_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "description": "TrustZone register - RAM00 Memory Rule Register 3 (ram00_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "description": "TrustZone register - RAM01 Memory Rule Register 0 (ram01_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "description": "TrustZone register - RAM01 Memory Rule Register 1 (ram01_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "description": "TrustZone register - RAM01 Memory Rule Register 2 (ram01_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "description": "TrustZone register - RAM01 Memory Rule Register 3 (ram01_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "description": "TrustZone register - RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "description": "TrustZone register - RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "description": "TrustZone register - RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "description": "TrustZone register - RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "description": "TrustZone register - RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "description": "TrustZone register - RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "description": "TrustZone register - RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "description": "TrustZone register - RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "description": "TrustZone register - RAM20 Memory Rule Register 0 (ram20_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "description": "TrustZone register - RAM20 Memory Rule Register 1 (ram20_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "description": "TrustZone register - RAM20 Memory Rule Register 2 (ram20_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "description": "TrustZone register - RAM20 Memory Rule Register 3 (ram20_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "description": "TrustZone register - RAM21 Memory Rule Register 0 (ram21_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "description": "TrustZone register - RAM21 Memory Rule Register 1 (ram21_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "description": "TrustZone register - RAM21 Memory Rule Register 2 (ram21_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "description": "TrustZone register - RAM21 Memory Rule Register 3 (ram21_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "description": "TrustZone register - RAM22 Memory Rule Register 0 (ram22_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "description": "TrustZone register - RAM22 Memory Rule Register 1 (ram22_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "description": "TrustZone register - RAM22 Memory Rule Register 2 (ram22_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "description": "TrustZone register - RAM22 Memory Rule Register 3 (ram22_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "description": "TrustZone register - RAM23 Memory Rule Register 0 (ram23_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "description": "TrustZone register - RAM23 Memory Rule Register 1 (ram23_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "description": "TrustZone register - RAM23 Memory Rule Register 2 (ram23_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "description": "TrustZone register - RAM23 Memory Rule Register 3 (ram23_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "RAM3 Slave Rule Register (ram3_slave_rule)", + "description": "TrustZone register - RAM3 Slave Rule Register (ram3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "description": "TrustZone register - RAM30 Memory Rule Register 0 (ram30_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "description": "TrustZone register - RAM30 Memory Rule Register 1 (ram30_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "description": "TrustZone register - RAM30 Memory Rule Register 2 (ram30_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "description": "TrustZone register - RAM30 Memory Rule Register 3 (ram30_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "description": "TrustZone register - RAM31 Memory Rule Register 0 (ram31_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "description": "TrustZone register - RAM31 Memory Rule Register 1 (ram31_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "description": "TrustZone register - RAM31 Memory Rule Register 2 (ram31_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "description": "TrustZone register - RAM31 Memory Rule Register 3 (ram31_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "description": "TrustZone register - RAM32 Memory Rule Register 0 (ram32_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "description": "TrustZone register - RAM32 Memory Rule Register 1 (ram32_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "description": "TrustZone register - RAM32 Memory Rule Register 2 (ram32_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "description": "TrustZone register - RAM32 Memory Rule Register 3 (ram32_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "description": "TrustZone register - RAM33 Memory Rule Register 0 (ram33_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "description": "TrustZone register - RAM33 Memory Rule Register 1 (ram33_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "description": "TrustZone register - RAM33 Memory Rule Register 2 (ram33_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "description": "TrustZone register - RAM33 Memory Rule Register 3 (ram33_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "RAM4 Slave Rule Register (ram4_slave_rule)", + "description": "TrustZone register - RAM4 Slave Rule Register (ram4_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "description": "TrustZone register - RAM40 Memory Rule Register 0 (ram40_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "description": "TrustZone register - RAM40 Memory Rule Register 1 (ram40_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "description": "TrustZone register - RAM40 Memory Rule Register 2 (ram40_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "description": "TrustZone register - RAM40 Memory Rule Register 3 (ram40_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "description": "TrustZone register - RAM41 Memory Rule Register 0 (ram41_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "description": "TrustZone register - RAM41 Memory Rule Register 1 (ram41_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "description": "TrustZone register - RAM41 Memory Rule Register 2 (ram41_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "description": "TrustZone register - RAM41 Memory Rule Register 3 (ram41_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "description": "TrustZone register - RAM42 Memory Rule Register 0 (ram42_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "description": "TrustZone register - RAM42 Memory Rule Register 1 (ram42_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "description": "TrustZone register - RAM42 Memory Rule Register 2 (ram42_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "description": "TrustZone register - RAM42 Memory Rule Register 3 (ram42_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "description": "TrustZone register - RAM43 Memory Rule Register 0 (ram43_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "description": "TrustZone register - RAM43 Memory Rule Register 1 (ram43_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "description": "TrustZone register - RAM43 Memory Rule Register 2 (ram43_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "description": "TrustZone register - RAM43 Memory Rule Register 3 (ram43_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "RAM5 Slave Rule Register (ram5_slave_rule)", + "description": "TrustZone register - RAM5 Slave Rule Register (ram5_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "description": "TrustZone register - RAM50 Memory Rule Register 0 (ram50_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "description": "TrustZone register - RAM50 Memory Rule Register 1 (ram50_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "description": "TrustZone register - RAM50 Memory Rule Register 2 (ram50_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "description": "TrustZone register - RAM50 Memory Rule Register 3 (ram50_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "description": "TrustZone register - RAM51 Memory Rule Register 0 (ram51_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "description": "TrustZone register - RAM51 Memory Rule Register 1 (ram51_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "description": "TrustZone register - RAM51 Memory Rule Register 2 (ram51_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "description": "TrustZone register - RAM51 Memory Rule Register 3 (ram51_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "description": "TrustZone register - RAM52 Memory Rule Register 0 (ram52_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "description": "TrustZone register - RAM52 Memory Rule Register 1 (ram52_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "description": "TrustZone register - RAM52 Memory Rule Register 2 (ram52_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "description": "TrustZone register - RAM52 Memory Rule Register 3 (ram52_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "description": "TrustZone register - RAM53 Memory Rule Register 0 (ram53_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "description": "TrustZone register - RAM53 Memory Rule Register 1 (ram53_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "description": "TrustZone register - RAM53 Memory Rule Register 2 (ram53_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "description": "TrustZone register - RAM53 Memory Rule Register 3 (ram53_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "RAM6 Slave Rule Register (ram6_slave_rule)", + "description": "TrustZone register - RAM6 Slave Rule Register (ram6_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "description": "TrustZone register - RAM60 Memory Rule Register 0 (ram60_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "description": "TrustZone register - RAM60 Memory Rule Register 1 (ram60_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "description": "TrustZone register - RAM60 Memory Rule Register 2 (ram60_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "description": "TrustZone register - RAM60 Memory Rule Register 3 (ram60_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "description": "TrustZone register - RAM61 Memory Rule Register 0 (ram61_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "description": "TrustZone register - RAM61 Memory Rule Register 1 (ram61_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "description": "TrustZone register - RAM61 Memory Rule Register 2 (ram61_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "description": "TrustZone register - RAM61 Memory Rule Register 3 (ram61_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "description": "TrustZone register - RAM62 Memory Rule Register 0 (ram62_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "description": "TrustZone register - RAM62 Memory Rule Register 1 (ram62_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "description": "TrustZone register - RAM62 Memory Rule Register 2 (ram62_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "description": "TrustZone register - RAM62 Memory Rule Register 3 (ram62_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "description": "TrustZone register - RAM63 Memory Rule Register 0 (ram63_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "description": "TrustZone register - RAM63 Memory Rule Register 1 (ram63_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "description": "TrustZone register - RAM63 Memory Rule Register 2 (ram63_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "description": "TrustZone register - RAM63 Memory Rule Register 3 (ram63_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "RAM7 Slave Rule Register (ram7_slave_rule)", + "description": "TrustZone register - RAM7 Slave Rule Register (ram7_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "description": "TrustZone register - RAM70 Memory Rule Register 0 (ram70_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "description": "TrustZone register - RAM70 Memory Rule Register 1 (ram70_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "description": "TrustZone register - RAM70 Memory Rule Register 2 (ram70_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "description": "TrustZone register - RAM70 Memory Rule Register 3 (ram70_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "description": "TrustZone register - RAM71 Memory Rule Register 0 (ram71_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "description": "TrustZone register - RAM71 Memory Rule Register 1 (ram71_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "description": "TrustZone register - RAM71 Memory Rule Register 2 (ram71_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "description": "TrustZone register - RAM71 Memory Rule Register 3 (ram71_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "description": "TrustZone register - RAM72 Memory Rule Register 0 (ram72_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "description": "TrustZone register - RAM72 Memory Rule Register 1 (ram72_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "description": "TrustZone register - RAM72 Memory Rule Register 2 (ram72_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "description": "TrustZone register - RAM72 Memory Rule Register 3 (ram72_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "description": "TrustZone register - RAM73 Memory Rule Register 0 (ram73_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "description": "TrustZone register - RAM73 Memory Rule Register 1 (ram73_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "description": "TrustZone register - RAM73 Memory Rule Register 2 (ram73_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "description": "TrustZone register - RAM73 Memory Rule Register 3 (ram73_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "RAM8 Slave Rule Register (ram8_slave_rule)", + "description": "TrustZone register - RAM8 Slave Rule Register (ram8_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "description": "TrustZone register - RAM80 Memory Rule Register 0 (ram80_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "description": "TrustZone register - RAM80 Memory Rule Register 1 (ram80_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "description": "TrustZone register - RAM80 Memory Rule Register 2 (ram80_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "description": "TrustZone register - RAM80 Memory Rule Register 3 (ram80_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "description": "TrustZone register - RAM81 Memory Rule Register 0 (ram81_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "description": "TrustZone register - RAM81 Memory Rule Register 1 (ram81_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "description": "TrustZone register - RAM81 Memory Rule Register 2 (ram81_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "description": "TrustZone register - RAM81 Memory Rule Register 3 (ram81_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "RAM82 Memory Rule Register 0 (ram82_mem_rule0)", + "description": "TrustZone register - RAM82 Memory Rule Register 0 (ram82_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "RAM82 Memory Rule Register 1 (ram82_mem_rule1)", + "description": "TrustZone register - RAM82 Memory Rule Register 1 (ram82_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "RAM82 Memory Rule Register 2 (ram82_mem_rule2)", + "description": "TrustZone register - RAM82 Memory Rule Register 2 (ram82_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "RAM82 Memory Rule Register 3 (ram82_mem_rule3)", + "description": "TrustZone register - RAM82 Memory Rule Register 3 (ram82_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "RAM83 Memory Rule Register 0 (ram83_mem_rule0)", + "description": "TrustZone register - RAM83 Memory Rule Register 0 (ram83_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "RAM83 Memory Rule Register 1 (ram83_mem_rule1)", + "description": "TrustZone register - RAM83 Memory Rule Register 1 (ram83_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "RAM83 Memory Rule Register 2 (ram83_mem_rule2)", + "description": "TrustZone register - RAM83 Memory Rule Register 2 (ram83_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "RAM83 Memory Rule Register 3 (ram83_mem_rule3)", + "description": "TrustZone register - RAM83 Memory Rule Register 3 (ram83_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "HiFi4 DSP Slave Rule Register (pif_hifi4_x_slave_rule0)", + "description": "TrustZone register - HiFi4 DSP Slave Rule Register (pif_hifi4_x_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 0 (pif_hifi4_x_mem_rule0)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 0 (pif_hifi4_x_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 1 (pif_hifi4_x_mem_rule1)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 1 (pif_hifi4_x_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 2 (pif_hifi4_x_mem_rule2)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 2 (pif_hifi4_x_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "HiFi4 DSP Memory Rule Register 3 (pif_hifi4_x_mem_rule3)", + "description": "TrustZone register - HiFi4 DSP Memory Rule Register 3 (pif_hifi4_x_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "description": "TrustZone register - APB Bridge Slave Rule Register (apb_bridge_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register (ahb_periph0_slave_rule)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register (ahb_periph0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "AIPS bridge 0 Memory Rule Register (aips_bridge0_slave_rule)", + "description": "TrustZone register - AIPS bridge 0 Memory Rule Register (aips_bridge0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "AIPS bridge 1 Slave Rule Register (aips_bridge1_slave_rule)", + "description": "TrustZone register - AIPS bridge 1 Slave Rule Register (aips_bridge1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 0 (aips_bridge1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 1 (aips_bridge1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 2 (aips_bridge1_mem_rule2)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 2 (aips_bridge1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 3 (aips_bridge1_mem_rule3)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 3 (aips_bridge1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register (ahb_periph2_slave_rule)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register (ahb_periph2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "AHB Peripherals 2 Security Memory Rule Register (ahb_periph2_security_mem_rule)", + "description": "TrustZone register - AHB Peripherals 2 Security Memory Rule Register (ahb_periph2_security_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register (ahb_periph3_slave_rule)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register (ahb_periph3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "description": "TrustZone register - Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "description": "TrustZone register - Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "Secure GPIO Mask Register 2 (sec_gpio_mask2)", + "description": "TrustZone register - Secure GPIO Mask Register 2 (sec_gpio_mask2)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "Secure GPIO Mask Register 3 (sec_gpio_mask3)", + "description": "TrustZone register - Secure GPIO Mask Register 3 (sec_gpio_mask3)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "Secure GPIO Mask Register 4 (sec_gpio_mask4)", + "description": "TrustZone register - Secure GPIO Mask Register 4 (sec_gpio_mask4)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "Secure GPIO Mask Register 5 (sec_gpio_mask5)", + "description": "TrustZone register - Secure GPIO Mask Register 5 (sec_gpio_mask5)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "Secure GPIO Mask Register 6 (sec_gpio_mask6)", + "description": "TrustZone register - Secure GPIO Mask Register 6 (sec_gpio_mask6)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "Secure GPIO Mask Register 7 (sec_gpio_mask7)", + "description": "TrustZone register - Secure GPIO Mask Register 7 (sec_gpio_mask7)", + "default_value_int": "0xffffffff" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "Secure DSP Interrupt Mask Register (sec_hifi4_int_mask)", + "description": "TrustZone register - Secure DSP Interrupt Mask Register (sec_hifi4_int_mask)", + "default_value_int": "0xffffffff" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "Secure GPIO Mask Lock Register (sec_gpio_mask_lock)", + "description": "TrustZone register - Secure GPIO Mask Lock Register (sec_gpio_mask_lock)", + "default_value_int": "0xaaaa" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "M33 Lock Control Register (m33_lock_reg)", + "description": "TrustZone register - M33 Lock Control Register (m33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt735s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt735s/database.yaml new file mode 100644 index 0000000..3e9aa50 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt735s/database.yaml @@ -0,0 +1,22 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt798s + +info: + memory_map: + # Memory map basic info + xspi1: + start_int: 0x08000000 + size_int: 0x08000000 + external: true + xspi0: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + sram: + start_int: 0x2000_0000 + size_int: 0x0050_0000 + external: false + non_xip_type: int_ram diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt758s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt758s/database.yaml new file mode 100644 index 0000000..99201eb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt758s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mimxrt798s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/database.yaml new file mode 100644 index 0000000..61bba9a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/database.yaml @@ -0,0 +1,496 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: + features: + fuses: + reg_spec: fuses_a0.json + + a1: + features: + mbi: + mbi_classes: + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestDigest + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + fuses: + reg_spec: fuses_a0.json + b0: + features: + mbi: + images: + xip: + plain: plain_xip + crc: crc_ram + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + signed: signed_ram + fcb: + mem_types: + xspi_nor: + reg_spec: fcb_xspi_nor_b0.json + # To be removed with next major release + deprecated_reg_names: + lookupTable_seq0_instr0: [lookupTable_0] + lookupTable_seq0_instr1: [lookupTable_1] + lookupTable_seq0_instr2: [lookupTable_2] + lookupTable_seq0_instr3: [lookupTable_3] + lookupTable_seq0_instr4: [lookupTable_4] + lookupTable_seq1_instr0: [lookupTable_5] + lookupTable_seq1_instr1: [lookupTable_6] + lookupTable_seq1_instr2: [lookupTable_7] + lookupTable_seq1_instr3: [lookupTable_8] + lookupTable_seq1_instr4: [lookupTable_9] + lookupTable_seq2_instr0: [lookupTable_10] + lookupTable_seq2_instr1: [lookupTable_11] + lookupTable_seq2_instr2: [lookupTable_12] + lookupTable_seq2_instr3: [lookupTable_13] + lookupTable_seq2_instr4: [lookupTable_14] + lookupTable_seq3_instr0: [lookupTable_15] + lookupTable_seq3_instr1: [lookupTable_16] + lookupTable_seq3_instr2: [lookupTable_17] + lookupTable_seq3_instr3: [lookupTable_18] + lookupTable_seq3_instr4: [lookupTable_19] + lookupTable_seq4_instr0: [lookupTable_20] + lookupTable_seq4_instr1: [lookupTable_21] + lookupTable_seq4_instr2: [lookupTable_22] + lookupTable_seq4_instr3: [lookupTable_23] + lookupTable_seq4_instr4: [lookupTable_24] + lookupTable_seq5_instr0: [lookupTable_25] + lookupTable_seq5_instr1: [lookupTable_26] + lookupTable_seq5_instr2: [lookupTable_27] + lookupTable_seq5_instr3: [lookupTable_28] + lookupTable_seq5_instr4: [lookupTable_29] + lookupTable_seq6_instr0: [lookupTable_30] + lookupTable_seq6_instr1: [lookupTable_31] + lookupTable_seq6_instr2: [lookupTable_32] + lookupTable_seq6_instr3: [lookupTable_33] + lookupTable_seq6_instr4: [lookupTable_34] + lookupTable_seq7_instr0: [lookupTable_35] + lookupTable_seq7_instr1: [lookupTable_36] + lookupTable_seq7_instr2: [lookupTable_37] + lookupTable_seq7_instr3: [lookupTable_38] + lookupTable_seq7_instr4: [lookupTable_39] + lookupTable_seq8_instr0: [lookupTable_40] + lookupTable_seq8_instr1: [lookupTable_41] + lookupTable_seq8_instr2: [lookupTable_42] + lookupTable_seq8_instr3: [lookupTable_43] + lookupTable_seq8_instr4: [lookupTable_44] + lookupTable_seq9_instr0: [lookupTable_45] + lookupTable_seq9_instr1: [lookupTable_46] + lookupTable_seq9_instr2: [lookupTable_47] + lookupTable_seq9_instr3: [lookupTable_48] + lookupTable_seq9_instr4: [lookupTable_49] + lookupTable_seq10_instr0: [lookupTable_50] + lookupTable_seq10_instr1: [lookupTable_51] + lookupTable_seq10_instr2: [lookupTable_52] + lookupTable_seq10_instr3: [lookupTable_53] + lookupTable_seq10_instr4: [lookupTable_54] + lookupTable_seq11_instr0: [lookupTable_55] + lookupTable_seq11_instr1: [lookupTable_56] + lookupTable_seq11_instr2: [lookupTable_57] + lookupTable_seq11_instr3: [lookupTable_58] + lookupTable_seq11_instr4: [lookupTable_59] + lookupTable_seq12_instr0: [lookupTable_60] + lookupTable_seq12_instr1: [lookupTable_61] + lookupTable_seq12_instr2: [lookupTable_62] + lookupTable_seq12_instr3: [lookupTable_63] + lookupTable_seq12_instr4: [lookupTable_64] + lookupTable_seq13_instr0: [lookupTable_65] + lookupTable_seq13_instr1: [lookupTable_66] + lookupTable_seq13_instr2: [lookupTable_67] + lookupTable_seq13_instr3: [lookupTable_68] + lookupTable_seq13_instr4: [lookupTable_69] + lookupTable_seq14_instr0: [lookupTable_70] + lookupTable_seq14_instr1: [lookupTable_71] + lookupTable_seq14_instr2: [lookupTable_72] + lookupTable_seq14_instr3: [lookupTable_73] + lookupTable_seq14_instr4: [lookupTable_74] + lookupTable_seq15_instr0: [lookupTable_75] + lookupTable_seq15_instr1: [lookupTable_76] + lookupTable_seq15_instr2: [lookupTable_77] + lookupTable_seq15_instr3: [lookupTable_78] + lookupTable_seq15_instr4: [lookupTable_79] + lookupTable_seq16_instr0: [lookupTable_80] + lookupTable_seq16_instr1: [lookupTable_81] + lookupTable_seq16_instr2: [lookupTable_82] + lookupTable_seq16_instr3: [lookupTable_83] + lookupTable_seq16_instr4: [lookupTable_84] + lookupTable_seq17_instr0: [lookupTable_85] + lookupTable_seq17_instr1: [lookupTable_86] + lookupTable_seq17_instr2: [lookupTable_87] + lookupTable_seq17_instr3: [lookupTable_88] + lookupTable_seq17_instr4: [lookupTable_89] + fuses: + reg_spec: fuses_b0.json +latest: b0 + +# General MCU information +info: + purpose: i.MX RT Crossover MCUs + spsdk_predecessor_name: rt7xx + # Web page of MCU representative + web: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt700-crossover-mcu-with-arm-cortex-m33-npu-dsp-and-gpu-cores:i.MX-RT700 + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0026 + memory_map: + # Memory map basic info + xspi1: + start_int: 0x08000000 + size_int: 0x08000000 + external: true + xspi0: + start_int: 0x28000000 + size_int: 0x08000000 + external: true + sram: + start_int: 0x2000_0000 + size_int: 0x0078_0000 + external: false + non_xip_type: int_ram + +features: + # ======== Blhost section ======== + blhost: + sub_features: [overridden_properties] + overridden_properties: + 17: "life-cycle" + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x20070000 + size: 0x1000 + + # ======== Fuses description section ======== + fuses: + grouped_registers: + - uid: rkth + name: RKTH + width: 384 + config_as_hexstring: true + reversed: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key + table hash. For ECC P-256 keys RKTH is a 32-byte SHA-256 digest of four + SHA-256 digests computed over four OEM public keys (OEM has four + private-public key pairs in case one of its private keys becomes + compromised) or in case that ECC P-384 keys are used, RKTH is 48-byte + SHA-384 digest. + sub_regs: + - fuse88 + - fuse89 + - fuse90 + - fuse91 + - fuse92 + - fuse93 + - fuse94 + - fuse95 + - fuse96 + - fuse97 + - fuse98 + - fuse99 + - uid: cust_mk_sk + name: CUST_MK_SK + width: 384 + config_as_hexstring: true + #reversed: true + alternative_widths: [256] + description: CUST_MK_SK + sub_regs: + - fuse100 + - fuse101 + - fuse102 + - fuse103 + - fuse104 + - fuse105 + - fuse106 + - fuse107 + - fuse108 + - fuse109 + - fuse110 + - fuse111 + + # ======== DAT section ======== + dat: + socc: 0x8 # SOCC identification + dmbox_ap_ix: 2 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: "cert_block_21" + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinRelocTable + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestCrc + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifestCrc + - Mbi_MixinImageSubType + - Mbi_MixinImageVersion + - Mbi_MixinFwVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + signed: signed_ram + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - copy + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + key_wraps_version: 2 + + # ======== FCB section ======== + fcb: + mem_types: + xspi_nor: + reg_spec: fcb_xspi_nor_a0.json + # To be removed with next major release + deprecated_reg_names: + lookupTable_seq0_instr0: [lookupTable_0] + lookupTable_seq0_instr1: [lookupTable_1] + lookupTable_seq0_instr2: [lookupTable_2] + lookupTable_seq0_instr3: [lookupTable_3] + lookupTable_seq0_instr4: [lookupTable_4] + lookupTable_seq1_instr0: [lookupTable_5] + lookupTable_seq1_instr1: [lookupTable_6] + lookupTable_seq1_instr2: [lookupTable_7] + lookupTable_seq1_instr3: [lookupTable_8] + lookupTable_seq1_instr4: [lookupTable_9] + lookupTable_seq2_instr0: [lookupTable_10] + lookupTable_seq2_instr1: [lookupTable_11] + lookupTable_seq2_instr2: [lookupTable_12] + lookupTable_seq2_instr3: [lookupTable_13] + lookupTable_seq2_instr4: [lookupTable_14] + lookupTable_seq3_instr0: [lookupTable_15] + lookupTable_seq3_instr1: [lookupTable_16] + lookupTable_seq3_instr2: [lookupTable_17] + lookupTable_seq3_instr3: [lookupTable_18] + lookupTable_seq3_instr4: [lookupTable_19] + lookupTable_seq4_instr0: [lookupTable_20] + lookupTable_seq4_instr1: [lookupTable_21] + lookupTable_seq4_instr2: [lookupTable_22] + lookupTable_seq4_instr3: [lookupTable_23] + lookupTable_seq4_instr4: [lookupTable_24] + lookupTable_seq5_instr0: [lookupTable_25] + lookupTable_seq5_instr1: [lookupTable_26] + lookupTable_seq5_instr2: [lookupTable_27] + lookupTable_seq5_instr3: [lookupTable_28] + lookupTable_seq5_instr4: [lookupTable_29] + lookupTable_seq6_instr0: [lookupTable_30] + lookupTable_seq6_instr1: [lookupTable_31] + lookupTable_seq6_instr2: [lookupTable_32] + lookupTable_seq6_instr3: [lookupTable_33] + lookupTable_seq6_instr4: [lookupTable_34] + lookupTable_seq7_instr0: [lookupTable_35] + lookupTable_seq7_instr1: [lookupTable_36] + lookupTable_seq7_instr2: [lookupTable_37] + lookupTable_seq7_instr3: [lookupTable_38] + lookupTable_seq7_instr4: [lookupTable_39] + lookupTable_seq8_instr0: [lookupTable_40] + lookupTable_seq8_instr1: [lookupTable_41] + lookupTable_seq8_instr2: [lookupTable_42] + lookupTable_seq8_instr3: [lookupTable_43] + lookupTable_seq8_instr4: [lookupTable_44] + lookupTable_seq9_instr0: [lookupTable_45] + lookupTable_seq9_instr1: [lookupTable_46] + lookupTable_seq9_instr2: [lookupTable_47] + lookupTable_seq9_instr3: [lookupTable_48] + lookupTable_seq9_instr4: [lookupTable_49] + lookupTable_seq10_instr0: [lookupTable_50] + lookupTable_seq10_instr1: [lookupTable_51] + lookupTable_seq10_instr2: [lookupTable_52] + lookupTable_seq10_instr3: [lookupTable_53] + lookupTable_seq10_instr4: [lookupTable_54] + lookupTable_seq11_instr0: [lookupTable_55] + lookupTable_seq11_instr1: [lookupTable_56] + lookupTable_seq11_instr2: [lookupTable_57] + lookupTable_seq11_instr3: [lookupTable_58] + lookupTable_seq11_instr4: [lookupTable_59] + lookupTable_seq12_instr0: [lookupTable_60] + lookupTable_seq12_instr1: [lookupTable_61] + lookupTable_seq12_instr2: [lookupTable_62] + lookupTable_seq12_instr3: [lookupTable_63] + lookupTable_seq12_instr4: [lookupTable_64] + lookupTable_seq13_instr0: [lookupTable_65] + lookupTable_seq13_instr1: [lookupTable_66] + lookupTable_seq13_instr2: [lookupTable_67] + lookupTable_seq13_instr3: [lookupTable_68] + lookupTable_seq13_instr4: [lookupTable_69] + lookupTable_seq14_instr0: [lookupTable_70] + lookupTable_seq14_instr1: [lookupTable_71] + lookupTable_seq14_instr2: [lookupTable_72] + lookupTable_seq14_instr3: [lookupTable_73] + lookupTable_seq14_instr4: [lookupTable_74] + lookupTable_seq15_instr0: [lookupTable_75] + lookupTable_seq15_instr1: [lookupTable_76] + lookupTable_seq15_instr2: [lookupTable_77] + lookupTable_seq15_instr3: [lookupTable_78] + lookupTable_seq15_instr4: [lookupTable_79] + + # ======== XMCD section ======== + xmcd: + header: + reg_spec: ../../common/xmcd/xspi_ram_header.json + mem_types: + xspi_ram: + simplified: + reg_spec: ../../common/xmcd/xspi_ram_simplified.json + # ======== Bootable image section ======== + bootable_image: + mem_types: + xspi_nor: + segments: + fcb: 0x0000 + xmcd: 0x0300 + mbi: 0x4000 + remap_align: 0x40000 # 256 KB + sd: + segments: + mbi: 0x1000 + emmc: + segments: + mbi: 0x1000 + + # ======== Shadow registers section ======== + shadow_regs: {} + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB31] + key_blob_offset: 0 + key_blob_command_position: -1 + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - copy + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + + # ======== Trust Zone section ======== + tz: + data_file: tz.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + xspi_nor: + instances: [0, 1] + sd: + instances: [0, 1] + interfaces: [instance_0, instance_1] + emmc: + instances: [0, 1] + interfaces: [instance_0, instance_1] + spi_nor: + reg_spec: ../../common/memcfg/opt_word_spi_nor_legacy.json + instances: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_a0.json new file mode 100644 index 0000000..b61f164 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_a0.json @@ -0,0 +1,2101 @@ +{ + "cpu": "MIMXRT798s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x0" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0: internal sampling 2: DQS pad loopback 3: External DQS signal ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, others to 0. ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type. 0: No mode change 1: Quad enable (switch from SPI to Quad mode) 2: Spi2Xpi (switch from SPI to DPI, QPI, or OPI mode) 3: Xpi2Spi (switch from DPI, QPI, or OPI to SPI mode) ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for Device mode configuration command, unit: 100us ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info [ 7:0] - Number of required sequences [15:8] - Sequence index ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": "Controller Miscellaneous Configuration Options", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: 1 for Serial NOR flash memory ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency 1: 30 MHz 2: 50 MHz 3: 60 MHz 4: 80 MHz 5: 100 MHz 6: 120 MHz 7: 133 MHz 8: 166 MHz 9: 200 MHz ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "lookupTable_seq0_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "lookupTable_seq0_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "lookupTable_seq0_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "lookupTable_seq0_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "lookupTable_seq0_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "lookupTable_seq1_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "lookupTable_seq1_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "lookupTable_seq1_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "lookupTable_seq1_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "lookupTable_seq1_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "lookupTable_seq2_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "lookupTable_seq2_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "lookupTable_seq2_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "lookupTable_seq2_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "lookupTable_seq2_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "lookupTable_seq3_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "lookupTable_seq3_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "lookupTable_seq3_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "lookupTable_seq3_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "lookupTable_seq3_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "lookupTable_seq4_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "lookupTable_seq4_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "lookupTable_seq4_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "lookupTable_seq4_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "lookupTable_seq4_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "lookupTable_seq5_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "lookupTable_seq5_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "lookupTable_seq5_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "lookupTable_seq5_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "lookupTable_seq5_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "lookupTable_seq6_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "lookupTable_seq6_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "lookupTable_seq6_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "lookupTable_seq6_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "lookupTable_seq6_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "lookupTable_seq7_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "lookupTable_seq7_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "lookupTable_seq7_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "lookupTable_seq7_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "lookupTable_seq7_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "lookupTable_seq8_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "lookupTable_seq8_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "lookupTable_seq8_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "lookupTable_seq8_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "lookupTable_seq8_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "lookupTable_seq9_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "lookupTable_seq9_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "lookupTable_seq9_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "lookupTable_seq9_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "lookupTable_seq9_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "lookupTable_seq10_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "lookupTable_seq10_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "lookupTable_seq10_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "lookupTable_seq10_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "lookupTable_seq10_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "lookupTable_seq11_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "lookupTable_seq11_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "lookupTable_seq11_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "lookupTable_seq11_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "lookupTable_seq11_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "lookupTable_seq12_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "lookupTable_seq12_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "lookupTable_seq12_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "lookupTable_seq12_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lookupTable_seq12_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lookupTable_seq13_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lookupTable_seq13_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lookupTable_seq13_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lookupTable_seq13_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lookupTable_seq13_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lookupTable_seq14_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lookupTable_seq14_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lookupTable_seq14_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lookupTable_seq14_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lookupTable_seq14_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lookupTable_seq15_instr0", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "lookupTable_seq15_instr1", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "lookupTable_seq15_instr2", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "lookupTable_seq15_instr3", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "lookupTable_seq15_instr4", + "description": " [0x080-0x1bf] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1C0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1C0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1C4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1C4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1C8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1C8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1CC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1CC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1D0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1D4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1D8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1D8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1DC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1DC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x1c0-0x1ef] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1E0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1E0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "lutCustomSeq_9", + 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a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_b0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_b0.json new file mode 100644 index 0000000..ca3eb13 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fcb_xspi_nor_b0.json @@ -0,0 +1,2091 @@ +{ + "cpu": "MIMXRT798s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + 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"access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": "Control Miscellaneous Options for Flash Configuration Block", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: 1 for Serial NOR flash memory ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency 1: 30 MHz 2: 50 MHz 3: 60 MHz 4: 80 MHz 5: 100 MHz 6: 120 MHz 7: 133 MHz 8: 166 MHz 9: 200 MHz ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "lookupTable_seq0_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "lookupTable_seq0_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "lookupTable_seq0_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "lookupTable_seq0_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "lookupTable_seq0_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "lookupTable_seq1_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "lookupTable_seq1_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "lookupTable_seq1_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "lookupTable_seq1_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "lookupTable_seq1_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "lookupTable_seq2_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "lookupTable_seq2_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "lookupTable_seq2_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "lookupTable_seq2_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "lookupTable_seq2_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "lookupTable_seq3_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "lookupTable_seq3_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "lookupTable_seq3_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "lookupTable_seq3_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "lookupTable_seq3_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "lookupTable_seq4_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "lookupTable_seq4_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "lookupTable_seq4_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "lookupTable_seq4_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "lookupTable_seq4_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "lookupTable_seq5_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "lookupTable_seq5_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "lookupTable_seq5_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "lookupTable_seq5_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "lookupTable_seq5_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "lookupTable_seq6_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "lookupTable_seq6_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "lookupTable_seq6_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "lookupTable_seq6_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "lookupTable_seq6_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "lookupTable_seq7_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "lookupTable_seq7_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "lookupTable_seq7_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "lookupTable_seq7_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "lookupTable_seq7_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "lookupTable_seq8_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "lookupTable_seq8_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "lookupTable_seq8_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "lookupTable_seq8_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "lookupTable_seq8_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "lookupTable_seq9_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "lookupTable_seq9_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "lookupTable_seq9_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "lookupTable_seq9_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "lookupTable_seq9_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "lookupTable_seq10_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "lookupTable_seq10_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "lookupTable_seq10_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "lookupTable_seq10_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "lookupTable_seq10_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "lookupTable_seq11_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "lookupTable_seq11_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "lookupTable_seq11_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "lookupTable_seq11_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "lookupTable_seq11_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "lookupTable_seq12_instr0", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "lookupTable_seq12_instr1", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "lookupTable_seq12_instr2", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "lookupTable_seq12_instr3", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lookupTable_seq12_instr4", + "description": " [0x080-0x1e7] Lookup table holds Flash command sequences ", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lookupTable_seq13_instr0", + "description": " [0x080-0x1e7] Lookup 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"is_reserved": true + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_a0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_a0.json new file mode 100644 index 0000000..9160880 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_a0.json @@ -0,0 +1,4741 @@ +{ + "cpu": "MIMXRT798S", + "shadow_reg_base_addr_int": "0x40018000", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0", + "index_int": "0", + "shadow_reg_offset_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG0_LOCK[2:0]", + "description": "Boot Configuration Lock", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK[2:0]", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1", + "index_int": "0x0001", + "shadow_reg_offset_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "XSPI0_IPED_CFG_LOCK[2:0]", + "description": "XSPI0 IPED configuration Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "XSPI1_IPED_CFG_LOCK[2:0]", + "description": "XSPI1 IPED configuration Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2", + "index_int": "0x0002", + "shadow_reg_offset_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-3-5", + "name": "ROTKH_LOCK[2:0]", + "description": "ROTKH Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-9-11", + "name": "REVOKE_LOCK[2:0]", + "description": "Revoke Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-12-14", + "name": "CUST_MK_SK_LOCK[2:0]", + "description": "CUST_MK_SK Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse3", + "name": "LOCK_CFG3", + "description": "LOCK_CFG3", + "index_int": "0x0003", + "shadow_reg_offset_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse3-bits-0-2", + "name": "LIFE_CYCLE_LOCK[2:0]", + "description": "Life Cycle Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse3-bits-6-8", + "name": "NS_FW_VER_LOCK[2:0]", + "description": "Non-Secure Firmware version Lock Bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse3-bits-9-11", + "name": "SEC_FW_VER_LOCK[2:0]", + "description": "Secure Firmware version Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse5", + "name": "LOCK_CFG5", + "description": "LOCK_CFG5", + "index_int": "0x0005", + "shadow_reg_offset_int": "0x0014", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse5-bits-6-8", + "name": "BOOT_CFG1_LOCK[2:0]", + "description": "BOOT_CFG Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-9-11", + "name": "CUST_GP_BANK0_LOCK[2:0]", + "description": "Customer BOOTCFG0 Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "OEM configuration", + "description": "OEM device and Debug Credential (DC) constraints" + }, + "registers": [ + { + "id": "fuse37", + "name": "LIFECYCLE", + "description": "Device lifecycle and CC_SOCU debug access restrictions per debug domain.", + "index_int": "0x0025", + "shadow_reg_offset_int": "0x0094", + "default_value_int": "0x00030003", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse37-bits-0-7", + "name": "LC_STATE_RED", + "description": "Redundant Life Cycle state", + "values": [ + { + "name": "DEVELOP", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "Alternative in-field application state that prevents use of field return/failure analysis states. The rest of the behavior of the device is the same as the In-field state." + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "NXP field return state (CQC = Customer Quality Complaint)." + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-8", + "name": "CPU0_NIDEN_DIS", + "description": "CPU0 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-9", + "name": "CPU0_DBGEN_DIS", + "description": "CPU0 Invasive Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-10", + "name": "CPU0_SPNIDEN_DIS", + "description": "CPU0 Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-11", + "name": "CPU0_SPIDEN_DIS", + "description": "CPU0 Secure invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-12", + "name": "CPU1_NIDEN_DIS", + "description": "CPU0 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-13", + "name": "CPU1_DBGEN_DIS", + "description": "CPU0 Invasive Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-14", + "name": "CPU1_SPNIDEN_DIS", + "description": "CPU0 Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-15", + "name": "CPU1_SPIDEN_DIS", + "description": "CPU0 Secure invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 8, + "id": "fuse37-bits-16-23", + "name": "BP_LC_STATE_RED", + "description": "Bit-protection: Redundant Life Cycle state", + "values": [ + { + "name": "DEVELOP", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "Alternative in-field application state that prevents use of field return/failure analysis states. The rest of the behavior of the device is the same as the In-field state." + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "NXP field return state (CQC = Customer Quality Complaint)." + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-24", + "name": "BP_CPU0_NIDEN_DIS", + "description": "Bit-protection: CPU1 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-25", + "name": "BP_CPU0_DBGEN_DIS", + "description": "Bit-protection: CPU1 Invasive Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-26", + "name": "BP_CPU0_SPNIDEN_DIS", + "description": "Bit-protection: CPU1 Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-27", + "name": "BP_CPU0_SPIDEN_DIS", + "description": "Bit-protection: CPU1 Secure invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-28", + "name": "BP_CPU1_NIDEN_DIS", + "description": "Bit-protection: CPU1 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-29", + "name": "BP_CPU1_DBGEN_DIS", + "description": "Bit-protection: CPU1 Invasive Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-30", + "name": "BP_CPU1_SPNIDEN_DIS", + "description": "Bit-protection: CPU1 Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-31", + "name": "BP_CPU1_SPIDEN_DIS", + "description": "Bit-protection: CPU1 Secure invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + } + ] + }, + { + "id": "fuse132", + "name": "IMAGE_KEY_REVOKE[15:0]", + "description": "Image Key Revoke", + "index_int": "0x0084", + "shadow_reg_offset_int": "0x0210", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse133", + "name": "DCFG_CC_VU[15:0]", + "description": "Device Configuration for Credential Constraints Vendor-Usage", + "index_int": "0x0085", + "shadow_reg_offset_int": "0x0214", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse134", + "name": "ROTK_REVOKE", + "description": "ROTK_USAGE", + "index_int": "0x0086", + "shadow_reg_offset_int": "0x0218", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse134-bit-0", + "name": "ROTK0_EX_IMG_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 from being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-1", + "name": "ROTK0_EX_SB3_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 from being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-2", + "name": "ROTK0_EX_DBG_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 from being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-4", + "name": "ROTK1_EX_IMG_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 from being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-5", + "name": "ROTK1_EX_SB3_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 from being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-6", + "name": "ROTK1_EX_DBG_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 from being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-8", + "name": "ROTK2_EX_IMG_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 from being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-9", + "name": "ROTK2_EX_SB3_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 from being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-10", + "name": "ROTK2_EX_DBG_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 from being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-12", + "name": "ROTK3_EX_IMG_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 from being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-13", + "name": "ROTK3_EX_SB3_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 from being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-14", + "name": "ROTK3_EX_DBG_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 from being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse143", + "name": "LIFECYCLE_DP", + "description": "Device lifecycle and CC_SOCU debug access restrictions per debug domain.", + "index_int": "0x008F", + "shadow_reg_offset_int": "0x023C", + "default_value_int": "0x00030003", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse143-bits-0-7", + "name": "LC_STATE", + "description": "Life Cycle state", + "values": [ + { + "name": "DEVELOP", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "Alternative in-field application state that prevents use of field return/failure analysis states. The rest of the behavior of the device is the same as the In-field state." + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "NXP field return state (CQC = Customer Quality Complaint)." + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-8", + "name": "HIFI4_NIDEN_DIS", + "description": "HiFi4 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-9", + "name": "HIFI4_DBGEN_DIS", + "description": "HiFi4 Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-10", + "name": "HIFI1_NIDEN_DIS", + "description": "HiFi1 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-11", + "name": "HIFI1_DBGEN_DIS", + "description": "HiFi1 Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-12", + "name": "AHBAP_DBGEN_DIS", + "description": "AHBAP Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-13", + "name": "AHBAP_SPIDEN_DIS", + "description": "AHBAP Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-14", + "name": "EZHV_DBGEN_DIS", + "description": "EZHV Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-15", + "name": "SOC_CORESIGHT_DIS", + "description": "CoreSight Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 8, + "id": "fuse143-bits-16-23", + "name": "BP_LC_STATE", + "description": "Bit-protection: Life Cycle state", + "values": [ + { + "name": "DEVELOP", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "DEVELOP2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "IN_FIELD", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "IN_FIELD_LOCKED", + "value": 207, + "description": "Alternative in-field application state that prevents use of field return/failure analysis states. The rest of the behavior of the device is the same as the In-field state." + }, + { + "name": "FIELD_RETURN_OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "FAILURE_ANALYSIS", + "value": 127, + "description": "NXP field return state (CQC = Customer Quality Complaint)." + }, + { + "name": "BRICKED", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-24", + "name": "BP_HIFI4_NIDEN_DIS", + "description": "Bit-protection: HiFi4 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-25", + "name": "BP_HIFI4_DBGEN_DIS", + "description": "Bit-protection: HiFi4 Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-26", + "name": "BP_HIFI1_NIDEN_DIS", + "description": "Bit-protection: HiFi1 Non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-27", + "name": "BP_HIFI1_DBGEN_DIS", + "description": "Bit-protection: HiFi1 Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-28", + "name": "BP_AHBAP_DBGEN_DIS", + "description": "Bit-protection: AHBAP Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-29", + "name": "BP_AHBAP_SPIDEN_DIS", + "description": "Bit-protection: AHBAP Secure non-invasive debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-30", + "name": "BP_EZHV_DBGEN_DIS", + "description": "Bit-protection: EZHV Debug Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-31", + "name": "BP_SOC_CORESIGHT_DIS", + "description": "Bit-protection: CoreSight Disable", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "RKTH", + "description": "OEM Root Key Table Hash" + }, + "registers": [ + { + "id": "fuse88", + "name": "RKTH0", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0058", + "shadow_reg_offset_int": "0x0160", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse88-bits-0-31", + "name": "ROTKH[31:0]", + "description": "ROTKH[31:0] field" + } + ] + }, + { + "id": "fuse89", + "name": "RKTH1", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0059", + "shadow_reg_offset_int": "0x0164", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse89-bits-0-31", + "name": "ROTKH[63:32]", + "description": "ROTKH[63:32] field" + } + ] + }, + { + "id": "fuse90", + "name": "RKTH2", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005A", + "shadow_reg_offset_int": "0x0168", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse90-bits-0-31", + "name": "ROTKH[95:64]", + "description": "ROTKH[95:64] field" + } + ] + }, + { + "id": "fuse91", + "name": "RKTH3", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005B", + "shadow_reg_offset_int": "0x016C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse91-bits-0-31", + "name": "ROTKH[127:96]", + "description": "ROTKH[127:96] field" + } + ] + }, + { + "id": "fuse92", + "name": "RKTH4", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005C", + "shadow_reg_offset_int": "0x0170", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse92-bits-0-31", + "name": "ROTKH[159:128]", + "description": "ROTKH[159:128] field" + } + ] + }, + { + "id": "fuse93", + "name": "RKTH5", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005D", + "shadow_reg_offset_int": "0x0174", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse93-bits-0-31", + "name": "ROTKH[191:160]", + "description": "ROTKH[191:160] field" + } + ] + }, + { + "id": "fuse94", + "name": "RKTH6", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005E", + "shadow_reg_offset_int": "0x0178", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse94-bits-0-31", + "name": "ROTKH[223:192]", + "description": "ROTKH[223:192] field" + } + ] + }, + { + "id": "fuse95", + "name": "RKTH7", + "description": "Root of Trust Keys Table hash", + "index_int": "0x005F", + "shadow_reg_offset_int": "0x017C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse95-bits-0-31", + "name": "ROTKH[255:224]", + "description": "ROTKH[255:224] field" + } + ] + }, + { + "id": "fuse96", + "name": "RKTH8", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0060", + "shadow_reg_offset_int": "0x0180", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse96-bits-0-31", + "name": "ROTKH[287:256]", + "description": "ROTKH[287:256] field" + } + ] + }, + { + "id": "fuse97", + "name": "RKTH9", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0061", + "shadow_reg_offset_int": "0x0184", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse97-bits-0-31", + "name": "ROTKH[319:288]", + "description": "ROTKH[319:288] field" + } + ] + }, + { + "id": "fuse98", + "name": "RKTH10", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0062", + "shadow_reg_offset_int": "0x0188", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse98-bits-0-31", + "name": "ROTKH[351:320]", + "description": "ROTKH[351:320] field" + } + ] + }, + { + "id": "fuse99", + "name": "RKTH11", + "description": "Root of Trust Keys Table hash", + "index_int": "0x0063", + "shadow_reg_offset_int": "0x018C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse99-bits-0-31", + "name": "ROTKH[383:352]", + "description": "ROTKH[383:352] field" + } + ] + } + ] + }, + { + "group": { + "name": "CUST_MK_SK", + "description": "Customer Master Key Symmetric Key" + }, + "registers": [ + { + "id": "fuse100", + "name": "CUST_MK_SK0", + "description": "Customer MK_SK", + "index_int": "0x0064", + "shadow_reg_offset_int": "0x0190", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse100-bits-0-31", + "name": "CUST_MK_SK_BLOB[31:0]", + "description": "CUST_MK_SK_BLOB[31:0] field" + } + ] + }, + { + "id": "fuse101", + "name": "CUST_MK_SK1", + "description": "Customer MK_SK", + "index_int": "0x0065", + "shadow_reg_offset_int": "0x0194", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse101-bits-0-31", + "name": "CUST_MK_SK_BLOB[63:32]", + "description": "CUST_MK_SK_BLOB[63:32] field" + } + ] + }, + { + "id": "fuse102", + "name": "CUST_MK_SK2", + "description": "Customer MK_SK", + "index_int": "0x0066", + "shadow_reg_offset_int": "0x0198", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse102-bits-0-31", + "name": "CUST_MK_SK_BLOB[95:64]", + "description": "CUST_MK_SK_BLOB[95:64] field" + } + ] + }, + { + "id": "fuse103", + "name": "CUST_MK_SK3", + "description": "Customer MK_SK", + "index_int": "0x0067", + "shadow_reg_offset_int": "0x019C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse103-bits-0-31", + "name": "CUST_MK_SK_BLOB[127:96]", + "description": "CUST_MK_SK_BLOB[127:96] field" + } + ] + }, + { + "id": "fuse104", + "name": "CUST_MK_SK4", + "description": "Customer MK_SK", + "index_int": "0x0068", + "shadow_reg_offset_int": "0x01A0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse104-bits-0-31", + "name": "CUST_MK_SK_BLOB[159:128]", + "description": "CUST_MK_SK_BLOB[159:128] field" + } + ] + }, + { + "id": "fuse105", + "name": "CUST_MK_SK5", + "description": "Customer MK_SK", + "index_int": "0x0069", + "shadow_reg_offset_int": "0x01A4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse105-bits-0-31", + "name": "CUST_MK_SK_BLOB[191:160]", + "description": "CUST_MK_SK_BLOB[191:160] field" + } + ] + }, + { + "id": "fuse106", + "name": "CUST_MK_SK6", + "description": "Customer MK_SK", + "index_int": "0x006A", + "shadow_reg_offset_int": "0x01A8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse106-bits-0-31", + "name": "CUST_MK_SK_BLOB[223:192]", + "description": "CUST_MK_SK_BLOB[223:192] field" + } + ] + }, + { + "id": "fuse107", + "name": "CUST_MK_SK7", + "description": "Customer MK_SK", + "index_int": "0x006B", + "shadow_reg_offset_int": "0x01AC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse107-bits-0-31", + "name": "CUST_MK_SK_BLOB[255:224]", + "description": "CUST_MK_SK_BLOB[255:224] field" + } + ] + }, + { + "id": "fuse108", + "name": "CUST_MK_SK8", + "description": "Customer MK_SK", + "index_int": "0x006C", + "shadow_reg_offset_int": "0x01B0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse108-bits-0-31", + "name": "CUST_MK_SK_BLOB[287:256]", + "description": "CUST_MK_SK_BLOB[287:256] field" + } + ] + }, + { + "id": "fuse109", + "name": "CUST_MK_SK9", + "description": "Customer MK_SK", + "index_int": "0x006D", + "shadow_reg_offset_int": "0x01B4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse109-bits-0-31", + "name": "CUST_MK_SK_BLOB[319:288]", + "description": "CUST_MK_SK_BLOB[319:288] field" + } + ] + }, + { + "id": "fuse110", + "name": "CUST_MK_SK10", + "description": "Customer MK_SK", + "index_int": "0x006E", + "shadow_reg_offset_int": "0x01B8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse110-bits-0-31", + "name": "CUST_MK_SK_BLOB[351:320]", + "description": "CUST_MK_SK_BLOB[351:320] field" + } + ] + }, + { + "id": "fuse111", + "name": "CUST_MK_SK11", + "description": "Customer MK_SK", + "index_int": "0x006F", + "shadow_reg_offset_int": "0x01BC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse111-bits-0-31", + "name": "CUST_MK_SK_BLOB[383:352]", + "description": "CUST_MK_SK_BLOB[383:352] field" + } + ] + } + ] + }, + { + "group": { + "name": "NS_FW_VER", + "description": "Non-Secure Firmware Version" + }, + "registers": [ + { + "id": "fuse112", + "name": "NS_FW_VER[15:0]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0070", + "shadow_reg_offset_int": "0x01C0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse113", + "name": "NS_FW_VER[31:16]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0071", + "shadow_reg_offset_int": "0x01C4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse114", + "name": "NS_FW_VER[47:32]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0072", + "shadow_reg_offset_int": "0x01C8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse115", + "name": "NS_FW_VER[63:48]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0073", + "shadow_reg_offset_int": "0x01CC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse116", + "name": "NS_FW_VER[79:64]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0074", + "shadow_reg_offset_int": "0x01D0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse117", + "name": "NS_FW_VER[95:80]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0075", + "shadow_reg_offset_int": "0x01D4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse118", + "name": "NS_FW_VER[111:96]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0076", + "shadow_reg_offset_int": "0x01D8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse119", + "name": "NS_FW_VER[127:112]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0077", + "shadow_reg_offset_int": "0x01DC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse120", + "name": "NS_FW_VER[143:128]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0078", + "shadow_reg_offset_int": "0x01E0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse121", + "name": "NS_FW_VER[159:144]", + "description": "Non-Secure Firmware Version", + "index_int": "0x0079", + "shadow_reg_offset_int": "0x01E4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse122", + "name": "NS_FW_VER[175:160]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007A", + "shadow_reg_offset_int": "0x01E8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse123", + "name": "NS_FW_VER[191:176]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007B", + "shadow_reg_offset_int": "0x01EC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse124", + "name": "NS_FW_VER[207:192]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007C", + "shadow_reg_offset_int": "0x01F0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse125", + "name": "NS_FW_VER[223:208]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007D", + "shadow_reg_offset_int": "0x01F4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse126", + "name": "NS_FW_VER[239:224]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007E", + "shadow_reg_offset_int": "0x01F8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + }, + { + "id": "fuse127", + "name": "NS_FW_VER[255:240]", + "description": "Non-Secure Firmware Version", + "index_int": "0x007F", + "shadow_reg_offset_int": "0x01FC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "SEC_FW_VER", + "description": "Secure Firmware Version" + }, + "registers": [ + { + "id": "fuse128", + "name": "SEC_FW_VER[15:0]", + "description": "Secure Firmware Version", + "index_int": "0x0080", + "shadow_reg_offset_int": "0x0200", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse129", + "name": "SEC_FW_VER[31:16]", + "description": "Secure Firmware Version", + "index_int": "0x0081", + "shadow_reg_offset_int": "0x0204", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse130", + "name": "SEC_FW_VER[47:32]", + "description": "Secure Firmware Version", + "index_int": "0x0082", + "shadow_reg_offset_int": "0x0208", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse131", + "name": "SEC_FW_VER[63:48]", + "description": "Secure Firmware Version", + "index_int": "0x0083", + "shadow_reg_offset_int": "0x020C", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "Boot configuration", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse136", + "name": "BOOT_CFG0", + "description": "BOOT_CFG0 register", + "index_int": "0x0088", + "shadow_reg_offset_int": "0x0220", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 2, + "id": "fuse136-bits-0-1", + "name": "BOOT_SRC[1:0]", + "description": "Specify the boot source selection.", + "values": [ + { + "name": "00", + "value": 0, + "description": "ISP pins determine the source" + }, + { + "name": "01", + "value": 1, + "description": "XSPI NOR flash" + }, + { + "name": "10", + "value": 2, + "description": "uSDHC flash" + }, + { + "name": "11", + "value": 3, + "description": "Serial boot (ISP)" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-2", + "name": "BOOT_IF_INST", + "description": "Specify boot interface instance when XSPI or uSDHC boot modes are selected.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Instance 0 (XSPI0 or uSDHC0)" + }, + { + "name": "1", + "value": 1, + "description": "Instance 1 (XSPI1 or uSDHC1)" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-3", + "name": "ISP_UART_DIS", + "description": "Disable LPUART interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-4", + "name": "ISP_SPI_DIS", + "description": "Disable LPSPI interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-5", + "name": "ISP_I2C_DIS", + "description": "Disable LPI2C interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-6", + "name": "ISP_USB_DIS", + "description": "Disable USB0 interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-7", + "name": "ISP_eUSB_DIS", + "description": "Disable USB1 interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-8", + "name": "ISP_MODE_PIN_DIS", + "description": "Disable boot mode selection using ISP mode pins.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-9", + "name": "ISP_DM_DIS", + "description": "Disable ISP mode entry through debug mailbox command.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-10", + "name": "ISP_FT_DIS", + "description": "Disable ISP mode entry as a fall through if valid image is not found in boot media.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-11", + "name": "ISP_API_DIS", + "description": "Disable ISP mode entry using ROM API.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 2, + "id": "fuse136-bits-12-13", + "name": "BOOT_SPEED", + "description": "System clock speed during boot.", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal boot (192 MHz) - VDD1 = 1.0 V" + }, + { + "name": "Low", + "value": 2, + "description": "Low speed boot (32 MHz) -VDD1 = 1.0 V" + }, + { + "name": "Middle", + "value": 3, + "description": "Middle speed boot (192 MHz) - VDD1 = 1.0 V" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-14", + "name": "FA_CMD_DIS", + "description": "Controls whether DM-AP set FA mode command can be issued after authentication.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-15", + "name": "NXP_FW_DIS", + "description": "Disable loading NXP signed SB3 files.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + } + ] + }, + { + "id": "fuse137", + "name": "BOOT_CFG1", + "description": "SECURE_BOOT_CFG", + "index_int": "0x0089", + "shadow_reg_offset_int": "0x0224", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse137-bit-0", + "name": "ENF_SEC_BOOT", + "description": "Enforce secure boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Image header define boot" + }, + { + "name": "1", + "value": 1, + "description": "Enforce secure boot" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-1", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite defined crypto algorithms for secure boot, update and debug features.", + "values": [ + { + "name": "0", + "value": 0, + "description": "ECDSA P-256, SHA256, AES128" + }, + { + "name": "1", + "value": 1, + "description": "ECDSA P-384, SHA384, AES256" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-2", + "name": "ENF_TZM_PRESET", + "description": "Enforce TZM preset data. If absent image is deemed corrupted.", + "values": [ + { + "name": "0", + "value": 0, + "description": "TZM data is optional;" + }, + { + "name": "1", + "value": 1, + "description": "Image should contain TZM data" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-3", + "name": "REC_BOOT_EN", + "description": "Recovery boot through LP_FLEXCOMM is enabled.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse137-bit-5", + "name": "DIS_XSPI_XIP", + "description": "Disable XIP image execution through XIP flash interfaces.", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-6", + "name": "DICE_SKIP", + "description": "Skip DICE CDI calculation during boot to reduce boot time.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "DICE enabled" + }, + { + "name": "Disable", + "value": 1, + "description": "DICE disabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-7", + "name": "DICE_INC_NXP", + "description": "When set include NXP configuration fuse data in CDI calculations.", + "values": [ + { + "name": "Not include", + "value": 0, + "description": "Not include NXP configuration" + }, + { + "name": "Include", + "value": 1, + "description": "Include NXP configuration" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-8", + "name": "DICE_INC_CUST", + "description": "When set include customer boot configuration fuse data in CDI calculations.", + "values": [ + { + "name": "Not include", + "value": 0, + "description": "Not include customer boot configuration" + }, + { + "name": "Include", + "value": 1, + "description": "Include customer boot configuration" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-9", + "name": "FIPS_PUF_EN", + "description": "Enable self-test of PUF IP before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-10", + "name": "FIPS_KDF_EN", + "description": "Enable FIPS self-test of CKDF algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-11", + "name": "FIPS_CMAC_EN", + "description": "Enable FIPS self-test of CMAC algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-12", + "name": "FIPS_DRBG_EN", + "description": "Enable FIPS self-test of DRBG algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-13", + "name": "FIPS_ECDSA_EN", + "description": "Enable FIPS self-test of ECDSA algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-14", + "name": "FIPS_AES_EN", + "description": "Enable FIPS self-test of AES algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-15", + "name": "FIPS_SHA2_EN", + "description": "Enable FIPS self-test of SHA2 algorithm before usage during boot.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + } + ] + }, + { + "id": "fuse138", + "name": "BOOT_CFG2", + "description": "BOOT_CFG2 register", + "index_int": "0x008A", + "shadow_reg_offset_int": "0x0228", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 4 + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse138-bit-5", + "name": "DCFG_UUID", + "description": "Enable UUID matching check during Debug Credential (DC) validation.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse138-bit-7", + "name": "IPED1_XEX_EN", + "description": "Enforce XEX mode for all IPED1 regions.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 4, + "id": "fuse138-bits-8-11", + "name": "IPED0_LOCK_CTX[3:0]", + "description": "Lock the corresponding IPED context.\n0b - Disable\n1b - Enable" + }, + { + "width": 4, + "id": "fuse138-bits-12-15", + "name": "IPED1_LOCK_CTX[3:0]", + "description": "Lock the corresponding IPED context.\n0b - Disable\n1b - Enable" + } + ] + }, + { + "id": "fuse139", + "name": "BOOT_CFG3", + "description": "BOOT_CFG3 register", + "index_int": "0x008B", + "shadow_reg_offset_int": "0x022C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse139-bits-0-3", + "name": "IPED0_GCM_CTX[3:0]", + "description": "Enable GCM mode for corresponding IPED context.\n0b - Disable\n1b - Enable" + }, + { + "width": 4, + "id": "fuse139-bits-4-7", + "name": "IPED0_GCM_AHBERR_CTX[3:0]", + "description": "Enable AHB error on GCM tag failure for corresponding IPED context.\n0b - Disable\n1b - Enable" + }, + { + "width": 4, + "id": "fuse139-bits-8-11", + "name": "IPED1_GCM_CTX[3:0]", + "description": "Enable GCM mode for corresponding IPED context.\n0b - Disable\n1b - Enable" + }, + { + "width": 4, + "id": "fuse139-bits-12-15", + "name": "IPED1_GCM_AHBERR_CTX[3:0]", + "description": "Enable AHB error on GCM tag failure for corresponding IPED context.\n0b - Disable\n1b - Enable" + } + ] + }, + { + "id": "fuse140", + "name": "BOOT_CFG4", + "description": "BOOT_STATUS_LEDS", + "index_int": "0x008C", + "shadow_reg_offset_int": "0x0230", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse140-bit-0", + "name": "BOOT_RETRY_FAIL_LED_PIN_EN", + "description": "Boot Retry fail LED enable bit. ROM sets this GPIO after exhausting boot retry count.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-1", + "name": "BOOT_RETRY_FAIL_LED_PIN_POL", + "description": "Output polarity. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-2-4", + "name": "BOOT_RETRY_FAIL_LED_PIN_PORT", + "description": "GPIO port. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-5-9", + "name": "BOOT_RETRY_FAIL_LED_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 1, + "id": "fuse140-bit-10", + "name": "SENSOR_RESET_LED_PIN_EN", + "description": "Sensor Reset LED enable bit. ROM sets this GPIO when last warm reset cause is detected as ITRC reset.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-11", + "name": "SENSOR_RESET_LED_PIN_POL", + "description": "Output polarity. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-12-14", + "name": "SENSOR_RESET_LED_PIN_PORT", + "description": "GPIO port. Output polarity. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-15-19", + "name": "SENSOR_RESET_LED_PIN_GPIO", + "description": "GPIO pin number. Output polarity. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 1, + "id": "fuse140-bit-20", + "name": "ISP_REC_LED_PIN_EN", + "description": "LED enable bit. ROM sets this GPIO whenever boot image is not found in boot media and before entering ISP or recovery boot mode. Output polarity.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-21", + "name": "ISP_REC_LED_PIN_POL", + "description": "Output polarity. Output polarity. This field is valid only if ISP_REC_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-22-24", + "name": "ISP_REC_LED_PIN_PORT", + "description": "GPIO port. This field is valid only if ISP_REC_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-25-29", + "name": "ISP_REC_LED_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if ISP_REC_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse141", + "name": "BOOT_CFG5", + "description": "BOOT_TIMERS", + "index_int": "0x008D", + "shadow_reg_offset_int": "0x0234", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse141-bits-0-7", + "name": "WDOG_TIMEOUT_10MS", + "description": "A 10 ms timer started before jumping to user application.\nnd - n x 10 ms" + }, + { + "width": 8, + "id": "fuse141-bits-8-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Device enters deep-power down state if it idles beyond this time during ISP command handling loop.\nnd - n x 1s" + }, + { + "width": 4, + "id": "fuse141-bits-16-19", + "name": "REC_BOOT_FC", + "description": "Specifies the LP_FLEXCOMM connected to 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.\nxd - LP_FLEXCOMMx is selected, x = 0-13" + }, + { + "width": 2, + "id": "fuse141-bits-20-21", + "name": "REC_BOOT_FC_PCS", + "description": "Specifies LP_FLEXCOMM PCS connected to 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.", + "values": [ + { + "name": "PCS0", + "value": 0, + "description": "PCS0" + }, + { + "name": "PCS1", + "value": 1, + "description": "PCS1" + }, + { + "name": "PCS2", + "value": 2, + "description": "PCS2" + }, + { + "name": "PCS3", + "value": 3, + "description": "PCS3" + } + ] + }, + { + "width": 2, + "id": "fuse141-bits-22-23", + "name": "REC_BOOT_FC_BAUDRATE", + "description": "Specifies LP_FLEXCOMM baudrate with 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.", + "values": [ + { + "name": "20MHz", + "value": 0, + "description": "20MHz" + }, + { + "name": "10MHz", + "value": 1, + "description": "10MHz" + }, + { + "name": "5MHz", + "value": 2, + "description": "5MHz" + }, + { + "name": "2MHz", + "value": 3, + "description": "2MHz" + } + ] + }, + { + "width": 8 + } + ] + }, + { + "id": "fuse142", + "name": "BOOT_CFG6", + "description": "BOOT_CFG6 register", + "index_int": "0x008E", + "shadow_reg_offset_int": "0x0238", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse142-bits-0-15", + "name": "USB_VID[15:0]", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse142-bits-16-31", + "name": "USB1_PID[15:0]", + "description": "USB1 Product ID" + } + ] + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "PRINCE IPED configuration" + }, + "registers": [ + { + "id": "fuse144", + "name": "XSPI0_IPED_CTX0", + "description": "XSPI0_IPED_CTX0 register", + "index_int": "0x0090", + "shadow_reg_offset_int": "0x0240", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse144-bits-0-15", + "name": "XSPI0_START_OFFSET_0", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse144-bits-16-31", + "name": "XSPI0_LENGTH_0", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse145", + "name": "XSPI0_IPED_CTX1", + "description": "XSPI0_IPED_CTX1 register", + "index_int": "0x0091", + "shadow_reg_offset_int": "0x0244", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse145-bits-0-15", + "name": "XSPI0_START_OFFSET_1", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse145-bits-16-31", + "name": "XSPI0_LENGTH_1", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse146", + "name": "XSPI0_IPED_CTX2", + "description": "XSPI0_IPED_CTX2 register", + "index_int": "0x0092", + "shadow_reg_offset_int": "0x0248", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse146-bits-0-15", + "name": "XSPI0_START_OFFSET_2", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse146-bits-16-31", + "name": "XSPI0_LENGTH_2", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse147", + "name": "XSPI0_IPED_CTX3", + "description": "XSPI0_IPED_CTX3 register", + "index_int": "0x0093", + "shadow_reg_offset_int": "0x024C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse147-bits-0-15", + "name": "XSPI0_START_OFFSET_3", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse147-bits-16-31", + "name": "XSPI0_LENGTH_3", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse148", + "name": "XSPI1_IPED_CTX0", + "description": "XSPI1_IPED_CTX0 register", + "index_int": "0x0094", + "shadow_reg_offset_int": "0x0250", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse148-bits-0-15", + "name": "XSPI1_START_OFFSET_0", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse148-bits-16-31", + "name": "XSPI1_LENGTH_0", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse149", + "name": "XSPI1_IPED_CTX1", + "description": "XSPI1_IPED_CTX1 register", + "index_int": "0x0095", + "shadow_reg_offset_int": "0x0254", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse149-bits-0-15", + "name": "XSPI1_START_OFFSET_1", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse149-bits-16-31", + "name": "XSPI1_LENGTH_1", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse150", + "name": "XSPI1_IPED_CTX2", + "description": "XSPI1_IPED_CTX2 register", + "index_int": "0x0096", + "shadow_reg_offset_int": "0x0258", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse150-bits-0-15", + "name": "XSPI1_START_OFFSET_2", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse150-bits-16-31", + "name": "XSPI1_LENGTH_2", + "description": "LENGTH (4KB block counts)" + } + ] + }, + { + "id": "fuse151", + "name": "XSPI1_IPED_CTX3", + "description": "XSPI1_IPED_CTX3 register", + "index_int": "0x0097", + "shadow_reg_offset_int": "0x025C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse151-bits-0-15", + "name": "XSPI1_START_OFFSET_3", + "description": "START_OFFSET (4KB aligned)" + }, + { + "width": 16, + "id": "fuse151-bits-16-31", + "name": "XSPI1_LENGTH_3", + "description": "LENGTH (4KB block counts)" + } + ] + } + ] + }, + { + "group": { + "name": "XSPI", + "description": "XSPI configuration" + }, + "registers": [ + { + "id": "fuse152", + "name": "XSPI_CFG0", + "description": "XSPI_CFG0 register", + "index_int": "0x0098", + "shadow_reg_offset_int": "0x0260", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse152-bit-0", + "name": "XSPI_FLASH_AUTO_PROBE_EN", + "description": "Quad SPI or Octal SPI flash memory auto-probe feature enable", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-1-3", + "name": "XSPI_FLASH_PROBE_TYPE", + "description": "Quad SPI or Octal SPI flash memory probe type", + "values": [ + { + "name": "000", + "value": 0, + "description": "Quad SPI NOR flash memory" + }, + { + "name": "001", + "value": 1, + "description": "Macronix Octal flash memory" + }, + { + "name": "010", + "value": 2, + "description": "Micron Octal flash memory" + }, + { + "name": "011", + "value": 3, + "description": "Adesto Octal flash memory" + }, + { + "name": "100", + "value": 4, + "description": "Octal SDR" + }, + { + "name": "101", + "value": 5, + "description": "Octal DDR" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-4-6", + "name": "XSPI_FLASH_TYPE", + "description": "Typical serial NOR flash memory types", + "values": [ + { + "name": "000", + "value": 0, + "description": "Quad SPI flash memory address (by default, the chip supports 3B read)" + }, + { + "name": "010", + "value": 2, + "description": "HyperFlash 1.8 V" + }, + { + "name": "011", + "value": 3, + "description": "HyperFlash 3.3 V" + }, + { + "name": "100", + "value": 4, + "description": "MXIC Octal DDR" + }, + { + "name": "101", + "value": 5, + "description": "Micron Octal DDR" + } + ] + }, + { + "width": 4, + "id": "fuse152-bits-7-10", + "name": "XSPI_FLASH_DUMMY_CYCLES", + "description": "Quad SPI or Octal SPI dummy cycles for read command\n0000b - Dummy cycles probed automatically\nOther value - Number of dummy cycles" + }, + { + "width": 3, + "id": "fuse152-bits-11-13", + "name": "XSPI_FLASH_BOOT_FREQ", + "description": "Quad SPI or Octal SPI flash interface frequency", + "values": [ + { + "name": "80 MHz", + "value": 0, + "description": "80 MHz" + }, + { + "name": "60 MHz", + "value": 1, + "description": "60 MHz" + }, + { + "name": "50 MHz", + "value": 2, + "description": "50 MHz" + }, + { + "name": "100 MHz", + "value": 3, + "description": "100 MHz" + }, + { + "name": "120 MHz", + "value": 4, + "description": "120 MHz" + }, + { + "name": "133 MHz", + "value": 5, + "description": "133 MHz" + }, + { + "name": "166 MHz", + "value": 6, + "description": "166 MHz" + }, + { + "name": "200 MHz", + "value": 7, + "description": "200 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse152-bit-14", + "name": "XSPI_RESET_PIN_EN", + "description": "Enable to reset flash memory by reset pin or JEDEC", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse152-bit-15", + "name": "XSPI_NOR_RESET_TYPE", + "description": "HW reset or JEDEC reset. This field is valid only if XSPI_RESET_PIN_EN is set.", + "values": [ + { + "name": "Pin reset", + "value": 0, + "description": "Pin reset" + }, + { + "name": "JEDEC reset", + "value": 1, + "description": "JEDEC reset" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-16-18", + "name": "XSPI_RESET_PIN_PORT", + "description": "GPIO port. This field is valid only if XSPI_RESET_PIN_EN is set." + }, + { + "width": 5, + "id": "fuse152-bits-19-23", + "name": "XSPI_RESET_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if XSPI_RESET_PIN_EN is set." + }, + { + "width": 2, + "id": "fuse152-bits-24-25", + "name": "XSPI_HOLD_TIME", + "description": "Wait time before accessing serial flash memory", + "values": [ + { + "name": "500 us", + "value": 0, + "description": "500 us" + }, + { + "name": "1 ms", + "value": 1, + "description": "1 ms" + }, + { + "name": "3 ms", + "value": 2, + "description": "3 ms" + }, + { + "name": "10 ms", + "value": 3, + "description": "10 ms" + } + ] + }, + { + "width": 4, + "id": "fuse152-bits-26-29", + "name": "XSPI_PWR_HOLD_TIME", + "description": "Delay (wait time) after POR before accessing Quad SPI or Octal SPI flash memory devices, in addition to the delay that the QSPI_HOLD TIME field specifies", + "values": [ + { + "name": "0000", + "value": 0, + "description": "No delay" + }, + { + "name": "0001", + "value": 1, + "description": "Additional 100 us" + }, + { + "name": "0010", + "value": 2, + "description": "Additional 500 us" + }, + { + "name": "0011", + "value": 3, + "description": "Additional 1 ms" + }, + { + "name": "0100", + "value": 4, + "description": "Additional 10 ms" + }, + { + "name": "0101", + "value": 5, + "description": "Additional 20 ms" + }, + { + "name": "0110", + "value": 6, + "description": "Additional 40 ms" + }, + { + "name": "0111", + "value": 7, + "description": "Additional 60 ms" + }, + { + "name": "1000", + "value": 8, + "description": "Additional 80 ms" + }, + { + "name": "1001", + "value": 9, + "description": "Additional 100 ms" + }, + { + "name": "1010", + "value": 10, + "description": "Additional 120 ms" + }, + { + "name": "1011", + "value": 11, + "description": "Additional 140 ms" + }, + { + "name": "1100", + "value": 12, + "description": "Additional 160 ms" + }, + { + "name": "1101", + "value": 13, + "description": "Additional 180 ms" + }, + { + "name": "1110", + "value": 14, + "description": "Additional 200 ms" + }, + { + "name": "1111", + "value": 15, + "description": "Additional 220 ms" + } + ] + }, + { + "width": 2, + "id": "fuse152-bits-30-31", + "name": "XSPI_FLASH_DUMMY_CYCLES_UPPER", + "description": "Quad/Octal-SPI dummy cycles upper 2 bit for read command." + } + ] + }, + { + "id": "fuse153", + "name": "XSPI_CFG1", + "description": "XSPI_CFG1 register", + "index_int": "0x0099", + "shadow_reg_offset_int": "0x0264", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse153-bits-0-6", + "name": "XSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for Flash read sampling via external DQS\n0b - Use the delay cell value calculated by ROM\nOthers - Use the delay cell value in terms of 100 ps" + }, + { + "width": 10, + "id": "fuse153-bits-7-16", + "name": "XSPI_FLASH_SEC_IMAGE_OFFSET", + "description": "Offset of the second image\nxd - x multiplied by 128 KB" + }, + { + "width": 7, + "id": "fuse153-bits-17-23", + "name": "XSPI_FLASH_IMAGE_SIZE", + "description": "Size of the second image\n0d - Same size as the image offset (XSPI_IMAGE_OFFSET)\n1d - 128 KB\n2d - 256 KB\nmd - m x 128 KB (m = 3-7)\n8d - 1 MB\nnd - (n-7) \u00d7 1 MB (n = 8-71)" + }, + { + "width": 3, + "id": "fuse153-bits-24-26", + "name": "XSPI_FLASH_ENHANCE_MODE", + "description": "XSPI enhance mode", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable" + }, + { + "name": "FORCE_LOOPBACK_DQS", + "value": 5, + "description": "Force using internal loopback DQS" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "fuse154", + "name": "XSPI_CFG2", + "description": "XSPI_CFG2 register", + "index_int": "0x009A", + "shadow_reg_offset_int": "0x0268", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse154-bits-0-31", + "name": "XSPI_FLASH_SDR_DLLCRA", + "description": "Configure DLL and the subordinate delay chain for flash memory with SDR interface, see XSPI_DLLCRA register for more details." + } + ] + }, + { + "id": "fuse155", + "name": "XSPI_CFG3", + "description": "XSPI_CFG3 register", + "index_int": "0x009B", + "shadow_reg_offset_int": "0x026C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse155-bits-0-31", + "name": "XSPI_FLASH_SDR_SMPR", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with SDR interface. See XSPI_SMPR register for more details." + } + ] + }, + { + "id": "fuse156", + "name": "XSPI_CFG4", + "description": "XSPI_CFG4 register", + "index_int": "0x009C", + "shadow_reg_offset_int": "0x0270", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse156-bits-0-31", + "name": "XSPI_FLASH_DDR_DLLCRA", + "description": "Configure DLL and the subordinate delay chain for flash memory with DDR interface, see XSPI_DLLCRA register for more details." + } + ] + }, + { + "id": "fuse157", + "name": "XSPI_CFG5", + "description": "XSPI_CFG5 register", + "index_int": "0x009D", + "shadow_reg_offset_int": "0x0274", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse157-bits-0-31", + "name": "XSPI_FLASH_DDR_SMPR", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with DDR interface. See XSPI_SMPR register for more details." + } + ] + } + ] + }, + { + "group": { + "name": "SDHC", + "description": "SDHC configuration" + }, + "registers": [ + { + "id": "fuse158", + "name": "SDHC_CFGF0", + "description": "SDHC_CFGF0 register (for uSDHC0)", + "index_int": "0x009E", + "shadow_reg_offset_int": "0x0278", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse158-bits-0-1", + "name": "SDHC_BUS_WIDTH", + "description": "eMMC bus width selection", + "values": [ + { + "name": "4 bits", + "value": 0, + "description": "4 bits" + }, + { + "name": "8 bits", + "value": 1, + "description": "8 bits" + }, + { + "name": "4 bits DDR", + "value": 2, + "description": "4 bits DDR" + }, + { + "name": "8 bits DDR", + "value": 3, + "description": "8 bits DDR" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-2", + "name": "SDHC_PWR_CYCLE_EN", + "description": "Power cycle enable", + "values": [ + { + "name": "No", + "value": 0, + "description": "No power cycle" + }, + { + "name": "Yes", + "value": 1, + "description": "Power cycle enabled via RST pad" + } + ] + }, + { + "width": 2, + "id": "fuse158-bits-3-4", + "name": "SDHC_PWR_CYCLE_WAIT", + "description": "Power down wait selection", + "values": [ + { + "name": "20 ms", + "value": 0, + "description": "20 ms" + }, + { + "name": "10 ms", + "value": 1, + "description": "10 ms" + }, + { + "name": "5 ms", + "value": 2, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 3, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse158-bits-5-6", + "name": "SDHC_PWR_STABLE_WAIT", + "description": "Power up wait selection", + "values": [ + { + "name": "5 ms", + "value": 0, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-7", + "name": "SDHC_PWR_POL", + "description": "uSDHC reset polarity selection", + "values": [ + { + "name": "Low", + "value": 0, + "description": "Reset active low" + }, + { + "name": "High", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse158-bit-9", + "name": "SDHC_RESET_PRE_IDLE", + "description": "eMMC disable pre-idle selection", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-10", + "name": "SDHC_MMC_SPEED", + "description": "eMMC speed selection", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal speed" + }, + { + "name": "High", + "value": 1, + "description": "High speed" + } + ] + }, + { + "width": 21 + } + ] + }, + { + "id": "fuse159", + "name": "SDHC_CFGF1", + "description": "SDHC_CFGF1 register (for uSDHC1)", + "index_int": "0x009F", + "shadow_reg_offset_int": "0x027C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse159-bits-0-1", + "name": "SDHC_CFGF1_SDHC_BUS_WIDTH0", + "description": "eMMC bus width selection", + "values": [ + { + "name": "4 bits", + "value": 0, + "description": "4 bits" + }, + { + "name": "8 bits", + "value": 1, + "description": "8 bits" + }, + { + "name": "4 bits DDR", + "value": 2, + "description": "4 bits DDR" + }, + { + "name": "8 bits DDR", + "value": 3, + "description": "8 bits DDR" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-2", + "name": "SDHC_CFGF1_SDHC_PWR_CYCLE_EN1", + "description": "Power cycle enable", + "values": [ + { + "name": "No", + "value": 0, + "description": "No power cycle" + }, + { + "name": "Yes", + "value": 1, + "description": "Power cycle enabled via RST pad" + } + ] + }, + { + "width": 2, + "id": "fuse159-bits-3-4", + "name": "SDHC_CFGF1_SDHC_PWR_CYCLE_WAIT2", + "description": "Power down wait selection", + "values": [ + { + "name": "20 ms", + "value": 0, + "description": "20 ms" + }, + { + "name": "10 ms", + "value": 1, + "description": "10 ms" + }, + { + "name": "5 ms", + "value": 2, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 3, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse159-bits-5-6", + "name": "SDHC_CFGF1_SDHC_PWR_STABLE_WAIT3", + "description": "Power up wait selection", + "values": [ + { + "name": "5 ms", + "value": 0, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-7", + "name": "SDHC_CFGF1_SDHC_PWR_POL4", + "description": "uSDHC reset polarity selection", + "values": [ + { + "name": "Low", + "value": 0, + "description": "Reset active low" + }, + { + "name": "High", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse159-bit-9", + "name": "SDHC_CFGF1_SDHC_RESET_PRE_IDLE6", + "description": "eMMC disable pre-idle selection", + "values": [ + { + "name": "Enabled", + "value": 0, + "description": "Enabled" + }, + { + "name": "Disabled", + "value": 1, + "description": "Disabled" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-10", + "name": "SDHC_CFGF1_SDHC_MMC_SPEED7", + "description": "eMMC speed selection", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal speed" + }, + { + "name": "High", + "value": 1, + "description": "High speed" + } + ] + }, + { + "width": 21 + } + ] + } + ] + }, + { + "group": { + "name": "Miscellaneous", + "description": "Miscellaneous configuration" + }, + "registers": [ + { + "id": "fuse160", + "name": "BOOT_CFG8", + "description": "BOOT_CFG8 register", + "index_int": "0x00A0", + "shadow_reg_offset_int": "0x0280", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 1 + }, + { + "width": 3 + }, + { + "width": 5 + }, + { + "width": 1, + "id": "fuse160-bit-9", + "name": "DBG_OVER_USB_LOCK", + "description": "Enable debug over USB register write lock. ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3, + "id": "fuse160-bits-10-12", + "name": "DBG_OVER_USB_SEL_PORT", + "description": "Defines which GPIO port is selected to enable debug over USB0 pins feature.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse160-bits-13-17", + "name": "DBG_OVER_USB_SEL_GPIO", + "description": "Defines which GPIO pin is selected to enable debug over USB0 pins feature.\nxd - GPIO pin x" + }, + { + "width": 7, + "id": "fuse160-bits-18-24", + "name": "LPI2C_ADDRESS", + "description": "If 0x00, defaults to 0x10 for LPI2C slave address.\nIf not 0x00, use this value as the 7-bit LPI2C slave address" + }, + { + "width": 7 + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_b0.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_b0.json new file mode 100644 index 0000000..e1d5010 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/fuses_b0.json @@ -0,0 +1,5978 @@ +{ + "cpu": "MIMXRT798S", + "shadow_reg_base_addr_int": "0x40018000", + "groups": [ + { + "group": { + "name": "Locks", + "description": "Lock bits allowing to lock access to specified fuses" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "LOCK_CFG0 fuse word", + "index_int": "0", + "shadow_reg_offset_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG0_LOCK", + "description": "Boot Configuration Lock", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 9 + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "Lock for Fuse Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "LOCK_CFG1 fuse word", + "index_int": "0x0001", + "shadow_reg_offset_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-3-5", + "name": "XSPI0_IPED_CFG_LOCK", + "description": "XSPI0 IPED configuration Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "XSPI1_IPED_CFG_LOCK", + "description": "XSPI1 IPED configuration Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 7 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "LOCK_CFG2 fuse word", + "index_int": "0x0002", + "shadow_reg_offset_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-3-5", + "name": "ROTKH_LOCK", + "description": "ROTKH Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-6-8", + "name": "GPR1_LOCK", + "description": "Unique ID Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-9-11", + "name": "REVOKE_LOCK", + "description": "Revoke Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse2-bits-12-14", + "name": "CUST_MK_SK_LOCK", + "description": "CUST_MK_SK Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse3", + "name": "LOCK_CFG3", + "description": "LOCK_CFG3 fuse word", + "index_int": "0x0003", + "shadow_reg_offset_int": "0x000C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse3-bits-0-2", + "name": "LIFE_CYCLE_LOCK", + "description": "Life Cycle Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse3-bits-6-8", + "name": "NS_FW_VER_LOCK", + "description": "Non-Secure Firmware version Lock Bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse3-bits-9-11", + "name": "SEC_FW_VER_LOCK", + "description": "Secure Firmware version Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse3-bits-12-14", + "name": "GPR0_LOCK", + "description": "GPR0 Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1, + "id": "fuse3-bit-15", + "name": "CUST_GP_BANK2_LOCK[0]", + "description": "Customer BOOTCFG2 Lock bits(Write Protection bit[0])", + "values": [ + { + "name": "NO WP", + "value": 0, + "description": "NO WP" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + } + ] + } + ] + }, + { + "id": "fuse4", + "name": "LOCK_CFG4", + "description": "LOCK_CFG4 fuse word", + "index_int": "0x0004", + "shadow_reg_offset_int": "0x0010", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 15 + }, + { + "width": 1, + "id": "fuse4-bit-15", + "name": "CUST_GP_BANK2_LOCK[1]", + "description": "Customer BOOTCFG2 Lock bits(Over-write Protection bit[1])", + "values": [ + { + "name": "No OP", + "value": 0, + "description": "No OP" + }, + { + "name": "OP", + "value": 1, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + } + ] + } + ] + }, + { + "id": "fuse5", + "name": "LOCK_CFG5", + "description": "LOCK_CFG5 fuse word", + "index_int": "0x0005", + "shadow_reg_offset_int": "0x0014", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 6 + }, + { + "width": 3, + "id": "fuse5-bits-6-8", + "name": "BOOT_CFG1_LOCK", + "description": "BOOT_CFG Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-9-11", + "name": "CUST_GP_BANK0_LOCK", + "description": "Customer BOOTCFG0 Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 3, + "id": "fuse5-bits-12-14", + "name": "CUST_GP_BANK1_LOCK", + "description": "Customer BOOTCFG1 Lock bits", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked (fuses can be read, sensed, burned or over-ridden in the corresponding OTP shadow register)" + }, + { + "name": "WP", + "value": 1, + "description": "WP (Write Protect, the controlled field can not be burned)" + }, + { + "name": "OP", + "value": 2, + "description": "OP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + }, + { + "name": "OP+WP", + "value": 3, + "description": "OP + WP (Over-ride + Write Protect, the controlled field can not be overridden nor burned)" + }, + { + "name": "RP", + "value": 4, + "description": "RP (Read Protect, the controlled field can be sensed only, but can't be read from shadow registers)" + }, + { + "name": "RP+WP", + "value": 5, + "description": "RP+WP (Read + Write Protect, the controlled field can be sensed, overridden, but can't be read nor burned)" + }, + { + "name": "RP+OP", + "value": 6, + "description": "RP+OP (Read + Over-ride Protect, the controlled field can be sensed, burned, but can't be read nor over-written)" + }, + { + "name": "All Locks", + "value": 7, + "description": "All Locks (The controlled field can't be read, sensed, burned or overridden in corresponding OTP shadow register)" + } + ] + }, + { + "width": 1, + "id": "fuse5-bit-15", + "name": "CUST_GP_BANK2_LOCK[2]", + "description": "Customer BOOTCFG2 Lock bits(Read Protection bit[2])", + "values": [ + { + "name": "No RP", + "value": 0, + "description": "No RP" + }, + { + "name": "RP", + "value": 1, + "description": "RP (Over-ride Protect, the controlled field shadow registers can not be over-written)" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "OEM configuration", + "description": "OEM device and Debug Credential (DC) constraints" + }, + "registers": [ + { + "id": "fuse37", + "name": "DCFG_CC_SOCU", + "description": "DCFG_CC_SOCU fuse word", + "index_int": "0x0025", + "shadow_reg_offset_int": "0x0094", + "default_value_int": "0x0003", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse37-bits-0-7", + "name": "LC_STATE_RED", + "description": "Redundant Life Cycle" + }, + { + "width": 1, + "id": "fuse37-bit-8", + "name": "CPU0_NIDEN_DIS", + "description": "CPU0 Non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-9", + "name": "CPU0_DBGEN_DIS", + "description": "CPU0 Invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-10", + "name": "CPU0_SPNIDEN_DIS", + "description": "CPU0 Secure non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-11", + "name": "CPU0_SPIDEN_DIS", + "description": "CPU0 Secure invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-12", + "name": "CPU1_NIDEN_DIS", + "description": "CPU1 Non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-13", + "name": "CPU1_DBGEN_DIS", + "description": "CPU1 Invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-14", + "name": "CPU1_SPNIDEN_DIS", + "description": "CPU1 Secure non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse37-bit-15", + "name": "CPU1_SPIDEN_DIS", + "description": "CPU1 Secure invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 16 + } + ] + }, + { + "id": "fuse132", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revoke", + "index_int": "0x0084", + "shadow_reg_offset_int": "0x0210", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse133", + "name": "DCFG_CC_VU", + "description": "General purpose MC counter", + "index_int": "0x0085", + "shadow_reg_offset_int": "0x0214", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse134", + "name": "ROTK_USAGE", + "description": "ROTK_USAGE fuse word", + "index_int": "0x0086", + "shadow_reg_offset_int": "0x0218", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse134-bit-0", + "name": "ROTK0_EX_IMG_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 as being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-1", + "name": "ROTK0_EX_SB3_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 as being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-2", + "name": "ROTK0_EX_DBG_AUTH", + "description": "When set exclude RoTK0 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK0 as being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK0 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-4", + "name": "ROTK1_EX_IMG_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 as being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-5", + "name": "ROTK1_EX_SB3_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 as being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-6", + "name": "ROTK1_EX_DBG_AUTH", + "description": "When set exclude RoTK1 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK1 as being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK1 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-8", + "name": "ROTK2_EX_IMG_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 as being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-9", + "name": "ROTK2_EX_SB3_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 as being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-10", + "name": "ROTK2_EX_DBG_AUTH", + "description": "When set exclude RoTK2 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK2 as being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK2 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse134-bit-12", + "name": "ROTK3_EX_IMG_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for boot image authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 as being used as root of trust key for boot image authentication" + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for boot image authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-13", + "name": "ROTK3_EX_SB3_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for FW update image (SB3) authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 as being used as root of trust key for FW update image (SB3) authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for FW update image (SB3) authentication." + } + ] + }, + { + "width": 1, + "id": "fuse134-bit-14", + "name": "ROTK3_EX_DBG_AUTH", + "description": "When set exclude RoTK3 from being used as root of trust key for debug authentication.", + "values": [ + { + "name": "Include", + "value": 0, + "description": "Include RoTK3 as being used as root of trust key for debug authentication." + }, + { + "name": "Exclude", + "value": 1, + "description": "Exclude RoTK3 from being used as root of trust key for debug authentication." + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse135", + "name": "CUST_CTR0", + "description": "For customer use", + "index_int": "0x0087", + "shadow_reg_offset_int": "0x021C", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16 + }, + { + "id": "fuse143", + "name": "DCFG_CC_SOCU_AHB", + "description": "DCFG_CC_SOCU_AHB fuse word", + "index_int": "0x008F", + "shadow_reg_offset_int": "0x023C", + "default_value_int": "0x0003", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse143-bits-0-7", + "name": "LC_STATE", + "description": "Life Cycle" + }, + { + "width": 1, + "id": "fuse143-bit-8", + "name": "HIFI4_NIDEN_DIS", + "description": "HiFi4 Non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-9", + "name": "HIFI4_DBGEN_DIS", + "description": "HiFi4 debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-10", + "name": "HIFI1_NIDEN_DIS", + "description": "HiFi1 Non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-11", + "name": "HIFI1_DBGEN_DIS", + "description": "HiFi1 debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-12", + "name": "AHBAP_DBGEN_DIS", + "description": "AHBAP Debug Disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-13", + "name": "AHBAP_SPIDEN_DIS", + "description": "AHBAP Secure non-invasive debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-14", + "name": "EZHV_DBGEN_DIS", + "description": "EZHV debug disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse143-bit-15", + "name": "SOC_CORESIGHT_DIS", + "description": "CoreSight Disable", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 16 + } + ] + } + ] + }, + { + "group": { + "name": "RKTH", + "description": "OEM Root Key Table Hash" + }, + "registers": [ + { + "id": "fuse88", + "name": "ROTKH0", + "description": "Root of trust keys table hash", + "index_int": "0x0058", + "shadow_reg_offset_int": "0x0160", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse88-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse89", + "name": "ROTKH1", + "description": "Root of trust keys table hash", + "index_int": "0x0059", + "shadow_reg_offset_int": "0x0164", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse89-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse90", + "name": "ROTKH2", + "description": "Root of trust keys table hash", + "index_int": "0x005A", + "shadow_reg_offset_int": "0x0168", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse90-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse91", + "name": "ROTKH3", + "description": "Root of trust keys table hash", + "index_int": "0x005B", + "shadow_reg_offset_int": "0x016C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse91-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse92", + "name": "ROTKH4", + "description": "Root of trust keys table hash", + "index_int": "0x005C", + "shadow_reg_offset_int": "0x0170", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse92-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse93", + "name": "ROTKH5", + "description": "Root of trust keys table hash", + "index_int": "0x005D", + "shadow_reg_offset_int": "0x0174", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse93-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse94", + "name": "ROTKH6", + "description": "Root of trust keys table hash", + "index_int": "0x005E", + "shadow_reg_offset_int": "0x0178", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse94-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse95", + "name": "ROTKH7", + "description": "Root of trust keys table hash", + "index_int": "0x005F", + "shadow_reg_offset_int": "0x017C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse95-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse96", + "name": "ROTKH8", + "description": "Root of trust keys table hash", + "index_int": "0x0060", + "shadow_reg_offset_int": "0x0180", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse96-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse97", + "name": "ROTKH9", + "description": "Root of trust keys table hash", + "index_int": "0x0061", + "shadow_reg_offset_int": "0x0184", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse97-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse98", + "name": "ROTKH10", + "description": "Root of trust keys table hash", + "index_int": "0x0062", + "shadow_reg_offset_int": "0x0188", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse98-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + }, + { + "id": "fuse99", + "name": "ROTKH11", + "description": "Root of trust keys table hash", + "index_int": "0x0063", + "shadow_reg_offset_int": "0x018C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse99-bits-0-31", + "name": "ROTKH", + "description": "Root of trust keys table hash" + } + ] + } + ] + }, + { + "group": { + "name": "CUST_MK_SK", + "description": "Customer Master Key Symmetric Key" + }, + "registers": [ + { + "id": "fuse100", + "name": "CUST_MK_SK0", + "description": "Customer MK_SK", + "index_int": "0x0064", + "shadow_reg_offset_int": "0x0190", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse100-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse101", + "name": "CUST_MK_SK1", + "description": "Customer MK_SK", + "index_int": "0x0065", + "shadow_reg_offset_int": "0x0194", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse101-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse102", + "name": "CUST_MK_SK2", + "description": "Customer MK_SK", + "index_int": "0x0066", + "shadow_reg_offset_int": "0x0198", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse102-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse103", + "name": "CUST_MK_SK3", + "description": "Customer MK_SK", + "index_int": "0x0067", + "shadow_reg_offset_int": "0x019C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse103-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse104", + "name": "CUST_MK_SK4", + "description": "Customer MK_SK", + "index_int": "0x0068", + "shadow_reg_offset_int": "0x01A0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse104-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse105", + "name": "CUST_MK_SK5", + "description": "Customer MK_SK", + "index_int": "0x0069", + "shadow_reg_offset_int": "0x01A4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse105-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse106", + "name": "CUST_MK_SK6", + "description": "Customer MK_SK", + "index_int": "0x006A", + "shadow_reg_offset_int": "0x01A8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse106-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse107", + "name": "CUST_MK_SK7", + "description": "Customer MK_SK", + "index_int": "0x006B", + "shadow_reg_offset_int": "0x01AC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse107-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse108", + "name": "CUST_MK_SK8", + "description": "Customer MK_SK", + "index_int": "0x006C", + "shadow_reg_offset_int": "0x01B0", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse108-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse109", + "name": "CUST_MK_SK9", + "description": "Customer MK_SK", + "index_int": "0x006D", + "shadow_reg_offset_int": "0x01B4", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse109-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse110", + "name": "CUST_MK_SK10", + "description": "Customer MK_SK", + "index_int": "0x006E", + "shadow_reg_offset_int": "0x01B8", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse110-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + }, + { + "id": "fuse111", + "name": "CUST_MK_SK11", + "description": "Customer MK_SK", + "index_int": "0x006F", + "shadow_reg_offset_int": "0x01BC", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse111-bits-0-31", + "name": "CUST_MK_SK_BLOB", + "description": "Customer MK_SK" + } + ] + } + ] + }, + { + "group": { + "name": "NS_FW_VER", + "description": "Non-Secure Firmware Version" + }, + "registers": [ + { + "id": "fuse112", + "name": "NS_FW_VER0-CUST_CTR9", + "description": "NS_FW_VER0-CUST_CTR9 fuse word", + "deprecated_names": [ + "NS_FW_VER0" + ], + "index_int": "0x0070", + "shadow_reg_offset_int": "0x01C0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse112-bits-0-15", + "name": "NS_FW_VER[15:0]-CUST_CTR9", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse113", + "name": "NS_FW_VER1-CUST_CTR10", + "description": "NS_FW_VER1-CUST_CTR10 fuse word", + "deprecated_names": [ + "NS_FW_VER1" + ], + "index_int": "0x0071", + "shadow_reg_offset_int": "0x01C4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse113-bits-0-15", + "name": "NS_FW_VER[31:16]-CUST_CTR10", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse114", + "name": "NS_FW_VER2-CUST_CTR11", + "description": "NS_FW_VER2-CUST_CTR11 fuse word", + "deprecated_names": [ + "NS_FW_VER2" + ], + "index_int": "0x0072", + "shadow_reg_offset_int": "0x01C8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse114-bits-0-15", + "name": "NS_FW_VER[47:32]-CUST_CTR11", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse115", + "name": "NS_FW_VER3-CUST_CTR12", + "description": "NS_FW_VER3-CUST_CTR12 fuse word", + "deprecated_names": [ + "NS_FW_VER3" + ], + "index_int": "0x0073", + "shadow_reg_offset_int": "0x01CC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse115-bits-0-15", + "name": "NS_FW_VER[63:48]-CUST_CTR12", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse116", + "name": "NS_FW_VER4-CUST_CTR13", + "description": "NS_FW_VER4-CUST_CTR13 fuse word", + "deprecated_names": [ + "NS_FW_VER4" + ], + "index_int": "0x0074", + "shadow_reg_offset_int": "0x01D0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse116-bits-0-15", + "name": "NS_FW_VER[79:64]-CUST_CTR13", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse117", + "name": "NS_FW_VER5-CUST_CTR14", + "description": "NS_FW_VER5-CUST_CTR14 fuse word", + "deprecated_names": [ + "NS_FW_VER5" + ], + "index_int": "0x0075", + "shadow_reg_offset_int": "0x01D4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse117-bits-0-15", + "name": "NS_FW_VER[95:80]-CUST_CTR14", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse118", + "name": "NS_FW_VER6-CUST_CTR15", + "description": "NS_FW_VER6-CUST_CTR15 fuse word", + "deprecated_names": [ + "NS_FW_VER6" + ], + "index_int": "0x0076", + "shadow_reg_offset_int": "0x01D8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse118-bits-0-15", + "name": "NS_FW_VER[111:96]-CUST_CTR15", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse119", + "name": "NS_FW_VER7-CUST_CTR16", + "description": "NS_FW_VER7-CUST_CTR16 fuse word", + "deprecated_names": [ + "NS_FW_VER7" + ], + "index_int": "0x0077", + "shadow_reg_offset_int": "0x01DC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse119-bits-0-15", + "name": "NS_FW_VER[127:112]-CUST_CTR16", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse120", + "name": "NS_FW_VER8-CUST_CTR17", + "description": "NS_FW_VER8-CUST_CTR17 fuse word", + "deprecated_names": [ + "NS_FW_VER8" + ], + "index_int": "0x0078", + "shadow_reg_offset_int": "0x01E0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse120-bits-0-15", + "name": "NS_FW_VER[143:128]-CUST_CTR17", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse121", + "name": "NS_FW_VER9-CUST_CTR18", + "description": "NS_FW_VER9-CUST_CTR18 fuse word", + "deprecated_names": [ + "NS_FW_VER9" + ], + "index_int": "0x0079", + "shadow_reg_offset_int": "0x01E4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse121-bits-0-15", + "name": "NS_FW_VER[159:144]-CUST_CTR18", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse122", + "name": "NS_FW_VER10-CUST_CTR19", + "description": "NS_FW_VER10-CUST_CTR19 fuse word", + "deprecated_names": [ + "NS_FW_VER10" + ], + "index_int": "0x007A", + "shadow_reg_offset_int": "0x01E8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse122-bits-0-15", + "name": "NS_FW_VER[175:160]-CUST_CTR19", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse123", + "name": "NS_FW_VER11-CUST_CTR20", + "description": "NS_FW_VER11-CUST_CTR20 fuse word", + "deprecated_names": [ + "NS_FW_VER11" + ], + "index_int": "0x007B", + "shadow_reg_offset_int": "0x01EC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse123-bits-0-15", + "name": "NS_FW_VER[191:176]-CUST_CTR20", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse124", + "name": "NS_FW_VER12-CUST_CTR21", + "description": "NS_FW_VER12-CUST_CTR21 fuse word", + "deprecated_names": [ + "NS_FW_VER12" + ], + "index_int": "0x007C", + "shadow_reg_offset_int": "0x01F0", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse124-bits-0-15", + "name": "NS_FW_VER[207:192]-CUST_CTR21", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse125", + "name": "NS_FW_VER13-CUST_CTR22", + "description": "NS_FW_VER13-CUST_CTR22 fuse word", + "deprecated_names": [ + "NS_FW_VER13" + ], + "index_int": "0x007D", + "shadow_reg_offset_int": "0x01F4", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse125-bits-0-15", + "name": "NS_FW_VER[223:208]-CUST_CTR22", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse126", + "name": "NS_FW_VER14-CUST_CTR23", + "description": "NS_FW_VER14-CUST_CTR23 fuse word", + "deprecated_names": [ + "NS_FW_VER14" + ], + "index_int": "0x007E", + "shadow_reg_offset_int": "0x01F8", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse126-bits-0-15", + "name": "NS_FW_VER[239:224]-CUST_CTR23", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version/For customer use" + } + ] + }, + { + "id": "fuse127", + "name": "NS_FW_VER15-CUST_CTR24", + "description": "NS_FW_VER15-CUST_CTR24 fuse word", + "deprecated_names": [ + "NS_FW_VER15" + ], + "index_int": "0x007F", + "shadow_reg_offset_int": "0x01FC", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse127-bits-0-15", + "name": "NS_FW_VER[255:240]-CUST_CTR24", + "deprecated_names": [ + "NS_FW_VER" + ], + "description": "Non-Secure firmware version-For customer use" + } + ] + } + ] + }, + { + "group": { + "name": "SEC_FW_VER", + "description": "Secure Firmware Version" + }, + "registers": [ + { + "id": "fuse128", + "name": "SEC_FW_VER0", + "description": "SEC_FW_VER0 fuse word", + "index_int": "0x0080", + "shadow_reg_offset_int": "0x0200", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse128-bits-0-15", + "name": "SEC_FW_VER", + "description": "Secure firmware version" + } + ] + }, + { + "id": "fuse129", + "name": "SEC_FW_VER1", + "description": "SEC_FW_VER1 fuse word", + "index_int": "0x0081", + "shadow_reg_offset_int": "0x0204", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse129-bits-0-15", + "name": "SEC_FW_VER", + "description": "Secure firmware version" + } + ] + }, + { + "id": "fuse130", + "name": "SEC_FW_VER2", + "description": "SEC_FW_VER2 fuse word", + "index_int": "0x0082", + "shadow_reg_offset_int": "0x0208", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse130-bits-0-15", + "name": "SEC_FW_VER", + "description": "Secure firmware version" + } + ] + }, + { + "id": "fuse131", + "name": "SEC_FW_VER3", + "description": "SEC_FW_VER3 fuse word", + "index_int": "0x0083", + "shadow_reg_offset_int": "0x020C", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse131-bits-0-15", + "name": "SEC_FW_VER", + "description": "Secure firmware version" + } + ] + } + ] + }, + { + "group": { + "name": "Boot configuration", + "description": "Boot configuration" + }, + "registers": [ + { + "id": "fuse136", + "name": "BOOT_CFG0", + "description": "BOOT_CFG0 fuse word", + "index_int": "0x0088", + "shadow_reg_offset_int": "0x0220", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 2, + "id": "fuse136-bits-0-1", + "name": "BOOT_SRC", + "description": "Specify the boot source", + "values": [ + { + "name": "ISP pins", + "value": 0, + "description": "ISP pins determine the source" + }, + { + "name": "XSPI NOR flash", + "value": 1, + "description": "XSPI NOR flash" + }, + { + "name": "uSDHC flash", + "value": 2, + "description": "uSDHC flash" + }, + { + "name": "XSPI NAND flash", + "value": 3, + "description": "XSPI NAND flash" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-2", + "name": "BOOT_IF_INST", + "description": "Specify boot interface instance when XSPI or uSDHC is selected as boot source.", + "values": [ + { + "name": "Instance 0", + "value": 0, + "description": "Instance 0 (XSPI0 or uSDHC0)" + }, + { + "name": "Instance 1", + "value": 1, + "description": "Instance 1 (XSPI1 or uSDHC1)" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-3", + "name": "ISP_UART_DIS", + "description": "Disable LPUART interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-4", + "name": "ISP_SPI_DIS", + "description": "Disable LPSPI interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-5", + "name": "ISP_I2C_DIS", + "description": "Disable LPI2C interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-6", + "name": "ISP_USB_DIS", + "description": "Disable HS USB (USB0) interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-7", + "name": "ISP_eUSB_DIS", + "description": "Disable eUSB (USB1) interface during ISP/serial boot mode.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-8", + "name": "ISP_MODE_PIN_DIS", + "description": "Disable boot mode selection using ISP mode pins.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-9", + "name": "ISP_DM_DIS", + "description": "Disable ISP mode entry through debug mailbox command.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-10", + "name": "ISP_FT_DIS", + "description": "Disable ISP mode entry as a fall through if valid image is not found in boot media.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-11", + "name": "ISP_API_DIS", + "description": "Disable ISP mode entry using ROM API.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 2, + "id": "fuse136-bits-12-13", + "name": "BOOT_SPEED", + "description": "System clock speed during boot.", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal boot (192 MHz) - VDD2 = 1.0 V" + }, + { + "name": "High", + "value": 1, + "description": "High speed boot (300 MHz) - VDD2 = 1.1 V" + }, + { + "name": "Low", + "value": 2, + "description": "Low speed boot (32 MHz) -VDD2 = 1.0 V" + }, + { + "name": "Middle", + "value": 3, + "description": "Middle speed boot (192 MHz) - VDD2 = 1.0 V" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-14", + "name": "FA_CMD_DIS", + "description": "Controls whether DM-AP set FA mode command can be issued after authentication.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse136-bit-15", + "name": "NXP_FW_DIS", + "description": "Disable loading NXP signed SB3 files.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + } + ] + }, + { + "id": "fuse137", + "name": "BOOT_CFG1", + "description": "BOOT_CFG1 fuse word", + "index_int": "0x0089", + "shadow_reg_offset_int": "0x0224", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse137-bit-0", + "name": "ENF_SEC_BOOT", + "description": "Enforce secure boot.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Image header define boot" + }, + { + "name": "1", + "value": 1, + "description": "Enforce secure boot" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-1", + "name": "ENF_CNSA", + "description": "Enforce CNSA suite defined crypto algorithms for secure boot, update and debug features.", + "values": [ + { + "name": "0", + "value": 0, + "description": "ECDSA P-256, SHA256, AES128" + }, + { + "name": "1", + "value": 1, + "description": "ECDSA P-384, SHA384, AES256" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-2", + "name": "ENF_TZM_PRESET", + "description": "Enforce TZM preset data. If absent image is deemed corrupted.", + "values": [ + { + "name": "0", + "value": 0, + "description": "TZM data is optional;" + }, + { + "name": "1", + "value": 1, + "description": "Image should contain TZM data" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-3", + "name": "REC_BOOT_EN", + "description": "Enable recovery boot through LP_FLEXCOM.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse137-bit-5", + "name": "DIS_XSPI_XIP", + "description": "Disable XIP image execution through XIP flash interfaces.", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-6", + "name": "DICE_SKIP", + "description": "Skip DICE CDI calculation during boot to reduce boot time.", + "values": [ + { + "name": "DICE enabled", + "value": 0, + "description": "DICE enabled" + }, + { + "name": "DICE disabled", + "value": 1, + "description": "DICE disabled" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-7", + "name": "DICE_INC_NXP", + "description": "When set include NXP configuration fuse data in CDI calculations.", + "values": [ + { + "name": "Not include", + "value": 0, + "description": "Not include NXP configuration" + }, + { + "name": "Include", + "value": 1, + "description": "Include NXP configuration" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-8", + "name": "DICE_INC_CUST", + "description": "When set include customer boot configuration fuse data in CDI calculations.", + "values": [ + { + "name": "Not include", + "value": 0, + "description": "Not include customer boot configuration" + }, + { + "name": "Include", + "value": 1, + "description": "Include customer boot configuration" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-9", + "name": "FIPS_PUF_EN", + "description": "Enable self-test of PUF IP before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-10", + "name": "FIPS_KDF_EN", + "description": "Enable FIPS self-test of CKDF and CMAC algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-11", + "name": "FIPS_HMAC_EN", + "description": "Enable FIPS self-test of HMAC algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-12", + "name": "FIPS_DRBG_EN", + "description": "Enable FIPS self-test of DRBG algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-13", + "name": "FIPS_ECDSA_EN", + "description": "Enable FIPS self-test of ECDSA algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-14", + "name": "FIPS_AES_EN", + "description": "Enable FIPS self-test of AES algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse137-bit-15", + "name": "FIPS_SHA2_EN", + "description": "Enable FIPS self-test of SHA2 algorithm before usage during boot.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + } + ] + }, + { + "id": "fuse138", + "name": "BOOT_CFG2", + "description": "BOOT_CFG2 fuse word", + "index_int": "0x008A", + "shadow_reg_offset_int": "0x0228", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse138-bit-0", + "name": "XSPI_NOR_RESET_TYPE_SOFT_EN", + "description": "Enable to send 6699 reset sequence before XSPI boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse138-bit-1", + "name": "IPED_CTX_EN", + "description": "Default IPED configuration are generated from fuse word 144 to 151", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse138-bit-2", + "name": "XSPI_NOR_RDP_EN", + "description": "Enable to release the NOR flash from Deep Power-down mode. It will send ABh before XSPI NOR boot", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse138-bit-3", + "name": "XSPI_CACHE64_EN", + "description": "Enable the pSRAM cache", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse138-bit-5", + "name": "DCFG_UUID", + "description": "Enable UUID matching check during Debug Credential (DC) validation.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse138-bit-6", + "name": "XSPI_DQS_INTERNAL_LOOPBACK_EN", + "description": "Enable to use internal loopback DQS as XSPI read clock ", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse138-bit-7", + "name": "IPED1_XEX_EN", + "description": "Enable XEX mode for all IPED1 regions.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 4, + "id": "fuse138-bits-8-11", + "name": "IPED0_LOCK_CTX", + "description": "Lock the corresponding IPED0 context.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock" + } + ] + }, + { + "width": 4, + "id": "fuse138-bits-12-15", + "name": "IPED1_LOCK_CTX", + "description": "Lock the corresponding IPED1 context.", + "values": [ + { + "name": "Unlock", + "value": 0, + "description": "Unlock" + }, + { + "name": "Lock", + "value": 1, + "description": "Lock" + } + ] + } + ] + }, + { + "id": "fuse139", + "name": "BOOT_CFG3", + "description": "BOOT_CFG3 (IPED CTX mode) fuse word", + "index_int": "0x008B", + "shadow_reg_offset_int": "0x022C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 4, + "id": "fuse139-bits-0-3", + "name": "IPED0_GCM_CTX", + "description": "Enable GCM mode for corresponding IPED0 context.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 4, + "id": "fuse139-bits-4-7", + "name": "IPED0_GCM_AHBERR_CTX", + "description": "Enable AHB error on GCM tag failure for corresponding IPED0 context.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 4, + "id": "fuse139-bits-8-11", + "name": "IPED1_GCM_CTX", + "description": "Enable GCM mode for corresponding IPED1 context.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 4, + "id": "fuse139-bits-12-15", + "name": "IPED1_GCM_AHBERR_CTX", + "description": "Enable AHB error on GCM tag failure for corresponding IPED1 context.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + } + ] + }, + { + "id": "fuse140", + "name": "BOOT_CFG4", + "description": "BOOT_CFG4 fuse word", + "index_int": "0x008C", + "shadow_reg_offset_int": "0x0230", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse140-bit-0", + "name": "BOOT_RETRY_FAIL_LED_PIN_EN", + "description": "Boot Retry fail LED enable bit. ROM sets this GPIO after exhausting boot retry count.", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-1", + "name": "BOOT_RETRY_FAIL_LED_PIN_POL", + "description": "Output polarity. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-2-4", + "name": "BOOT_RETRY_FAIL_LED_PIN_PORT", + "description": "GPIO port. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-5-9", + "name": "BOOT_RETRY_FAIL_LED_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if BOOT_RETRY_FAIL_LED_PIN_EN is set.\nxd - GPIO pin x." + }, + { + "width": 1, + "id": "fuse140-bit-10", + "name": "SENSOR_RESET_LED_PIN_EN", + "description": "Sensor Reset LED enable bit. ROM sets this GPIO when last warm reset cause is detected as ITRC reset.", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-11", + "name": "SENSOR_RESET_LED_PIN_POL", + "description": "Output polarity. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-12-14", + "name": "SENSOR_RESET_LED_PIN_PORT", + "description": "GPIO port. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-15-19", + "name": "SENSOR_RESET_LED_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if SENSOR_RESET_LED_PIN_EN is set.\nxd - GPIO pin x." + }, + { + "width": 1, + "id": "fuse140-bit-20", + "name": "ISP_REC_LED_PIN_EN", + "description": "LED enable bit. ROM sets this GPIO whenever boot image is not found in boot media and before entering ISP or recovery boot mode. Output polarity. ", + "values": [ + { + "name": "Disabled", + "value": 0, + "description": "Disabled" + }, + { + "name": "Enabled", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse140-bit-21", + "name": "ISP_REC_LED_PIN_POL", + "description": "Output polarity. Output polarity. This field is valid only if ISP_REC_LED_PIN_EN is set.", + "values": [ + { + "name": "High", + "value": 0, + "description": "Output high" + }, + { + "name": "Low", + "value": 1, + "description": "Output low" + } + ] + }, + { + "width": 3, + "id": "fuse140-bits-22-24", + "name": "ISP_REC_LED_PIN_PORT", + "description": "GPIO port. This field is valid only if ISP_REC_LED_PIN_EN is set.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse140-bits-25-29", + "name": "ISP_REC_LED_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if ISP_REC_LED_PIN_EN is set.\nxd - GPIO pin x." + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse141", + "name": "BOOT_CFG5", + "description": "BOOT_CFG5 fuse word", + "index_int": "0x008D", + "shadow_reg_offset_int": "0x0234", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse141-bits-0-7", + "name": "WDOG_TIMEOUT_10MS", + "description": "A 10 ms timer started before jumping to user application.\nnd - n x 10 ms" + }, + { + "width": 8, + "id": "fuse141-bits-8-15", + "name": "POWERDOWN_TIMEOUT_SECS", + "description": "Device enters deep-power down state if it idles beyond this time during ISP command handling loop.\nnd - n x 1 s" + }, + { + "width": 4, + "id": "fuse141-bits-16-19", + "name": "REC_BOOT_FC", + "description": "Specifies the LP_FLEXCOMM connected to 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.\nxd - LP_FLEXCOMMx is selected, x = 0-13" + }, + { + "width": 2, + "id": "fuse141-bits-20-21", + "name": "REC_BOOT_FC_PCS", + "description": "Specifies LP_FLEXCOMM PCS connected to 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.", + "values": [ + { + "name": "PCS0", + "value": 0, + "description": "PCS0" + }, + { + "name": "PCS1", + "value": 1, + "description": "PCS1" + }, + { + "name": "PCS2", + "value": 2, + "description": "PCS2" + }, + { + "name": "PCS3", + "value": 3, + "description": "PCS3" + } + ] + }, + { + "width": 2, + "id": "fuse141-bits-22-23", + "name": "REC_BOOT_FC_BAUDRATE", + "description": "Specifies LP_FLEXCOMM baudrate with 1-bit SPI flash used for recovery boot. This field is valid only if REC_BOOT_EN is set.", + "values": [ + { + "name": "20 MHz", + "value": 0, + "description": "20 MHz" + }, + { + "name": "10 MHz", + "value": 1, + "description": "10 MHz" + }, + { + "name": "5 MHz", + "value": 2, + "description": "5 MHz" + }, + { + "name": "2 MHz", + "value": 3, + "description": "2 MHz" + } + ] + }, + { + "width": 2, + "id": "fuse141-bits-24-25", + "name": "XTAL_FREQ", + "description": "Specifies external XTAL frequency", + "values": [ + { + "name": "24 MHz", + "value": 0, + "description": "24 MHz" + }, + { + "name": "30 MHz", + "value": 1, + "description": "30 MHz" + }, + { + "name": "32 MHz", + "value": 2, + "description": "32 MHz" + }, + { + "name": "19.2 MHz", + "value": 3, + "description": "19.2 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse141-bit-26", + "name": "OSC_HIGH_GAIN_MODE", + "description": "Specifies power mode of external XTAL", + "values": [ + { + "name": "Low power mode", + "value": 0, + "description": "Low power mode." + }, + { + "name": "High gain mode", + "value": 1, + "description": "High gain mode" + } + ] + }, + { + "width": 5, + "id": "fuse141-bits-27-31", + "name": "OSC_SETTLING_TIME", + "description": "Specifies the settling time of OSC\n0d - 390 \u03bcs (default)\nnd - n \u00d7 100 \u03bcs \u00d7 1.3" + } + ] + }, + { + "id": "fuse142", + "name": "BOOT_CFG6", + "description": "BOOT_CFG6 fuse word", + "index_int": "0x008E", + "shadow_reg_offset_int": "0x0238", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse142-bits-0-15", + "name": "USB_VID", + "description": "USB Vendor ID" + }, + { + "width": 16, + "id": "fuse142-bits-16-31", + "name": "USB_PID", + "description": "USB Product ID" + } + ] + }, + { + "id": "fuse160", + "name": "BOOT_CFG8", + "description": "BOOT_CFG8 fuse word", + "index_int": "0x00A0", + "shadow_reg_offset_int": "0x0280", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 8 + }, + { + "width": 1, + "id": "fuse160-bit-8", + "name": "DBG_OVER_USB_DIS", + "description": "Disable debug over USB0 pins. ", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse160-bit-9", + "name": "DBG_OVER_USB_LOCK", + "description": "Enable debug over USB register write lock. ", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "fuse160-bits-10-12", + "name": "DBG_OVER_USB_SEL_PORT", + "description": "Defines which GPIO port is selected to enable debug over USB0 pins feature.\nxd - GPIO port x" + }, + { + "width": 5, + "id": "fuse160-bits-13-17", + "name": "DBG_OVER_USB_SEL_GPIO", + "description": "Defines which GPIO pin is selected to enable debug over USB0 pins feature.\nxd - GPIO pin x" + }, + { + "width": 7, + "id": "fuse160-bits-18-24", + "name": "LPI2C_ADDRESS", + "description": "If 00h, defaults to 10h for LPI2C target address.\nIf not 00h, use this value as the 7-bit LPI2C target address" + }, + { + "width": 7, + "id": "fuse160-bits-25-31", + "name": "USBPLL_LOCK_TIME", + "description": "Specifies the lock time of USB PLL\n0d - 30 \u00b5s (default)\nnd - n \u00d7 10 \u00b5s" + } + ] + }, + { + "id": "fuse161", + "name": "OTP_XSPI_NAND_CFG9", + "description": "OTP_XSPI_NAND_CFG9 fuse word", + "index_int": "0x00A1", + "shadow_reg_offset_int": "0x0284", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse161-bit-0", + "name": "XSPI_NAND_SEARCH_CNT", + "description": "0b - Search at most 1 block (for BCB)", + "values": [ + { + "name": "0", + "value": 0, + "description": "Search at most 1 block (for BCB)" + }, + { + "name": "1", + "value": 1, + "description": "Search at most 2 blocks" + } + ] + }, + { + "width": 1, + "id": "fuse161-bit-1", + "name": "XSPI_NAND_COL_ADDR_WIDTH", + "description": "0b - 11 bits (for 2 KB-page devices)", + "values": [ + { + "name": "11 bits", + "value": 0, + "description": "11 bits (for 2 KB-page devices)" + }, + { + "name": "12 bits", + "value": 1, + "description": "12 bits (for 4 KB-page devices)" + } + ] + }, + { + "width": 2, + "id": "fuse161-bits-2-3", + "name": "XSPI_NAND_CS_INTERVAL", + "description": "CS de-asserted interval between two commands", + "values": [ + { + "name": "100 ns", + "value": 0, + "description": "100 ns" + }, + { + "name": "200 ns", + "value": 1, + "description": "200 ns" + }, + { + "name": "400 ns", + "value": 2, + "description": "400 ns" + }, + { + "name": "50 ns", + "value": 3, + "description": "50 ns" + } + ] + }, + { + "width": 2, + "id": "fuse161-bits-4-5", + "name": "XSPI_NAND_SEARCH_STRIDE", + "description": "BCB search step/stride, aligned with block size", + "values": [ + { + "name": "64 pages", + "value": 0, + "description": "64 pages" + }, + { + "name": "128 pages", + "value": 1, + "description": "128 pages" + }, + { + "name": "256 pages", + "value": 2, + "description": "256 pages" + }, + { + "name": "32 pages", + "value": 3, + "description": "32 pages" + } + ] + }, + { + "width": 2, + "id": "fuse161-bits-6-7", + "name": "XSPI_NAND_HOLD_TIME", + "description": "Hold time before interaction with NAND", + "values": [ + { + "name": "00", + "value": 0, + "description": "Wait until NAND is idle (by polling NAND's status register)" + }, + { + "name": "500 us", + "value": 1, + "description": "500 us" + }, + { + "name": "1 ms", + "value": 2, + "description": "1 ms" + }, + { + "name": "3 ms", + "value": 3, + "description": "3 ms" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse161-bits-10-11", + "name": "XSPI_NAND_RESET_TYPE", + "description": "00b - No reset before interaction with NAND", + "values": [ + { + "name": "00", + "value": 0, + "description": "No reset before interaction with NAND" + }, + { + "name": "01", + "value": 1, + "description": "Reset the NAND with FFh" + }, + { + "name": "10", + "value": 2, + "description": "Reset the NAND with 66h, 99h" + }, + { + "name": "11", + "value": 3, + "description": "Reset the NAND with dedicated reset pin" + } + ] + }, + { + "width": 4 + }, + { + "width": 3, + "id": "fuse161-bits-16-18", + "name": "XSPI_NAND_FREQ", + "description": "000b - 80 MHz ", + "values": [ + { + "name": "80 MHz", + "value": 0, + "description": "80 MHz" + }, + { + "name": "100 MHz", + "value": 1, + "description": "100 MHz" + }, + { + "name": "120 MHz", + "value": 2, + "description": "120 MHz" + }, + { + "name": "133 MHz", + "value": 3, + "description": "133 MHz" + }, + { + "name": "166 MHz", + "value": 4, + "description": "166 MHz" + }, + { + "name": "200 MHz", + "value": 5, + "description": "200 MHz" + }, + { + "name": "60 MHz", + "value": 6, + "description": "60 MHz" + }, + { + "name": "30 MHz", + "value": 7, + "description": "30 MHz" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "fuse161-bits-21-22", + "name": "XSPI_PAGES_PER_BLOCK", + "description": "00b - 64 Pages", + "values": [ + { + "name": "64 Pages", + "value": 0, + "description": "64 Pages" + }, + { + "name": "128 Pages", + "value": 1, + "description": "128 Pages" + }, + { + "name": "256 Pages", + "value": 2, + "description": "256 Pages" + }, + { + "name": "32 Pages", + "value": 3, + "description": "32 Pages" + } + ] + }, + { + "width": 1 + }, + { + "width": 8, + "id": "fuse161-bits-24-31", + "name": "XSPI_FEATURE_CONFIG", + "description": "Used for loading the arguments/parameters for device configuration commands\nbit 0 - For Micron memory, it must be configured as 0b to disable continue read mode; for Macronix or Winbond memory, it must be configured as 1b to enable quad mode.\nbit 3 - For Winbond memory, it must be configured as 1b to enable buffer mode.\nbit 4 - Must be configured as 1b to enable error code correction\nOthers - Reserved" + } + ] + }, + { + "id": "fuse162", + "name": "BOOT_CFG10", + "description": "BOOT_CFG10 fuse word", + "index_int": "0x00A2", + "shadow_reg_offset_int": "0x0288", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse162-bits-0-3", + "name": "XSPI_CFG_ERASE_SZ", + "description": "Erase size for configuration pages. \nnd - Erase size 2(n+8) bytes" + }, + { + "width": 15, + "id": "fuse162-bits-4-18", + "name": "XSPI_STATIC_CFG_OFFSET", + "description": "Offset expressed as multiple of 4 KB from where configuration pages/sectors start. Maximum memory mapped XSPI space is 128 MB hence 10 bit field.\nXSPI_STATIC_CFG_ADDR = 0800_0000h + (XSPI_STATIC_CFG_OFFSET x 4096)" + }, + { + "width": 9, + "id": "fuse162-bits-19-27", + "name": "IMAGE0_OFFSET", + "description": "Offset expressed as multiple of 4 KB from where configuration pages/sectors start." + }, + { + "width": 1, + "id": "fuse162-bit-28", + "name": "XSPI_ARB_NS_FW_VER", + "description": "Field determines which firmware version counter should be used for anti-rollback checking of dynamic configuration pages.", + "values": [ + { + "name": "0", + "value": 0, + "description": "Use OTP_SEC_FW_VERSION (up to 63)" + }, + { + "name": "1", + "value": 1, + "description": "Use OTP_NS_FW_VERSION (up to 255)" + } + ] + }, + { + "width": 3 + } + ] + } + ] + }, + { + "group": { + "name": "PRINCE", + "description": "PRINCE IPED configuration" + }, + "registers": [ + { + "id": "fuse144", + "name": "XSPI0_IPED_CTX0", + "description": "XSPI0_IPED_CTX0 fuse word", + "index_int": "0x0090", + "shadow_reg_offset_int": "0x0240", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse144-bits-0-15", + "name": "XSPI0_START_OFFSET_0", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse144-bits-16-31", + "name": "XSPI0_LENGTH_0", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse145", + "name": "XSPI0_IPED_CTX1", + "description": "XSPI0_IPED_CTX1 fuse word", + "index_int": "0x0091", + "shadow_reg_offset_int": "0x0244", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse145-bits-0-15", + "name": "XSPI0_START_OFFSET_1", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse145-bits-16-31", + "name": "XSPI0_LENGTH_1", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse146", + "name": "XSPI0_IPED_CTX2", + "description": "XSPI0_IPED_CTX2 fuse word", + "index_int": "0x0092", + "shadow_reg_offset_int": "0x0248", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse146-bits-0-15", + "name": "XSPI0_START_OFFSET_2", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse146-bits-16-31", + "name": "XSPI0_LENGTH_2", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse147", + "name": "XSPI0_IPED_CTX3", + "description": "XSPI0_IPED_CTX3 fuse word", + "index_int": "0x0093", + "shadow_reg_offset_int": "0x024C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse147-bits-0-15", + "name": "XSPI0_START_OFFSET_3", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse147-bits-16-31", + "name": "XSPI0_LENGTH_3", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse148", + "name": "XSPI1_IPED_CTX0", + "description": "XSPI1_IPED_CTX0 fuse word", + "index_int": "0x0094", + "shadow_reg_offset_int": "0x0250", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse148-bits-0-15", + "name": "XSPI1_START_OFFSET_0", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse148-bits-16-31", + "name": "XSPI1_LENGTH_0", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse149", + "name": "XSPI1_IPED_CTX1", + "description": "XSPI1_IPED_CTX1 fuse word", + "index_int": "0x0095", + "shadow_reg_offset_int": "0x0254", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse149-bits-0-15", + "name": "XSPI1_START_OFFSET_1", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse149-bits-16-31", + "name": "XSPI1_LENGTH_1", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse150", + "name": "XSPI1_IPED_CTX2", + "description": "XSPI1_IPED_CTX2 fuse word", + "index_int": "0x0096", + "shadow_reg_offset_int": "0x0258", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse150-bits-0-15", + "name": "XSPI1_START_OFFSET_2", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse150-bits-16-31", + "name": "XSPI1_LENGTH_2", + "description": "LENGTH (4 KB block counts)" + } + ] + }, + { + "id": "fuse151", + "name": "XSPI1_IPED_CTX3", + "description": "XSPI1_IPED_CTX3 fuse word", + "index_int": "0x0097", + "shadow_reg_offset_int": "0x025C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse151-bits-0-15", + "name": "XSPI1_START_OFFSET_3", + "description": "START_OFFSET (4 KB aligned)" + }, + { + "width": 16, + "id": "fuse151-bits-16-31", + "name": "XSPI1_LENGTH_3", + "description": "LENGTH (4 KB block counts)" + } + ] + } + ] + }, + { + "group": { + "name": "XSPI", + "description": "XSPI configuration" + }, + "registers": [ + { + "id": "fuse152", + "name": "XSPI_CFG0", + "description": "XSPI_CFG0 fuse word", + "index_int": "0x0098", + "shadow_reg_offset_int": "0x0260", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse152-bit-0", + "name": "XSPI_FLASH_AUTO_PROBE_EN", + "description": "Quad SPI or Octal SPI flash memory auto-probe feature enable", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-1-3", + "name": "XSPI_FLASH_PROBE_TYPE", + "description": "Quad SPI or Octal SPI flash memory probe type", + "values": [ + { + "name": "000", + "value": 0, + "description": "Quad SPI NOR flash memory" + }, + { + "name": "001", + "value": 1, + "description": "Macronix Octal flash memory" + }, + { + "name": "010", + "value": 2, + "description": "Micron Octal flash memory" + }, + { + "name": "011", + "value": 3, + "description": "Adesto Octal flash memory" + }, + { + "name": "Octal SDR", + "value": 4, + "description": "Octal SDR" + }, + { + "name": "Octal DDR", + "value": 5, + "description": "Octal DDR" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-4-6", + "name": "XSPI_FLASH_TYPE", + "description": "Typical serial NOR flash memory types", + "values": [ + { + "name": "000", + "value": 0, + "description": "Quad SPI flash memory address (by default, the chip supports 3B read)" + }, + { + "name": "010", + "value": 2, + "description": "HyperFlash 1.8 V" + }, + { + "name": "011", + "value": 3, + "description": "HyperFlash 3.3 V" + }, + { + "name": "MXIC Octal DDR", + "value": 4, + "description": "MXIC Octal DDR" + }, + { + "name": "101", + "value": 5, + "description": "Micron Octal DDR" + } + ] + }, + { + "width": 4, + "id": "fuse152-bits-7-10", + "name": "XSPI_FLASH_DUMMY_CYCLES", + "description": "Together with XSPI_FLASH_DUMMY_CYCLES_UPPER, the 6-bit field configures Quad SPI or Octal SPI dummy cycles for read command", + "values": [ + { + "name": "000000", + "value": 0, + "description": "Dummy cycles probed automatically" + }, + { + "name": "0001", + "value": 1, + "description": "Number of dummy cycles" + }, + { + "name": "0010", + "value": 2, + "description": "Number of dummy cycles" + }, + { + "name": "0011", + "value": 3, + "description": "Number of dummy cycles" + }, + { + "name": "0100", + "value": 4, + "description": "Number of dummy cycles" + }, + { + "name": "0101", + "value": 5, + "description": "Number of dummy cycles" + }, + { + "name": "0110", + "value": 6, + "description": "Number of dummy cycles" + }, + { + "name": "0111", + "value": 7, + "description": "Number of dummy cycles" + }, + { + "name": "1000", + "value": 8, + "description": "Number of dummy cycles" + }, + { + "name": "1001", + "value": 9, + "description": "Number of dummy cycles" + }, + { + "name": "1010", + "value": 10, + "description": "Number of dummy cycles" + }, + { + "name": "1011", + "value": 11, + "description": "Number of dummy cycles" + }, + { + "name": "1100", + "value": 12, + "description": "Number of dummy cycles" + }, + { + "name": "1101", + "value": 13, + "description": "Number of dummy cycles" + }, + { + "name": "1110", + "value": 14, + "description": "Number of dummy cycles" + }, + { + "name": "1111", + "value": 15, + "description": "Number of dummy cycles" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-11-13", + "name": "XSPI_FLASH_BOOT_FREQ", + "description": "Quad SPI or Octal SPI flash interface frequency", + "values": [ + { + "name": "80 MHz", + "value": 0, + "description": "80 MHz" + }, + { + "name": "60 MHz", + "value": 1, + "description": "60 MHz" + }, + { + "name": "50 MHz", + "value": 2, + "description": "50 MHz" + }, + { + "name": "100 MHz", + "value": 3, + "description": "100 MHz" + }, + { + "name": "120 MHz", + "value": 4, + "description": "120 MHz" + }, + { + "name": "133 MHz", + "value": 5, + "description": "133 MHz" + }, + { + "name": "166 MHz", + "value": 6, + "description": "166 MHz" + }, + { + "name": "200 MHz", + "value": 7, + "description": "200 MHz" + } + ] + }, + { + "width": 1, + "id": "fuse152-bit-14", + "name": "XSPI_RESET_PIN_EN", + "description": "Enable to reset flash memory by reset pin or JEDEC", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "Enable", + "value": 1, + "description": "Enable" + } + ] + }, + { + "width": 1, + "id": "fuse152-bit-15", + "name": "XSPI_NOR_RESET_TYPE", + "description": "This field is valid only if XSPI_RESET_PIN_EN is set.", + "values": [ + { + "name": "Pin reset", + "value": 0, + "description": "Pin reset" + }, + { + "name": "JEDEC reset", + "value": 1, + "description": "JEDEC reset" + } + ] + }, + { + "width": 3, + "id": "fuse152-bits-16-18", + "name": "XSPI_RESET_PIN_PORT", + "description": "GPIO port number. This field is valid only if XSPI_RESET_PIN_EN is set." + }, + { + "width": 5, + "id": "fuse152-bits-19-23", + "name": "XSPI_RESET_PIN_GPIO", + "description": "GPIO pin number. This field is valid only if XSPI_RESET_PIN_EN is set." + }, + { + "width": 2, + "id": "fuse152-bits-24-25", + "name": "XSPI_HOLD_TIME", + "description": "Wait time before accessing serial flash memory", + "values": [ + { + "name": "500 us", + "value": 0, + "description": "500 us" + }, + { + "name": "1 ms", + "value": 1, + "description": "1 ms" + }, + { + "name": "3 ms", + "value": 2, + "description": "3 ms" + }, + { + "name": "10 ms", + "value": 3, + "description": "10 ms" + } + ] + }, + { + "width": 4, + "id": "fuse152-bits-26-29", + "name": "XSPI_PWR_HOLD_TIME", + "description": "Delay (wait time) after POR before accessing Quad SPI or Octal SPI flash memory devices, in addition to the delay that the XSPI_HOLD_TIME field specifies", + "values": [ + { + "name": "No delay", + "value": 0, + "description": "No delay" + }, + { + "name": "0001", + "value": 1, + "description": "Additional 100 us" + }, + { + "name": "0010", + "value": 2, + "description": "Additional 500 us" + }, + { + "name": "Additional 1 ms", + "value": 3, + "description": "Additional 1 ms" + }, + { + "name": "0100", + "value": 4, + "description": "Additional 10 ms" + }, + { + "name": "0101", + "value": 5, + "description": "Additional 20 ms" + }, + { + "name": "0110", + "value": 6, + "description": "Additional 40 ms" + }, + { + "name": "0111", + "value": 7, + "description": "Additional 60 ms" + }, + { + "name": "1000", + "value": 8, + "description": "Additional 80 ms" + }, + { + "name": "1001", + "value": 9, + "description": "Additional 100 ms" + }, + { + "name": "1010", + "value": 10, + "description": "Additional 120 ms" + }, + { + "name": "1011", + "value": 11, + "description": "Additional 140 ms" + }, + { + "name": "1100", + "value": 12, + "description": "Additional 160 ms" + }, + { + "name": "1101", + "value": 13, + "description": "Additional 180 ms" + }, + { + "name": "1110", + "value": 14, + "description": "Additional 200 ms" + }, + { + "name": "1111", + "value": 15, + "description": "Additional 220 ms" + } + ] + }, + { + "width": 2, + "id": "fuse152-bits-30-31", + "name": "XSPI_FLASH_DUMMY_CYCLES_UPPER", + "description": "Quad/Octal-SPI dummy cycles upper 2 bits for read command. See XSPI_FLASH_DUMMY_CYCLES" + } + ] + }, + { + "id": "fuse153", + "name": "XSPI_CFG1", + "description": "XSPI_CFG1 fuse word", + "index_int": "0x0099", + "shadow_reg_offset_int": "0x0264", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 7, + "id": "fuse153-bits-0-6", + "name": "XSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for flash read sampling via external DQS\n0 - Use the delay cell value calculated by ROM\nOthers - Use the delay cell value in terms of 100 ps" + }, + { + "width": 10, + "id": "fuse153-bits-7-16", + "name": "XSPI_FLASH_SEC_IMAGE_OFFSET", + "description": "Offset of the second image\nxd - x multiplied by 128 KB" + }, + { + "width": 7, + "id": "fuse153-bits-17-23", + "name": "XSPI_FLASH_IMAGE_SIZE", + "description": "Size of the second image\n0d - Same size as the image offset (XSPI_IMAGE_OFFSET)\n1d - 128 KB\n2d - 256 KB\nmd - m \u00d7 128 KB (m = 3-7)\n8d - 1 MB\nnd - (n-7) \u00d7 1 MB (n = 8-71)" + }, + { + "width": 3, + "id": "fuse153-bits-24-26", + "name": "XSPI_FLASH_ENHANCE_MODE", + "description": "XSPI enhance mode", + "values": [ + { + "name": "Disable", + "value": 0, + "description": "Disable" + }, + { + "name": "101", + "value": 5, + "description": "Force using internal loopback DQS" + } + ] + }, + { + "width": 5 + } + ] + }, + { + "id": "fuse154", + "name": "XSPI_CFG2", + "description": "Configure DLL and the subordinate delay chain for flash memory with SDR interface, see XSPI_DLLCRA register for more details.", + "index_int": "0x009A", + "shadow_reg_offset_int": "0x0268", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse154-bits-0-31", + "name": "XSPI_FLASH_SDR_DLLCRA", + "description": "Configure DLL and the subordinate delay chain for flash memory with SDR interface, see XSPI_DLLCRA register for more details." + } + ] + }, + { + "id": "fuse155", + "name": "XSPI_CFG3", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with SDR interface. See XSPI_SMPR register for more details.", + "index_int": "0x009B", + "shadow_reg_offset_int": "0x026C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse155-bits-0-31", + "name": "XSPI_FLASH_SDR_SMPR", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with SDR interface. See XSPI_SMPR register for more details." + } + ] + }, + { + "id": "fuse156", + "name": "XSPI_CFG4", + "description": "Configure DLL and the subordinate delay chain for flash memory with DDR interface, see XSPI_DLLCRA register for more details.", + "index_int": "0x009C", + "shadow_reg_offset_int": "0x0270", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse156-bits-0-31", + "name": "XSPI_FLASH_DDR_DLLCRA", + "description": "Configure DLL and the subordinate delay chain for flash memory with DDR interface, see XSPI_DLLCRA register for more details." + } + ] + }, + { + "id": "fuse157", + "name": "XSPI_CFG5", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with DDR interface. See XSPI_SMPR register for more details.", + "index_int": "0x009D", + "shadow_reg_offset_int": "0x0274", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse157-bits-0-31", + "name": "XSPI_FLASH_DDR_SMPR", + "description": "Configure how XSPI samples the incoming data from external serial flash memory with DDR interface. See XSPI_SMPR register for more details." + } + ] + } + ] + }, + { + "group": { + "name": "SDHC", + "description": "SDHC configuration" + }, + "registers": [ + { + "id": "fuse158", + "name": "SDHC_CFGF0", + "description": "SDHC_CFGF0 (for uSDHC0) fuse word", + "index_int": "0x009E", + "shadow_reg_offset_int": "0x0278", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse158-bits-0-1", + "name": "SDHC_BUS_WIDTH", + "description": "eMMC bus width selection", + "values": [ + { + "name": "4 bits", + "value": 0, + "description": "4 bits" + }, + { + "name": "8 bits", + "value": 1, + "description": "8 bits" + }, + { + "name": "4 bits DDR", + "value": 2, + "description": "4 bits DDR" + }, + { + "name": "8 bits DDR", + "value": 3, + "description": "8 bits DDR" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-2", + "name": "SDHC_PWR_CYCLE_EN", + "description": "Power cycle enable", + "values": [ + { + "name": "No power cycle", + "value": 0, + "description": "No power cycle" + }, + { + "name": "Enabled", + "value": 1, + "description": "Power cycle enabled via RST pad" + } + ] + }, + { + "width": 2, + "id": "fuse158-bits-3-4", + "name": "SDHC_PWR_CYCLE_WAIT", + "description": "Power down wait selection", + "values": [ + { + "name": "20 ms", + "value": 0, + "description": "20 ms" + }, + { + "name": "10 ms", + "value": 1, + "description": "10 ms" + }, + { + "name": "5 ms", + "value": 2, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 3, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse158-bits-5-6", + "name": "SDHC_PWR_STABLE_WAIT", + "description": "Power up wait selection", + "values": [ + { + "name": "5 ms", + "value": 0, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-7", + "name": "SDHC_PWR_POL", + "description": "uSDHC reset polarity selection", + "values": [ + { + "name": "Low", + "value": 0, + "description": "Reset active low" + }, + { + "name": "High", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse158-bit-9", + "name": "SDHC_RESET_PRE_IDLE", + "description": "eMMC disable pre-idle selection", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse158-bit-10", + "name": "SDHC_MMC_SPEED", + "description": "eMMC speed selection", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal speed" + }, + { + "name": "High", + "value": 1, + "description": "High speed" + } + ] + }, + { + "width": 21 + } + ] + }, + { + "id": "fuse159", + "name": "SDHC_CFGF1", + "description": "SDHC_CFGF1 (for uSDHC1) fuse word", + "index_int": "0x009F", + "shadow_reg_offset_int": "0x027C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 2, + "id": "fuse159-bits-0-1", + "name": "SDHC_BUS_WIDTH", + "description": "eMMC bus width selection", + "values": [ + { + "name": "4 bits", + "value": 0, + "description": "4 bits" + }, + { + "name": "8 bits", + "value": 1, + "description": "8 bits" + }, + { + "name": "4 bits DDR", + "value": 2, + "description": "4 bits DDR" + }, + { + "name": "8 bits DDR", + "value": 3, + "description": "8 bits DDR" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-2", + "name": "SDHC_PWR_CYCLE_EN", + "description": "Power cycle enable", + "values": [ + { + "name": "No power cycle", + "value": 0, + "description": "No power cycle" + }, + { + "name": "Enabled", + "value": 1, + "description": "Power cycle enabled via RST pad" + } + ] + }, + { + "width": 2, + "id": "fuse159-bits-3-4", + "name": "SDHC_PWR_CYCLE_WAIT", + "description": "Power down wait selection", + "values": [ + { + "name": "20 ms", + "value": 0, + "description": "20 ms" + }, + { + "name": "10 ms", + "value": 1, + "description": "10 ms" + }, + { + "name": "5 ms", + "value": 2, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 3, + "description": "2.5 ms" + } + ] + }, + { + "width": 2, + "id": "fuse159-bits-5-6", + "name": "SDHC_PWR_STABLE_WAIT", + "description": "Power up wait selection", + "values": [ + { + "name": "5 ms", + "value": 0, + "description": "5 ms" + }, + { + "name": "2.5 ms", + "value": 1, + "description": "2.5 ms" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-7", + "name": "SDHC_PWR_POL", + "description": "uSDHC reset polarity selection", + "values": [ + { + "name": "Low", + "value": 0, + "description": "Reset active low" + }, + { + "name": "High", + "value": 1, + "description": "Reset active high" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse159-bit-9", + "name": "SDHC_RESET_PRE_IDLE", + "description": "eMMC disable pre-idle selection", + "values": [ + { + "name": "Enable", + "value": 0, + "description": "Enable" + }, + { + "name": "Disable", + "value": 1, + "description": "Disable" + } + ] + }, + { + "width": 1, + "id": "fuse159-bit-10", + "name": "SDHC_MMC_SPEED", + "description": "eMMC speed selection", + "values": [ + { + "name": "Normal", + "value": 0, + "description": "Normal speed" + }, + { + "name": "High", + "value": 1, + "description": "High speed" + } + ] + }, + { + "width": 21 + } + ] + } + ] + }, + { + "group": { + "name": "Customer", + "description": "General purpose for customer use" + }, + "registers": [ + { + "id": "fuse163", + "name": "BOOT_CFG11", + "description": "For customer use", + "index_int": "0x00A3", + "shadow_reg_offset_int": "0x028C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse164", + "name": "BOOT_CFG12", + "description": "For customer use", + "index_int": "0x00A4", + "shadow_reg_offset_int": "0x0290", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse165", + "name": "BOOT_CFG13", + "description": "For customer use", + "index_int": "0x00A5", + "shadow_reg_offset_int": "0x0294", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse166", + "name": "BOOT_CFG14", + "description": "For customer use", + "index_int": "0x00A6", + "shadow_reg_offset_int": "0x0298", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse167", + "name": "BOOT_CFG15", + "description": "For customer use", + "index_int": "0x00A7", + "shadow_reg_offset_int": "0x029C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + } + }, + { + "id": "fuse168", + "name": "BOOT_CFG16-CUST_CTR1", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG16" + ], + "index_int": "0x00A8", + "shadow_reg_offset_int": "0x02A0", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse169", + "name": "BOOT_CFG17-CUST_CTR2", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG17" + ], + "index_int": "0x00A9", + "shadow_reg_offset_int": "0x02A4", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse170", + "name": "BOOT_CFG18-CUST_CTR3", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG18" + ], + "index_int": "0x00AA", + "shadow_reg_offset_int": "0x02A8", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse171", + "name": "BOOT_CFG19-CUST_CTR4", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG19" + ], + "index_int": "0x00AB", + "shadow_reg_offset_int": "0x02AC", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse172", + "name": "BOOT_CFG20-CUST_CTR5", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG20" + ], + "index_int": "0x00AC", + "shadow_reg_offset_int": "0x02B0", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse173", + "name": "BOOT_CFG21-CUST_CTR6", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG21" + ], + "index_int": "0x00AD", + "shadow_reg_offset_int": "0x02B4", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse174", + "name": "BOOT_CFG22-CUST_CTR7", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG22" + ], + "index_int": "0x00AE", + "shadow_reg_offset_int": "0x02B8", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse175", + "name": "BOOT_CFG23-CUST_CTR8", + "description": "For customer use", + "deprecated_names": [ + "BOOT_CFG23" + ], + "index_int": "0x00AF", + "shadow_reg_offset_int": "0x02BC", + "lock": { + "register_id": "fuse5", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse176", + "name": "BOOT_CFG24", + "description": "For customer use", + "index_int": "0x00B0", + "shadow_reg_offset_int": "0x02C0", + "individual_write_lock": "implicit" + }, + { + "id": "fuse177", + "name": "BOOT_CFG25", + "description": "For customer use", + "index_int": "0x00B1", + "shadow_reg_offset_int": "0x02C4", + "individual_write_lock": "implicit" + }, + { + "id": "fuse178", + "name": "BOOT_CFG26", + "description": "For customer use", + "index_int": "0x00B2", + "shadow_reg_offset_int": "0x02C8", + "individual_write_lock": "implicit" + }, + { + "id": "fuse179", + "name": "BOOT_CFG27", + "description": "For customer use", + "index_int": "0x00B3", + "shadow_reg_offset_int": "0x02CC", + "individual_write_lock": "implicit" + }, + { + "id": "fuse180", + "name": "BOOT_CFG28", + "description": "For customer use", + "index_int": "0x00B4", + "shadow_reg_offset_int": "0x02D0", + "individual_write_lock": "implicit" + }, + { + "id": "fuse181", + "name": "BOOT_CFG29", + "description": "For customer use", + "index_int": "0x00B5", + "shadow_reg_offset_int": "0x02D4", + "individual_write_lock": "implicit" + }, + { + "id": "fuse182", + "name": "BOOT_CFG30", + "description": "For customer use", + "index_int": "0x00B6", + "shadow_reg_offset_int": "0x02D8", + "individual_write_lock": "implicit" + }, + { + "id": "fuse183", + "name": "BOOT_CFG31", + "description": "For customer use", + "index_int": "0x00B7", + "shadow_reg_offset_int": "0x02DC", + "individual_write_lock": "implicit" + }, + { + "id": "fuse451", + "name": "NXP_GPR5_CFG3", + "description": "NXP_GPR5_CFG3 fuse word", + "index_int": "0x01C3", + "shadow_reg_offset_int": "0x070C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse451-bits-0-15", + "name": "PVT_SENSE_A", + "description": "PVTS-ML Sense A value\nRead only" + }, + { + "width": 16, + "id": "fuse451-bits-16-31", + "name": "PVT_SENSE_B", + "description": "PVTS-ML Sense B value\nRead only" + } + ] + }, + { + "id": "fuse452", + "name": "NXP_GPR5_CFG4", + "description": "NXP_GPR5_CFG4 fuse word", + "index_int": "0x01C4", + "shadow_reg_offset_int": "0x0710", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 16, + "id": "fuse452-bits-0-15", + "name": "PVT_CMPT_A", + "description": "PVTS-ML Compute A value\nRead only" + }, + { + "width": 16, + "id": "fuse452-bits-16-31", + "name": "PVT_CMPT_B", + "description": "PVTS-ML Compute B value\nRead only" + } + ] + }, + { + "id": "fuse460", + "name": "GPR1_CFG0", + "description": "General purpose fuse for customer use", + "index_int": "0x01CC", + "shadow_reg_offset_int": "0x0730", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse461", + "name": "GPR1_CFG1", + "description": "General purpose fuse for customer use", + "index_int": "0x01CD", + "shadow_reg_offset_int": "0x0734", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse462", + "name": "GPR1_CFG2", + "description": "General purpose fuse for customer use", + "index_int": "0x01CE", + "shadow_reg_offset_int": "0x0738", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse463", + "name": "GPR1_CFG3", + "description": "General purpose fuse for customer use", + "index_int": "0x01CF", + "shadow_reg_offset_int": "0x073C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + }, + { + "id": "fuse472", + "name": "GPR0_CFG0", + "description": "General purpose fuse for customer use", + "index_int": "0x01D8", + "shadow_reg_offset_int": "0x0760", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse473", + "name": "GPR0_CFG1", + "description": "General purpose fuse for customer use", + "index_int": "0x01D9", + "shadow_reg_offset_int": "0x0764", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse474", + "name": "GPR0_CFG2", + "description": "General purpose fuse for customer use", + "index_int": "0x01DA", + "shadow_reg_offset_int": "0x0768", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse475", + "name": "GPR0_CFG3", + "description": "General purpose fuse for customer use", + "index_int": "0x01DB", + "shadow_reg_offset_int": "0x076C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse476", + "name": "GPR0_CFG4", + "description": "General purpose fuse for customer use", + "index_int": "0x01DC", + "shadow_reg_offset_int": "0x0770", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse477", + "name": "GPR0_CFG5", + "description": "General purpose fuse for customer use", + "index_int": "0x01DD", + "shadow_reg_offset_int": "0x0774", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse478", + "name": "GPR0_CFG6", + "description": "General purpose fuse for customer use", + "index_int": "0x01DE", + "shadow_reg_offset_int": "0x0778", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse479", + "name": "GPR0_CFG7", + "description": "General purpose fuse for customer use", + "index_int": "0x01DF", + "shadow_reg_offset_int": "0x077C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + } + }, + { + "id": "fuse480", + "name": "GPR0_CFG8", + "description": "General purpose fuse for customer use", + "index_int": "0x01E0", + "shadow_reg_offset_int": "0x0780", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse481", + "name": "GPR0_CFG9", + "description": "General purpose fuse for customer use", + "index_int": "0x01E1", + "shadow_reg_offset_int": "0x0784", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + } + ] + }, + { + "group": { + "name": "PVT", + "description": "Domain PVT setpoint" + }, + "registers": [ + { + "id": "fuse482", + "name": "SENSE_PVT_SP3", + "description": "Sense domain PVT setpoint 3 CPU1/HiFi1 \u2013 Freq/Volt\n250 MHz PVTS delay values, HiFi1[15:8], CPU1[7:0]", + "index_int": "0x01E2", + "shadow_reg_offset_int": "0x0788", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse483", + "name": "COM_PVT_SP3", + "description": "Compute domain PVT setpoint 3 CPU0/HiFi4 \u2013 Freq/Volt\n325 MHz PVTS delay values, HiFi4[15:8], CPU0[7:0]", + "index_int": "0x01E3", + "shadow_reg_offset_int": "0x078C", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse484", + "name": "SENSE_PVT_SP2", + "description": "Sense domain PVT setpoint 2 CPU1/HiFi1 \u2013 Freq/Volt\n160 MHz PVTS delay values, HiFi1[15:8], CPU1[7:0]", + "index_int": "0x01E4", + "shadow_reg_offset_int": "0x0790", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse485", + "name": "COM_PVT_SP2", + "description": "Compute domain PVT setpoint 2 CPU0/HiFi4 \u2013 Freq/Volt\n192 MHz PVTS delay values, HiFi4[15:8], CPU0[7:0]", + "index_int": "0x01E5", + "shadow_reg_offset_int": "0x0794", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse486", + "name": "SENSE_PVT_SP1", + "description": "Sense domain PVT setpoint 1 CPU1/HiFi1 \u2013 Freq/Volt\n100 MHz PVTS delay values, HiFi1[15:8], CPU1[7:0]", + "index_int": "0x01E6", + "shadow_reg_offset_int": "0x0798", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + }, + { + "id": "fuse487", + "name": "COM_PVT_SP1", + "description": "Compute domain PVT setpoint 1 CPU0/HiFi4 \u2013 Freq/Volt\n110 MHz PVTS delay values, HiFi4[15:8], CPU0[7:0]", + "index_int": "0x01E7", + "shadow_reg_offset_int": "0x079C", + "lock": { + "register_id": "fuse3", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16 + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/tz.json new file mode 100644 index 0000000..8cfb3f2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mimxrt798s/tz.json @@ -0,0 +1,5253 @@ +{ + "cpu": "mimxrt798s", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CORE0 CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CORE0 CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CORE0 CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CORE0 CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CORE0 CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CORE0 CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "CORE0 CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CORE0 CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "CORE0 CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "description": "TrustZone register - CORE0 CM33 Interrupt target non-secure register 2 (cm33_nvic_itns2)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "CORE0 CM33 Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "description": "TrustZone register - CORE0 CM33 Interrupt target non-secure register 3 (cm33_nvic_itns3)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "CORE0 CM33 Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "description": "TrustZone register - CORE0 CM33 Interrupt target non-secure register 4 (cm33_nvic_itns4)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CORE0 Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - CORE0 Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "CORE0 CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CORE0 CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "CORE0 CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CORE0 CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "CORE0 CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CORE0 CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "CORE0 MPU Control Register.*/(cm33_mpu_ctrl)", + "description": "TrustZone register - CORE0 MPU Control Register.*/(cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "CORE0 MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - CORE0 MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "CORE0 MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - CORE0 MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "CORE0 MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - CORE0 MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "CORE0 MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - CORE0 MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "CORE0 MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - CORE0 MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "CORE0 MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - CORE0 MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "CORE0 MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - CORE0 MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "CORE0 MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - CORE0 MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "CORE0 MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - CORE0 MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "CORE0 MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - CORE0 MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "CORE0 MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - CORE0 MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "CORE0 MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - CORE0 MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "CORE0 MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - CORE0 MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "CORE0 MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - CORE0 MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "CORE0 MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - CORE0 MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "CORE0 MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - CORE0 MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "CORE0 MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - CORE0 MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "CORE0 MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - CORE0 MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Control Register.*/(cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "CORE0 Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - CORE0 Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "CORE0 SAU Control Register.*/(cm33_sau_ctrl)", + "description": "TrustZone register - CORE0 SAU Control Register.*/(cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "CORE0 SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - CORE0 SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "CORE0 SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - CORE0 SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "CORE0 SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - CORE0 SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "CORE0 SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - CORE0 SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "CORE0 SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - CORE0 SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "CORE0 SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - CORE0 SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "CORE0 SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - CORE0 SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "CORE0 SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - CORE0 SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "CORE0 SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - CORE0 SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "CORE0 SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - CORE0 SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "CORE0 SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - CORE0 SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "CORE0 SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - CORE0 SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "CORE0 SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - CORE0 SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "CORE0 SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - CORE0 SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "CORE0 SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - CORE0 SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "CORE0 SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - CORE0 SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "COMPUTE ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - COMPUTE ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "COMPUTE ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - COMPUTE ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "COMPUTE ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - COMPUTE ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "COMPUTE ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - COMPUTE ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 0 Memory Rule Register 0 (xspi1_region0_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI1 Region 0 Memory Rule Register 0 (xspi1_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 0 Memory Rule Register 1 (xspi1_region0_mem_rule1)", + "description": "TrustZone register - COMPUTE XSPI1 Region 0 Memory Rule Register 1 (xspi1_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 0 Memory Rule Register 2 (xspi1_region0_mem_rule2)", + "description": "TrustZone register - COMPUTE XSPI1 Region 0 Memory Rule Register 2 (xspi1_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 0 Memory Rule Register 3 (xspi1_region0_mem_rule3)", + "description": "TrustZone register - COMPUTE XSPI1 Region 0 Memory Rule Register 3 (xspi1_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 1 Memory Rule Register 0 (xspi1_region1_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI1 Region 1 Memory Rule Register 0 (xspi1_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 2 Memory Rule Register 0 (xspi1_region2_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI1 Region 2 Memory Rule Register 0 (xspi1_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 3 Memory Rule Register 0 (xspi1_region3_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI1 Region 3 Memory Rule Register 0 (xspi1_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "COMPUTE XSPI1 Region 4 Memory Rule Register 0 (xspi1_region4_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI1 Region 4 Memory Rule Register 0 (xspi1_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 0 Memory Rule Register 0 (xspi0_region0_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI0 Region 0 Memory Rule Register 0 (xspi0_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 0 Memory Rule Register 1 (xspi0_region0_mem_rule1)", + "description": "TrustZone register - COMPUTE XSPI0 Region 0 Memory Rule Register 1 (xspi0_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 0 Memory Rule Register 2 (xspi0_region0_mem_rule2)", + "description": "TrustZone register - COMPUTE XSPI0 Region 0 Memory Rule Register 2 (xspi0_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 0 Memory Rule Register 3 (xspi0_region0_mem_rule3)", + "description": "TrustZone register - COMPUTE XSPI0 Region 0 Memory Rule Register 3 (xspi0_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 1 Memory Rule Register 0 (xspi0_region1_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI0 Region 1 Memory Rule Register 0 (xspi0_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 2 Memory Rule Register 0 (xspi0_region2_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI0 Region 2 Memory Rule Register 0 (xspi0_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 3 Memory Rule Register 0 (xspi0_region3_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI0 Region 3 Memory Rule Register 0 (xspi0_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "COMPUTE XSPI0 Region 4 Memory Rule Register 0 (xspi0_region4_mem_rule0)", + "description": "TrustZone register - COMPUTE XSPI0 Region 4 Memory Rule Register 0 (xspi0_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "COMPUTE PKC RAM Memory Rule Register 0 (pkc_ram_rule0)", + "description": "TrustZone register - COMPUTE PKC RAM Memory Rule Register 0 (pkc_ram_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "COMPUTE RAM0 Memory Rule Register 0 (sram_0_rule0)", + "description": "TrustZone register - COMPUTE RAM0 Memory Rule Register 0 (sram_0_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "COMPUTE RAM0 Memory Rule Register 1 (sram_0_rule1)", + "description": "TrustZone register - COMPUTE RAM0 Memory Rule Register 1 (sram_0_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "COMPUTE RAM0 Memory Rule Register 2 (sram_0_rule2)", + "description": "TrustZone register - COMPUTE RAM0 Memory Rule Register 2 (sram_0_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "COMPUTE RAM0 Memory Rule Register 3 (sram_0_rule3)", + "description": "TrustZone register - COMPUTE RAM0 Memory Rule Register 3 (sram_0_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "COMPUTE RAM1 Memory Rule Register 0 (sram_1_rule0)", + "description": "TrustZone register - COMPUTE RAM1 Memory Rule Register 0 (sram_1_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "COMPUTE RAM1 Memory Rule Register 1 (sram_1_rule1)", + "description": "TrustZone register - COMPUTE RAM1 Memory Rule Register 1 (sram_1_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "COMPUTE RAM1 Memory Rule Register 2 (sram_1_rule2)", + "description": "TrustZone register - COMPUTE RAM1 Memory Rule Register 2 (sram_1_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "COMPUTE RAM1 Memory Rule Register 3 (sram_1_rule3)", + "description": "TrustZone register - COMPUTE RAM1 Memory Rule Register 3 (sram_1_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "COMPUTE RAM2 Memory Rule Register 0 (sram_2_rule0)", + "description": "TrustZone register - COMPUTE RAM2 Memory Rule Register 0 (sram_2_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "COMPUTE RAM2 Memory Rule Register 1 (sram_2_rule1)", + "description": "TrustZone register - COMPUTE RAM2 Memory Rule Register 1 (sram_2_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "COMPUTE RAM2 Memory Rule Register 2 (sram_2_rule2)", + "description": "TrustZone register - COMPUTE RAM2 Memory Rule Register 2 (sram_2_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "COMPUTE RAM2 Memory Rule Register 3 (sram_2_rule3)", + "description": "TrustZone register - COMPUTE RAM2 Memory Rule Register 3 (sram_2_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "COMPUTE RAM3 Memory Rule Register 0 (sram_3_rule0)", + "description": "TrustZone register - COMPUTE RAM3 Memory Rule Register 0 (sram_3_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "COMPUTE RAM3 Memory Rule Register 1 (sram_3_rule1)", + "description": "TrustZone register - COMPUTE RAM3 Memory Rule Register 1 (sram_3_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "COMPUTE RAM3 Memory Rule Register 2 (sram_3_rule2)", + "description": "TrustZone register - COMPUTE RAM3 Memory Rule Register 2 (sram_3_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "COMPUTE RAM3 Memory Rule Register 3 (sram_3_rule3)", + "description": "TrustZone register - COMPUTE RAM3 Memory Rule Register 3 (sram_3_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "COMPUTE RAM4 Memory Rule Register 0 (sram_4_rule0)", + "description": "TrustZone register - COMPUTE RAM4 Memory Rule Register 0 (sram_4_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "COMPUTE RAM4 Memory Rule Register 1 (sram_4_rule1)", + "description": "TrustZone register - COMPUTE RAM4 Memory Rule Register 1 (sram_4_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "COMPUTE RAM4 Memory Rule Register 2 (sram_4_rule2)", + "description": "TrustZone register - COMPUTE RAM4 Memory Rule Register 2 (sram_4_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "COMPUTE RAM4 Memory Rule Register 3 (sram_4_rule3)", + "description": "TrustZone register - COMPUTE RAM4 Memory Rule Register 3 (sram_4_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "COMPUTE RAM5 Memory Rule Register 0 (sram_5_rule0)", + "description": "TrustZone register - COMPUTE RAM5 Memory Rule Register 0 (sram_5_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "COMPUTE RAM5 Memory Rule Register 1 (sram_5_rule1)", + "description": "TrustZone register - COMPUTE RAM5 Memory Rule Register 1 (sram_5_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "COMPUTE RAM5 Memory Rule Register 2 (sram_5_rule2)", + "description": "TrustZone register - COMPUTE RAM5 Memory Rule Register 2 (sram_5_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "COMPUTE RAM5 Memory Rule Register 3 (sram_5_rule3)", + "description": "TrustZone register - COMPUTE RAM5 Memory Rule Register 3 (sram_5_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "COMPUTE RAM6 Memory Rule Register 0 (sram_6_rule0)", + "description": "TrustZone register - COMPUTE RAM6 Memory Rule Register 0 (sram_6_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "COMPUTE RAM6 Memory Rule Register 1 (sram_6_rule1)", + "description": "TrustZone register - COMPUTE RAM6 Memory Rule Register 1 (sram_6_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "COMPUTE RAM6 Memory Rule Register 2 (sram_6_rule2)", + "description": "TrustZone register - COMPUTE RAM6 Memory Rule Register 2 (sram_6_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "COMPUTE RAM6 Memory Rule Register 3 (sram_6_rule3)", + "description": "TrustZone register - COMPUTE RAM6 Memory Rule Register 3 (sram_6_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "COMPUTE RAM7 Memory Rule Register 0 (sram_7_rule0)", + "description": "TrustZone register - COMPUTE RAM7 Memory Rule Register 0 (sram_7_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "COMPUTE RAM7 Memory Rule Register 1 (sram_7_rule1)", + "description": "TrustZone register - COMPUTE RAM7 Memory Rule Register 1 (sram_7_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "COMPUTE RAM7 Memory Rule Register 2 (sram_7_rule2)", + "description": "TrustZone register - COMPUTE RAM7 Memory Rule Register 2 (sram_7_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "COMPUTE RAM7 Memory Rule Register 3 (sram_7_rule3)", + "description": "TrustZone register - COMPUTE RAM7 Memory Rule Register 3 (sram_7_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "COMPUTE RAM8 Memory Rule Register 0 (sram_8_rule0)", + "description": "TrustZone register - COMPUTE RAM8 Memory Rule Register 0 (sram_8_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "COMPUTE RAM8 Memory Rule Register 1 (sram_8_rule1)", + "description": "TrustZone register - COMPUTE RAM8 Memory Rule Register 1 (sram_8_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "COMPUTE RAM8 Memory Rule Register 2 (sram_8_rule2)", + "description": "TrustZone register - COMPUTE RAM8 Memory Rule Register 2 (sram_8_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "COMPUTE RAM8 Memory Rule Register 3 (sram_8_rule3)", + "description": "TrustZone register - COMPUTE RAM8 Memory Rule Register 3 (sram_8_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "COMPUTE RAM9 Memory Rule Register 0 (sram_9_rule0)", + "description": "TrustZone register - COMPUTE RAM9 Memory Rule Register 0 (sram_9_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "COMPUTE RAM9 Memory Rule Register 1 (sram_9_rule1)", + "description": "TrustZone register - COMPUTE RAM9 Memory Rule Register 1 (sram_9_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "COMPUTE RAM9 Memory Rule Register 2 (sram_9_rule2)", + "description": "TrustZone register - COMPUTE RAM9 Memory Rule Register 2 (sram_9_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "COMPUTE RAM9 Memory Rule Register 3 (sram_9_rule3)", + "description": "TrustZone register - COMPUTE RAM9 Memory Rule Register 3 (sram_9_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "COMPUTE RAM10 Memory Rule Register 0 (sram_10_rule0)", + "description": "TrustZone register - COMPUTE RAM10 Memory Rule Register 0 (sram_10_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "COMPUTE RAM10 Memory Rule Register 1 (sram_10_rule1)", + "description": "TrustZone register - COMPUTE RAM10 Memory Rule Register 1 (sram_10_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "COMPUTE RAM10 Memory Rule Register 2 (sram_10_rule2)", + "description": "TrustZone register - COMPUTE RAM10 Memory Rule Register 2 (sram_10_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "COMPUTE RAM10 Memory Rule Register 3 (sram_10_rule3)", + "description": "TrustZone register - COMPUTE RAM10 Memory Rule Register 3 (sram_10_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "COMPUTE RAM11 Memory Rule Register 0 (sram_11_rule0)", + "description": "TrustZone register - COMPUTE RAM11 Memory Rule Register 0 (sram_11_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "COMPUTE RAM11 Memory Rule Register 1 (sram_11_rule1)", + "description": "TrustZone register - COMPUTE RAM11 Memory Rule Register 1 (sram_11_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "COMPUTE RAM11 Memory Rule Register 2 (sram_11_rule2)", + "description": "TrustZone register - COMPUTE RAM11 Memory Rule Register 2 (sram_11_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "COMPUTE RAM11 Memory Rule Register 3 (sram_11_rule3)", + "description": "TrustZone register - COMPUTE RAM11 Memory Rule Register 3 (sram_11_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "COMPUTE RAM12 Memory Rule Register 0 (sram_12_rule0)", + "description": "TrustZone register - COMPUTE RAM12 Memory Rule Register 0 (sram_12_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "COMPUTE RAM12 Memory Rule Register 1 (sram_12_rule1)", + "description": "TrustZone register - COMPUTE RAM12 Memory Rule Register 1 (sram_12_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "COMPUTE RAM12 Memory Rule Register 2 (sram_12_rule2)", + "description": "TrustZone register - COMPUTE RAM12 Memory Rule Register 2 (sram_12_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "COMPUTE RAM12 Memory Rule Register 3 (sram_12_rule3)", + "description": "TrustZone register - COMPUTE RAM12 Memory Rule Register 3 (sram_12_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "COMPUTE RAM13 Memory Rule Register 0 (sram_13_rule0)", + "description": "TrustZone register - COMPUTE RAM13 Memory Rule Register 0 (sram_13_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "COMPUTE RAM13 Memory Rule Register 1 (sram_13_rule1)", + "description": "TrustZone register - COMPUTE RAM13 Memory Rule Register 1 (sram_13_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "COMPUTE RAM13 Memory Rule Register 2 (sram_13_rule2)", + "description": "TrustZone register - COMPUTE RAM13 Memory Rule Register 2 (sram_13_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "COMPUTE RAM13 Memory Rule Register 3 (sram_13_rule3)", + "description": "TrustZone register - COMPUTE RAM13 Memory Rule Register 3 (sram_13_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "COMPUTE RAM14 Memory Rule Register 0 (sram_14_rule0)", + "description": "TrustZone register - COMPUTE RAM14 Memory Rule Register 0 (sram_14_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "COMPUTE RAM14 Memory Rule Register 1 (sram_14_rule1)", + "description": "TrustZone register - COMPUTE RAM14 Memory Rule Register 1 (sram_14_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "COMPUTE RAM14 Memory Rule Register 2 (sram_14_rule2)", + "description": "TrustZone register - COMPUTE RAM14 Memory Rule Register 2 (sram_14_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "COMPUTE RAM14 Memory Rule Register 3 (sram_14_rule3)", + "description": "TrustZone register - COMPUTE RAM14 Memory Rule Register 3 (sram_14_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "COMPUTE RAM15 Memory Rule Register 0 (sram_15_rule0)", + "description": "TrustZone register - COMPUTE RAM15 Memory Rule Register 0 (sram_15_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "COMPUTE RAM15 Memory Rule Register 1 (sram_15_rule1)", + "description": "TrustZone register - COMPUTE RAM15 Memory Rule Register 1 (sram_15_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "COMPUTE RAM15 Memory Rule Register 2 (sram_15_rule2)", + "description": "TrustZone register - COMPUTE RAM15 Memory Rule Register 2 (sram_15_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "COMPUTE RAM15 Memory Rule Register 3 (sram_15_rule3)", + "description": "TrustZone register - COMPUTE RAM15 Memory Rule Register 3 (sram_15_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "COMPUTE RAM16 Memory Rule Register 0 (sram_16_rule0)", + "description": "TrustZone register - COMPUTE RAM16 Memory Rule Register 0 (sram_16_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "COMPUTE RAM16 Memory Rule Register 1 (sram_16_rule1)", + "description": "TrustZone register - COMPUTE RAM16 Memory Rule Register 1 (sram_16_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "COMPUTE RAM16 Memory Rule Register 2 (sram_16_rule2)", + "description": "TrustZone register - COMPUTE RAM16 Memory Rule Register 2 (sram_16_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "COMPUTE RAM16 Memory Rule Register 3 (sram_16_rule3)", + "description": "TrustZone register - COMPUTE RAM16 Memory Rule Register 3 (sram_16_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "COMPUTE RAM17 Memory Rule Register 0 (sram_17_rule0)", + "description": "TrustZone register - COMPUTE RAM17 Memory Rule Register 0 (sram_17_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "COMPUTE RAM17 Memory Rule Register 1 (sram_17_rule1)", + "description": "TrustZone register - COMPUTE RAM17 Memory Rule Register 1 (sram_17_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "COMPUTE RAM17 Memory Rule Register 2 (sram_17_rule2)", + "description": "TrustZone register - COMPUTE RAM17 Memory Rule Register 2 (sram_17_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "COMPUTE RAM17 Memory Rule Register 3 (sram_17_rule3)", + "description": "TrustZone register - COMPUTE RAM17 Memory Rule Register 3 (sram_17_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "COMPUTE RAM18 Memory Rule Register 0 (sram_18_rule0)", + "description": "TrustZone register - COMPUTE RAM18 Memory Rule Register 0 (sram_18_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "COMPUTE RAM18 Memory Rule Register 1 (sram_18_rule1)", + "description": "TrustZone register - COMPUTE RAM18 Memory Rule Register 1 (sram_18_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "COMPUTE RAM18 Memory Rule Register 2 (sram_18_rule2)", + "description": "TrustZone register - COMPUTE RAM18 Memory Rule Register 2 (sram_18_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "COMPUTE RAM18 Memory Rule Register 3 (sram_18_rule3)", + "description": "TrustZone register - COMPUTE RAM18 Memory Rule Register 3 (sram_18_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "COMPUTE RAM19 Memory Rule Register 0 (sram_19_rule0)", + "description": "TrustZone register - COMPUTE RAM19 Memory Rule Register 0 (sram_19_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "COMPUTE RAM19 Memory Rule Register 1 (sram_19_rule1)", + "description": "TrustZone register - COMPUTE RAM19 Memory Rule Register 1 (sram_19_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "COMPUTE RAM19 Memory Rule Register 2 (sram_19_rule2)", + "description": "TrustZone register - COMPUTE RAM19 Memory Rule Register 2 (sram_19_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "COMPUTE RAM19 Memory Rule Register 3 (sram_19_rule3)", + "description": "TrustZone register - COMPUTE RAM19 Memory Rule Register 3 (sram_19_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "COMPUTE RAM20 Memory Rule Register 0 (sram_20_rule0)", + "description": "TrustZone register - COMPUTE RAM20 Memory Rule Register 0 (sram_20_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "COMPUTE RAM20 Memory Rule Register 1 (sram_20_rule1)", + "description": "TrustZone register - COMPUTE RAM20 Memory Rule Register 1 (sram_20_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "COMPUTE RAM20 Memory Rule Register 2 (sram_20_rule2)", + "description": "TrustZone register - COMPUTE RAM20 Memory Rule Register 2 (sram_20_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "COMPUTE RAM20 Memory Rule Register 3 (sram_20_rule3)", + "description": "TrustZone register - COMPUTE RAM20 Memory Rule Register 3 (sram_20_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "COMPUTE RAM21 Memory Rule Register 0 (sram_21_rule0)", + "description": "TrustZone register - COMPUTE RAM21 Memory Rule Register 0 (sram_21_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "COMPUTE RAM21 Memory Rule Register 1 (sram_21_rule1)", + "description": "TrustZone register - COMPUTE RAM21 Memory Rule Register 1 (sram_21_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "COMPUTE RAM21 Memory Rule Register 2 (sram_21_rule2)", + "description": "TrustZone register - COMPUTE RAM21 Memory Rule Register 2 (sram_21_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "COMPUTE RAM21 Memory Rule Register 3 (sram_21_rule3)", + "description": "TrustZone register - COMPUTE RAM21 Memory Rule Register 3 (sram_21_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "COMPUTE RAM22 Memory Rule Register 0 (sram_22_rule0)", + "description": "TrustZone register - COMPUTE RAM22 Memory Rule Register 0 (sram_22_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "COMPUTE RAM22 Memory Rule Register 1 (sram_22_rule1)", + "description": "TrustZone register - COMPUTE RAM22 Memory Rule Register 1 (sram_22_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "COMPUTE RAM22 Memory Rule Register 2 (sram_22_rule2)", + "description": "TrustZone register - COMPUTE RAM22 Memory Rule Register 2 (sram_22_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "COMPUTE RAM22 Memory Rule Register 3 (sram_22_rule3)", + "description": "TrustZone register - COMPUTE RAM22 Memory Rule Register 3 (sram_22_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "COMPUTE RAM23 Memory Rule Register 0 (sram_23_rule0)", + "description": "TrustZone register - COMPUTE RAM23 Memory Rule Register 0 (sram_23_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "COMPUTE RAM23 Memory Rule Register 1 (sram_23_rule1)", + "description": "TrustZone register - COMPUTE RAM23 Memory Rule Register 1 (sram_23_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "COMPUTE RAM23 Memory Rule Register 2 (sram_23_rule2)", + "description": "TrustZone register - COMPUTE RAM23 Memory Rule Register 2 (sram_23_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "COMPUTE RAM23 Memory Rule Register 3 (sram_23_rule3)", + "description": "TrustZone register - COMPUTE RAM23 Memory Rule Register 3 (sram_23_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "COMPUTE RAM24 Memory Rule Register 0 (sram_24_rule0)", + "description": "TrustZone register - COMPUTE RAM24 Memory Rule Register 0 (sram_24_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "COMPUTE RAM24 Memory Rule Register 1 (sram_24_rule1)", + "description": "TrustZone register - COMPUTE RAM24 Memory Rule Register 1 (sram_24_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "COMPUTE RAM24 Memory Rule Register 2 (sram_24_rule2)", + "description": "TrustZone register - COMPUTE RAM24 Memory Rule Register 2 (sram_24_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "COMPUTE RAM24 Memory Rule Register 3 (sram_24_rule3)", + "description": "TrustZone register - COMPUTE RAM24 Memory Rule Register 3 (sram_24_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "COMPUTE RAM25 Memory Rule Register 0 (sram_25_rule0)", + "description": "TrustZone register - COMPUTE RAM25 Memory Rule Register 0 (sram_25_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "COMPUTE RAM25 Memory Rule Register 1 (sram_25_rule1)", + "description": "TrustZone register - COMPUTE RAM25 Memory Rule Register 1 (sram_25_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "COMPUTE RAM25 Memory Rule Register 2 (sram_25_rule2)", + "description": "TrustZone register - COMPUTE RAM25 Memory Rule Register 2 (sram_25_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "COMPUTE RAM25 Memory Rule Register 3 (sram_25_rule3)", + "description": "TrustZone register - COMPUTE RAM25 Memory Rule Register 3 (sram_25_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "COMPUTE RAM26 Memory Rule Register 0 (sram_26_rule0)", + "description": "TrustZone register - COMPUTE RAM26 Memory Rule Register 0 (sram_26_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "COMPUTE RAM26 Memory Rule Register 1 (sram_26_rule1)", + "description": "TrustZone register - COMPUTE RAM26 Memory Rule Register 1 (sram_26_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "COMPUTE RAM26 Memory Rule Register 2 (sram_26_rule2)", + "description": "TrustZone register - COMPUTE RAM26 Memory Rule Register 2 (sram_26_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "COMPUTE RAM26 Memory Rule Register 3 (sram_26_rule3)", + "description": "TrustZone register - COMPUTE RAM26 Memory Rule Register 3 (sram_26_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "COMPUTE RAM27 Memory Rule Register 0 (sram_27_rule0)", + "description": "TrustZone register - COMPUTE RAM27 Memory Rule Register 0 (sram_27_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "COMPUTE RAM27 Memory Rule Register 1 (sram_27_rule1)", + "description": "TrustZone register - COMPUTE RAM27 Memory Rule Register 1 (sram_27_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "COMPUTE RAM27 Memory Rule Register 2 (sram_27_rule2)", + "description": "TrustZone register - COMPUTE RAM27 Memory Rule Register 2 (sram_27_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "COMPUTE RAM27 Memory Rule Register 3 (sram_27_rule3)", + "description": "TrustZone register - COMPUTE RAM27 Memory Rule Register 3 (sram_27_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "COMPUTE RAM28 Memory Rule Register 0 (sram_28_rule0)", + "description": "TrustZone register - COMPUTE RAM28 Memory Rule Register 0 (sram_28_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "COMPUTE RAM28 Memory Rule Register 1 (sram_28_rule1)", + "description": "TrustZone register - COMPUTE RAM28 Memory Rule Register 1 (sram_28_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "COMPUTE RAM28 Memory Rule Register 2 (sram_28_rule2)", + "description": "TrustZone register - COMPUTE RAM28 Memory Rule Register 2 (sram_28_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "COMPUTE RAM28 Memory Rule Register 3 (sram_28_rule3)", + "description": "TrustZone register - COMPUTE RAM28 Memory Rule Register 3 (sram_28_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "COMPUTE RAM29 Memory Rule Register 0 (sram_29_rule0)", + "description": "TrustZone register - COMPUTE RAM29 Memory Rule Register 0 (sram_29_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "COMPUTE RAM29 Memory Rule Register 1 (sram_29_rule1)", + "description": "TrustZone register - COMPUTE RAM29 Memory Rule Register 1 (sram_29_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "COMPUTE RAM29 Memory Rule Register 2 (sram_29_rule2)", + "description": "TrustZone register - COMPUTE RAM29 Memory Rule Register 2 (sram_29_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "COMPUTE RAM29 Memory Rule Register 3 (sram_29_rule3)", + "description": "TrustZone register - COMPUTE RAM29 Memory Rule Register 3 (sram_29_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "COMPUTE HIFI4 TCM Memory Rule Register 0 (hifi4_tcm_rule0)", + "description": "TrustZone register - COMPUTE HIFI4 TCM Memory Rule Register 0 (hifi4_tcm_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "COMPUTE HIFI4 TCM Memory Rule Register 1 (hifi4_tcm_rule1)", + "description": "TrustZone register - COMPUTE HIFI4 TCM Memory Rule Register 1 (hifi4_tcm_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "COMPUTE HIFI4 TCM Memory Rule Register 2 (hifi4_tcm_rule2)", + "description": "TrustZone register - COMPUTE HIFI4 TCM Memory Rule Register 2 (hifi4_tcm_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "COMPUTE HIFI4 TCM Memory Rule Register 3 (hifi4_tcm_rule3)", + "description": "TrustZone register - COMPUTE HIFI4 TCM Memory Rule Register 3 (hifi4_tcm_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "COMPUTE COMPUTE domain to MEDIA domain Access Rule Register (compute2media_rule)", + "description": "TrustZone register - COMPUTE COMPUTE domain to MEDIA domain Access Rule Register (compute2media_rule)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "COMPUTE COMPUTE Pbus domain Rule Register (mbus2pbus_rule)", + "description": "TrustZone register - COMPUTE COMPUTE Pbus domain Rule Register (mbus2pbus_rule)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves Rule Register 0 (ahb_peripheral0_slave_rule0)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves Rule Register 0 (ahb_peripheral0_slave_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 0 (ahb_peripheral0_slave_hsgpio_rule0)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 0 (ahb_peripheral0_slave_hsgpio_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 1 (ahb_peripheral0_slave_hsgpio_rule1)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 1 (ahb_peripheral0_slave_hsgpio_rule1)", + "default_value_int": "0x33" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 2 (ahb_peripheral0_slave_hsgpio_rule2)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 2 (ahb_peripheral0_slave_hsgpio_rule2)", + "default_value_int": "0x33" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 3 (ahb_peripheral0_slave_hsgpio_rule3)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 3 (ahb_peripheral0_slave_hsgpio_rule3)", + "default_value_int": "0x33" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 4 (ahb_peripheral0_slave_hsgpio_rule4)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 4 (ahb_peripheral0_slave_hsgpio_rule4)", + "default_value_int": "0x33" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 5 (ahb_peripheral0_slave_hsgpio_rule5)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 5 (ahb_peripheral0_slave_hsgpio_rule5)", + "default_value_int": "0x33" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 6 (ahb_peripheral0_slave_hsgpio_rule6)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 6 (ahb_peripheral0_slave_hsgpio_rule6)", + "default_value_int": "0x33" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 7 (ahb_peripheral0_slave_hsgpio_rule7)", + "description": "TrustZone register - COMPUTE AHB Peripheral 0 Slaves HSGPIO Rule Register 7 (ahb_peripheral0_slave_hsgpio_rule7)", + "default_value_int": "0x33" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 1 Slaves Rule Register (ahb_peripheral1_slave_rule)", + "description": "TrustZone register - COMPUTE AHB Peripheral 1 Slaves Rule Register (ahb_peripheral1_slave_rule)", + "default_value_int": "0x33333333" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 0 (aips1_bridge_group0_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 0 (aips1_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 1 (aips1_bridge_group0_mem_rule1)", + "description": "TrustZone register - COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 1 (aips1_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 2 (aips1_bridge_group0_mem_rule2)", + "description": "TrustZone register - COMPUTE AIPS1 Bridge Group 0 Memory Rule Register 2 (aips1_bridge_group0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "COMPUTE AIPS1 Bridge Group 1 Memory Rule Register 0 (aips1_bridge_group1_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS1 Bridge Group 1 Memory Rule Register 0 (aips1_bridge_group1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "COMPUTE AIPS1 Bridge Group 1 Memory Rule Register 1 (aips1_bridge_group1_mem_rule1)", + "description": "TrustZone register - COMPUTE AIPS1 Bridge Group 1 Memory Rule Register 1 (aips1_bridge_group1_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "COMPUTE AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "description": "TrustZone register - COMPUTE AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "COMPUTE AHB Peripheral 2 Slaves Rule Register 0 (ahb_peripheral2_slave_rule0)", + "description": "TrustZone register - COMPUTE AHB Peripheral 2 Slaves Rule Register 0 (ahb_peripheral2_slave_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "COMPUTE AIPS0 Bridge Group 0 Memory Rule Register 0 (aips0_bridge_group0_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS0 Bridge Group 0 Memory Rule Register 0 (aips0_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "COMPUTE AIPS0 Bridge Group 0 Memory Rule Register 1 (aips0_bridge_group0_mem_rule1)", + "description": "TrustZone register - COMPUTE AIPS0 Bridge Group 0 Memory Rule Register 1 (aips0_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "COMPUTE AIPS0 Bridge Group 1 Memory Rule Register 0 (aips0_bridge_group1_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS0 Bridge Group 1 Memory Rule Register 0 (aips0_bridge_group1_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 0 Rule 0 (apb_slave_group0_rule0)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 0 Rule 0 (apb_slave_group0_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 0 Rule 1 (apb_slave_group0_rule1)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 0 Rule 1 (apb_slave_group0_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 0 Rule 2 (apb_slave_group0_rule2)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 0 Rule 2 (apb_slave_group0_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 0 Rule 3 (apb_slave_group0_rule3)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 0 Rule 3 (apb_slave_group0_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 1 Rule 0 (apb_slave_group1_rule0)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 1 Rule 0 (apb_slave_group1_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 1 Rule 1 (apb_slave_group1_rule1)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 1 Rule 1 (apb_slave_group1_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3C0", + "offset_int": "0x3c0", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 1 Rule 2 (apb_slave_group1_rule2)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 1 Rule 2 (apb_slave_group1_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field3C4", + "offset_int": "0x3c4", + "reg_width": 32, + "name": "COMPUTE APB Bridge Peripheral 1 Rule 3 (apb_slave_group1_rule3)", + "description": "TrustZone register - COMPUTE APB Bridge Peripheral 1 Rule 3 (apb_slave_group1_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field3C8", + "offset_int": "0x3c8", + "reg_width": 32, + "name": "COMPUTE Shared APB Bridge Peripheral 0 Rule 0 (shared_apb_slave_group0_rule0)", + "description": "TrustZone register - COMPUTE Shared APB Bridge Peripheral 0 Rule 0 (shared_apb_slave_group0_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3CC", + "offset_int": "0x3cc", + "reg_width": 32, + "name": "COMPUTE Shared APB Bridge Peripheral 0 Rule 1 (shared_apb_slave_group0_rule1)", + "description": "TrustZone register - COMPUTE Shared APB Bridge Peripheral 0 Rule 1 (shared_apb_slave_group0_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3D0", + "offset_int": "0x3d0", + "reg_width": 32, + "name": "COMPUTE AIPS2 Bridge Group 0 Memory Rule Register 0 (aips2_bridge_group0_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS2 Bridge Group 0 Memory Rule Register 0 (aips2_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3D4", + "offset_int": "0x3d4", + "reg_width": 32, + "name": "COMPUTE AIPS2 Bridge Group 0 Memory Rule Register 1 (aips2_bridge_group0_mem_rule1)", + "description": "TrustZone register - COMPUTE AIPS2 Bridge Group 0 Memory Rule Register 1 (aips2_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3D8", + "offset_int": "0x3d8", + "reg_width": 32, + "name": "COMPUTE AIPS2 Bridge Group 1 Memory Rule Register 0 (aips2_bridge_group1_mem_rule0)", + "description": "TrustZone register - COMPUTE AIPS2 Bridge Group 1 Memory Rule Register 0 (aips2_bridge_group1_mem_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field3DC", + "offset_int": "0x3dc", + "reg_width": 32, + "name": "COMPUTE Sense Domain AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_sense_rule0)", + "description": "TrustZone register - COMPUTE Sense Domain AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_sense_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field3E0", + "offset_int": "0x3e0", + "reg_width": 32, + "name": "COMPUTE APB Debug Peripheral Rule Register 0 (apb_debug_mem_rule0)", + "description": "TrustZone register - COMPUTE APB Debug Peripheral Rule Register 0 (apb_debug_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field3E4", + "offset_int": "0x3e4", + "reg_width": 32, + "name": "COMPUTE APB Debug Peripheral Rule Register 1 (apb_debug_mem_rule1)", + "description": "TrustZone register - COMPUTE APB Debug Peripheral Rule Register 1 (apb_debug_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field3E8", + "offset_int": "0x3e8", + "reg_width": 32, + "name": "COMPUTE APB Debug Peripheral Rule Register 2 (apb_debug_mem_rule2)", + "description": "TrustZone register - COMPUTE APB Debug Peripheral Rule Register 2 (apb_debug_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field3EC", + "offset_int": "0x3ec", + "reg_width": 32, + "name": "COMPUTE MEDIA domain AHB peripheral slave Rule Register (media_ahb_peripheral_slave_rule0)", + "description": "TrustZone register - COMPUTE MEDIA domain AHB peripheral slave Rule Register (media_ahb_peripheral_slave_rule0)", + "default_value_int": "0x3" + }, + { + "id": "field3F0", + "offset_int": "0x3f0", + "reg_width": 32, + "name": "COMPUTE MEDIA domain APB peripheral slave Rule Register (media_apb_peripheral_slave_rule0)", + "description": "TrustZone register - COMPUTE MEDIA domain APB peripheral slave Rule Register (media_apb_peripheral_slave_rule0)", + "default_value_int": "0x3" + }, + { + "id": "field3F4", + "offset_int": "0x3f4", + "reg_width": 32, + "name": "COMPUTE EZHV SRAM Memory Rule Register (ezhv_sram_rule0)", + "description": "TrustZone register - COMPUTE EZHV SRAM Memory Rule Register (ezhv_sram_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field3F8", + "offset_int": "0x3f8", + "reg_width": 32, + "name": "COMPUTE Access enable for COMPUTE domain masters to ARB0RAM partitions Register (compute_arb0ram_access_enable)", + "description": "TrustZone register - COMPUTE Access enable for COMPUTE domain masters to ARB0RAM partitions Register (compute_arb0ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field3FC", + "offset_int": "0x3fc", + "reg_width": 32, + "name": "COMPUTE Access enable for SENSE domain masters to ARB0RAM partitions Register (sense_arb0ram_access_enable)", + "description": "TrustZone register - COMPUTE Access enable for SENSE domain masters to ARB0RAM partitions Register (sense_arb0ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field400", + "offset_int": "0x400", + "reg_width": 32, + "name": "COMPUTE Access enable for MEDIA domain masters to ARB0RAM partitions Register (media_arb0ram_access_enable)", + "description": "TrustZone register - COMPUTE Access enable for MEDIA domain masters to ARB0RAM partitions Register (media_arb0ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field404", + "offset_int": "0x404", + "reg_width": 32, + "name": "COMPUTE Access enable for NEUTRON domain masters to ARB0RAM partitions Register (neutron_arb0ram_access_enable)", + "description": "TrustZone register - COMPUTE Access enable for NEUTRON domain masters to ARB0RAM partitions Register (neutron_arb0ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field408", + "offset_int": "0x408", + "reg_width": 32, + "name": "COMPUTE Access enable for HIFI4 domain masters to ARB0RAM partitions Register (hifi4_arb0ram_access_enable)", + "description": "TrustZone register - COMPUTE Access enable for HIFI4 domain masters to ARB0RAM partitions Register (hifi4_arb0ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field40C", + "offset_int": "0x40c", + "reg_width": 32, + "name": "COMPUTE Master Secure Level Register (master_sec_level)", + "description": "TrustZone register - COMPUTE Master Secure Level Register (master_sec_level)", + "default_value_int": "0x0" + }, + { + "id": "field410", + "offset_int": "0x410", + "reg_width": 32, + "name": "COMPUTE Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - COMPUTE Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xffffffff" + }, + { + "id": "field414", + "offset_int": "0x414", + "reg_width": 32, + "name": "COMPUTE CM33 Lock Control Register 0 (cpu0_lock_reg0)", + "description": "TrustZone register - COMPUTE CM33 Lock Control Register 0 (cpu0_lock_reg0)", + "default_value_int": "0x2aa" + }, + { + "id": "field418", + "offset_int": "0x418", + "reg_width": 32, + "name": "COMPUTE Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - COMPUTE Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field41C", + "offset_int": "0x41c", + "reg_width": 32, + "name": "COMPUTE Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - COMPUTE Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field420", + "offset_int": "0x420", + "reg_width": 32, + "name": "SENSE RAM0 Memory Rule Register 0 (sram_0_rule0)", + "description": "TrustZone register - SENSE RAM0 Memory Rule Register 0 (sram_0_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field424", + "offset_int": "0x424", + "reg_width": 32, + "name": "SENSE RAM0 Memory Rule Register 1 (sram_0_rule1)", + "description": "TrustZone register - SENSE RAM0 Memory Rule Register 1 (sram_0_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field428", + "offset_int": "0x428", + "reg_width": 32, + "name": "SENSE RAM0 Memory Rule Register 2 (sram_0_rule2)", + "description": "TrustZone register - SENSE RAM0 Memory Rule Register 2 (sram_0_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field42C", + "offset_int": "0x42c", + "reg_width": 32, + "name": "SENSE RAM0 Memory Rule Register 3 (sram_0_rule3)", + "description": "TrustZone register - SENSE RAM0 Memory Rule Register 3 (sram_0_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field430", + "offset_int": "0x430", + "reg_width": 32, + "name": "SENSE RAM1 Memory Rule Register 0 (sram_1_rule0)", + "description": "TrustZone register - SENSE RAM1 Memory Rule Register 0 (sram_1_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field434", + "offset_int": "0x434", + "reg_width": 32, + "name": "SENSE RAM1 Memory Rule Register 1 (sram_1_rule1)", + "description": "TrustZone register - SENSE RAM1 Memory Rule Register 1 (sram_1_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field438", + "offset_int": "0x438", + "reg_width": 32, + "name": "SENSE RAM1 Memory Rule Register 2 (sram_1_rule2)", + "description": "TrustZone register - SENSE RAM1 Memory Rule Register 2 (sram_1_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field43C", + "offset_int": "0x43c", + "reg_width": 32, + "name": "SENSE RAM1 Memory Rule Register 3 (sram_1_rule3)", + "description": "TrustZone register - SENSE RAM1 Memory Rule Register 3 (sram_1_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field440", + "offset_int": "0x440", + "reg_width": 32, + "name": "SENSE RAM2 Memory Rule Register 0 (sram_2_rule0)", + "description": "TrustZone register - SENSE RAM2 Memory Rule Register 0 (sram_2_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field444", + "offset_int": "0x444", + "reg_width": 32, + "name": "SENSE RAM2 Memory Rule Register 1 (sram_2_rule1)", + "description": "TrustZone register - SENSE RAM2 Memory Rule Register 1 (sram_2_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field448", + "offset_int": "0x448", + "reg_width": 32, + "name": "SENSE RAM2 Memory Rule Register 2 (sram_2_rule2)", + "description": "TrustZone register - SENSE RAM2 Memory Rule Register 2 (sram_2_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field44C", + "offset_int": "0x44c", + "reg_width": 32, + "name": "SENSE RAM2 Memory Rule Register 3 (sram_2_rule3)", + "description": "TrustZone register - SENSE RAM2 Memory Rule Register 3 (sram_2_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field450", + "offset_int": "0x450", + "reg_width": 32, + "name": "SENSE RAM3 Memory Rule Register 0 (sram_3_rule0)", + "description": "TrustZone register - SENSE RAM3 Memory Rule Register 0 (sram_3_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field454", + "offset_int": "0x454", + "reg_width": 32, + "name": "SENSE RAM3 Memory Rule Register 1 (sram_3_rule1)", + "description": "TrustZone register - SENSE RAM3 Memory Rule Register 1 (sram_3_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field458", + "offset_int": "0x458", + "reg_width": 32, + "name": "SENSE RAM3 Memory Rule Register 2 (sram_3_rule2)", + "description": "TrustZone register - SENSE RAM3 Memory Rule Register 2 (sram_3_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field45C", + "offset_int": "0x45c", + "reg_width": 32, + "name": "SENSE RAM3 Memory Rule Register 3 (sram_3_rule3)", + "description": "TrustZone register - SENSE RAM3 Memory Rule Register 3 (sram_3_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field460", + "offset_int": "0x460", + "reg_width": 32, + "name": "SENSE RAM4 Memory Rule Register 0 (sram_4_rule0)", + "description": "TrustZone register - SENSE RAM4 Memory Rule Register 0 (sram_4_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field464", + "offset_int": "0x464", + "reg_width": 32, + "name": "SENSE RAM4 Memory Rule Register 1 (sram_4_rule1)", + "description": "TrustZone register - SENSE RAM4 Memory Rule Register 1 (sram_4_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field468", + "offset_int": "0x468", + "reg_width": 32, + "name": "SENSE RAM4 Memory Rule Register 2 (sram_4_rule2)", + "description": "TrustZone register - SENSE RAM4 Memory Rule Register 2 (sram_4_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field46C", + "offset_int": "0x46c", + "reg_width": 32, + "name": "SENSE RAM4 Memory Rule Register 3 (sram_4_rule3)", + "description": "TrustZone register - SENSE RAM4 Memory Rule Register 3 (sram_4_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field470", + "offset_int": "0x470", + "reg_width": 32, + "name": "SENSE RAM5 Memory Rule Register 0 (sram_5_rule0)", + "description": "TrustZone register - SENSE RAM5 Memory Rule Register 0 (sram_5_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field474", + "offset_int": "0x474", + "reg_width": 32, + "name": "SENSE RAM5 Memory Rule Register 1 (sram_5_rule1)", + "description": "TrustZone register - SENSE RAM5 Memory Rule Register 1 (sram_5_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field478", + "offset_int": "0x478", + "reg_width": 32, + "name": "SENSE RAM5 Memory Rule Register 2 (sram_5_rule2)", + "description": "TrustZone register - SENSE RAM5 Memory Rule Register 2 (sram_5_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field47C", + "offset_int": "0x47c", + "reg_width": 32, + "name": "SENSE RAM5 Memory Rule Register 3 (sram_5_rule3)", + "description": "TrustZone register - SENSE RAM5 Memory Rule Register 3 (sram_5_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field480", + "offset_int": "0x480", + "reg_width": 32, + "name": "SENSE RAM6 Memory Rule Register 0 (sram_6_rule0)", + "description": "TrustZone register - SENSE RAM6 Memory Rule Register 0 (sram_6_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field484", + "offset_int": "0x484", + "reg_width": 32, + "name": "SENSE RAM6 Memory Rule Register 1 (sram_6_rule1)", + "description": "TrustZone register - SENSE RAM6 Memory Rule Register 1 (sram_6_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field488", + "offset_int": "0x488", + "reg_width": 32, + "name": "SENSE RAM6 Memory Rule Register 2 (sram_6_rule2)", + "description": "TrustZone register - SENSE RAM6 Memory Rule Register 2 (sram_6_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field48C", + "offset_int": "0x48c", + "reg_width": 32, + "name": "SENSE RAM6 Memory Rule Register 3 (sram_6_rule3)", + "description": "TrustZone register - SENSE RAM6 Memory Rule Register 3 (sram_6_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field490", + "offset_int": "0x490", + "reg_width": 32, + "name": "SENSE RAM7 Memory Rule Register 0 (sram_7_rule0)", + "description": "TrustZone register - SENSE RAM7 Memory Rule Register 0 (sram_7_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field494", + "offset_int": "0x494", + "reg_width": 32, + "name": "SENSE RAM7 Memory Rule Register 1 (sram_7_rule1)", + "description": "TrustZone register - SENSE RAM7 Memory Rule Register 1 (sram_7_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field498", + "offset_int": "0x498", + "reg_width": 32, + "name": "SENSE RAM7 Memory Rule Register 2 (sram_7_rule2)", + "description": "TrustZone register - SENSE RAM7 Memory Rule Register 2 (sram_7_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field49C", + "offset_int": "0x49c", + "reg_width": 32, + "name": "SENSE RAM7 Memory Rule Register 3 (sram_7_rule3)", + "description": "TrustZone register - SENSE RAM7 Memory Rule Register 3 (sram_7_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4A0", + "offset_int": "0x4a0", + "reg_width": 32, + "name": "SENSE RAM8 Memory Rule Register 0 (sram_8_rule0)", + "description": "TrustZone register - SENSE RAM8 Memory Rule Register 0 (sram_8_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4A4", + "offset_int": "0x4a4", + "reg_width": 32, + "name": "SENSE RAM8 Memory Rule Register 1 (sram_8_rule1)", + "description": "TrustZone register - SENSE RAM8 Memory Rule Register 1 (sram_8_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4A8", + "offset_int": "0x4a8", + "reg_width": 32, + "name": "SENSE RAM8 Memory Rule Register 2 (sram_8_rule2)", + "description": "TrustZone register - SENSE RAM8 Memory Rule Register 2 (sram_8_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4AC", + "offset_int": "0x4ac", + "reg_width": 32, + "name": "SENSE RAM8 Memory Rule Register 3 (sram_8_rule3)", + "description": "TrustZone register - SENSE RAM8 Memory Rule Register 3 (sram_8_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4B0", + "offset_int": "0x4b0", + "reg_width": 32, + "name": "SENSE RAM9 Memory Rule Register 0 (sram_9_rule0)", + "description": "TrustZone register - SENSE RAM9 Memory Rule Register 0 (sram_9_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4B4", + "offset_int": "0x4b4", + "reg_width": 32, + "name": "SENSE RAM9 Memory Rule Register 1 (sram_9_rule1)", + "description": "TrustZone register - SENSE RAM9 Memory Rule Register 1 (sram_9_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4B8", + "offset_int": "0x4b8", + "reg_width": 32, + "name": "SENSE RAM9 Memory Rule Register 2 (sram_9_rule2)", + "description": "TrustZone register - SENSE RAM9 Memory Rule Register 2 (sram_9_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4BC", + "offset_int": "0x4bc", + "reg_width": 32, + "name": "SENSE RAM9 Memory Rule Register 3 (sram_9_rule3)", + "description": "TrustZone register - SENSE RAM9 Memory Rule Register 3 (sram_9_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4C0", + "offset_int": "0x4c0", + "reg_width": 32, + "name": "SENSE RAM10 Memory Rule Register 0 (sram_10_rule0)", + "description": "TrustZone register - SENSE RAM10 Memory Rule Register 0 (sram_10_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4C4", + "offset_int": "0x4c4", + "reg_width": 32, + "name": "SENSE RAM10 Memory Rule Register 1 (sram_10_rule1)", + "description": "TrustZone register - SENSE RAM10 Memory Rule Register 1 (sram_10_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4C8", + "offset_int": "0x4c8", + "reg_width": 32, + "name": "SENSE RAM10 Memory Rule Register 2 (sram_10_rule2)", + "description": "TrustZone register - SENSE RAM10 Memory Rule Register 2 (sram_10_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4CC", + "offset_int": "0x4cc", + "reg_width": 32, + "name": "SENSE RAM10 Memory Rule Register 3 (sram_10_rule3)", + "description": "TrustZone register - SENSE RAM10 Memory Rule Register 3 (sram_10_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4D0", + "offset_int": "0x4d0", + "reg_width": 32, + "name": "SENSE RAM11 Memory Rule Register 0 (sram_11_rule0)", + "description": "TrustZone register - SENSE RAM11 Memory Rule Register 0 (sram_11_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4D4", + "offset_int": "0x4d4", + "reg_width": 32, + "name": "SENSE RAM11 Memory Rule Register 1 (sram_11_rule1)", + "description": "TrustZone register - SENSE RAM11 Memory Rule Register 1 (sram_11_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4D8", + "offset_int": "0x4d8", + "reg_width": 32, + "name": "SENSE RAM11 Memory Rule Register 2 (sram_11_rule2)", + "description": "TrustZone register - SENSE RAM11 Memory Rule Register 2 (sram_11_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4DC", + "offset_int": "0x4dc", + "reg_width": 32, + "name": "SENSE RAM11 Memory Rule Register 3 (sram_11_rule3)", + "description": "TrustZone register - SENSE RAM11 Memory Rule Register 3 (sram_11_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4E0", + "offset_int": "0x4e0", + "reg_width": 32, + "name": "SENSE RAM12 Memory Rule Register 0 (sram_12_rule0)", + "description": "TrustZone register - SENSE RAM12 Memory Rule Register 0 (sram_12_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4E4", + "offset_int": "0x4e4", + "reg_width": 32, + "name": "SENSE RAM12 Memory Rule Register 1 (sram_12_rule1)", + "description": "TrustZone register - SENSE RAM12 Memory Rule Register 1 (sram_12_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4E8", + "offset_int": "0x4e8", + "reg_width": 32, + "name": "SENSE RAM12 Memory Rule Register 2 (sram_12_rule2)", + "description": "TrustZone register - SENSE RAM12 Memory Rule Register 2 (sram_12_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4EC", + "offset_int": "0x4ec", + "reg_width": 32, + "name": "SENSE RAM12 Memory Rule Register 3 (sram_12_rule3)", + "description": "TrustZone register - SENSE RAM12 Memory Rule Register 3 (sram_12_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field4F0", + "offset_int": "0x4f0", + "reg_width": 32, + "name": "SENSE RAM13 Memory Rule Register 0 (sram_13_rule0)", + "description": "TrustZone register - SENSE RAM13 Memory Rule Register 0 (sram_13_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field4F4", + "offset_int": "0x4f4", + "reg_width": 32, + "name": "SENSE RAM13 Memory Rule Register 1 (sram_13_rule1)", + "description": "TrustZone register - SENSE RAM13 Memory Rule Register 1 (sram_13_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field4F8", + "offset_int": "0x4f8", + "reg_width": 32, + "name": "SENSE RAM13 Memory Rule Register 2 (sram_13_rule2)", + "description": "TrustZone register - SENSE RAM13 Memory Rule Register 2 (sram_13_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field4FC", + "offset_int": "0x4fc", + "reg_width": 32, + "name": "SENSE RAM13 Memory Rule Register 3 (sram_13_rule3)", + "description": "TrustZone register - SENSE RAM13 Memory Rule Register 3 (sram_13_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field500", + "offset_int": "0x500", + "reg_width": 32, + "name": "SENSE RAM14 Memory Rule Register 0 (sram_14_rule0)", + "description": "TrustZone register - SENSE RAM14 Memory Rule Register 0 (sram_14_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field504", + "offset_int": "0x504", + "reg_width": 32, + "name": "SENSE RAM14 Memory Rule Register 1 (sram_14_rule1)", + "description": "TrustZone register - SENSE RAM14 Memory Rule Register 1 (sram_14_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field508", + "offset_int": "0x508", + "reg_width": 32, + "name": "SENSE RAM14 Memory Rule Register 2 (sram_14_rule2)", + "description": "TrustZone register - SENSE RAM14 Memory Rule Register 2 (sram_14_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field50C", + "offset_int": "0x50c", + "reg_width": 32, + "name": "SENSE RAM14 Memory Rule Register 3 (sram_14_rule3)", + "description": "TrustZone register - SENSE RAM14 Memory Rule Register 3 (sram_14_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field510", + "offset_int": "0x510", + "reg_width": 32, + "name": "SENSE RAM15 Memory Rule Register 0 (sram_15_rule0)", + "description": "TrustZone register - SENSE RAM15 Memory Rule Register 0 (sram_15_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field514", + "offset_int": "0x514", + "reg_width": 32, + "name": "SENSE RAM15 Memory Rule Register 1 (sram_15_rule1)", + "description": "TrustZone register - SENSE RAM15 Memory Rule Register 1 (sram_15_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field518", + "offset_int": "0x518", + "reg_width": 32, + "name": "SENSE RAM15 Memory Rule Register 2 (sram_15_rule2)", + "description": "TrustZone register - SENSE RAM15 Memory Rule Register 2 (sram_15_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field51C", + "offset_int": "0x51c", + "reg_width": 32, + "name": "SENSE RAM15 Memory Rule Register 3 (sram_15_rule3)", + "description": "TrustZone register - SENSE RAM15 Memory Rule Register 3 (sram_15_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field520", + "offset_int": "0x520", + "reg_width": 32, + "name": "SENSE RAM16 Memory Rule Register 0 (sram_16_rule0)", + "description": "TrustZone register - SENSE RAM16 Memory Rule Register 0 (sram_16_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field524", + "offset_int": "0x524", + "reg_width": 32, + "name": "SENSE RAM16 Memory Rule Register 1 (sram_16_rule1)", + "description": "TrustZone register - SENSE RAM16 Memory Rule Register 1 (sram_16_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field528", + "offset_int": "0x528", + "reg_width": 32, + "name": "SENSE RAM16 Memory Rule Register 2 (sram_16_rule2)", + "description": "TrustZone register - SENSE RAM16 Memory Rule Register 2 (sram_16_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field52C", + "offset_int": "0x52c", + "reg_width": 32, + "name": "SENSE RAM16 Memory Rule Register 3 (sram_16_rule3)", + "description": "TrustZone register - SENSE RAM16 Memory Rule Register 3 (sram_16_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field530", + "offset_int": "0x530", + "reg_width": 32, + "name": "SENSE RAM17 Memory Rule Register 0 (sram_17_rule0)", + "description": "TrustZone register - SENSE RAM17 Memory Rule Register 0 (sram_17_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field534", + "offset_int": "0x534", + "reg_width": 32, + "name": "SENSE RAM17 Memory Rule Register 1 (sram_17_rule1)", + "description": "TrustZone register - SENSE RAM17 Memory Rule Register 1 (sram_17_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field538", + "offset_int": "0x538", + "reg_width": 32, + "name": "SENSE RAM17 Memory Rule Register 2 (sram_17_rule2)", + "description": "TrustZone register - SENSE RAM17 Memory Rule Register 2 (sram_17_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field53C", + "offset_int": "0x53c", + "reg_width": 32, + "name": "SENSE RAM17 Memory Rule Register 3 (sram_17_rule3)", + "description": "TrustZone register - SENSE RAM17 Memory Rule Register 3 (sram_17_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field540", + "offset_int": "0x540", + "reg_width": 32, + "name": "SENSE RAM18 Memory Rule Register 0 (sram_18_rule0)", + "description": "TrustZone register - SENSE RAM18 Memory Rule Register 0 (sram_18_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field544", + "offset_int": "0x544", + "reg_width": 32, + "name": "SENSE RAM18 Memory Rule Register 1 (sram_18_rule1)", + "description": "TrustZone register - SENSE RAM18 Memory Rule Register 1 (sram_18_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field548", + "offset_int": "0x548", + "reg_width": 32, + "name": "SENSE RAM18 Memory Rule Register 2 (sram_18_rule2)", + "description": "TrustZone register - SENSE RAM18 Memory Rule Register 2 (sram_18_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field54C", + "offset_int": "0x54c", + "reg_width": 32, + "name": "SENSE RAM18 Memory Rule Register 3 (sram_18_rule3)", + "description": "TrustZone register - SENSE RAM18 Memory Rule Register 3 (sram_18_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field550", + "offset_int": "0x550", + "reg_width": 32, + "name": "SENSE RAM19 Memory Rule Register 0 (sram_19_rule0)", + "description": "TrustZone register - SENSE RAM19 Memory Rule Register 0 (sram_19_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field554", + "offset_int": "0x554", + "reg_width": 32, + "name": "SENSE RAM19 Memory Rule Register 1 (sram_19_rule1)", + "description": "TrustZone register - SENSE RAM19 Memory Rule Register 1 (sram_19_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field558", + "offset_int": "0x558", + "reg_width": 32, + "name": "SENSE RAM19 Memory Rule Register 2 (sram_19_rule2)", + "description": "TrustZone register - SENSE RAM19 Memory Rule Register 2 (sram_19_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field55C", + "offset_int": "0x55c", + "reg_width": 32, + "name": "SENSE RAM19 Memory Rule Register 3 (sram_19_rule3)", + "description": "TrustZone register - SENSE RAM19 Memory Rule Register 3 (sram_19_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field560", + "offset_int": "0x560", + "reg_width": 32, + "name": "SENSE RAM20 Memory Rule Register 0 (sram_20_rule0)", + "description": "TrustZone register - SENSE RAM20 Memory Rule Register 0 (sram_20_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field564", + "offset_int": "0x564", + "reg_width": 32, + "name": "SENSE RAM20 Memory Rule Register 1 (sram_20_rule1)", + "description": "TrustZone register - SENSE RAM20 Memory Rule Register 1 (sram_20_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field568", + "offset_int": "0x568", + "reg_width": 32, + "name": "SENSE RAM20 Memory Rule Register 2 (sram_20_rule2)", + "description": "TrustZone register - SENSE RAM20 Memory Rule Register 2 (sram_20_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field56C", + "offset_int": "0x56c", + "reg_width": 32, + "name": "SENSE RAM20 Memory Rule Register 3 (sram_20_rule3)", + "description": "TrustZone register - SENSE RAM20 Memory Rule Register 3 (sram_20_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field570", + "offset_int": "0x570", + "reg_width": 32, + "name": "SENSE RAM21 Memory Rule Register 0 (sram_21_rule0)", + "description": "TrustZone register - SENSE RAM21 Memory Rule Register 0 (sram_21_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field574", + "offset_int": "0x574", + "reg_width": 32, + "name": "SENSE RAM21 Memory Rule Register 1 (sram_21_rule1)", + "description": "TrustZone register - SENSE RAM21 Memory Rule Register 1 (sram_21_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field578", + "offset_int": "0x578", + "reg_width": 32, + "name": "SENSE RAM21 Memory Rule Register 2 (sram_21_rule2)", + "description": "TrustZone register - SENSE RAM21 Memory Rule Register 2 (sram_21_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field57C", + "offset_int": "0x57c", + "reg_width": 32, + "name": "SENSE RAM21 Memory Rule Register 3 (sram_21_rule3)", + "description": "TrustZone register - SENSE RAM21 Memory Rule Register 3 (sram_21_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field580", + "offset_int": "0x580", + "reg_width": 32, + "name": "SENSE RAM22 Memory Rule Register 0 (sram_22_rule0)", + "description": "TrustZone register - SENSE RAM22 Memory Rule Register 0 (sram_22_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field584", + "offset_int": "0x584", + "reg_width": 32, + "name": "SENSE RAM22 Memory Rule Register 1 (sram_22_rule1)", + "description": "TrustZone register - SENSE RAM22 Memory Rule Register 1 (sram_22_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field588", + "offset_int": "0x588", + "reg_width": 32, + "name": "SENSE RAM22 Memory Rule Register 2 (sram_22_rule2)", + "description": "TrustZone register - SENSE RAM22 Memory Rule Register 2 (sram_22_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field58C", + "offset_int": "0x58c", + "reg_width": 32, + "name": "SENSE RAM22 Memory Rule Register 3 (sram_22_rule3)", + "description": "TrustZone register - SENSE RAM22 Memory Rule Register 3 (sram_22_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field590", + "offset_int": "0x590", + "reg_width": 32, + "name": "SENSE RAM23 Memory Rule Register 0 (sram_23_rule0)", + "description": "TrustZone register - SENSE RAM23 Memory Rule Register 0 (sram_23_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field594", + "offset_int": "0x594", + "reg_width": 32, + "name": "SENSE RAM23 Memory Rule Register 1 (sram_23_rule1)", + "description": "TrustZone register - SENSE RAM23 Memory Rule Register 1 (sram_23_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field598", + "offset_int": "0x598", + "reg_width": 32, + "name": "SENSE RAM23 Memory Rule Register 2 (sram_23_rule2)", + "description": "TrustZone register - SENSE RAM23 Memory Rule Register 2 (sram_23_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field59C", + "offset_int": "0x59c", + "reg_width": 32, + "name": "SENSE RAM23 Memory Rule Register 3 (sram_23_rule3)", + "description": "TrustZone register - SENSE RAM23 Memory Rule Register 3 (sram_23_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5A0", + "offset_int": "0x5a0", + "reg_width": 32, + "name": "SENSE RAM24 Memory Rule Register 0 (sram_24_rule0)", + "description": "TrustZone register - SENSE RAM24 Memory Rule Register 0 (sram_24_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5A4", + "offset_int": "0x5a4", + "reg_width": 32, + "name": "SENSE RAM24 Memory Rule Register 1 (sram_24_rule1)", + "description": "TrustZone register - SENSE RAM24 Memory Rule Register 1 (sram_24_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5A8", + "offset_int": "0x5a8", + "reg_width": 32, + "name": "SENSE RAM24 Memory Rule Register 2 (sram_24_rule2)", + "description": "TrustZone register - SENSE RAM24 Memory Rule Register 2 (sram_24_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5AC", + "offset_int": "0x5ac", + "reg_width": 32, + "name": "SENSE RAM24 Memory Rule Register 3 (sram_24_rule3)", + "description": "TrustZone register - SENSE RAM24 Memory Rule Register 3 (sram_24_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5B0", + "offset_int": "0x5b0", + "reg_width": 32, + "name": "SENSE RAM25 Memory Rule Register 0 (sram_25_rule0)", + "description": "TrustZone register - SENSE RAM25 Memory Rule Register 0 (sram_25_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5B4", + "offset_int": "0x5b4", + "reg_width": 32, + "name": "SENSE RAM25 Memory Rule Register 1 (sram_25_rule1)", + "description": "TrustZone register - SENSE RAM25 Memory Rule Register 1 (sram_25_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5B8", + "offset_int": "0x5b8", + "reg_width": 32, + "name": "SENSE RAM25 Memory Rule Register 2 (sram_25_rule2)", + "description": "TrustZone register - SENSE RAM25 Memory Rule Register 2 (sram_25_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5BC", + "offset_int": "0x5bc", + "reg_width": 32, + "name": "SENSE RAM25 Memory Rule Register 3 (sram_25_rule3)", + "description": "TrustZone register - SENSE RAM25 Memory Rule Register 3 (sram_25_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5C0", + "offset_int": "0x5c0", + "reg_width": 32, + "name": "SENSE RAM26 Memory Rule Register 0 (sram_26_rule0)", + "description": "TrustZone register - SENSE RAM26 Memory Rule Register 0 (sram_26_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5C4", + "offset_int": "0x5c4", + "reg_width": 32, + "name": "SENSE RAM26 Memory Rule Register 1 (sram_26_rule1)", + "description": "TrustZone register - SENSE RAM26 Memory Rule Register 1 (sram_26_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5C8", + "offset_int": "0x5c8", + "reg_width": 32, + "name": "SENSE RAM26 Memory Rule Register 2 (sram_26_rule2)", + "description": "TrustZone register - SENSE RAM26 Memory Rule Register 2 (sram_26_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5CC", + "offset_int": "0x5cc", + "reg_width": 32, + "name": "SENSE RAM26 Memory Rule Register 3 (sram_26_rule3)", + "description": "TrustZone register - SENSE RAM26 Memory Rule Register 3 (sram_26_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5D0", + "offset_int": "0x5d0", + "reg_width": 32, + "name": "SENSE RAM27 Memory Rule Register 0 (sram_27_rule0)", + "description": "TrustZone register - SENSE RAM27 Memory Rule Register 0 (sram_27_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5D4", + "offset_int": "0x5d4", + "reg_width": 32, + "name": "SENSE RAM27 Memory Rule Register 1 (sram_27_rule1)", + "description": "TrustZone register - SENSE RAM27 Memory Rule Register 1 (sram_27_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5D8", + "offset_int": "0x5d8", + "reg_width": 32, + "name": "SENSE RAM27 Memory Rule Register 2 (sram_27_rule2)", + "description": "TrustZone register - SENSE RAM27 Memory Rule Register 2 (sram_27_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5DC", + "offset_int": "0x5dc", + "reg_width": 32, + "name": "SENSE RAM27 Memory Rule Register 3 (sram_27_rule3)", + "description": "TrustZone register - SENSE RAM27 Memory Rule Register 3 (sram_27_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5E0", + "offset_int": "0x5e0", + "reg_width": 32, + "name": "SENSE RAM28 Memory Rule Register 0 (sram_28_rule0)", + "description": "TrustZone register - SENSE RAM28 Memory Rule Register 0 (sram_28_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5E4", + "offset_int": "0x5e4", + "reg_width": 32, + "name": "SENSE RAM28 Memory Rule Register 1 (sram_28_rule1)", + "description": "TrustZone register - SENSE RAM28 Memory Rule Register 1 (sram_28_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5E8", + "offset_int": "0x5e8", + "reg_width": 32, + "name": "SENSE RAM28 Memory Rule Register 2 (sram_28_rule2)", + "description": "TrustZone register - SENSE RAM28 Memory Rule Register 2 (sram_28_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5EC", + "offset_int": "0x5ec", + "reg_width": 32, + "name": "SENSE RAM28 Memory Rule Register 3 (sram_28_rule3)", + "description": "TrustZone register - SENSE RAM28 Memory Rule Register 3 (sram_28_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field5F0", + "offset_int": "0x5f0", + "reg_width": 32, + "name": "SENSE RAM29 Memory Rule Register 0 (sram_29_rule0)", + "description": "TrustZone register - SENSE RAM29 Memory Rule Register 0 (sram_29_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field5F4", + "offset_int": "0x5f4", + "reg_width": 32, + "name": "SENSE RAM29 Memory Rule Register 1 (sram_29_rule1)", + "description": "TrustZone register - SENSE RAM29 Memory Rule Register 1 (sram_29_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field5F8", + "offset_int": "0x5f8", + "reg_width": 32, + "name": "SENSE RAM29 Memory Rule Register 2 (sram_29_rule2)", + "description": "TrustZone register - SENSE RAM29 Memory Rule Register 2 (sram_29_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field5FC", + "offset_int": "0x5fc", + "reg_width": 32, + "name": "SENSE RAM29 Memory Rule Register 3 (sram_29_rule3)", + "description": "TrustZone register - SENSE RAM29 Memory Rule Register 3 (sram_29_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field600", + "offset_int": "0x600", + "reg_width": 32, + "name": "SENSE AHB Peripheral 10 Slaves Rule Register 0 (ahb_peripheral10_slave_rule0)", + "description": "TrustZone register - SENSE AHB Peripheral 10 Slaves Rule Register 0 (ahb_peripheral10_slave_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field604", + "offset_int": "0x604", + "reg_width": 32, + "name": "SENSE AIPS5 Bridge Group 0 Memory Rule Register 0 (aips5_bridge_group0_mem_rule0)", + "description": "TrustZone register - SENSE AIPS5 Bridge Group 0 Memory Rule Register 0 (aips5_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field608", + "offset_int": "0x608", + "reg_width": 32, + "name": "SENSE AIPS5 Bridge Group 0 Memory Rule Register 1 (aips5_bridge_group0_mem_rule1)", + "description": "TrustZone register - SENSE AIPS5 Bridge Group 0 Memory Rule Register 1 (aips5_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field60C", + "offset_int": "0x60c", + "reg_width": 32, + "name": "SENSE AIPS5 Bridge Group 0 Memory Rule Register 2 (aips5_bridge_group0_mem_rule2)", + "description": "TrustZone register - SENSE AIPS5 Bridge Group 0 Memory Rule Register 2 (aips5_bridge_group0_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field610", + "offset_int": "0x610", + "reg_width": 32, + "name": "SENSE AIPS5 Bridge Group 0 Memory Rule Register 3 (aips5_bridge_group0_mem_rule3)", + "description": "TrustZone register - SENSE AIPS5 Bridge Group 0 Memory Rule Register 3 (aips5_bridge_group0_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field614", + "offset_int": "0x614", + "reg_width": 32, + "name": "SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 0 (ahb_peripheral10_slave_hsgpio_rule0)", + "description": "TrustZone register - SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 0 (ahb_peripheral10_slave_hsgpio_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field618", + "offset_int": "0x618", + "reg_width": 32, + "name": "SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 1 (ahb_peripheral10_slave_hsgpio_rule1)", + "description": "TrustZone register - SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 1 (ahb_peripheral10_slave_hsgpio_rule1)", + "default_value_int": "0x33" + }, + { + "id": "field61C", + "offset_int": "0x61c", + "reg_width": 32, + "name": "SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 2 (ahb_peripheral10_slave_hsgpio_rule2)", + "description": "TrustZone register - SENSE AHB Peripheral 10 Slaves HSGPIO Rule Register 2 (ahb_peripheral10_slave_hsgpio_rule2)", + "default_value_int": "0x33" + }, + { + "id": "field620", + "offset_int": "0x620", + "reg_width": 32, + "name": "SENSE AIPS2 Bridge Group 0 Memory Rule Register 0 (aips2_bridge_group0_mem_rule0)", + "description": "TrustZone register - SENSE AIPS2 Bridge Group 0 Memory Rule Register 0 (aips2_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field624", + "offset_int": "0x624", + "reg_width": 32, + "name": "SENSE AIPS2 Bridge Group 0 Memory Rule Register 1 (aips2_bridge_group0_mem_rule1)", + "description": "TrustZone register - SENSE AIPS2 Bridge Group 0 Memory Rule Register 1 (aips2_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field628", + "offset_int": "0x628", + "reg_width": 32, + "name": "SENSE AIPS2 Bridge Group 1 Memory Rule Register 0 (aips2_bridge_group1_mem_rule0)", + "description": "TrustZone register - SENSE AIPS2 Bridge Group 1 Memory Rule Register 0 (aips2_bridge_group1_mem_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field62C", + "offset_int": "0x62c", + "reg_width": 32, + "name": "SENSE AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "description": "TrustZone register - SENSE AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field630", + "offset_int": "0x630", + "reg_width": 32, + "name": "SENSE APB Debug Peripheral Rule Register 0 (apb_debug_mem_rule0)", + "description": "TrustZone register - SENSE APB Debug Peripheral Rule Register 0 (apb_debug_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field634", + "offset_int": "0x634", + "reg_width": 32, + "name": "SENSE APB Debug Peripheral Rule Register 1 (apb_debug_mem_rule1)", + "description": "TrustZone register - SENSE APB Debug Peripheral Rule Register 1 (apb_debug_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field638", + "offset_int": "0x638", + "reg_width": 32, + "name": "SENSE APB Debug Peripheral Rule Register 2 (apb_debug_mem_rule2)", + "description": "TrustZone register - SENSE APB Debug Peripheral Rule Register 2 (apb_debug_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field63C", + "offset_int": "0x63c", + "reg_width": 32, + "name": "SENSE APB Bridge Peripheral 0 Rule 0 (sense_apb_slave_group0_rule0)", + "description": "TrustZone register - SENSE APB Bridge Peripheral 0 Rule 0 (sense_apb_slave_group0_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field640", + "offset_int": "0x640", + "reg_width": 32, + "name": "SENSE APB Bridge Peripheral 0 Rule 1 (sense_apb_slave_group0_rule1)", + "description": "TrustZone register - SENSE APB Bridge Peripheral 0 Rule 1 (sense_apb_slave_group0_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field644", + "offset_int": "0x644", + "reg_width": 32, + "name": "SENSE APB Bridge Peripheral 0 Rule 2 (sense_apb_slave_group0_rule2)", + "description": "TrustZone register - SENSE APB Bridge Peripheral 0 Rule 2 (sense_apb_slave_group0_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field648", + "offset_int": "0x648", + "reg_width": 32, + "name": "SENSE Shared APB Bridge Peripheral 0 Rule 0 (shared_apb_slave_group0_rule0)", + "description": "TrustZone register - SENSE Shared APB Bridge Peripheral 0 Rule 0 (shared_apb_slave_group0_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field64C", + "offset_int": "0x64c", + "reg_width": 32, + "name": "SENSE Shared APB Bridge Peripheral 0 Rule 1 (shared_apb_slave_group0_rule1)", + "description": "TrustZone register - SENSE Shared APB Bridge Peripheral 0 Rule 1 (shared_apb_slave_group0_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field650", + "offset_int": "0x650", + "reg_width": 32, + "name": "SENSE SENSE domain to MEDIA domain Access Rule Register (sense2media_rule)", + "description": "TrustZone register - SENSE SENSE domain to MEDIA domain Access Rule Register (sense2media_rule)", + "default_value_int": "0x3" + }, + { + "id": "field654", + "offset_int": "0x654", + "reg_width": 32, + "name": "SENSE MEDIA domain AHB peripheral slave Rule Register (media_ahb_peripheral_slave_rule0)", + "description": "TrustZone register - SENSE MEDIA domain AHB peripheral slave Rule Register (media_ahb_peripheral_slave_rule0)", + "default_value_int": "0x3" + }, + { + "id": "field658", + "offset_int": "0x658", + "reg_width": 32, + "name": "SENSE MEDIA domain APB peripheral slave Rule Register (media_apb_peripheral_slave_rule0)", + "description": "TrustZone register - SENSE MEDIA domain APB peripheral slave Rule Register (media_apb_peripheral_slave_rule0)", + "default_value_int": "0x3" + }, + { + "id": "field65C", + "offset_int": "0x65c", + "reg_width": 32, + "name": "SENSE EZHV SRAM Memory Rule Register (ezhv_sram_rule0)", + "description": "TrustZone register - SENSE EZHV SRAM Memory Rule Register (ezhv_sram_rule0)", + "default_value_int": "0x3" + }, + { + "id": "field660", + "offset_int": "0x660", + "reg_width": 32, + "name": "SENSE Access enable for COMPUTE domain masters to ARB1RAM partitions Register (compute_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for COMPUTE domain masters to ARB1RAM partitions Register (compute_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field664", + "offset_int": "0x664", + "reg_width": 32, + "name": "SENSE Access enable for SENSE domain masters to ARB1RAM partitions Register (sense_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for SENSE domain masters to ARB1RAM partitions Register (sense_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field668", + "offset_int": "0x668", + "reg_width": 32, + "name": "SENSE Access enable for MEDIA domain masters to ARB1RAM partitions Register (media_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for MEDIA domain masters to ARB1RAM partitions Register (media_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field66C", + "offset_int": "0x66c", + "reg_width": 32, + "name": "SENSE Access enable for NEUTRON domain masters to ARB1RAM partitions Register (neutron_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for NEUTRON domain masters to ARB1RAM partitions Register (neutron_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field670", + "offset_int": "0x670", + "reg_width": 32, + "name": "SENSE Access enable for HIFI4 domain masters to ARB1RAM partitions Register (hifi4_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for HIFI4 domain masters to ARB1RAM partitions Register (hifi4_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field674", + "offset_int": "0x674", + "reg_width": 32, + "name": "SENSE Access enable for HIFI1 domain masters to ARB1RAM partitions Register (hifi1_arb1ram_access_enable)", + "description": "TrustZone register - SENSE Access enable for HIFI1 domain masters to ARB1RAM partitions Register (hifi1_arb1ram_access_enable)", + "default_value_int": "0x3fffffff" + }, + { + "id": "field678", + "offset_int": "0x678", + "reg_width": 32, + "name": "SENSE Access enable for COMPUTE domain masters to common APB peripherals (compute_apb_peripheral_access_enable)", + "description": "TrustZone register - SENSE Access enable for COMPUTE domain masters to common APB peripherals (compute_apb_peripheral_access_enable)", + "default_value_int": "0xfff" + }, + { + "id": "field67C", + "offset_int": "0x67c", + "reg_width": 32, + "name": "SENSE Access enable for SENSE domain masters to common APB peripherals (sense_apb_peripheral_access_enable)", + "description": "TrustZone register - SENSE Access enable for SENSE domain masters to common APB peripherals (sense_apb_peripheral_access_enable)", + "default_value_int": "0xfff" + }, + { + "id": "field680", + "offset_int": "0x680", + "reg_width": 32, + "name": "SENSE Access enable for COMPUTE domain masters to common AIPS peripherals (compute_aips_peripheral_access_enable)", + "description": "TrustZone register - SENSE Access enable for COMPUTE domain masters to common AIPS peripherals (compute_aips_peripheral_access_enable)", + "default_value_int": "0xfffff" + }, + { + "id": "field684", + "offset_int": "0x684", + "reg_width": 32, + "name": "SENSE Access enable for SENSE domain masters to common AIPS peripherals (sense_aips_peripheral_access_enable)", + "description": "TrustZone register - SENSE Access enable for SENSE domain masters to common AIPS peripherals (sense_aips_peripheral_access_enable)", + "default_value_int": "0xfffff" + }, + { + "id": "field688", + "offset_int": "0x688", + "reg_width": 32, + "name": "SENSE Master Secure Level Register (master_sec_level)", + "description": "TrustZone register - SENSE Master Secure Level Register (master_sec_level)", + "default_value_int": "0x0" + }, + { + "id": "field68C", + "offset_int": "0x68c", + "reg_width": 32, + "name": "SENSE Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - SENSE Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xffffffff" + }, + { + "id": "field690", + "offset_int": "0x690", + "reg_width": 32, + "name": "SENSE CM33 Lock Control Register 0 (cpu0_lock_reg0)", + "description": "TrustZone register - SENSE CM33 Lock Control Register 0 (cpu0_lock_reg0)", + "default_value_int": "0x2aa" + }, + { + "id": "field694", + "offset_int": "0x694", + "reg_width": 32, + "name": "SENSE Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - SENSE Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field698", + "offset_int": "0x698", + "reg_width": 32, + "name": "SENSE Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - SENSE Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field69C", + "offset_int": "0x69c", + "reg_width": 32, + "name": "MEDIA AHB peripheral 0 Rule Register (ahb_peripheral_slave_p0_slave_rule0)", + "description": "TrustZone register - MEDIA AHB peripheral 0 Rule Register (ahb_peripheral_slave_p0_slave_rule0)", + "default_value_int": "0x333" + }, + { + "id": "field6A0", + "offset_int": "0x6a0", + "reg_width": 32, + "name": "MEDIA AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "description": "TrustZone register - MEDIA AHB Secure Control Peripheral Rule 0 (ahb_secure_ctrl_peripheral_rule0)", + "default_value_int": "0x3333" + }, + { + "id": "field6A4", + "offset_int": "0x6a4", + "reg_width": 32, + "name": "MEDIA AIPS4 Bridge Group 0 Memory Rule Register 0 (aips4_bridge_group0_mem_rule0)", + "description": "TrustZone register - MEDIA AIPS4 Bridge Group 0 Memory Rule Register 0 (aips4_bridge_group0_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field6A8", + "offset_int": "0x6a8", + "reg_width": 32, + "name": "MEDIA AIPS4 Bridge Group 0 Memory Rule Register 1 (aips4_bridge_group0_mem_rule1)", + "description": "TrustZone register - MEDIA AIPS4 Bridge Group 0 Memory Rule Register 1 (aips4_bridge_group0_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field6AC", + "offset_int": "0x6ac", + "reg_width": 32, + "name": "MEDIA AHB peripheral 1 Rule Register (ahb_peripheral_slave_p1_slave_rule0)", + "description": "TrustZone register - MEDIA AHB peripheral 1 Rule Register (ahb_peripheral_slave_p1_slave_rule0)", + "default_value_int": "0x33333" + }, + { + "id": "field6B0", + "offset_int": "0x6b0", + "reg_width": 32, + "name": "MEDIA APB peripheral slave Rule Register 0 (media_apb_peripheral_slave_rule0)", + "description": "TrustZone register - MEDIA APB peripheral slave Rule Register 0 (media_apb_peripheral_slave_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field6B4", + "offset_int": "0x6b4", + "reg_width": 32, + "name": "MEDIA APB peripheral slave Rule Register 0 (media_apb_peripheral_slave_rule1)", + "description": "TrustZone register - MEDIA APB peripheral slave Rule Register 0 (media_apb_peripheral_slave_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field6B8", + "offset_int": "0x6b8", + "reg_width": 32, + "name": "MEDIA EZHV SRAM Memory Rule Register 0 (ezhv_sram_rule0)", + "description": "TrustZone register - MEDIA EZHV SRAM Memory Rule Register 0 (ezhv_sram_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field6BC", + "offset_int": "0x6bc", + "reg_width": 32, + "name": "MEDIA EZHV SRAM Memory Rule Register 1 (ezhv_sram_rule1)", + "description": "TrustZone register - MEDIA EZHV SRAM Memory Rule Register 1 (ezhv_sram_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field6C0", + "offset_int": "0x6c0", + "reg_width": 32, + "name": "MEDIA EZHV SRAM Memory Rule Register 2 (ezhv_sram_rule2)", + "description": "TrustZone register - MEDIA EZHV SRAM Memory Rule Register 2 (ezhv_sram_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field6C4", + "offset_int": "0x6c4", + "reg_width": 32, + "name": "MEDIA EZHV SRAM Memory Rule Register 3 (ezhv_sram_rule3)", + "description": "TrustZone register - MEDIA EZHV SRAM Memory Rule Register 3 (ezhv_sram_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field6C8", + "offset_int": "0x6c8", + "reg_width": 32, + "name": "MEDIA RAM0 Memory Rule Register 0 (sram_0_rule0)", + "description": "TrustZone register - MEDIA RAM0 Memory Rule Register 0 (sram_0_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field6CC", + "offset_int": "0x6cc", + "reg_width": 32, + "name": "MEDIA RAM0 Memory Rule Register 1 (sram_0_rule1)", + "description": "TrustZone register - MEDIA RAM0 Memory Rule Register 1 (sram_0_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field6D0", + "offset_int": "0x6d0", + "reg_width": 32, + "name": "MEDIA RAM0 Memory Rule Register 2 (sram_0_rule2)", + "description": "TrustZone register - MEDIA RAM0 Memory Rule Register 2 (sram_0_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field6D4", + "offset_int": "0x6d4", + "reg_width": 32, + "name": "MEDIA RAM0 Memory Rule Register 3 (sram_0_rule3)", + "description": "TrustZone register - MEDIA RAM0 Memory Rule Register 3 (sram_0_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field6D8", + "offset_int": "0x6d8", + "reg_width": 32, + "name": "MEDIA RAM1 Memory Rule Register 0 (sram_1_rule0)", + "description": "TrustZone register - MEDIA RAM1 Memory Rule Register 0 (sram_1_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field6DC", + "offset_int": "0x6dc", + "reg_width": 32, + "name": "MEDIA RAM1 Memory Rule Register 1 (sram_1_rule1)", + "description": "TrustZone register - MEDIA RAM1 Memory Rule Register 1 (sram_1_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field6E0", + "offset_int": "0x6e0", + "reg_width": 32, + "name": "MEDIA RAM1 Memory Rule Register 2 (sram_1_rule2)", + "description": "TrustZone register - MEDIA RAM1 Memory Rule Register 2 (sram_1_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field6E4", + "offset_int": "0x6e4", + "reg_width": 32, + "name": "MEDIA RAM1 Memory Rule Register 3 (sram_1_rule3)", + "description": "TrustZone register - MEDIA RAM1 Memory Rule Register 3 (sram_1_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field6E8", + "offset_int": "0x6e8", + "reg_width": 32, + "name": "MEDIA RAM2 Memory Rule Register 0 (sram_2_rule0)", + "description": "TrustZone register - MEDIA RAM2 Memory Rule Register 0 (sram_2_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field6EC", + "offset_int": "0x6ec", + "reg_width": 32, + "name": "MEDIA RAM2 Memory Rule Register 1 (sram_2_rule1)", + "description": "TrustZone register - MEDIA RAM2 Memory Rule Register 1 (sram_2_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field6F0", + "offset_int": "0x6f0", + "reg_width": 32, + "name": "MEDIA RAM2 Memory Rule Register 2 (sram_2_rule2)", + "description": "TrustZone register - MEDIA RAM2 Memory Rule Register 2 (sram_2_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field6F4", + "offset_int": "0x6f4", + "reg_width": 32, + "name": "MEDIA RAM2 Memory Rule Register 3 (sram_2_rule3)", + "description": "TrustZone register - MEDIA RAM2 Memory Rule Register 3 (sram_2_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field6F8", + "offset_int": "0x6f8", + "reg_width": 32, + "name": "MEDIA RAM3 Memory Rule Register 0 (sram_3_rule0)", + "description": "TrustZone register - MEDIA RAM3 Memory Rule Register 0 (sram_3_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field6FC", + "offset_int": "0x6fc", + "reg_width": 32, + "name": "MEDIA RAM3 Memory Rule Register 1 (sram_3_rule1)", + "description": "TrustZone register - MEDIA RAM3 Memory Rule Register 1 (sram_3_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field700", + "offset_int": "0x700", + "reg_width": 32, + "name": "MEDIA RAM3 Memory Rule Register 2 (sram_3_rule2)", + "description": "TrustZone register - MEDIA RAM3 Memory Rule Register 2 (sram_3_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field704", + "offset_int": "0x704", + "reg_width": 32, + "name": "MEDIA RAM3 Memory Rule Register 3 (sram_3_rule3)", + "description": "TrustZone register - MEDIA RAM3 Memory Rule Register 3 (sram_3_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field708", + "offset_int": "0x708", + "reg_width": 32, + "name": "MEDIA RAM4 Memory Rule Register 0 (sram_4_rule0)", + "description": "TrustZone register - MEDIA RAM4 Memory Rule Register 0 (sram_4_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field70C", + "offset_int": "0x70c", + "reg_width": 32, + "name": "MEDIA RAM4 Memory Rule Register 1 (sram_4_rule1)", + "description": "TrustZone register - MEDIA RAM4 Memory Rule Register 1 (sram_4_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field710", + "offset_int": "0x710", + "reg_width": 32, + "name": "MEDIA RAM4 Memory Rule Register 2 (sram_4_rule2)", + "description": "TrustZone register - MEDIA RAM4 Memory Rule Register 2 (sram_4_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field714", + "offset_int": "0x714", + "reg_width": 32, + "name": "MEDIA RAM4 Memory Rule Register 3 (sram_4_rule3)", + "description": "TrustZone register - MEDIA RAM4 Memory Rule Register 3 (sram_4_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field718", + "offset_int": "0x718", + "reg_width": 32, + "name": "MEDIA RAM5 Memory Rule Register 0 (sram_5_rule0)", + "description": "TrustZone register - MEDIA RAM5 Memory Rule Register 0 (sram_5_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field71C", + "offset_int": "0x71c", + "reg_width": 32, + "name": "MEDIA RAM5 Memory Rule Register 1 (sram_5_rule1)", + "description": "TrustZone register - MEDIA RAM5 Memory Rule Register 1 (sram_5_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field720", + "offset_int": "0x720", + "reg_width": 32, + "name": "MEDIA RAM5 Memory Rule Register 2 (sram_5_rule2)", + "description": "TrustZone register - MEDIA RAM5 Memory Rule Register 2 (sram_5_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field724", + "offset_int": "0x724", + "reg_width": 32, + "name": "MEDIA RAM5 Memory Rule Register 3 (sram_5_rule3)", + "description": "TrustZone register - MEDIA RAM5 Memory Rule Register 3 (sram_5_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field728", + "offset_int": "0x728", + "reg_width": 32, + "name": "MEDIA RAM6 Memory Rule Register 0 (sram_6_rule0)", + "description": "TrustZone register - MEDIA RAM6 Memory Rule Register 0 (sram_6_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field72C", + "offset_int": "0x72c", + "reg_width": 32, + "name": "MEDIA RAM6 Memory Rule Register 1 (sram_6_rule1)", + "description": "TrustZone register - MEDIA RAM6 Memory Rule Register 1 (sram_6_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field730", + "offset_int": "0x730", + "reg_width": 32, + "name": "MEDIA RAM6 Memory Rule Register 2 (sram_6_rule2)", + "description": "TrustZone register - MEDIA RAM6 Memory Rule Register 2 (sram_6_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field734", + "offset_int": "0x734", + "reg_width": 32, + "name": "MEDIA RAM6 Memory Rule Register 3 (sram_6_rule3)", + "description": "TrustZone register - MEDIA RAM6 Memory Rule Register 3 (sram_6_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field738", + "offset_int": "0x738", + "reg_width": 32, + "name": "MEDIA RAM7 Memory Rule Register 0 (sram_7_rule0)", + "description": "TrustZone register - MEDIA RAM7 Memory Rule Register 0 (sram_7_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field73C", + "offset_int": "0x73c", + "reg_width": 32, + "name": "MEDIA RAM7 Memory Rule Register 1 (sram_7_rule1)", + "description": "TrustZone register - MEDIA RAM7 Memory Rule Register 1 (sram_7_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field740", + "offset_int": "0x740", + "reg_width": 32, + "name": "MEDIA RAM7 Memory Rule Register 2 (sram_7_rule2)", + "description": "TrustZone register - MEDIA RAM7 Memory Rule Register 2 (sram_7_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field744", + "offset_int": "0x744", + "reg_width": 32, + "name": "MEDIA RAM7 Memory Rule Register 3 (sram_7_rule3)", + "description": "TrustZone register - MEDIA RAM7 Memory Rule Register 3 (sram_7_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field748", + "offset_int": "0x748", + "reg_width": 32, + "name": "MEDIA RAM8 Memory Rule Register 0 (sram_8_rule0)", + "description": "TrustZone register - MEDIA RAM8 Memory Rule Register 0 (sram_8_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field74C", + "offset_int": "0x74c", + "reg_width": 32, + "name": "MEDIA RAM8 Memory Rule Register 1 (sram_8_rule1)", + "description": "TrustZone register - MEDIA RAM8 Memory Rule Register 1 (sram_8_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field750", + "offset_int": "0x750", + "reg_width": 32, + "name": "MEDIA RAM8 Memory Rule Register 2 (sram_8_rule2)", + "description": "TrustZone register - MEDIA RAM8 Memory Rule Register 2 (sram_8_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field754", + "offset_int": "0x754", + "reg_width": 32, + "name": "MEDIA RAM8 Memory Rule Register 3 (sram_8_rule3)", + "description": "TrustZone register - MEDIA RAM8 Memory Rule Register 3 (sram_8_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field758", + "offset_int": "0x758", + "reg_width": 32, + "name": "MEDIA RAM9 Memory Rule Register 0 (sram_9_rule0)", + "description": "TrustZone register - MEDIA RAM9 Memory Rule Register 0 (sram_9_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field75C", + "offset_int": "0x75c", + "reg_width": 32, + "name": "MEDIA RAM9 Memory Rule Register 1 (sram_9_rule1)", + "description": "TrustZone register - MEDIA RAM9 Memory Rule Register 1 (sram_9_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field760", + "offset_int": "0x760", + "reg_width": 32, + "name": "MEDIA RAM9 Memory Rule Register 2 (sram_9_rule2)", + "description": "TrustZone register - MEDIA RAM9 Memory Rule Register 2 (sram_9_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field764", + "offset_int": "0x764", + "reg_width": 32, + "name": "MEDIA RAM9 Memory Rule Register 3 (sram_9_rule3)", + "description": "TrustZone register - MEDIA RAM9 Memory Rule Register 3 (sram_9_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field768", + "offset_int": "0x768", + "reg_width": 32, + "name": "MEDIA RAM10 Memory Rule Register 0 (sram_10_rule0)", + "description": "TrustZone register - MEDIA RAM10 Memory Rule Register 0 (sram_10_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field76C", + "offset_int": "0x76c", + "reg_width": 32, + "name": "MEDIA RAM10 Memory Rule Register 1 (sram_10_rule1)", + "description": "TrustZone register - MEDIA RAM10 Memory Rule Register 1 (sram_10_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field770", + "offset_int": "0x770", + "reg_width": 32, + "name": "MEDIA RAM10 Memory Rule Register 2 (sram_10_rule2)", + "description": "TrustZone register - MEDIA RAM10 Memory Rule Register 2 (sram_10_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field774", + "offset_int": "0x774", + "reg_width": 32, + "name": "MEDIA RAM10 Memory Rule Register 3 (sram_10_rule3)", + "description": "TrustZone register - MEDIA RAM10 Memory Rule Register 3 (sram_10_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field778", + "offset_int": "0x778", + "reg_width": 32, + "name": "MEDIA RAM11 Memory Rule Register 0 (sram_11_rule0)", + "description": "TrustZone register - MEDIA RAM11 Memory Rule Register 0 (sram_11_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field77C", + "offset_int": "0x77c", + "reg_width": 32, + "name": "MEDIA RAM11 Memory Rule Register 1 (sram_11_rule1)", + "description": "TrustZone register - MEDIA RAM11 Memory Rule Register 1 (sram_11_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field780", + "offset_int": "0x780", + "reg_width": 32, + "name": "MEDIA RAM11 Memory Rule Register 2 (sram_11_rule2)", + "description": "TrustZone register - MEDIA RAM11 Memory Rule Register 2 (sram_11_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field784", + "offset_int": "0x784", + "reg_width": 32, + "name": "MEDIA RAM11 Memory Rule Register 3 (sram_11_rule3)", + "description": "TrustZone register - MEDIA RAM11 Memory Rule Register 3 (sram_11_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field788", + "offset_int": "0x788", + "reg_width": 32, + "name": "MEDIA RAM12 Memory Rule Register 0 (sram_12_rule0)", + "description": "TrustZone register - MEDIA RAM12 Memory Rule Register 0 (sram_12_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field78C", + "offset_int": "0x78c", + "reg_width": 32, + "name": "MEDIA RAM12 Memory Rule Register 1 (sram_12_rule1)", + "description": "TrustZone register - MEDIA RAM12 Memory Rule Register 1 (sram_12_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field790", + "offset_int": "0x790", + "reg_width": 32, + "name": "MEDIA RAM12 Memory Rule Register 2 (sram_12_rule2)", + "description": "TrustZone register - MEDIA RAM12 Memory Rule Register 2 (sram_12_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field794", + "offset_int": "0x794", + "reg_width": 32, + "name": "MEDIA RAM12 Memory Rule Register 3 (sram_12_rule3)", + "description": "TrustZone register - MEDIA RAM12 Memory Rule Register 3 (sram_12_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field798", + "offset_int": "0x798", + "reg_width": 32, + "name": "MEDIA RAM13 Memory Rule Register 0 (sram_13_rule0)", + "description": "TrustZone register - MEDIA RAM13 Memory Rule Register 0 (sram_13_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field79C", + "offset_int": "0x79c", + "reg_width": 32, + "name": "MEDIA RAM13 Memory Rule Register 1 (sram_13_rule1)", + "description": "TrustZone register - MEDIA RAM13 Memory Rule Register 1 (sram_13_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7A0", + "offset_int": "0x7a0", + "reg_width": 32, + "name": "MEDIA RAM13 Memory Rule Register 2 (sram_13_rule2)", + "description": "TrustZone register - MEDIA RAM13 Memory Rule Register 2 (sram_13_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7A4", + "offset_int": "0x7a4", + "reg_width": 32, + "name": "MEDIA RAM13 Memory Rule Register 3 (sram_13_rule3)", + "description": "TrustZone register - MEDIA RAM13 Memory Rule Register 3 (sram_13_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7A8", + "offset_int": "0x7a8", + "reg_width": 32, + "name": "MEDIA RAM14 Memory Rule Register 0 (sram_14_rule0)", + "description": "TrustZone register - MEDIA RAM14 Memory Rule Register 0 (sram_14_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7AC", + "offset_int": "0x7ac", + "reg_width": 32, + "name": "MEDIA RAM14 Memory Rule Register 1 (sram_14_rule1)", + "description": "TrustZone register - MEDIA RAM14 Memory Rule Register 1 (sram_14_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7B0", + "offset_int": "0x7b0", + "reg_width": 32, + "name": "MEDIA RAM14 Memory Rule Register 2 (sram_14_rule2)", + "description": "TrustZone register - MEDIA RAM14 Memory Rule Register 2 (sram_14_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7B4", + "offset_int": "0x7b4", + "reg_width": 32, + "name": "MEDIA RAM14 Memory Rule Register 3 (sram_14_rule3)", + "description": "TrustZone register - MEDIA RAM14 Memory Rule Register 3 (sram_14_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7B8", + "offset_int": "0x7b8", + "reg_width": 32, + "name": "MEDIA RAM15 Memory Rule Register 0 (sram_15_rule0)", + "description": "TrustZone register - MEDIA RAM15 Memory Rule Register 0 (sram_15_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7BC", + "offset_int": "0x7bc", + "reg_width": 32, + "name": "MEDIA RAM15 Memory Rule Register 1 (sram_15_rule1)", + "description": "TrustZone register - MEDIA RAM15 Memory Rule Register 1 (sram_15_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7C0", + "offset_int": "0x7c0", + "reg_width": 32, + "name": "MEDIA RAM15 Memory Rule Register 2 (sram_15_rule2)", + "description": "TrustZone register - MEDIA RAM15 Memory Rule Register 2 (sram_15_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7C4", + "offset_int": "0x7c4", + "reg_width": 32, + "name": "MEDIA RAM15 Memory Rule Register 3 (sram_15_rule3)", + "description": "TrustZone register - MEDIA RAM15 Memory Rule Register 3 (sram_15_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7C8", + "offset_int": "0x7c8", + "reg_width": 32, + "name": "MEDIA RAM16 Memory Rule Register 0 (sram_16_rule0)", + "description": "TrustZone register - MEDIA RAM16 Memory Rule Register 0 (sram_16_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7CC", + "offset_int": "0x7cc", + "reg_width": 32, + "name": "MEDIA RAM16 Memory Rule Register 1 (sram_16_rule1)", + "description": "TrustZone register - MEDIA RAM16 Memory Rule Register 1 (sram_16_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7D0", + "offset_int": "0x7d0", + "reg_width": 32, + "name": "MEDIA RAM16 Memory Rule Register 2 (sram_16_rule2)", + "description": "TrustZone register - MEDIA RAM16 Memory Rule Register 2 (sram_16_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7D4", + "offset_int": "0x7d4", + "reg_width": 32, + "name": "MEDIA RAM16 Memory Rule Register 3 (sram_16_rule3)", + "description": "TrustZone register - MEDIA RAM16 Memory Rule Register 3 (sram_16_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7D8", + "offset_int": "0x7d8", + "reg_width": 32, + "name": "MEDIA RAM17 Memory Rule Register 0 (sram_17_rule0)", + "description": "TrustZone register - MEDIA RAM17 Memory Rule Register 0 (sram_17_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7DC", + "offset_int": "0x7dc", + "reg_width": 32, + "name": "MEDIA RAM17 Memory Rule Register 1 (sram_17_rule1)", + "description": "TrustZone register - MEDIA RAM17 Memory Rule Register 1 (sram_17_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7E0", + "offset_int": "0x7e0", + "reg_width": 32, + "name": "MEDIA RAM17 Memory Rule Register 2 (sram_17_rule2)", + "description": "TrustZone register - MEDIA RAM17 Memory Rule Register 2 (sram_17_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7E4", + "offset_int": "0x7e4", + "reg_width": 32, + "name": "MEDIA RAM17 Memory Rule Register 3 (sram_17_rule3)", + "description": "TrustZone register - MEDIA RAM17 Memory Rule Register 3 (sram_17_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7E8", + "offset_int": "0x7e8", + "reg_width": 32, + "name": "MEDIA RAM18 Memory Rule Register 0 (sram_18_rule0)", + "description": "TrustZone register - MEDIA RAM18 Memory Rule Register 0 (sram_18_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7EC", + "offset_int": "0x7ec", + "reg_width": 32, + "name": "MEDIA RAM18 Memory Rule Register 1 (sram_18_rule1)", + "description": "TrustZone register - MEDIA RAM18 Memory Rule Register 1 (sram_18_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field7F0", + "offset_int": "0x7f0", + "reg_width": 32, + "name": "MEDIA RAM18 Memory Rule Register 2 (sram_18_rule2)", + "description": "TrustZone register - MEDIA RAM18 Memory Rule Register 2 (sram_18_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field7F4", + "offset_int": "0x7f4", + "reg_width": 32, + "name": "MEDIA RAM18 Memory Rule Register 3 (sram_18_rule3)", + "description": "TrustZone register - MEDIA RAM18 Memory Rule Register 3 (sram_18_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field7F8", + "offset_int": "0x7f8", + "reg_width": 32, + "name": "MEDIA RAM19 Memory Rule Register 0 (sram_19_rule0)", + "description": "TrustZone register - MEDIA RAM19 Memory Rule Register 0 (sram_19_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field7FC", + "offset_int": "0x7fc", + "reg_width": 32, + "name": "MEDIA RAM19 Memory Rule Register 1 (sram_19_rule1)", + "description": "TrustZone register - MEDIA RAM19 Memory Rule Register 1 (sram_19_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field800", + "offset_int": "0x800", + "reg_width": 32, + "name": "MEDIA RAM19 Memory Rule Register 2 (sram_19_rule2)", + "description": "TrustZone register - MEDIA RAM19 Memory Rule Register 2 (sram_19_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field804", + "offset_int": "0x804", + "reg_width": 32, + "name": "MEDIA RAM19 Memory Rule Register 3 (sram_19_rule3)", + "description": "TrustZone register - MEDIA RAM19 Memory Rule Register 3 (sram_19_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field808", + "offset_int": "0x808", + "reg_width": 32, + "name": "MEDIA RAM20 Memory Rule Register 0 (sram_20_rule0)", + "description": "TrustZone register - MEDIA RAM20 Memory Rule Register 0 (sram_20_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field80C", + "offset_int": "0x80c", + "reg_width": 32, + "name": "MEDIA RAM20 Memory Rule Register 1 (sram_20_rule1)", + "description": "TrustZone register - MEDIA RAM20 Memory Rule Register 1 (sram_20_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field810", + "offset_int": "0x810", + "reg_width": 32, + "name": "MEDIA RAM20 Memory Rule Register 2 (sram_20_rule2)", + "description": "TrustZone register - MEDIA RAM20 Memory Rule Register 2 (sram_20_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field814", + "offset_int": "0x814", + "reg_width": 32, + "name": "MEDIA RAM20 Memory Rule Register 3 (sram_20_rule3)", + "description": "TrustZone register - MEDIA RAM20 Memory Rule Register 3 (sram_20_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field818", + "offset_int": "0x818", + "reg_width": 32, + "name": "MEDIA RAM21 Memory Rule Register 0 (sram_21_rule0)", + "description": "TrustZone register - MEDIA RAM21 Memory Rule Register 0 (sram_21_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field81C", + "offset_int": "0x81c", + "reg_width": 32, + "name": "MEDIA RAM21 Memory Rule Register 1 (sram_21_rule1)", + "description": "TrustZone register - MEDIA RAM21 Memory Rule Register 1 (sram_21_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field820", + "offset_int": "0x820", + "reg_width": 32, + "name": "MEDIA RAM21 Memory Rule Register 2 (sram_21_rule2)", + "description": "TrustZone register - MEDIA RAM21 Memory Rule Register 2 (sram_21_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field824", + "offset_int": "0x824", + "reg_width": 32, + "name": "MEDIA RAM21 Memory Rule Register 3 (sram_21_rule3)", + "description": "TrustZone register - MEDIA RAM21 Memory Rule Register 3 (sram_21_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field828", + "offset_int": "0x828", + "reg_width": 32, + "name": "MEDIA RAM22 Memory Rule Register 0 (sram_22_rule0)", + "description": "TrustZone register - MEDIA RAM22 Memory Rule Register 0 (sram_22_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field82C", + "offset_int": "0x82c", + "reg_width": 32, + "name": "MEDIA RAM22 Memory Rule Register 1 (sram_22_rule1)", + "description": "TrustZone register - MEDIA RAM22 Memory Rule Register 1 (sram_22_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field830", + "offset_int": "0x830", + "reg_width": 32, + "name": "MEDIA RAM22 Memory Rule Register 2 (sram_22_rule2)", + "description": "TrustZone register - MEDIA RAM22 Memory Rule Register 2 (sram_22_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field834", + "offset_int": "0x834", + "reg_width": 32, + "name": "MEDIA RAM22 Memory Rule Register 3 (sram_22_rule3)", + "description": "TrustZone register - MEDIA RAM22 Memory Rule Register 3 (sram_22_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field838", + "offset_int": "0x838", + "reg_width": 32, + "name": "MEDIA RAM23 Memory Rule Register 0 (sram_23_rule0)", + "description": "TrustZone register - MEDIA RAM23 Memory Rule Register 0 (sram_23_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field83C", + "offset_int": "0x83c", + "reg_width": 32, + "name": "MEDIA RAM23 Memory Rule Register 1 (sram_23_rule1)", + "description": "TrustZone register - MEDIA RAM23 Memory Rule Register 1 (sram_23_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field840", + "offset_int": "0x840", + "reg_width": 32, + "name": "MEDIA RAM23 Memory Rule Register 2 (sram_23_rule2)", + "description": "TrustZone register - MEDIA RAM23 Memory Rule Register 2 (sram_23_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field844", + "offset_int": "0x844", + "reg_width": 32, + "name": "MEDIA RAM23 Memory Rule Register 3 (sram_23_rule3)", + "description": "TrustZone register - MEDIA RAM23 Memory Rule Register 3 (sram_23_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field848", + "offset_int": "0x848", + "reg_width": 32, + "name": "MEDIA RAM24 Memory Rule Register 0 (sram_24_rule0)", + "description": "TrustZone register - MEDIA RAM24 Memory Rule Register 0 (sram_24_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field84C", + "offset_int": "0x84c", + "reg_width": 32, + "name": "MEDIA RAM24 Memory Rule Register 1 (sram_24_rule1)", + "description": "TrustZone register - MEDIA RAM24 Memory Rule Register 1 (sram_24_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field850", + "offset_int": "0x850", + "reg_width": 32, + "name": "MEDIA RAM24 Memory Rule Register 2 (sram_24_rule2)", + "description": "TrustZone register - MEDIA RAM24 Memory Rule Register 2 (sram_24_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field854", + "offset_int": "0x854", + "reg_width": 32, + "name": "MEDIA RAM24 Memory Rule Register 3 (sram_24_rule3)", + "description": "TrustZone register - MEDIA RAM24 Memory Rule Register 3 (sram_24_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field858", + "offset_int": "0x858", + "reg_width": 32, + "name": "MEDIA RAM25 Memory Rule Register 0 (sram_25_rule0)", + "description": "TrustZone register - MEDIA RAM25 Memory Rule Register 0 (sram_25_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field85C", + "offset_int": "0x85c", + "reg_width": 32, + "name": "MEDIA RAM25 Memory Rule Register 1 (sram_25_rule1)", + "description": "TrustZone register - MEDIA RAM25 Memory Rule Register 1 (sram_25_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field860", + "offset_int": "0x860", + "reg_width": 32, + "name": "MEDIA RAM25 Memory Rule Register 2 (sram_25_rule2)", + "description": "TrustZone register - MEDIA RAM25 Memory Rule Register 2 (sram_25_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field864", + "offset_int": "0x864", + "reg_width": 32, + "name": "MEDIA RAM25 Memory Rule Register 3 (sram_25_rule3)", + "description": "TrustZone register - MEDIA RAM25 Memory Rule Register 3 (sram_25_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field868", + "offset_int": "0x868", + "reg_width": 32, + "name": "MEDIA RAM26 Memory Rule Register 0 (sram_26_rule0)", + "description": "TrustZone register - MEDIA RAM26 Memory Rule Register 0 (sram_26_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field86C", + "offset_int": "0x86c", + "reg_width": 32, + "name": "MEDIA RAM26 Memory Rule Register 1 (sram_26_rule1)", + "description": "TrustZone register - MEDIA RAM26 Memory Rule Register 1 (sram_26_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field870", + "offset_int": "0x870", + "reg_width": 32, + "name": "MEDIA RAM26 Memory Rule Register 2 (sram_26_rule2)", + "description": "TrustZone register - MEDIA RAM26 Memory Rule Register 2 (sram_26_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field874", + "offset_int": "0x874", + "reg_width": 32, + "name": "MEDIA RAM26 Memory Rule Register 3 (sram_26_rule3)", + "description": "TrustZone register - MEDIA RAM26 Memory Rule Register 3 (sram_26_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field878", + "offset_int": "0x878", + "reg_width": 32, + "name": "MEDIA RAM27 Memory Rule Register 0 (sram_27_rule0)", + "description": "TrustZone register - MEDIA RAM27 Memory Rule Register 0 (sram_27_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field87C", + "offset_int": "0x87c", + "reg_width": 32, + "name": "MEDIA RAM27 Memory Rule Register 1 (sram_27_rule1)", + "description": "TrustZone register - MEDIA RAM27 Memory Rule Register 1 (sram_27_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field880", + "offset_int": "0x880", + "reg_width": 32, + "name": "MEDIA RAM27 Memory Rule Register 2 (sram_27_rule2)", + "description": "TrustZone register - MEDIA RAM27 Memory Rule Register 2 (sram_27_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field884", + "offset_int": "0x884", + "reg_width": 32, + "name": "MEDIA RAM27 Memory Rule Register 3 (sram_27_rule3)", + "description": "TrustZone register - MEDIA RAM27 Memory Rule Register 3 (sram_27_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field888", + "offset_int": "0x888", + "reg_width": 32, + "name": "MEDIA RAM28 Memory Rule Register 0 (sram_28_rule0)", + "description": "TrustZone register - MEDIA RAM28 Memory Rule Register 0 (sram_28_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field88C", + "offset_int": "0x88c", + "reg_width": 32, + "name": "MEDIA RAM28 Memory Rule Register 1 (sram_28_rule1)", + "description": "TrustZone register - MEDIA RAM28 Memory Rule Register 1 (sram_28_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field890", + "offset_int": "0x890", + "reg_width": 32, + "name": "MEDIA RAM28 Memory Rule Register 2 (sram_28_rule2)", + "description": "TrustZone register - MEDIA RAM28 Memory Rule Register 2 (sram_28_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field894", + "offset_int": "0x894", + "reg_width": 32, + "name": "MEDIA RAM28 Memory Rule Register 3 (sram_28_rule3)", + "description": "TrustZone register - MEDIA RAM28 Memory Rule Register 3 (sram_28_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field898", + "offset_int": "0x898", + "reg_width": 32, + "name": "MEDIA RAM29 Memory Rule Register 0 (sram_29_rule0)", + "description": "TrustZone register - MEDIA RAM29 Memory Rule Register 0 (sram_29_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field89C", + "offset_int": "0x89c", + "reg_width": 32, + "name": "MEDIA RAM29 Memory Rule Register 1 (sram_29_rule1)", + "description": "TrustZone register - MEDIA RAM29 Memory Rule Register 1 (sram_29_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field8A0", + "offset_int": "0x8a0", + "reg_width": 32, + "name": "MEDIA RAM29 Memory Rule Register 2 (sram_29_rule2)", + "description": "TrustZone register - MEDIA RAM29 Memory Rule Register 2 (sram_29_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field8A4", + "offset_int": "0x8a4", + "reg_width": 32, + "name": "MEDIA RAM29 Memory Rule Register 3 (sram_29_rule3)", + "description": "TrustZone register - MEDIA RAM29 Memory Rule Register 3 (sram_29_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field8A8", + "offset_int": "0x8a8", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 0 Memory Rule Register 0 (xspi2_region0_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 0 Memory Rule Register 0 (xspi2_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8AC", + "offset_int": "0x8ac", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 0 Memory Rule Register 1 (xspi2_region0_mem_rule1)", + "description": "TrustZone register - MEDIA XSPI2 Region 0 Memory Rule Register 1 (xspi2_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field8B0", + "offset_int": "0x8b0", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 0 Memory Rule Register 2 (xspi2_region0_mem_rule2)", + "description": "TrustZone register - MEDIA XSPI2 Region 0 Memory Rule Register 2 (xspi2_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field8B4", + "offset_int": "0x8b4", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 0 Memory Rule Register 3 (xspi2_region0_mem_rule3)", + "description": "TrustZone register - MEDIA XSPI2 Region 0 Memory Rule Register 3 (xspi2_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field8B8", + "offset_int": "0x8b8", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 1 Memory Rule Register 0 (xspi2_region1_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 1 Memory Rule Register 0 (xspi2_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8BC", + "offset_int": "0x8bc", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 2 Memory Rule Register 0 (xspi2_region2_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 2 Memory Rule Register 0 (xspi2_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8C0", + "offset_int": "0x8c0", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 3 Memory Rule Register 0 (xspi2_region3_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 3 Memory Rule Register 0 (xspi2_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8C4", + "offset_int": "0x8c4", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 4 Memory Rule Register 0 (xspi2_region4_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 4 Memory Rule Register 0 (xspi2_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8C8", + "offset_int": "0x8c8", + "reg_width": 32, + "name": "MEDIA XSPI2 Region 5 Memory Rule Register 0 (xspi2_region5_mem_rule0)", + "description": "TrustZone register - MEDIA XSPI2 Region 5 Memory Rule Register 0 (xspi2_region5_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field8CC", + "offset_int": "0x8cc", + "reg_width": 32, + "name": "MEDIA Master Secure Level Register (master_sec_level)", + "description": "TrustZone register - MEDIA Master Secure Level Register (master_sec_level)", + "default_value_int": "0x0" + }, + { + "id": "field8D0", + "offset_int": "0x8d0", + "reg_width": 32, + "name": "MEDIA Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - MEDIA Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xffffffff" + }, + { + "id": "field8D4", + "offset_int": "0x8d4", + "reg_width": 32, + "name": "MEDIA Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - MEDIA Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field8D8", + "offset_int": "0x8d8", + "reg_width": 32, + "name": "MEDIA Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - MEDIA Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x865a" + }, + { + "id": "field8DC", + "offset_int": "0x8dc", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8E0", + "offset_int": "0x8e0", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8E4", + "offset_int": "0x8e4", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8E8", + "offset_int": "0x8e8", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8EC", + "offset_int": "0x8ec", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8F0", + "offset_int": "0x8f0", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8F4", + "offset_int": "0x8f4", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8F8", + "offset_int": "0x8f8", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field8FC", + "offset_int": "0x8fc", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field900", + "offset_int": "0x900", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field904", + "offset_int": "0x904", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field908", + "offset_int": "0x908", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field90C", + "offset_int": "0x90c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field910", + "offset_int": "0x910", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field914", + "offset_int": "0x914", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field918", + "offset_int": "0x918", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1)", + "default_value_int": "0xaaaaaa0a" + }, + { + "id": "field91C", + "offset_int": "0x91c", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field920", + "offset_int": "0x920", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field924", + "offset_int": "0x924", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field928", + "offset_int": "0x928", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field92C", + "offset_int": "0x92c", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field930", + "offset_int": "0x930", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field934", + "offset_int": "0x934", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field938", + "offset_int": "0x938", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field93C", + "offset_int": "0x93c", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field940", + "offset_int": "0x940", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field944", + "offset_int": "0x944", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field948", + "offset_int": "0x948", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field94C", + "offset_int": "0x94c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field950", + "offset_int": "0x950", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field954", + "offset_int": "0x954", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0_1)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field958", + "offset_int": "0x958", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1_1)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1_1)", + "default_value_int": "0xaa2aaa22" + }, + { + "id": "field95C", + "offset_int": "0x95c", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 0 (itrc_irq_out0_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field960", + "offset_int": "0x960", + "reg_width": 32, + "name": "ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "description": "TrustZone register - ITRC IRQ Trigger source selector register 1 (itrc_irq_out0_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field964", + "offset_int": "0x964", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 0 (itrc_css_reset_out1_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field968", + "offset_int": "0x968", + "reg_width": 32, + "name": "ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "description": "TrustZone register - ITRC CSS_RESET Trigger source selector register 1 (itrc_css_reset_out1_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field96C", + "offset_int": "0x96c", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 0 (itrc_puf_zeroize_out2_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field970", + "offset_int": "0x970", + "reg_width": 32, + "name": "ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "description": "TrustZone register - ITRC PUF_ZEROIZE Trigger source selector register 1 (itrc_puf_zeroize_out2_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field974", + "offset_int": "0x974", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 0 (itrc_ram_zeroize_out3_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field978", + "offset_int": "0x978", + "reg_width": 32, + "name": "ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "description": "TrustZone register - ITRC RAM_ZEROIZE Trigger source selector register 1 (itrc_ram_zeroize_out3_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field97C", + "offset_int": "0x97c", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 0 (itrc_chip_reset_out4_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field980", + "offset_int": "0x980", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger source selector register 1 (itrc_chip_reset_out4_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field984", + "offset_int": "0x984", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out5_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field988", + "offset_int": "0x988", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out5_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field98C", + "offset_int": "0x98c", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 0 (itrc_itr_out_out6_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field990", + "offset_int": "0x990", + "reg_width": 32, + "name": "ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "description": "TrustZone register - ITRC ITR_OUT Trigger source selector register 1 (itrc_itr_out_out6_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field994", + "offset_int": "0x994", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0_2)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 0 (itrc_itr_out_out7_sel0_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field998", + "offset_int": "0x998", + "reg_width": 32, + "name": "ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1_2)", + "description": "TrustZone register - ITRC EXT_KEY_RESET Trigger source selector register 1 (itrc_itr_out_out7_sel1_2)", + "default_value_int": "0x80002aaa" + }, + { + "id": "field99C", + "offset_int": "0x99c", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "description": "TrustZone register - GPIO0 Pin Control Non-Secure (gpio0_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field9A0", + "offset_int": "0x9a0", + "reg_width": 32, + "name": "GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "description": "TrustZone register - GPIO0 Pin Control Non-Privilege (gpio0_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field9A4", + "offset_int": "0x9a4", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Secure (gpio0_icns)", + "default_value_int": "0x0" + }, + { + "id": "field9A8", + "offset_int": "0x9a8", + "reg_width": 32, + "name": "GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "description": "TrustZone register - GPIO0 Interrupt Control Non-Privilege (gpio0_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field9AC", + "offset_int": "0x9ac", + "reg_width": 32, + "name": "GPIO0 Lock Register (gpio0_lock)", + "description": "TrustZone register - GPIO0 Lock Register (gpio0_lock)", + "default_value_int": "0x0" + }, + { + "id": "field9B0", + "offset_int": "0x9b0", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "description": "TrustZone register - GPIO1 Pin Control Non-Secure (gpio1_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field9B4", + "offset_int": "0x9b4", + "reg_width": 32, + "name": "GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "description": "TrustZone register - GPIO1 Pin Control Non-Privilege (gpio1_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field9B8", + "offset_int": "0x9b8", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Secure (gpio1_icns)", + "default_value_int": "0x0" + }, + { + "id": "field9BC", + "offset_int": "0x9bc", + "reg_width": 32, + "name": "GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "description": "TrustZone register - GPIO1 Interrupt Control Non-Privilege (gpio1_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field9C0", + "offset_int": "0x9c0", + "reg_width": 32, + "name": "GPIO1 Lock Register (gpio1_lock)", + "description": "TrustZone register - GPIO1 Lock Register (gpio1_lock)", + "default_value_int": "0x0" + }, + { + "id": "field9C4", + "offset_int": "0x9c4", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "description": "TrustZone register - GPIO2 Pin Control Non-Secure (gpio2_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field9C8", + "offset_int": "0x9c8", + "reg_width": 32, + "name": "GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "description": "TrustZone register - GPIO2 Pin Control Non-Privilege (gpio2_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field9CC", + "offset_int": "0x9cc", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Secure (gpio2_icns)", + "default_value_int": "0x0" + }, + { + "id": "field9D0", + "offset_int": "0x9d0", + "reg_width": 32, + "name": "GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "description": "TrustZone register - GPIO2 Interrupt Control Non-Privilege (gpio2_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field9D4", + "offset_int": "0x9d4", + "reg_width": 32, + "name": "GPIO2 Lock Register (gpio2_lock)", + "description": "TrustZone register - GPIO2 Lock Register (gpio2_lock)", + "default_value_int": "0x0" + }, + { + "id": "field9D8", + "offset_int": "0x9d8", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "description": "TrustZone register - GPIO3 Pin Control Non-Secure (gpio3_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field9DC", + "offset_int": "0x9dc", + "reg_width": 32, + "name": "GPIO3 Pin Control Non-Privilege (gpio3_pcnp)", + "description": "TrustZone register - GPIO3 Pin Control Non-Privilege (gpio3_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field9E0", + "offset_int": "0x9e0", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Secure (gpio3_icns)", + "default_value_int": "0x0" + }, + { + "id": "field9E4", + "offset_int": "0x9e4", + "reg_width": 32, + "name": "GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "description": "TrustZone register - GPIO3 Interrupt Control Non-Privilege (gpio3_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field9E8", + "offset_int": "0x9e8", + "reg_width": 32, + "name": "GPIO3 Lock Register (gpio3_lock)", + "description": "TrustZone register - GPIO3 Lock Register (gpio3_lock)", + "default_value_int": "0x0" + }, + { + "id": "field9EC", + "offset_int": "0x9ec", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "description": "TrustZone register - GPIO4 Pin Control Non-Secure (gpio4_pcns)", + "default_value_int": "0x0" + }, + { + "id": "field9F0", + "offset_int": "0x9f0", + "reg_width": 32, + "name": "GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "description": "TrustZone register - GPIO4 Pin Control Non-Privilege (gpio4_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "field9F4", + "offset_int": "0x9f4", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Secure (gpio4_icns)", + "default_value_int": "0x0" + }, + { + "id": "field9F8", + "offset_int": "0x9f8", + "reg_width": 32, + "name": "GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "description": "TrustZone register - GPIO4 Interrupt Control Non-Privilege (gpio4_icnp)", + "default_value_int": "0x0" + }, + { + "id": "field9FC", + "offset_int": "0x9fc", + "reg_width": 32, + "name": "GPIO4 Lock Register (gpio4_lock)", + "description": "TrustZone register - GPIO4 Lock Register (gpio4_lock)", + "default_value_int": "0x0" + }, + { + "id": "fieldA00", + "offset_int": "0xa00", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "description": "TrustZone register - GPIO5 Pin Control Non-Secure (gpio5_pcns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA04", + "offset_int": "0xa04", + "reg_width": 32, + "name": "GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "description": "TrustZone register - GPIO5 Pin Control Non-Privilege (gpio5_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA08", + "offset_int": "0xa08", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Secure (gpio5_icns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA0C", + "offset_int": "0xa0c", + "reg_width": 32, + "name": "GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "description": "TrustZone register - GPIO5 Interrupt Control Non-Privilege (gpio5_icnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA10", + "offset_int": "0xa10", + "reg_width": 32, + "name": "GPIO5 Lock Register (gpio5_lock)", + "description": "TrustZone register - GPIO5 Lock Register (gpio5_lock)", + "default_value_int": "0x0" + }, + { + "id": "fieldA14", + "offset_int": "0xa14", + "reg_width": 32, + "name": "GPIO6 Pin Control Non-Secure (gpio6_pcns)", + "description": "TrustZone register - GPIO6 Pin Control Non-Secure (gpio6_pcns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA18", + "offset_int": "0xa18", + "reg_width": 32, + "name": "GPIO6 Pin Control Non-Privilege (gpio6_pcnp)", + "description": "TrustZone register - GPIO6 Pin Control Non-Privilege (gpio6_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA1C", + "offset_int": "0xa1c", + "reg_width": 32, + "name": "GPIO6 Interrupt Control Non-Secure (gpio6_icns)", + "description": "TrustZone register - GPIO6 Interrupt Control Non-Secure (gpio6_icns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA20", + "offset_int": "0xa20", + "reg_width": 32, + "name": "GPIO6 Interrupt Control Non-Privilege (gpio6_icnp)", + "description": "TrustZone register - GPIO6 Interrupt Control Non-Privilege (gpio6_icnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA24", + "offset_int": "0xa24", + "reg_width": 32, + "name": "GPIO6 Lock Register (gpio6_lock)", + "description": "TrustZone register - GPIO6 Lock Register (gpio6_lock)", + "default_value_int": "0x0" + }, + { + "id": "fieldA28", + "offset_int": "0xa28", + "reg_width": 32, + "name": "GPIO7 Pin Control Non-Secure (gpio7_pcns)", + "description": "TrustZone register - GPIO7 Pin Control Non-Secure (gpio7_pcns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA2C", + "offset_int": "0xa2c", + "reg_width": 32, + "name": "GPIO7 Pin Control Non-Privilege (gpio7_pcnp)", + "description": "TrustZone register - GPIO7 Pin Control Non-Privilege (gpio7_pcnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA30", + "offset_int": "0xa30", + "reg_width": 32, + "name": "GPIO7 Interrupt Control Non-Secure (gpio7_icns)", + "description": "TrustZone register - GPIO7 Interrupt Control Non-Secure (gpio7_icns)", + "default_value_int": "0x0" + }, + { + "id": "fieldA34", + "offset_int": "0xa34", + "reg_width": 32, + "name": "GPIO7 Interrupt Control Non-Privilege (gpio7_icnp)", + "description": "TrustZone register - GPIO7 Interrupt Control Non-Privilege (gpio7_icnp)", + "default_value_int": "0x0" + }, + { + "id": "fieldA38", + "offset_int": "0xa38", + "reg_width": 32, + "name": "GPIO7 Lock Register (gpio7_lock)", + "description": "TrustZone register - GPIO7 Lock Register (gpio7_lock)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012/database.yaml new file mode 100644 index 0000000..6202756 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012/database.yaml @@ -0,0 +1,32 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81768 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Power + spsdk_predecessor_name: mwct2x12 + # Web page of MCU representative + web: https://www.nxp.com/products/power-management/wireless-power:WIRCHA_ICS + memory_map: # Memory map basic info + internal-flash: + start_int: 0x0 + size_int: 0x20000 + external: false + ram: + start_int: 0x60000 + size_int: 0x5000 + external: false + + +features: + wpc: + id_type: rsid + id_length: 96 + insert_puc_only: true + need_reset: true + need_address_adjust: true + check_lifecycle: 3 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012a/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012a/database.yaml new file mode 100644 index 0000000..6adefe5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2012a/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct2012 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2014s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2014s/database.yaml new file mode 100644 index 0000000..ca5c8e7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2014s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct2d17s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2015s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2015s/database.yaml new file mode 100644 index 0000000..ca5c8e7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2015s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct2d17s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2016s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2016s/database.yaml new file mode 100644 index 0000000..ca5c8e7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2016s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct2d17s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/database.yaml new file mode 100644 index 0000000..4d23360 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/database.yaml @@ -0,0 +1,22 @@ +# Copyright 2023-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mc56f81868 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Power + spsdk_predecessor_name: mwct2xd2 + # Web page of MCU representative + web: https://www.nxp.com/products/power-management/wireless-power:WIRCHA_ICS + +features: + wpc: + id_type: rsid + id_length: 96 + insert_puc_only: true + need_reset: true + need_address_adjust: true + check_lifecycle: 3 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/ifr.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/ifr.json new file mode 100644 index 0000000..2da5d3c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2/ifr.json @@ -0,0 +1,149 @@ +{ + "cpu": "MWCT20D2", + "groups": [ + { + "group": { + "name": "Customer IFR data", + "description": "Customer IFR data" + }, + "registers": [ + { + "id": "field000", + "name": "CUSTOMER_DEFINED0", + "description": "Customer defined", + "offset_int": "0x00C0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field001", + "name": "CUSTOMER_DEFINED1", + "description": "Customer defined", + "offset_int": "0x00C4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field002", + "name": "CUSTOMER_DEFINED2", + "description": "Customer defined", + "offset_int": "0x00C8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field003", + "name": "CUSTOMER_DEFINED3", + "description": "Customer defined", + "offset_int": "0x00CC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field004", + "name": "CUSTOMER_DEFINED4", + "description": "Customer defined", + "offset_int": "0x00D0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field005", + "name": "CUSTOMER_DEFINED5", + "description": "Customer defined", + "offset_int": "0x00D4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field006", + "name": "CUSTOMER_DEFINED6", + "description": "Customer defined", + "offset_int": "0x00D8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field007", + "name": "CUSTOMER_DEFINED7", + "description": "Customer defined", + "offset_int": "0x00DC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field008", + "name": "CUSTOMER_DEFINED8", + "description": "Customer defined", + "offset_int": "0x00E0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field009", + "name": "CUSTOMER_DEFINED9", + "description": "Customer defined", + "offset_int": "0x00E4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field010", + "name": "CUSTOMER_DEFINED10", + "description": "Customer defined", + "offset_int": "0x00E8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field011", + "name": "CUSTOMER_DEFINED11", + "description": "Customer defined", + "offset_int": "0x00EC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "ISK_CERT_HASH", + "description": "ISK_CERT_HASH" + }, + "registers": [ + { + "id": "field012", + "name": "ISK_CERT_HASH[31:0]", + "description": "ISK_CERT_HASH[31:0]", + "offset_int": "0x00F0", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field013", + "name": "ISK_CERT_HASH[63:32]", + "description": "ISK_CERT_HASH[63:32]", + "offset_int": "0x00F4", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field014", + "name": "ISK_CERT_HASH[95:64]", + "description": "ISK_CERT_HASH[95:64]", + "offset_int": "0x00F8", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + }, + { + "id": "field015", + "name": "ISK_CERT_HASH[127:96]", + "description": "ISK_CERT_HASH[127:96]", + "offset_int": "0x00FC", + "default_value_int": "0xFFFFFFFF", + "individual_write_lock": "implicit" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2a/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2a/database.yaml new file mode 100644 index 0000000..d4842c3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct20d2a/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct20d2 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d16s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d16s/database.yaml new file mode 100644 index 0000000..ca5c8e7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d16s/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: mwct2d17s diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d17s/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d17s/database.yaml new file mode 100644 index 0000000..73cded7 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/mwct2d17s/database.yaml @@ -0,0 +1,37 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a0: {} + +latest: a0 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Power + spsdk_predecessor_name: mwct2xxxs + # Web page of MCU representative + web: https://www.nxp.com/products/power-management/wireless-power/mwct2xxxs-microcontroller-for-wireless-charging-transmitter-ics:MWCT2xxxS + memory_map: {} # Memory map basic info + isp: + rom: {} + flashloader: + protocol: mboot + interfaces: ["uart", "usb"] + usb: + - vid: 0x15a2 + pid: 0x0073 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_0000 + + wpc: + id_type: computed_csr + id_length: 136 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/database.yaml new file mode 100644 index 0000000..495c23c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/database.yaml @@ -0,0 +1,184 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a4: {} +latest: a4 + +# General MCU information +info: + use_in_doc: True # Include this MCU in generated documentation + purpose: Wireless Connectivity MCUs + spsdk_predecessor_name: nhs52sxx + # Web page of MCU representative + web: https://www.nxp.com/products/wireless-connectivity/bluetooth-low-energy/nhs52s04-ultra-low-power-bluetooth-low-energy-solution-with-arm-cortex-m33-trustzone-for-medical-iot:NHS52S04 + memory_map: + # Memory map basic info + internal-flash_ns: + start_int: 0x0 + size_int: 0xFE000 + external: false + internal-flash_s: + start_int: 0x10000000 + size_int: 0xFE000 + external: false + mirror_of: internal-flash_ns + sram: + start_int: 0x20004000 + size_int: 0x1C000 + external: false + sramx: + start_int: 0x4000000 + size_int: 0x4000 + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0021 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_4000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert1] + rot_type: "cert_block_1" + + # ======== DAT section ======== + dat: + socc: 1 # SOCC identification + dmbox_ap_ix: 2 # Typical Index of debug mailbox access port is 2 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinLoadAddress + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinHwKey + - Mbi_MixinLoadAddress + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZone + - Mbi_MixinLoadAddress + - Mbi_MixinCertBlockV1 + - Mbi_MixinHwKey + - Mbi_ExportMixinAppTrustZoneCertBlock + - Mbi_ExportMixinRsaSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + crc: crc_ram + signed: signed_ram + + # ======== PFR section ======== + pfr: + cfpa: # CFPA description + address: 0xF_E000 + size: 512 + reg_spec: pfr_cfpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + computed_fields: + field01C: # VENDOR_USAGE + field01C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field020: # DCFG_CC_SOCU_NS_PIN + field020-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field024: # DCFG_CC_SOCU_NS_DFLT + field024-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + cmpa: # CMPA description + address: 0x10_4000 + size: 512 + reg_spec: pfr_cmpa.json + seal_start: field1E0 # SHA256_DIGEST0 + seal_count: 8 + grouped_registers: + - uid: cmpa_rotkh + name: ROTKH + width: 256 + config_as_hexstring: true + reversed: true + description: + ROTKH field is compounded by 8 32-bit fields and contains Root key + table hash + sub_regs: + - field060 + - field064 + - field068 + - field06C + - field070 + - field074 + - field078 + - field07C + computed_fields: + field008: # DCFG_CC_SOCU_PIN + field008-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + field00C: # DCFG_CC_SOCU_DFLT + field00C-bits16-31: pfr_reg_inverse_high_half # INVERSE_VALUE + + # ======== Secure binary v2.1 section ======== + sb21: + supported_commands: [erase, load, enable, fill, jump, version_check] + keyblobs: false + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Bootable image section ======== + bootable_image: + mem_types: + recovery_spi: + segments: + sb21: 0x00 + internal: + segments: + mbi: 0x00 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cfpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cfpa.json new file mode 100644 index 0000000..1619661 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cfpa.json @@ -0,0 +1,1523 @@ +{ + "cpu": "nhs52s04", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "HEADER", + "description": "CFPA header field", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field004", + "name": "VERSION", + "description": "CFPA version number", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field008", + "name": "S_FW_Version", + "description": "Secure firmware version (Monotonic counter)", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field00C", + "name": "NS_FW_Version", + "description": "Non-Secure firmware version (Monotonic counter)", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field010", + "name": "IMAGE_KEY_REVOKE", + "description": "Image key revocation ID (Monotonic counter)", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00014", + "name": "Reserved 0x00014", + "description": "This field is reserved for internal use", + "offset_int": "0x0014", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field018", + "name": "ROTKH_REVOKE", + "description": "Root of Trust Key Hash Revoke", + "offset_int": "0x0018", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field018-bits0-1", + "name": "RoTK0_EN", + "description": "RoT Key 0 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits2-3", + "name": "RoTK1_EN", + "description": "RoT Key 1 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits4-5", + "name": "RoTK2_EN", + "description": "RoT Key 2 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 2, + "id": "field018-bits6-7", + "name": "RoTK3_EN", + "description": "RoT Key 3 enable.", + "values": [ + { + "name": "INVALID", + "value": 0, + "description": "Invalid" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + }, + { + "name": "REVOKED_0", + "value": 2, + "description": "Key revoked" + }, + { + "name": "REVOKED_1", + "value": 3, + "description": "Key revoked" + } + ] + }, + { + "width": 24 + } + ] + }, + { + "id": "field01C", + "name": "VENDOR_USAGE", + "description": "Debug vendor usage field", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field01C-bits0-15", + "name": "DBG_VENDOR_USAGE", + "description": "DBG_VENDOR_USAGE." + }, + { + "width": 16, + "id": "field01C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field020", + "name": "DCFG_CC_SOCU_NS_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field020-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field020-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field020-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field024", + "name": "DCFG_CC_SOCU_NS_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field024-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field024-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field028", + "name": "ENABLE_FA_MODE", + "description": "Enable FA mode.", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field02C", + "name": "CMPA_PROG_IN_PROGRESS", + "description": "CMPA Page programming on going.", + "offset_int": "0x002C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Reserved 00030-0007C", + "description": "Reserved 00030-0007C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00050", + "name": "Reserved 0x00050", + "description": "This field is reserved for internal use", + "offset_int": "0x0050", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00054", + "name": "Reserved 0x00054", + "description": "This field is reserved for internal use", + "offset_int": "0x0054", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00058", + "name": "Reserved 0x00058", + "description": "This field is reserved for internal use", + "offset_int": "0x0058", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0005C", + "name": "Reserved 0x0005C", + "description": "This field is reserved for internal use", + "offset_int": "0x005C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00060", + "name": "Reserved 0x00060", + "description": "This field is reserved for internal use", + "offset_int": "0x0060", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00064", + "name": "Reserved 0x00064", + "description": "This field is reserved for internal use", + "offset_int": "0x0064", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00068", + "name": "Reserved 0x00068", + "description": "This field is reserved for internal use", + "offset_int": "0x0068", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0006C", + "name": "Reserved 0x0006C", + "description": "This field is reserved for internal use", + "offset_int": "0x006C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00070", + "name": "Reserved 0x00070", + "description": "This field is reserved for internal use", + "offset_int": "0x0070", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00074", + "name": "Reserved 0x00074", + "description": "This field is reserved for internal use", + "offset_int": "0x0074", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00078", + "name": "Reserved 0x00078", + "description": "This field is reserved for internal use", + "offset_int": "0x0078", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0007C", + "name": "Reserved 0x0007C", + "description": "This field is reserved for internal use", + "offset_int": "0x007C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field080", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0088", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x008C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + 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"description": "SHA256_DIGEST4 for DIGEST[159:128]", + "offset_int": "0x01F0", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F4", + "name": "SHA256_DIGEST5", + "description": "SHA256_DIGEST5 for DIGEST[191:160]", + "offset_int": "0x01F4", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1F8", + "name": "SHA256_DIGEST6", + "description": "SHA256_DIGEST6 for DIGEST[223:192]", + "offset_int": "0x01F8", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field1FC", + "name": "SHA256_DIGEST7", + "description": "SHA256_DIGEST7 for DIGEST[255:224]", + "offset_int": "0x01FC", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cmpa.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cmpa.json new file mode 100644 index 0000000..1102bc1 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/pfr_cmpa.json @@ -0,0 +1,4261 @@ +{ + "cpu": "nhs52s04", + "groups": [ + { + "group": { + "name": "Configuration", + "description": "Configuration" + }, + "registers": [ + { + "id": "field000", + "name": "BOOT_CFG", + "description": "Boot Configuration", + "offset_int": "0", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 4 + }, + { + "width": 3, + "id": "field000-bits4-6", + "name": "DEFAULT_ISP_MODE", + "description": "Default ISP mode:", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto ISP" + }, + { + "name": "UART_ISP", + "value": 2, + "description": "UART ISP" + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "SPI Slave ISP" + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "I2C Slave ISP" + }, + { + "name": "DISABLE", + "value": 7, + "description": "Disable ISP fall through" + } + ] + }, + { + "width": 2, + "id": "field000-bits7-8", + "name": "BOOT_SPEED", + "description": "Core clock:", + "values": [ + { + "name": "SYSTEM_SPEED_CODE", + "value": 0, + "description": "Defined by NMPA.SYSTEM_SPEED_CODE" + }, + { + "name": "FRO_12MHZ", + "value": 1, + "description": "12MHz FRO" + }, + { + "name": "FRO_32MHZ", + "value": 2, + "description": "32MHz FRO" + } + ] + }, + { + "width": 15 + }, + { + "width": 8, + "id": "field000-bits24-31", + "name": "BOOT_FAILURE_PIN", + "description": "GPIO port and number of the pin to use for indicating failure reason. \nThe toggle rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO pin" + } + ] + }, + { + "id": "field004", + "name": "SPI_FLASH_CFG", + "description": "SPI Flash Configuration", + "offset_int": "0x0004", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 5, + "id": "field004-bits0-4", + "name": "SPI_RECOVERY_BOOT_EN", + "description": "SPI flash recovery boot is enabled, if non-zero value is written to this field." + }, + { + "width": 27 + } + ] + }, + { + "id": "field008", + "name": "DCFG_CC_SOCU_PIN", + "description": "Device Configuration Credential Constraints for SoC specific Use Pinned. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x0008", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field008-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit1", + "name": "DBGEN", + "description": "Non Secure debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit4", + "name": "TAPEN", + "description": "JTAG TAP enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field008-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 1, + "id": "field008-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode Command enable", + "values": [ + { + "name": "USE_DAP", + "value": 0, + "description": "Use DAP to enable" + }, + { + "name": "FIXED_STATE", + "value": 1, + "description": "Fixed state" + } + ] + }, + { + "width": 7 + }, + { + "width": 1, + "id": "field008-bit15", + "name": "UUID_CHECK", + "description": "Enforce UUID match during Debug authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 16, + "id": "field008-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field00C", + "name": "DCFG_CC_SOCU_DFLT", + "description": "Device Configuration Credential Constraints for SoC specific Use Debug Filter. \nCombinations of PIN and DFLT bits and resulting restriction level: \n - PIN=1,DFLT=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n - PIN=0,DFLT=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through debug authentication process by providing appropriate Debug Credential (DC) certificate. \n - PIN=0,DFLT=1: Illegal setting. Part may lock-up if this setting is selected. \n - PIN=1,DFLT=0: Restriction level 3. Access to the sub-domain is permanently disabled and can't be reversed. This setting offers the highest level of restriction.", + "offset_int": "0x000C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field00C-bit0", + "name": "NIDEN", + "description": "Non Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit1", + "name": "DBGEN", + "description": "Non Secure debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit2", + "name": "SPNIDEN", + "description": "Secure non-invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit3", + "name": "SPIDEN", + "description": "Secure invasive debug fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit4", + "name": "TAPEN", + "description": "JTAG TAP fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "field00C-bit6", + "name": "ISPCMDEN", + "description": "ISP Boot Command fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "field00C-bit7", + "name": "PMCMDEN", + "description": "Programmers Mode fixed state", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 8 + }, + { + "width": 16, + "id": "field00C-bits16-31", + "name": "INVERSE_VALUE", + "description": "inverse value of bits [15:0]", + "calculated": "INVERSE" + } + ] + }, + { + "id": "field010", + "name": "VENDOR_USAGE", + "description": "Field.", + "offset_int": "0x0010", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16 + }, + { + "width": 16, + "id": "field010-bits16-31", + "name": "VENDOR_USAGE", + "description": "Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area." + } + ] + }, + { + "id": "field014", + "name": "SECURE_BOOT_CFG", + "description": "Secure Boot Configuration", + "offset_int": "0x0014", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 2, + "id": "field014-bits0-1", + "name": "RSA4K", + "description": "Select minimal key length. To enforce usage of RSA4096, setting 0b11 value is recommended to allow RSA4096 keys only.", + "values": [ + { + "name": "RSA2048", + "value": 0, + "description": "RSA2048 or higher can be used for image signing. Only RSA2048 can be used as debug keys." + }, + { + "name": "RSA4096_0", + "value": 1, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_1", + "value": 2, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + }, + { + "name": "RSA4096_2", + "value": 3, + "description": "Only RSA4096 keys can be used for image signing and debug authentication." + } + ] + }, + { + "width": 2, + "id": "field014-bits2-3", + "name": "DICE_INC_NXP_CFG", + "description": "Include NXP area in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits4-5", + "name": "DICE_CUST_CFG", + "description": "Include Customer factory area (including keys) in DICE computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits6-7", + "name": "SKIP_DICE", + "description": "Skip DICE computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable DICE" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable DICE" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable DICE" + } + ] + }, + { + "width": 2, + "id": "field014-bits8-9", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "HEADER", + "value": 0, + "description": "TZ-M image mode is taken from application image header" + }, + { + "name": "DISABLED", + "value": 1, + "description": "TZ-M disabled image, boots to non-secure mode" + }, + { + "name": "ENABLED", + "value": 2, + "description": "TZ-M enabled image, boots to secure mode" + }, + { + "name": "PRESET", + "value": 3, + "description": "TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header" + } + ] + }, + { + "width": 2, + "id": "field014-bits10-11", + "name": "BLOCK_SET_KEY", + "description": "Block PUF key code generation", + "values": [ + { + "name": "ALLOW", + "value": 0, + "description": "Allow PUF Key Code generation" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable PUF Key Code generation" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable PUF Key Code generation" + } + ] + }, + { + "width": 2 + }, + { + "width": 2, + "id": "field014-bits14-15", + "name": "DICE_INC_SEC_EPOCH", + "description": "Include security EPOCH in DICE", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits16-17", + "name": "SKIP_BOOT_SEED", + "description": "Skip boot seed computation", + "values": [ + { + "name": "ENABLE", + "value": 0, + "description": "Enable BOOT_SEED" + }, + { + "name": "DISABLE_0", + "value": 1, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_1", + "value": 2, + "description": "Disable BOOT_SEED" + }, + { + "name": "DISABLE_2", + "value": 3, + "description": "Disable BOOT_SEED" + } + ] + }, + { + "width": 2, + "id": "field014-bits18-19", + "name": "BOOT_SEED_INC_NXP_CFG", + "description": "Include NXP area in BOOT SEED computation", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits20-21", + "name": "BOOT_SEED_CUST_CFG", + "description": "Include Customer factory area (including keys) in BOOT SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 2, + "id": "field014-bits22-23", + "name": "BOOT_SEED_INC_SEC_EPOCH", + "description": "Include security EPOCH in BOOT_SEED computation.", + "values": [ + { + "name": "NOT_INCLUDE", + "value": 0, + "description": "not included" + }, + { + "name": "INCLUDE_0", + "value": 1, + "description": "included" + }, + { + "name": "INCLUDE_1", + "value": 2, + "description": "included" + }, + { + "name": "INCLUDE_2", + "value": 3, + "description": "included" + } + ] + }, + { + "width": 6 + }, + { + "width": 2, + "id": "field014-bits30-31", + "name": "SEC_BOOT_EN", + "description": "Secure boot enable", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Plain image (internal flash with or without CRC)" + }, + { + "name": "ENABLE_0", + "value": 1, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_1", + "value": 2, + "description": "Boot signed images. (internal flash, RSA signed)" + }, + { + "name": "ENABLE_2", + "value": 3, + "description": "Boot signed images. (internal flash, RSA signed)" + } + ] + } + ] + }, + { + "id": "Reserved00018", + "name": "Reserved 0x00018", + "description": "This field is reserved for internal use", + "offset_int": "0x0018", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field01C", + "name": "PRINCE_CFG", + "description": "Prince Configuration", + "offset_int": "0x001C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1 + }, + { + "width": 1, + "id": "field01C-bit1", + "name": "GEE", + "description": "Global Encryption Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit5", + "name": "GDE", + "description": "Global Decryption Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit9", + "name": "SLK", + "description": "System Lock Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 3 + }, + { + "width": 1, + "id": "field01C-bit13", + "name": "GLK", + "description": "Global Lock Enable", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 18 + } + ] + }, + { + "id": "field020", + "name": "BMAPCTX0", + "description": "Bitmap Control for Memory Context 0", + "offset_int": "0x0020", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field020-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field020-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field024", + "name": "BMAPCTX1", + "description": "Bitmap Control for Memory Context 1", + "offset_int": "0x0024", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field024-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field024-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field028", + "name": "BMAPCTX2", + "description": "Bitmap Control for Memory Context 2", + "offset_int": "0x0028", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field028-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field028-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + }, + { + "id": "field02C", + "name": "BMAPCTX3", + "description": "Bitmap Control for Memory Context 3", + "offset_int": "0x002C", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 1, + "id": "field02C-bit0", + "name": "BEN0", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit1", + "name": "BEN1", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit2", + "name": "BEN2", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit3", + "name": "BEN3", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit4", + "name": "BEN4", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit5", + "name": "BEN5", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit6", + "name": "BEN6", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit7", + "name": "BEN7", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit8", + "name": "BEN8", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit9", + "name": "BEN9", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit10", + "name": "BEN10", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit11", + "name": "BEN11", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit12", + "name": "BEN12", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit13", + "name": "BEN13", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit14", + "name": "BEN14", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit15", + "name": "BEN15", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit16", + "name": "BEN16", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit17", + "name": "BEN17", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit18", + "name": "BEN18", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit19", + "name": "BEN19", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit20", + "name": "BEN20", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit21", + "name": "BEN21", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit22", + "name": "BEN22", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit23", + "name": "BEN23", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit24", + "name": "BEN24", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit25", + "name": "BEN25", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit26", + "name": "BEN26", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit27", + "name": "BEN27", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit28", + "name": "BEN28", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit29", + "name": "BEN29", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit30", + "name": "BEN30", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + }, + { + "width": 1, + "id": "field02C-bit31", + "name": "BEN31", + "description": "Block enable for encryption/decryption", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable encryption/decryption" + }, + { + "name": "ENABLE", + "value": 1, + "description": "Enable encryption/decryption" + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "Reserved 00030-0004C", + "description": "Reserved 00030-0004C" + }, + "registers": [ + { + "id": "Reserved00030", + "name": "Reserved 0x00030", + "description": "This field is reserved for internal use", + "offset_int": "0x0030", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00034", + "name": "Reserved 0x00034", + "description": "This field is reserved for internal use", + "offset_int": "0x0034", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00038", + "name": "Reserved 0x00038", + "description": "This field is reserved for internal use", + "offset_int": "0x0038", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0003C", + "name": "Reserved 0x0003C", + "description": "This field is reserved for internal use", + "offset_int": "0x003C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00040", + "name": "Reserved 0x00040", + "description": "This field is reserved for internal use", + "offset_int": "0x0040", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00044", + "name": "Reserved 0x00044", + "description": "This field is reserved for internal use", + "offset_int": "0x0044", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved00048", + "name": "Reserved 0x00048", + "description": "This field is reserved for internal use", + "offset_int": "0x0048", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "Reserved0004C", + "name": "Reserved 0x0004C", + "description": "This field is reserved for internal use", + "offset_int": "0x004C", + "is_reserved": true, + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "BLE", + "description": "BLE unique addressing" + }, + "registers": [ + { + "id": "field050", + "name": "BLE_UNIQUE_ADDRESS0", + "description": "Bits 31 down to 0 of the BLE Unique Address to be used when BLE_UNIQUE_ADDRESS_VALID field is equal to 0xC3A5", + "offset_int": "0x0050", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field054", + "name": "BLE_UNIQUE_ADDRESS1", + "description": "BLE_UNIQUE_ADDRESS part 2", + "offset_int": "0x0054", + "default_value_int": "0", + "individual_write_lock": "none", + "bitfields": [ + { + "width": 16, + "id": "field054-bits0-15", + "name": "BLE_UNIQUE_ADDRESS_47_32", + "description": "Bits 47 down to 32 of the BLE Unique Address to be used when BLE_UNIQUE_ADDRESS_VALID field is equal to 0xC3A5" + }, + { + "width": 16, + "id": "field054-bits16-31", + "name": "BLE_UNIQUE_ADDRESS_VALID", + "description": "Use 48-bit value from BLE_UNIQUE_ADDRESS field as BLE address when this field is equal to 0xC3A5. If this field is different from 0xC3A5, check BLE_DEFAULT_ADDRESS_VALID field in NMPA to know which address to use." + } + ] + } + ] + }, + { + "group": { + "name": "FLASH_REMAP", + "description": "Flash image address remapping" + }, + "registers": [ + { + "id": "field058", + "name": "FLASH_REMAP_SIZE", + "description": "This 32-bit register contains the size of the image to remap, in bytes.", + "offset_int": "0x0058", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field05C", + "name": "FLASH_REMAP_OFFSET", + "description": "This 32-bit register contains the offset by which the image is to be remapped.", + "offset_int": "0x005C", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH fields" + }, + "registers": [ + { + "id": "field060", + "name": "ROTKH0", + "description": "ROTKH0 for Root of Trust Keys Table hash[255:224]", + "offset_int": "0x0060", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field064", + "name": "ROTKH1", + "description": "ROTKH1 for Root of Trust Keys Table hash[223:192]", + "offset_int": "0x0064", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field068", + "name": "ROTKH2", + "description": "ROTKH2 for Root of Trust Keys Table hash[191:160]", + "offset_int": "0x0068", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field06C", + "name": "ROTKH3", + "description": "ROTKH3 for Root of Trust Keys Table hash[159:128]", + "offset_int": "0x006C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field070", + "name": "ROTKH4", + "description": "ROTKH4 for Root of Trust Keys Table hash[127:96]", + "offset_int": "0x0070", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field074", + "name": "ROTKH5", + "description": "ROTKH5 for Root of Trust Keys Table hash[95:64]", + "offset_int": "0x0074", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field078", + "name": "ROTKH6", + "description": "ROTKH6 for Root of Trust Keys Table hash[63:32]", + "offset_int": "0x0078", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field07C", + "name": "ROTKH7", + "description": "ROTKH7 for Root of Trust Keys Table hash[31:0]", + "offset_int": "0x007C", + "access": "RO", + "default_value_int": "0", + "individual_write_lock": "none" + } + ] + }, + { + "group": { + "name": "Customer defined", + "description": "Customer defined" + }, + "registers": [ + { + "id": "field080", + "name": "CUSTOMER_DEFINED0", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0080", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field084", + "name": "CUSTOMER_DEFINED1", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field088", + "name": "CUSTOMER_DEFINED2", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0088", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field08C", + "name": "CUSTOMER_DEFINED3", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x008C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field090", + "name": "CUSTOMER_DEFINED4", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0090", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field094", + "name": "CUSTOMER_DEFINED5", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0094", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field098", + "name": "CUSTOMER_DEFINED6", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x0098", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field09C", + "name": "CUSTOMER_DEFINED7", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x009C", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A0", + "name": "CUSTOMER_DEFINED8", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A4", + "name": "CUSTOMER_DEFINED9", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0A8", + "name": "CUSTOMER_DEFINED10", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00A8", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0AC", + "name": "CUSTOMER_DEFINED11", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00AC", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B0", + "name": "CUSTOMER_DEFINED12", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B0", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B4", + "name": "CUSTOMER_DEFINED13", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B4", + "default_value_int": "0", + "individual_write_lock": "none" + }, + { + "id": "field0B8", + "name": "CUSTOMER_DEFINED14", + "description": "Customer Defined (Programmable through ROM API)", + "offset_int": "0x00B8", + "default_value_int": "0", + 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b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/tz.json new file mode 100644 index 0000000..efc38b9 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/nhs52s04/tz.json @@ -0,0 +1,861 @@ +{ + "cpu": "nhs52s04", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x20000" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register(cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register(cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register(cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register(cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register(cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register(cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register(cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register(cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0xfffffe1" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x20004000" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0xefffffe1" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x1000fe00" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x1000ffe3" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "description": "TrustZone register - FLASH/ROM Slave Rule Register 0 (flash_rom_slave_rule)", + "default_value_int": "0x30" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "FLASH Memory Rule Register 0 (flash_mem_rule0)", + "description": "TrustZone register - FLASH Memory Rule Register 0 (flash_mem_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "FLASH Memory Rule Register 1 (flash_mem_rule1)", + "description": "TrustZone register - FLASH Memory Rule Register 1 (flash_mem_rule1)", + "default_value_int": "0x32103210" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "FLASH Memory Rule Register 2 (flash_mem_rule2)", + "description": "TrustZone register - FLASH Memory Rule Register 2 (flash_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "RAMX Slave Rule Register (ramx_slave_rule)", + "description": "TrustZone register - RAMX Slave Rule Register (ramx_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "RAMX Memory Rule Register 0 (ramx_mem_rule)", + "description": "TrustZone register - RAMX Memory Rule Register 0 (ramx_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "RAM0 Slave Rule Register (ram0_slave_rule)", + "description": "TrustZone register - RAM0 Slave Rule Register (ram0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "description": "TrustZone register - RAM0 Memory Rule Register 0 (ram0_mem_rule)", + "default_value_int": "0x3333" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "RAM1 Slave Rule Register (ram1_slave_rule)", + "description": "TrustZone register - RAM1 Slave Rule Register (ram1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "description": "TrustZone register - RAM1 Memory Rule Register 0 (ram1_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "RAM2 Slave Rule Register (ram2_slave_rule)", + "description": "TrustZone register - RAM2 Slave Rule Register (ram2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "description": "TrustZone register - RAM2 Memory Rule Register 0 (ram2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "description": "TrustZone register - RAM2 Memory Rule Register 1 (ram2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "SPIFI Slave Rule Register (spifi_slave_rule)", + "description": "TrustZone register - SPIFI Slave Rule Register (spifi_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 0 (spifi_mem_rule0)", + "description": "TrustZone register - SPIFI Memory Rule Register 0 (spifi_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 1 (spifi_mem_rule1)", + "description": "TrustZone register - SPIFI Memory Rule Register 1 (spifi_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 2 (spifi_mem_rule2)", + "description": "TrustZone register - SPIFI Memory Rule Register 2 (spifi_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "SPIFI Memory Rule Register 3 (spifi_mem_rule3)", + "description": "TrustZone register - SPIFI Memory Rule Register 3 (spifi_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "description": "TrustZone register - APB Bridge Group Slave Rule Register (apb_grp_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x33" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "AHB port 7 Slave Rule Register 0 (ahb_port7_slave_rule0)", + "description": "TrustZone register - AHB port 7 Slave Rule Register 0 (ahb_port7_slave_rule0)", + "default_value_int": "0x3000000" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "AHB port 7 Slave Rule Register 1 (ahb_port7_slave_rule1)", + "description": "TrustZone register - AHB port 7 Slave Rule Register 1 (ahb_port7_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "AHB port 8 Slave Rule Register 0 (ahb_port8_slave_rule0)", + "description": "TrustZone register - AHB port 8 Slave Rule Register 0 (ahb_port8_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "AHB port 8 Slave Rule Register 1 (ahb_port8_slave_rule1)", + "description": "TrustZone register - AHB port 8 Slave Rule Register 1 (ahb_port8_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "AHB port 9 Slave Rule Register 0 (ahb_port9_slave_rule0)", + "description": "TrustZone register - AHB port 9 Slave Rule Register 0 (ahb_port9_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "AHB port 9 Slave Rule Register 1 (ahb_port9_slave_rule1)", + "description": "TrustZone register - AHB port 9 Slave Rule Register 1 (ahb_port9_slave_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "AHB port 10 Slave Rule Register 0 (ahb_port10_slave_rule0)", + "description": "TrustZone register - AHB port 10 Slave Rule Register 0 (ahb_port10_slave_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "AHB Memory Rule Register 0 (ahb_mem_rule0)", + "description": "TrustZone register - AHB Memory Rule Register 0 (ahb_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "Secure GPIO Register 0 (sec_gp_reg0)", + "description": "TrustZone register - Secure GPIO Register 0 (sec_gp_reg0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "Secure GPIO Lock Register (sec_gp_reg_lock)", + "description": "TrustZone register - Secure GPIO Lock Register (sec_gp_reg_lock)", + "default_value_int": "0x2" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "CM33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - CM33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x400002a9" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0xaaaa" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw610/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw610/database.yaml new file mode 100644 index 0000000..0af961b --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw610/database.yaml @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +alias: rw612 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/database.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/database.yaml new file mode 100644 index 0000000..6d6497f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/database.yaml @@ -0,0 +1,250 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +revisions: + a1: + # ======== DAT section ======== + dat: + socc: 0x04 # SOCC identification is same as on LPC55S3x in rev 1 + a2: {} +latest: a2 + +# General MCU information +info: + purpose: Wireless Connectivity MCUs + spsdk_predecessor_name: rw61x + # Web page of MCU representative + web: https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/wireless-mcu-with-integrated-tri-radio-1x1-wi-fi-6-plus-bluetooth-low-energy-5-4-802-15-4:RW612 + memory_map: # Memory map basic info + flexspi_ns: + start_int: 0x8000000 + size_int: 0x8000000 + external: true + flexspi_s: + start_int: 0x18000000 + size_int: 0x8000000 + external: true + mirror_of: flexspi_ns + sram: + start_int: 0x20000000 + size_int: 0x130000 + external: false + isp: + rom: + protocol: mboot + usb: + - vid: 0x1FC9 + pid: 0x0020 + +features: + # ======== Blhost section ======== + blhost: {} + + # ======== Fuses description section ======== + fuses: + grouped_registers: + - uid: rkth + name: RKTH + width: 384 + config_as_hexstring: true + reversed: true + alternative_widths: [256] + description: + ROTKH field is compounded by 12 32-bit fields and contains Root key + table hash. For ECC P-256 keys RKTH is a 32-byte SHA-256 digest of four + SHA-256 digests computed over four OEM public keys (OEM has four + private-public key pairs in case one of its private keys becomes + compromised) or in case that ECC P-384 keys are used, RKTH is 48-byte + SHA-384 digest. + sub_regs: + [ + fuse104, + fuse105, + fuse106, + fuse107, + fuse108, + fuse109, + fuse110, + fuse111, + fuse112, + fuse113, + fuse114, + fuse115, + ] + + # ======== Communication buffer section ======== + comm_buffer: + address: 0x2000_8000 + size: 0x1000 + + # ======== Certificate block section ======== + cert_block: + sub_features: [based_on_cert21] + rot_type: cert_block_21 + + # ======== DAT section ======== + dat: + socc: 0x0A # SOCC identification + dac_rot_type: not_available # The Dac packet doesn't contains the ROT hash + dmbox_ap_ix: 3 + + # ======== MBI section ======== + mbi: + mbi_classes: + plain_xip: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvtZeroTotalLength + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + plain_ram: + image_type: PLAIN_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + crc_ram: + image_type: CRC_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + crc_xip: + image_type: CRC_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinTrustZoneMandatory + - Mbi_MixinLoadAddress + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppTrustZone + - Mbi_ExportMixinCrcSign + signed_ram: + image_type: SIGNED_RAM_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifest + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersion + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + signed_xip: + image_type: SIGNED_XIP_IMAGE + mixins: + - Mbi_MixinApp + - Mbi_MixinIvt + - Mbi_MixinCertBlockV21 + - Mbi_MixinManifest + - Mbi_MixinLoadAddress + - Mbi_MixinFwVersion + - Mbi_MixinImageVersion + - Mbi_ExportMixinAppCertBlockManifest + - Mbi_ExportMixinEccSign + images: + xip: + plain: plain_xip + crc: crc_xip + signed: signed_xip + load_to_ram: + plain: plain_ram + crc: crc_ram + signed: signed_ram + + # ======== Shadow registers section ======== + shadow_regs: + write_address_offset: -0x0FEE_4000 # = 0x4000_A000 - 0x3012_6000 The rw61x is using different address for shadow registers write operations + flush_func: rw61x_update_scratch_reg + reset_type: nvic_reset # possible options: [hw_reset, nvic_reset] + possible_verification: False # RW61x doesn't allow verify writing of shadow registers + inverted_regs: + fuse33: fuse34 # DCFG_CC_SOCU -> DCFG_CC_SOCU_AP + computed_fields: + fuse33: # DCFG_CC_SOCU + fuse33-bits-0-7: comalg_dcfg_cc_socu_crc8 # CRC8[7:0] + fuse31: # DCFG_CC_SOCU_NS + fuse31-bits-0-7: comalg_dcfg_cc_socu_crc8 # CRC8_NS[7:0] + + # ======== FCB section ======== + fcb: + mem_types: + flexspi_nor: + reg_spec: fcb_flexspi_nor.json + reg_spec_modification: ../../common/fcb_flexspi_nor_modification.yaml + + # ======== Bootable image section ======== + bootable_image: + mem_types: + internal: + segments: + mbi: 0x00 + flexspi_nor: + segments: + fcb: 0x0400 + image_version_ap: 0x0600 + mbi: 0x1000 + remap_align: 0x40000 # 256 KB + image_pattern: ones + + # ======== Secure binary v3.1 section ======== + sb31: + supported_commands: + - erase + - load + - execute + - programFuses + - programIFR + - copy + - loadKeyBlob + - configureMemory + - fillMemory + - checkFwVersion + + # ======== Device Hardware Security Module (HSM) section ======== + devhsm: + sub_features: [DevHsmSB31] + supported_commands: + - erase + - load + - programFuses + - copy + - loadKeyBlob + - configureMemory + - fillMemory + flag: 0x2 + key_blob_offset: 0xF05C + key_blob_command_position: -1 + + # ======== TrustZone section ======== + tz: + reg_spec: tz.json + + # ======== Memory configuration ======== + memcfg: + peripherals: + flexspi_nor: + instances: [0] + spi_nor: + instances: [0, 1, 2, 3, 4] + + # ======== EL2GO TP section ======== + el2go_tp: + el2go_name: RW6 + prov_method: dispatch_fw + dispatch_method: write_reset + fw_load_address: 0x0800_1000 + ignored_otp_ranges: [92, 103, 104, 115] + use_prov_report: true diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fcb_flexspi_nor.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fcb_flexspi_nor.json new file mode 100644 index 0000000..14ada34 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fcb_flexspi_nor.json @@ -0,0 +1,25599 @@ +{ + "cpu": "RW612", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "tag", + "description": " [0x000-0x003] Tag, fixed value 0x42464346UL ", + "default_value_int": "0x42464346" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "version", + "description": " [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix ", + "default_value_int": "0x56010400" + }, + { + "id": "Reserved008", + "offset_int": "0x8", + "reg_width": 32, + "name": "reserved0", + "description": " [0x008-0x00b] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 8, + "name": "readSampleClkSrc", + "description": " [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 ", + "default_value_int": "0x0" + }, + { + "id": "field00D", + "offset_int": "0xd", + "reg_width": 8, + "name": "csHoldTime", + "description": " [0x00d-0x00d] CS hold time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00E", + "offset_int": "0xe", + "reg_width": 8, + "name": "csSetupTime", + "description": " [0x00e-0x00e] CS setup time, default value: 3 ", + "default_value_int": "0x0" + }, + { + "id": "field00F", + "offset_int": "0xf", + "reg_width": 8, + "name": "columnAddressWidth", + "description": " [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet ", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 8, + "name": "deviceModeCfgEnable", + "description": " [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field011", + "offset_int": "0x11", + "reg_width": 8, + "name": "deviceModeType", + "description": " [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc. ", + "default_value_int": "0x0" + }, + { + "id": "field012", + "offset_int": "0x12", + "reg_width": 16, + "name": "waitTimeCfgCommands", + "description": " [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command ", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "deviceModeSeq", + "description": " [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field014-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field014-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "deviceModeArg", + "description": " [0x018-0x01b] Argument/Parameter for device configuration ", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 8, + "name": "configCmdEnable", + "description": " [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable ", + "default_value_int": "0x0" + }, + { + "id": "field01D", + "offset_int": "0x1d", + "reg_width": 8, + "name": "configModeType_0", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01E", + "offset_int": "0x1e", + "reg_width": 8, + "name": "configModeType_1", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field01F", + "offset_int": "0x1f", + "reg_width": 8, + "name": "configModeType_2", + "description": " [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe ", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "configCmdSeqs_0", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field020-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field020-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "configCmdSeqs_1", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field024-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field024-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "configCmdSeqs_2", + "description": " [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field028-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field028-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "reserved1", + "description": " [0x02c-0x02f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "configCmdArgs_0", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "configCmdArgs_1", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "configCmdArgs_2", + "description": " [0x030-0x03b] Arguments/Parameters for device Configuration commands ", + "default_value_int": "0x0" + }, + { + "id": "Reserved03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "reserved2", + "description": " [0x03c-0x03f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "controllerMiscOption", + "description": " [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details ", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 8, + "name": "deviceType", + "description": " [0x044-0x044] Device Type: See Flash Type Definition for more details ", + "default_value_int": "0x0" + }, + { + "id": "field045", + "offset_int": "0x45", + "reg_width": 8, + "name": "sflashPadType", + "description": " [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal ", + "default_value_int": "0x0" + }, + { + "id": "field046", + "offset_int": "0x46", + "reg_width": 8, + "name": "serialClkFreq", + "description": " [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot Chapter for more details ", + "default_value_int": "0x0" + }, + { + "id": "field047", + "offset_int": "0x47", + "reg_width": 8, + "name": "lutCustomSeqEnable", + "description": " [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH ", + "default_value_int": "0x0" + }, + { + "id": "Reserved048", + "offset_int": "0x48", + "reg_width": 32, + "name": "reserved3_0", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "reserved3_1", + "description": " [0x048-0x04f] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "sflashA1Size", + "description": " [0x050-0x053] Size of Flash connected to A1 ", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "sflashA2Size", + "description": " [0x054-0x057] Size of Flash connected to A2 ", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "sflashB1Size", + "description": " [0x058-0x05b] Size of Flash connected to B1 ", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "sflashB2Size", + "description": " [0x05c-0x05f] Size of Flash connected to B2 ", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "csPadSettingOverride", + "description": " [0x060-0x063] CS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "sclkPadSettingOverride", + "description": " [0x064-0x067] SCK pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "dataPadSettingOverride", + "description": " [0x068-0x06b] data pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "dqsPadSettingOverride", + "description": " [0x06c-0x06f] DQS pad setting override value ", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "timeoutInMs", + "description": " [0x070-0x073] Timeout threshold for read status command ", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "commandInterval", + "description": " [0x074-0x077] CS deselect interval between two commands ", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 16, + "name": "dataValidTime_0", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field078-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field078-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07A", + "offset_int": "0x7a", + "reg_width": 16, + "name": "dataValidTime_1", + "description": " [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field07A-bits0-7", + "width": 8, + "name": "time_100ps", + "access": "RW", + "description": " Data valid time, in terms of 100ps " + }, + { + "id": "field07A-bits8-15", + "width": 8, + "name": "delay_cells", + "access": "RW", + "description": " Data valid time, in terms of delay cells " + } + ] + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 16, + "name": "busyOffset", + "description": " [0x07c-0x07d] Busy offset, valid value: 0-31 ", + "default_value_int": "0x0" + }, + { + "id": "field07E", + "offset_int": "0x7e", + "reg_width": 16, + "name": "busyBitPolarity", + "description": " [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - busy flag is 0 when flash device is busy ", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 16, + "name": "lookupTable_seq0_instr0", + "description": "Lookup table holds Flash command sequences 0, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field080-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field080-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field080-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field082", + "offset_int": "0x82", + "reg_width": 16, + "name": "lookupTable_seq0_instr1", + "description": "Lookup table holds Flash command sequences 0, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field082-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field082-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field082-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 16, + "name": "lookupTable_seq0_instr2", + "description": "Lookup table holds Flash command sequences 0, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field084-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field084-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field084-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field086", + "offset_int": "0x86", + "reg_width": 16, + "name": "lookupTable_seq0_instr3", + "description": "Lookup table holds Flash command sequences 0, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field086-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field086-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field086-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 16, + "name": "lookupTable_seq0_instr4", + "description": "Lookup table holds Flash command sequences 0, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field088-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field088-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field088-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08A", + "offset_int": "0x8A", + "reg_width": 16, + "name": "lookupTable_seq0_instr5", + "description": "Lookup table holds Flash command sequences 0, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08C", + "offset_int": "0x8C", + "reg_width": 16, + "name": "lookupTable_seq0_instr6", + "description": "Lookup table holds Flash command sequences 0, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field08E", + "offset_int": "0x8E", + "reg_width": 16, + "name": "lookupTable_seq0_instr7", + "description": "Lookup table holds Flash command sequences 0, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field08E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field08E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field08E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 16, + "name": "lookupTable_seq1_instr0", + "description": "Lookup table holds Flash command sequences 1, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field090-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field090-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field090-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field092", + "offset_int": "0x92", + "reg_width": 16, + "name": "lookupTable_seq1_instr1", + "description": "Lookup table holds Flash command sequences 1, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field092-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field092-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field092-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 16, + "name": "lookupTable_seq1_instr2", + "description": "Lookup table holds Flash command sequences 1, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field094-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field094-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field094-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field096", + "offset_int": "0x96", + "reg_width": 16, + "name": "lookupTable_seq1_instr3", + "description": "Lookup table holds Flash command sequences 1, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field096-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field096-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field096-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 16, + "name": "lookupTable_seq1_instr4", + "description": "Lookup table holds Flash command sequences 1, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field098-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field098-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field098-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09A", + "offset_int": "0x9A", + "reg_width": 16, + "name": "lookupTable_seq1_instr5", + "description": "Lookup table holds Flash command sequences 1, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09C", + "offset_int": "0x9C", + "reg_width": 16, + "name": "lookupTable_seq1_instr6", + "description": "Lookup table holds Flash command sequences 1, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field09E", + "offset_int": "0x9E", + "reg_width": 16, + "name": "lookupTable_seq1_instr7", + "description": "Lookup table holds Flash command sequences 1, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field09E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field09E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field09E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A0", + "offset_int": "0xA0", + "reg_width": 16, + "name": "lookupTable_seq2_instr0", + "description": "Lookup table holds Flash command sequences 2, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A2", + "offset_int": "0xA2", + "reg_width": 16, + "name": "lookupTable_seq2_instr1", + "description": "Lookup table holds Flash command sequences 2, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A4", + "offset_int": "0xA4", + "reg_width": 16, + "name": "lookupTable_seq2_instr2", + "description": "Lookup table holds Flash command sequences 2, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A6", + "offset_int": "0xA6", + "reg_width": 16, + "name": "lookupTable_seq2_instr3", + "description": "Lookup table holds Flash command sequences 2, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0A8", + "offset_int": "0xA8", + "reg_width": 16, + "name": "lookupTable_seq2_instr4", + "description": "Lookup table holds Flash command sequences 2, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0A8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0A8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0A8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AA", + "offset_int": "0xAA", + "reg_width": 16, + "name": "lookupTable_seq2_instr5", + "description": "Lookup table holds Flash command sequences 2, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AC", + "offset_int": "0xAC", + "reg_width": 16, + "name": "lookupTable_seq2_instr6", + "description": "Lookup table holds Flash command sequences 2, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0AE", + "offset_int": "0xAE", + "reg_width": 16, + "name": "lookupTable_seq2_instr7", + "description": "Lookup table holds Flash command sequences 2, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0AE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0AE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0AE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B0", + "offset_int": "0xB0", + "reg_width": 16, + "name": "lookupTable_seq3_instr0", + "description": "Lookup table holds Flash command sequences 3, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B2", + "offset_int": "0xB2", + "reg_width": 16, + "name": "lookupTable_seq3_instr1", + "description": "Lookup table holds Flash command sequences 3, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B4", + "offset_int": "0xB4", + "reg_width": 16, + "name": "lookupTable_seq3_instr2", + "description": "Lookup table holds Flash command sequences 3, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B6", + "offset_int": "0xB6", + "reg_width": 16, + "name": "lookupTable_seq3_instr3", + "description": "Lookup table holds Flash command sequences 3, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0B8", + "offset_int": "0xB8", + "reg_width": 16, + "name": "lookupTable_seq3_instr4", + "description": "Lookup table holds Flash command sequences 3, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0B8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0B8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0B8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BA", + "offset_int": "0xBA", + "reg_width": 16, + "name": "lookupTable_seq3_instr5", + "description": "Lookup table holds Flash command sequences 3, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BC", + "offset_int": "0xBC", + "reg_width": 16, + "name": "lookupTable_seq3_instr6", + "description": "Lookup table holds Flash command sequences 3, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0BE", + "offset_int": "0xBE", + "reg_width": 16, + "name": "lookupTable_seq3_instr7", + "description": "Lookup table holds Flash command sequences 3, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0BE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0BE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0BE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C0", + "offset_int": "0xC0", + "reg_width": 16, + "name": "lookupTable_seq4_instr0", + "description": "Lookup table holds Flash command sequences 4, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C2", + "offset_int": "0xC2", + "reg_width": 16, + "name": "lookupTable_seq4_instr1", + "description": "Lookup table holds Flash command sequences 4, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C4", + "offset_int": "0xC4", + "reg_width": 16, + "name": "lookupTable_seq4_instr2", + "description": "Lookup table holds Flash command sequences 4, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C6", + "offset_int": "0xC6", + "reg_width": 16, + "name": "lookupTable_seq4_instr3", + "description": "Lookup table holds Flash command sequences 4, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0C8", + "offset_int": "0xC8", + "reg_width": 16, + "name": "lookupTable_seq4_instr4", + "description": "Lookup table holds Flash command sequences 4, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0C8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0C8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0C8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CA", + "offset_int": "0xCA", + "reg_width": 16, + "name": "lookupTable_seq4_instr5", + "description": "Lookup table holds Flash command sequences 4, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CC", + "offset_int": "0xCC", + "reg_width": 16, + "name": "lookupTable_seq4_instr6", + "description": "Lookup table holds Flash command sequences 4, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0CE", + "offset_int": "0xCE", + "reg_width": 16, + "name": "lookupTable_seq4_instr7", + "description": "Lookup table holds Flash command sequences 4, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0CE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0CE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0CE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D0", + "offset_int": "0xD0", + "reg_width": 16, + "name": "lookupTable_seq5_instr0", + "description": "Lookup table holds Flash command sequences 5, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D2", + "offset_int": "0xD2", + "reg_width": 16, + "name": "lookupTable_seq5_instr1", + "description": "Lookup table holds Flash command sequences 5, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D4", + "offset_int": "0xD4", + "reg_width": 16, + "name": "lookupTable_seq5_instr2", + "description": "Lookup table holds Flash command sequences 5, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D6", + "offset_int": "0xD6", + "reg_width": 16, + "name": "lookupTable_seq5_instr3", + "description": "Lookup table holds Flash command sequences 5, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0D8", + "offset_int": "0xD8", + "reg_width": 16, + "name": "lookupTable_seq5_instr4", + "description": "Lookup table holds Flash command sequences 5, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0D8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0D8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0D8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DA", + "offset_int": "0xDA", + "reg_width": 16, + "name": "lookupTable_seq5_instr5", + "description": "Lookup table holds Flash command sequences 5, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DC", + "offset_int": "0xDC", + "reg_width": 16, + "name": "lookupTable_seq5_instr6", + "description": "Lookup table holds Flash command sequences 5, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0DE", + "offset_int": "0xDE", + "reg_width": 16, + "name": "lookupTable_seq5_instr7", + "description": "Lookup table holds Flash command sequences 5, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0DE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0DE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0DE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E0", + "offset_int": "0xE0", + "reg_width": 16, + "name": "lookupTable_seq6_instr0", + "description": "Lookup table holds Flash command sequences 6, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E2", + "offset_int": "0xE2", + "reg_width": 16, + "name": "lookupTable_seq6_instr1", + "description": "Lookup table holds Flash command sequences 6, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E4", + "offset_int": "0xE4", + "reg_width": 16, + "name": "lookupTable_seq6_instr2", + "description": "Lookup table holds Flash command sequences 6, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E6", + "offset_int": "0xE6", + "reg_width": 16, + "name": "lookupTable_seq6_instr3", + "description": "Lookup table holds Flash command sequences 6, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0E8", + "offset_int": "0xE8", + "reg_width": 16, + "name": "lookupTable_seq6_instr4", + "description": "Lookup table holds Flash command sequences 6, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0E8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0E8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0E8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EA", + "offset_int": "0xEA", + "reg_width": 16, + "name": "lookupTable_seq6_instr5", + "description": "Lookup table holds Flash command sequences 6, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EC", + "offset_int": "0xEC", + "reg_width": 16, + "name": "lookupTable_seq6_instr6", + "description": "Lookup table holds Flash command sequences 6, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0EE", + "offset_int": "0xEE", + "reg_width": 16, + "name": "lookupTable_seq6_instr7", + "description": "Lookup table holds Flash command sequences 6, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0EE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0EE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0EE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F0", + "offset_int": "0xF0", + "reg_width": 16, + "name": "lookupTable_seq7_instr0", + "description": "Lookup table holds Flash command sequences 7, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F0-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F0-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F0-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F2", + "offset_int": "0xF2", + "reg_width": 16, + "name": "lookupTable_seq7_instr1", + "description": "Lookup table holds Flash command sequences 7, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F2-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F2-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F2-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F4", + "offset_int": "0xF4", + "reg_width": 16, + "name": "lookupTable_seq7_instr2", + "description": "Lookup table holds Flash command sequences 7, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F4-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F4-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F4-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F6", + "offset_int": "0xF6", + "reg_width": 16, + "name": "lookupTable_seq7_instr3", + "description": "Lookup table holds Flash command sequences 7, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F6-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F6-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F6-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0F8", + "offset_int": "0xF8", + "reg_width": 16, + "name": "lookupTable_seq7_instr4", + "description": "Lookup table holds Flash command sequences 7, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0F8-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0F8-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0F8-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FA", + "offset_int": "0xFA", + "reg_width": 16, + "name": "lookupTable_seq7_instr5", + "description": "Lookup table holds Flash command sequences 7, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FA-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FA-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FA-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FC", + "offset_int": "0xFC", + "reg_width": 16, + "name": "lookupTable_seq7_instr6", + "description": "Lookup table holds Flash command sequences 7, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FC-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FC-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FC-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field0FE", + "offset_int": "0xFE", + "reg_width": 16, + "name": "lookupTable_seq7_instr7", + "description": "Lookup table holds Flash command sequences 7, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field0FE-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field0FE-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field0FE-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 16, + "name": "lookupTable_seq8_instr0", + "description": "Lookup table holds Flash command sequences 8, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field100-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field100-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field100-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field102", + "offset_int": "0x102", + "reg_width": 16, + "name": "lookupTable_seq8_instr1", + "description": "Lookup table holds Flash command sequences 8, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field102-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field102-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field102-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 16, + "name": "lookupTable_seq8_instr2", + "description": "Lookup table holds Flash command sequences 8, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field104-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field104-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field104-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field106", + "offset_int": "0x106", + "reg_width": 16, + "name": "lookupTable_seq8_instr3", + "description": "Lookup table holds Flash command sequences 8, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field106-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field106-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field106-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 16, + "name": "lookupTable_seq8_instr4", + "description": "Lookup table holds Flash command sequences 8, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field108-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field108-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field108-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10A", + "offset_int": "0x10A", + "reg_width": 16, + "name": "lookupTable_seq8_instr5", + "description": "Lookup table holds Flash command sequences 8, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10C", + "offset_int": "0x10C", + "reg_width": 16, + "name": "lookupTable_seq8_instr6", + "description": "Lookup table holds Flash command sequences 8, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field10E", + "offset_int": "0x10E", + "reg_width": 16, + "name": "lookupTable_seq8_instr7", + "description": "Lookup table holds Flash command sequences 8, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field10E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field10E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field10E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 16, + "name": "lookupTable_seq9_instr0", + "description": "Lookup table holds Flash command sequences 9, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field110-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field110-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field110-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field112", + "offset_int": "0x112", + "reg_width": 16, + "name": "lookupTable_seq9_instr1", + "description": "Lookup table holds Flash command sequences 9, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field112-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field112-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field112-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 16, + "name": "lookupTable_seq9_instr2", + "description": "Lookup table holds Flash command sequences 9, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field114-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field114-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field114-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field116", + "offset_int": "0x116", + "reg_width": 16, + "name": "lookupTable_seq9_instr3", + "description": "Lookup table holds Flash command sequences 9, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field116-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field116-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field116-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 16, + "name": "lookupTable_seq9_instr4", + "description": "Lookup table holds Flash command sequences 9, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field118-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field118-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field118-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11A", + "offset_int": "0x11A", + "reg_width": 16, + "name": "lookupTable_seq9_instr5", + "description": "Lookup table holds Flash command sequences 9, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11C", + "offset_int": "0x11C", + "reg_width": 16, + "name": "lookupTable_seq9_instr6", + "description": "Lookup table holds Flash command sequences 9, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field11E", + "offset_int": "0x11E", + "reg_width": 16, + "name": "lookupTable_seq9_instr7", + "description": "Lookup table holds Flash command sequences 9, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field11E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field11E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field11E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 16, + "name": "lookupTable_seq10_instr0", + "description": "Lookup table holds Flash command sequences 10, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field120-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field120-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field120-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field122", + "offset_int": "0x122", + "reg_width": 16, + "name": "lookupTable_seq10_instr1", + "description": "Lookup table holds Flash command sequences 10, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field122-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field122-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field122-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 16, + "name": "lookupTable_seq10_instr2", + "description": "Lookup table holds Flash command sequences 10, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field124-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field124-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field124-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field126", + "offset_int": "0x126", + "reg_width": 16, + "name": "lookupTable_seq10_instr3", + "description": "Lookup table holds Flash command sequences 10, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field126-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field126-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field126-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 16, + "name": "lookupTable_seq10_instr4", + "description": "Lookup table holds Flash command sequences 10, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field128-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field128-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field128-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12A", + "offset_int": "0x12A", + "reg_width": 16, + "name": "lookupTable_seq10_instr5", + "description": "Lookup table holds Flash command sequences 10, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12C", + "offset_int": "0x12C", + "reg_width": 16, + "name": "lookupTable_seq10_instr6", + "description": "Lookup table holds Flash command sequences 10, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field12E", + "offset_int": "0x12E", + "reg_width": 16, + "name": "lookupTable_seq10_instr7", + "description": "Lookup table holds Flash command sequences 10, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field12E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field12E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field12E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 16, + "name": "lookupTable_seq11_instr0", + "description": "Lookup table holds Flash command sequences 11, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field130-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field130-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field130-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field132", + "offset_int": "0x132", + "reg_width": 16, + "name": "lookupTable_seq11_instr1", + "description": "Lookup table holds Flash command sequences 11, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field132-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field132-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field132-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 16, + "name": "lookupTable_seq11_instr2", + "description": "Lookup table holds Flash command sequences 11, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field134-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field134-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field134-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field136", + "offset_int": "0x136", + "reg_width": 16, + "name": "lookupTable_seq11_instr3", + "description": "Lookup table holds Flash command sequences 11, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field136-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field136-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field136-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 16, + "name": "lookupTable_seq11_instr4", + "description": "Lookup table holds Flash command sequences 11, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field138-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field138-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field138-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13A", + "offset_int": "0x13A", + "reg_width": 16, + "name": "lookupTable_seq11_instr5", + "description": "Lookup table holds Flash command sequences 11, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13C", + "offset_int": "0x13C", + "reg_width": 16, + "name": "lookupTable_seq11_instr6", + "description": "Lookup table holds Flash command sequences 11, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field13E", + "offset_int": "0x13E", + "reg_width": 16, + "name": "lookupTable_seq11_instr7", + "description": "Lookup table holds Flash command sequences 11, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field13E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field13E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field13E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 16, + "name": "lookupTable_seq12_instr0", + "description": "Lookup table holds Flash command sequences 12, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field140-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field140-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field140-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field142", + "offset_int": "0x142", + "reg_width": 16, + "name": "lookupTable_seq12_instr1", + "description": "Lookup table holds Flash command sequences 12, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field142-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field142-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field142-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 16, + "name": "lookupTable_seq12_instr2", + "description": "Lookup table holds Flash command sequences 12, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field144-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field144-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field144-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field146", + "offset_int": "0x146", + "reg_width": 16, + "name": "lookupTable_seq12_instr3", + "description": "Lookup table holds Flash command sequences 12, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field146-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field146-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field146-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 16, + "name": "lookupTable_seq12_instr4", + "description": "Lookup table holds Flash command sequences 12, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field148-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field148-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field148-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14A", + "offset_int": "0x14A", + "reg_width": 16, + "name": "lookupTable_seq12_instr5", + "description": "Lookup table holds Flash command sequences 12, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14C", + "offset_int": "0x14C", + "reg_width": 16, + "name": "lookupTable_seq12_instr6", + "description": "Lookup table holds Flash command sequences 12, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field14E", + "offset_int": "0x14E", + "reg_width": 16, + "name": "lookupTable_seq12_instr7", + "description": "Lookup table holds Flash command sequences 12, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field14E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field14E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field14E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 16, + "name": "lookupTable_seq13_instr0", + "description": "Lookup table holds Flash command sequences 13, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field150-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field150-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field150-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field152", + "offset_int": "0x152", + "reg_width": 16, + "name": "lookupTable_seq13_instr1", + "description": "Lookup table holds Flash command sequences 13, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field152-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field152-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field152-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 16, + "name": "lookupTable_seq13_instr2", + "description": "Lookup table holds Flash command sequences 13, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field154-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field154-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field154-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field156", + "offset_int": "0x156", + "reg_width": 16, + "name": "lookupTable_seq13_instr3", + "description": "Lookup table holds Flash command sequences 13, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field156-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field156-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field156-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 16, + "name": "lookupTable_seq13_instr4", + "description": "Lookup table holds Flash command sequences 13, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field158-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field158-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field158-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15A", + "offset_int": "0x15A", + "reg_width": 16, + "name": "lookupTable_seq13_instr5", + "description": "Lookup table holds Flash command sequences 13, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15C", + "offset_int": "0x15C", + "reg_width": 16, + "name": "lookupTable_seq13_instr6", + "description": "Lookup table holds Flash command sequences 13, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field15E", + "offset_int": "0x15E", + "reg_width": 16, + "name": "lookupTable_seq13_instr7", + "description": "Lookup table holds Flash command sequences 13, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field15E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field15E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field15E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 16, + "name": "lookupTable_seq14_instr0", + "description": "Lookup table holds Flash command sequences 14, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field160-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field160-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field160-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field162", + "offset_int": "0x162", + "reg_width": 16, + "name": "lookupTable_seq14_instr1", + "description": "Lookup table holds Flash command sequences 14, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field162-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field162-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field162-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 16, + "name": "lookupTable_seq14_instr2", + "description": "Lookup table holds Flash command sequences 14, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field164-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field164-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field164-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field166", + "offset_int": "0x166", + "reg_width": 16, + "name": "lookupTable_seq14_instr3", + "description": "Lookup table holds Flash command sequences 14, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field166-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field166-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field166-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 16, + "name": "lookupTable_seq14_instr4", + "description": "Lookup table holds Flash command sequences 14, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field168-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field168-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field168-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16A", + "offset_int": "0x16A", + "reg_width": 16, + "name": "lookupTable_seq14_instr5", + "description": "Lookup table holds Flash command sequences 14, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16C", + "offset_int": "0x16C", + "reg_width": 16, + "name": "lookupTable_seq14_instr6", + "description": "Lookup table holds Flash command sequences 14, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field16E", + "offset_int": "0x16E", + "reg_width": 16, + "name": "lookupTable_seq14_instr7", + "description": "Lookup table holds Flash command sequences 14, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field16E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field16E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field16E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 16, + "name": "lookupTable_seq15_instr0", + "description": "Lookup table holds Flash command sequences 15, instruction 0", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field170-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field170-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field170-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field172", + "offset_int": "0x172", + "reg_width": 16, + "name": "lookupTable_seq15_instr1", + "description": "Lookup table holds Flash command sequences 15, instruction 1", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field172-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field172-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field172-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 16, + "name": "lookupTable_seq15_instr2", + "description": "Lookup table holds Flash command sequences 15, instruction 2", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field174-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field174-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field174-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field176", + "offset_int": "0x176", + "reg_width": 16, + "name": "lookupTable_seq15_instr3", + "description": "Lookup table holds Flash command sequences 15, instruction 3", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field176-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field176-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field176-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 16, + "name": "lookupTable_seq15_instr4", + "description": "Lookup table holds Flash command sequences 15, instruction 4", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field178-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field178-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field178-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17A", + "offset_int": "0x17A", + "reg_width": 16, + "name": "lookupTable_seq15_instr5", + "description": "Lookup table holds Flash command sequences 15, instruction 5", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17A-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17A-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17A-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17C", + "offset_int": "0x17C", + "reg_width": 16, + "name": "lookupTable_seq15_instr6", + "description": "Lookup table holds Flash command sequences 15, instruction 6", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17C-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17C-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17C-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field17E", + "offset_int": "0x17E", + "reg_width": 16, + "name": "lookupTable_seq15_instr7", + "description": "Lookup table holds Flash command sequences 15, instruction 7", + "default_value_int": "0x0", + "bitfields": [ + { + "width": 8, + "id": "field17E-bits-0-7", + "name": "OPERAND", + "description": "Instruction operand. Its values depends on used instruction" + }, + { + "width": 2, + "id": "field17E-bits-8-9", + "name": "NUM_PADS", + "description": "Number of pads used by instruction. Some instructions ignores this parameter.", + "values": [ + { + "name": "1PAD", + "value": 0, + "description": "Single mode. One pad is used." + }, + { + "name": "2PAD", + "value": 1, + "description": "Dual mode. Two pads are used." + }, + { + "name": "4PAD", + "value": 2, + "description": "Quad mode. Four pads are used." + }, + { + "name": "8PAD", + "value": 3, + "description": "Octal mode. Eight pads are used." + } + ] + }, + { + "width": 6, + "id": "field17E-bits-10-15", + "name": "OPERATION_CODE", + "description": "Instruction operation code.", + "values": [ + { + "name": "STOP", + "value": 0, + "description": "Stop execution and de-assert CS. Then, the next command sequence (to the same flash device) starts from instruction pointer 0." + }, + { + "name": "CMD_SDR", + "value": 1, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_SDR", + "value": 2, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_SDR", + "value": 3, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_SDR", + "value": 4, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_SDR", + "value": 5, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_SDR", + "value": 6, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_SDR", + "value": 7, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_SDR", + "value": 8, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_SDR", + "value": 9, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_SDR", + "value": 10, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_SDR", + "value": 11, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_SDR", + "value": 12, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_SDR", + "value": 13, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + }, + { + "name": "JMP_ON_CS", + "value": 31, + "description": "Stop execution, de-assert CS and save operand[7:0] as the instruction start pointer for next sequence.Normally this instruction is used to support Execute-In-Place enhanced mode. See XIP enhanced mode for more details.This instruction is only allowed for AHB read commands. There is interrupt status bit set (INTR[IPCMDERR] or INTR[AHBCMDERR]) when using this instruction in IP command or AHB write command." + }, + { + "name": "CMD_DDR", + "value": 33, + "description": "Transmit command code to Flash." + }, + { + "name": "RADDR_DDR", + "value": 34, + "description": "Transmit row address to Flash." + }, + { + "name": "CADDR_DDR", + "value": 35, + "description": "Transmit column address to Flash." + }, + { + "name": "MODE1_DDR", + "value": 36, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE2_DDR", + "value": 37, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE4_DDR", + "value": 38, + "description": "Transmit mode bits to Flash." + }, + { + "name": "MODE8_DDR", + "value": 39, + "description": "Transmit mode bits to Flash." + }, + { + "name": "WRITE_DDR", + "value": 40, + "description": "Transmit program data to Flash device." + }, + { + "name": "READ_DDR", + "value": 41, + "description": "Receive read data from Flash device. Read data is put into AHB_RX_BUF or IP_RX_FIFO." + }, + { + "name": "LEARN_DDR", + "value": 42, + "description": "Receive read data or Preamble bit from Flash deviceThe FlexSPI controller will compare the data line bits with DLPR register to determine a correct sampling clock phase." + }, + { + "name": "DATSZ_DDR", + "value": 43, + "description": "Transmit read or program data size (byte number) to Flash device." + }, + { + "name": "DUMMY_DDR", + "value": 44, + "description": "Leave data lines undriven by the FlexSPI controller. Turnaround cycles are provided from host driving to device driving. num_pads determines the number of pads in input mode." + }, + { + "name": "DUMMY_RWDS_DDR", + "value": 45, + "description": "This instruction is similar to DUMMY_SDR/DUMMY_DDR instruction. The difference lies in the dummy cycle number.DQS pin is called RWDS in HyperBus specification. See Dummy instruction for more details.Set operand as 'Latency count' for HyperBus devices." + } + ] + } + ] + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "lutCustomSeq_0", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field180-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field180-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "lutCustomSeq_1", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field184-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field184-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "lutCustomSeq_2", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field188-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field188-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "lutCustomSeq_3", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field18C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field18C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "lutCustomSeq_4", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field190-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field190-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "lutCustomSeq_5", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field194-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field194-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "lutCustomSeq_6", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field198-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field198-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "lutCustomSeq_7", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field19C-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field19C-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "lutCustomSeq_8", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A0-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A0-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "lutCustomSeq_9", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A4-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A4-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "lutCustomSeq_10", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1A8-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1A8-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "lutCustomSeq_11", + "description": " [0x180-0x1af] Customizable LUT Sequences ", + "default_value_int": "0x0", + "bitfields": [ + { + "id": "field1AC-bits0-7", + "width": 8, + "name": "seqNum", + "access": "RW", + "description": " Sequence Number, valid number: 1-16 " + }, + { + "id": "field1AC-bits8-15", + "width": 8, + "name": "seqId", + "access": "RW", + "description": " Sequence Index, valid number: 0-15 " + }, + { + "width": 16 + } + ] + }, + { + "id": "Reserved1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "reserved4_0", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "reserved4_1", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "reserved4_2", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "Reserved1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "reserved4_3", + "description": " [0x1b0-0x1bf] Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "pageSize", + "description": " Page size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "sectorSize", + "description": " Sector size of Serial NOR ", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 8, + "name": "ipcmdSerialClkFreq", + "description": " Clock frequency for IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1C9", + "offset_int": "0x1c9", + "reg_width": 8, + "name": "isUniformBlockSize", + "description": " Sector/Block size is the same ", + "default_value_int": "0x0" + }, + { + "id": "field1CA", + "offset_int": "0x1ca", + "reg_width": 8, + "name": "isDataOrderSwapped", + "description": " Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) ", + "default_value_int": "0x0" + }, + { + "id": "Reserved1CB", + "offset_int": "0x1cb", + "reg_width": 8, + "name": "reserved0_0", + "description": " Reserved for future use ", + "default_value_int": "0x0", + "is_reserved": true + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 8, + "name": "serialNorType", + "description": " Serial NOR Flash type: 0/1/2/3 ", + "default_value_int": "0x0" + }, + { + "id": "field1CD", + "offset_int": "0x1cd", + "reg_width": 8, + "name": "needExitNoCmdMode", + "description": " Need to exit NoCmd mode before other IP command ", + "default_value_int": "0x0" + }, + { + "id": "field1CE", + "offset_int": "0x1ce", + "reg_width": 8, + "name": "halfClkForNonReadCmd", + "description": " Half the Serial Clock for non-read command: true/false ", + "default_value_int": "0x0" + }, + { + "id": "field1CF", + "offset_int": "0x1cf", + "reg_width": 8, + "name": "needRestoreNoCmdMode", + "description": " Need to Restore NoCmd mode after IP command execution ", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "blockSize", + "description": " Block size ", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "flashStateCtx", + "description": " Flash State Context ", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "reserve2_0", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "reserve2_1", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "reserve2_2", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "reserve2_3", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "reserve2_4", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "reserve2_5", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "reserve2_6", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "reserve2_7", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "reserve2_8", + "description": " Reserved for future use ", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "reserve2_9", + "description": " Reserved for future use ", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fuses.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fuses.json new file mode 100644 index 0000000..53c0ebe --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/fuses.json @@ -0,0 +1,5392 @@ +{ + "cpu": "RW612", + "shadow_reg_base_addr_int": "0x4000A000", + "groups": [ + { + "group": { + "name": "Lock Settings", + "description": "Lock settings configuration" + }, + "registers": [ + { + "id": "fuse0", + "name": "LOCK_CFG0", + "description": "Lock configuration fuse word 0.", + "index_int": "0", + "shadow_reg_offset_int": "0", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse0-bits-0-2", + "name": "BOOT_CFG_LOCK", + "description": "When set, BOOT_CFG_LOCK[2:0] bits controls read/write/override protection to BOOT_CFG 0-6 fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-3-5", + "name": "SEC_BOOT_CFG_LOCK", + "description": "When set, SEC_BOOT_CFG_LOCK[2:0] bits controls read/write/override protection to SEC_BOOT_CFG 0-8 fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse0-bits-9-11", + "name": "DCFG_CC_SOCU_NS_LOCK", + "description": "When set, DCFG_CC_SOCU_NS_LOCK[2:0] bits controls read/write/override protection to DCFG_CC_SOCU_NS fuse word.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3, + "id": "fuse0-bits-12-14", + "name": "LOCK_CFG_LOCK", + "description": "When set, LOCK_CFG_LOCK[2:0] bits controls read/write/override protection to LOCK_CFG 0-2 fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse1", + "name": "LOCK_CFG1", + "description": "Lock configuration fuse word 1.", + "index_int": "0x0001", + "shadow_reg_offset_int": "0x0004", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3, + "id": "fuse1-bits-0-2", + "name": "CUST_KEY_LOCK", + "description": "When set, CUST_KEY_LOCK[2:0] bits controls read/write/override protection to CUST_SK_MK and RKTH fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse1-bits-6-8", + "name": "DCFG_CC_SOCU_LOCK", + "description": "When set, DCFG_CC_SOCU_LOCK[2:0] bits controls read/write/override protection to DCFG_CC_SOCU and DCFG_CC_SOCU_AP fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-9-11", + "name": "LIFECYCLE_LOCK", + "description": "When set, LIFECYCLE_LOCK[2:0] bits controls read/write/override protection to LIFE_CYCLE_STATE fuse word.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3, + "id": "fuse1-bits-12-14", + "name": "CRC_HI_LOCK", + "description": "When set, CRC_HI_LOCK[2:0] bits controls read/write/override protection to CRC 4-7 fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse2", + "name": "LOCK_CFG2", + "description": "Lock configuration fuse word 2.", + "index_int": "0x0002", + "shadow_reg_offset_int": "0x0008", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3 + }, + { + "width": 3, + "id": "fuse2-bits-9-11", + "name": "CRC_LO_LOCK", + "description": "When set, CRC_LO_LOCK[2:0] bits controls read/write/override protection to CRC 0-3 fuse words.", + "values": [ + { + "name": "Unlocked", + "value": 0, + "description": "Unlocked" + }, + { + "name": "WR_LOCK", + "value": 1, + "description": "Write Lock" + }, + { + "name": "OP_LOCK", + "value": 2, + "description": "Operational Lock" + }, + { + "name": "OP+WP_LOCK", + "value": 3, + "description": "OP and WP_LOCK" + }, + { + "name": "RD_LOCK", + "value": 4, + "description": "Read Lock" + }, + { + "name": "RP+WP_LOCK", + "value": 5, + "description": "RP and WP_LOCK" + }, + { + "name": "RP+OP_LOCK", + "value": 6, + "description": "RP and OP_LOCK" + }, + { + "name": "All locks", + "value": 7, + "description": "All locks" + } + ] + }, + { + "width": 3 + }, + { + "width": 1 + } + ] + } + ] + }, + { + "group": { + "name": "OEM Configuration", + "description": "OEM configuration" + }, + "registers": [ + { + "id": "fuse15", + "name": "BOOT_CFG0", + "description": "Boot configuration fuse word 0.", + "index_int": "0x000F", + "shadow_reg_offset_int": "0x003C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse15-bits-0-3", + "name": "PRIMARY_BOOT_SOURCE", + "description": "Primary boot source. (a.k.a. Master boot source)", + "values": [ + { + "name": "ISP_PIN_BOOT", + "value": 0, + "description": "ISP pins will determine boot source." + }, + { + "name": "FLEXSPI_BOOT", + "value": 1, + "description": "Boot from FlexSPI flash device using FlexSPI interface pins." + }, + { + "name": "SDIO_BOOT", + "value": 3, + "description": "Boot from SDIO (Serial) port." + }, + { + "name": "SPI_BOOT", + "value": 4, + "description": "Boot using SPI slave interface using master boot mode." + }, + { + "name": "I2C_BOOT", + "value": 5, + "description": "I2C boot mode." + }, + { + "name": "UART_BOOT", + "value": 6, + "description": "Boot using UART interface using master boot mode." + }, + { + "name": "USBHID_BOOT", + "value": 8, + "description": "USB-HID boot mode." + }, + { + "name": "ISP_MODE", + "value": 9, + "description": "Always enter ISP mode. DEFAULT_ISP_MODE field will determine the ISP interface." + }, + { + "name": "Test_MODE", + "value": 10, + "description": "Reserved" + }, + { + "name": "QSPI_FALLBACK_SPINOR_BOOT", + "value": 12, + "description": "Boot from Octal/Quad SPI flash device using FlexSPI channel A interface pins. If image is not found check recovery boot using SPI flash device through FlexComm." + } + ] + }, + { + "width": 3, + "id": "fuse15-bits-4-6", + "name": "DEFAULT_ISP_MODE", + "description": "ISP boot mode", + "values": [ + { + "name": "AUTO_ISP", + "value": 0, + "description": "Auto detect ISP mode. The RW61x probes active peripheral from one of the below serial interfaces and download image from the probed peripherals: UART, I2C, SPI, USB-HID." + }, + { + "name": "USB_HID_ISP", + "value": 1, + "description": "The USB HID class is used to download the image of the USB0 port." + }, + { + "name": "UART_ISP", + "value": 2, + "description": "Support ISP command interface on UART port only." + }, + { + "name": "SPI_ISP", + "value": 3, + "description": "Support ISP command interface on SPI port only." + }, + { + "name": "I2C_ISP", + "value": 4, + "description": "Support ISP command interface on I2C port only." + }, + { + "name": "DISABLE_ISP", + "value": 7, + "description": "Disable ISP fall through when proper image is not found on primary boot device." + } + ] + }, + { + "width": 1 + }, + { + "width": 2 + }, + { + "width": 1, + "id": "fuse15-bit-10", + "name": "STOP_ON_FAILURE", + "description": "If set, then enables GPIO Port and PIN information upon failure." + }, + { + "width": 1 + }, + { + "width": 2, + "id": "fuse15-bits-12-13", + "name": "TZM_IMAGE_TYPE", + "description": "TrustZone-M mode", + "values": [ + { + "name": "IGNORED", + "value": 0, + "description": "Ignored" + }, + { + "name": "ENFORCE_PRESET_VALUE", + "value": 1, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_PRESET_VALUE_1", + "value": 2, + "description": "Enforce preset TZM data in image manifest." + }, + { + "name": "ENFORCE_PRESET_VALUE_2", + "value": 3, + "description": "Enforce preset TZM data in image manifest." + } + ] + }, + { + "width": 2 + }, + { + "width": 3, + "id": "fuse15-bits-16-18", + "name": "REDUNDANT_SPI_PORT", + "description": "FlexComm port to use for redundant SPI flash boot.", + "values": [ + { + "name": "FC0", + "value": 0, + "description": "Use FlexCom0 pins P0_0 (SCK), P0_1 (MISO), P0_2 (MOSI), P0_3 (SEL)." + }, + { + "name": "FC1", + "value": 1, + "description": "Use FlexCom1 pins P0_7 (SCK), P0_8 (MISO), P0_9 (MOSI), P0_10 (SEL)." + }, + { + "name": "FC2", + "value": 2, + "description": "Use FlexCom2 pins P0_14 (SCK), P0_15 (MISO), P0_16 (MOSI), P0_17 (SEL)." + }, + { + "name": "FC3", + "value": 3, + "description": "Use FlexCom3 pins P0_21 (SCK), P0_22 (MISO), P0_23 (MOSI), P0_24 (SEL)." + }, + { + "name": "FC4", + "value": 4, + "description": "Use FlexCom4 pins P0_28 (SCK), P0_29 (MISO), P0_30 (MOSI), P0_31 (SEL)." + }, + { + "name": "FC5", + "value": 5, + "description": "Use FlexCom5 pins P1_3 (SCK), P1_4 (MISO), P1_5 (MOSI), P1_6 (SEL)." + }, + { + "name": "FC6", + "value": 6, + "description": "Use FlexCom6 pins P3_25 (SCK), P3_26 (MISO), P3_27 (MOSI), P3_28 (SEL)." + }, + { + "name": "FC7", + "value": 7, + "description": "Use FlexCom7 pins P4_0 (SCK), P4_1 (MISO), P4_2 (MOSI), P4_3 (SEL)." + } + ] + }, + { + "width": 2, + "id": "fuse15-bits-19-20", + "name": "SECURE_BOOT_EN", + "description": "Secure boot enable config", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Allow non-secure images with and without CRC. Used during development." + }, + { + "name": "DISABLED_RFU", + "value": 1, + "description": "RFU" + }, + { + "name": "ENABLED", + "value": 2, + "description": "Secure boot is enabled. Do complete ECDSA checking of signed images. (ECDSA signed)" + }, + { + "name": "ENABLED_1", + "value": 3, + "description": "Secure boot is enabled. Do complete ECDSA checking of signed images. (ECDSA signed)" + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse15-bit-22", + "name": "DICE_INC_OTP", + "description": "Include OTP fuse area in DICE computation", + "values": [ + { + "name": "NOT_INCLUDED", + "value": 0, + "description": "Not included" + }, + { + "name": "INCLUDED", + "value": 1, + "description": "Included" + } + ] + }, + { + "width": 1, + "id": "fuse15-bit-23", + "name": "DICE_SKIP", + "description": "Skip DICE computation", + "values": [ + { + "name": "NO_SKIP", + "value": 0, + "description": "Enable DICE" + }, + { + "name": "SKIP", + "value": 1, + "description": "Disable DICE" + } + ] + }, + { + "width": 3, + "id": "fuse15-bits-24-26", + "name": "BOOT_FAIL_PORT", + "description": "GPIO port number to use for indicating boot failure. Defines GPIO port number." + }, + { + "width": 5, + "id": "fuse15-bits-27-31", + "name": "BOOT_FAIL_PIN", + "description": "Defines GPIO pin number.\nNote: Please note GPIO[22:27] can not be used as BOOT_FAIL pins." + } + ] + }, + { + "id": "fuse16", + "name": "BOOT_CFG1", + "description": "Boot configuration word specifying FlexSPI flash devices settings.", + "index_int": "0x0010", + "shadow_reg_offset_int": "0x0040", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 1, + "id": "fuse16-bit-0", + "name": "FLEXSPI_AUTO_PROBE_EN", + "description": "Flash auto probe feature enable. Auto probing is enabled if the bit is 1.", + "values": [ + { + "name": "FLASH_AUTO_PROBE", + "value": 0, + "description": "The Boot ROM looks for a FCB on the flash. Boot ROM reads a 512 byte FCB into on-chip SRAM and configures the FlexSPI controller accordingly." + }, + { + "name": "FCB_FROM_FLASH", + "value": 1, + "description": "The Boot ROM will perform flash auto probe sequence using parameters from OTP fuse values for FLEXSPI_PROBE_TYPE, FLEXSPI_FLASH_TYPE, FLEXSPI_DUMMY_CYCLES, FLEXSPI_FREQUENCY." + } + ] + }, + { + "width": 3, + "id": "fuse16-bits-1-3", + "name": "FLEXSPI_PROBE_TYPE", + "description": "Flash probe type", + "values": [ + { + "name": "QSPI_NOR", + "value": 0, + "description": "QuadSPI NOR" + } + ] + }, + { + "width": 3, + "id": "fuse16-bits-4-6", + "name": "FLEXSPI_FLASH_TYPE", + "description": "Flash type. This field affects the default configuration of the Boot ROM Flash driver (before any input from flash itself is available).", + "values": [ + { + "name": "FLEXSPI_SDR_3B", + "value": 0, + "description": "Device supports SDR and uses 3 byte addresses for read. In case of autoprobing, when generating an FCB from the SFDP information, commands for SRD operation are generated. In case of configuration from FCB, for reading of flash memory, command 0x03 is used." + }, + { + "name": "FLEXSPI_DDR_4B", + "value": 1, + "description": "Device supports DDR and uses 4 byte addresses for read. In case of autoprobing, when generating an FCB from the SFDP information, the command set for DDR operation is used. In case of configuration from FCB, for reading of flash memory, command 0x13 is used." + } + ] + }, + { + "width": 4, + "id": "fuse16-bits-7-10", + "name": "FLEXSPI_DUMMY_CYCLES", + "description": "Dummy cycles for read command.", + "values": [ + { + "name": "AUTO_PROB", + "value": 0, + "description": "The dummy cycles are probed automatically." + }, + { + "name": "1", + "value": 1, + "description": "The number of dummy cycles is 1." + }, + { + "name": "2", + "value": 2, + "description": "The number of dummy cycles is 2." + }, + { + "name": "3", + "value": 3, + "description": "The number of dummy cycles is 3." + }, + { + "name": "4", + "value": 4, + "description": "The number of dummy cycles is 4." + }, + { + "name": "5", + "value": 5, + "description": "The number of dummy cycles is 5." + }, + { + "name": "6", + "value": 6, + "description": "The number of dummy cycles is 6." + }, + { + "name": "7", + "value": 7, + "description": "The number of dummy cycles is 7." + }, + { + "name": "8", + "value": 8, + "description": "The number of dummy cycles is 8." + }, + { + "name": "9", + "value": 9, + "description": "The number of dummy cycles is 9." + }, + { + "name": "10", + "value": 10, + "description": "The number of dummy cycles is 10." + }, + { + "name": "11", + "value": 11, + "description": "The number of dummy cycles is 11." + }, + { + "name": "12", + "value": 12, + "description": "The number of dummy cycles is 12." + }, + { + "name": "13", + "value": 13, + "description": "The number of dummy cycles is 13." + }, + { + "name": "14", + "value": 14, + "description": "The number of dummy cycles is 14." + }, + { + "name": "15", + "value": 15, + "description": "The number of dummy cycles is 15." + } + ] + }, + { + "width": 3, + "id": "fuse16-bits-11-13", + "name": "FLEXSPI_FREQUENCY", + "description": "Flash SPI clock frequency to use for auto probing.", + "values": [ + { + "name": "FLEXSPI_100MHZ", + "value": 0, + "description": "Use a clock frequency of 100 MHz." + }, + { + "name": "FLEXSPI_120MHZ", + "value": 1, + "description": "Use a clock frequency of 120 MHz." + }, + { + "name": "FLEXSPI_133MHZ", + "value": 2, + "description": "Use a clock frequency of 133 MHz." + }, + { + "name": "FLEXSPI_166MHZ", + "value": 3, + "description": "Use a clock frequency of 166 MHz." + }, + { + "name": "FLEXSPI_200MHZ", + "value": 4, + "description": "Use a clock frequency of 200 MHz." + }, + { + "name": "FLEXSPI_80MHZ", + "value": 5, + "description": "Use a clock frequency of 80 MHz." + }, + { + "name": "FLEXSPI_60MHZ", + "value": 6, + "description": "Use a clock frequency of 60 MHz." + }, + { + "name": "FLEXSPI_50MHZ", + "value": 7, + "description": "Use a clock frequency of 50 MHz." + } + ] + }, + { + "width": 2, + "id": "fuse16-bits-14-15", + "name": "FLEXSPI_RST_SEQ", + "description": "Select the flash reset sequence to use for regular boot.", + "values": [ + { + "name": "NO_RESET_PERFORMED", + "value": 0, + "description": "Don't perform any reset." + }, + { + "name": "JEDEC_RESET", + "value": 1, + "description": "The Boot ROM performs a reset sequence according to the JEDEC specification." + }, + { + "name": "RESET_COMMAND", + "value": 2, + "description": "The Boot ROM sends commands for resetting the flash. The sequence is fixed command byte 0x66 (enable reset) followed by command byte 0x99 (reset device) using SPI (single wire)." + }, + { + "name": "WAKEUP_COMMAND", + "value": 3, + "description": "The Boot ROM sends a wakeup command to the flash. The sequence is fixed command byte 0xAB using SPI (single wire). As the wakeup command is using SPI, it has to be ensured that the flash is in a mode where it can accept SPI commands before the system is put to low-power mode." + } + ] + }, + { + "width": 4, + "id": "fuse16-bits-16-19", + "name": "FLEXSPI_RST_HOLD_TIME", + "description": "Set the time to wait after reset sequence for regular boot.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No additional delay." + }, + { + "name": "100US_DELAY", + "value": 1, + "description": "Wait for 100 us." + }, + { + "name": "500US_DELAY", + "value": 2, + "description": "Wait for 500 us." + }, + { + "name": "1MS_DELAY", + "value": 3, + "description": "Wait for 1 ms." + }, + { + "name": "10MS_DELAY", + "value": 4, + "description": "Wait for 10 ms." + }, + { + "name": "20MS_DELAY", + "value": 5, + "description": "Wait for 20 ms." + }, + { + "name": "40MS_DELAY", + "value": 6, + "description": "Wait for 40 ms." + }, + { + "name": "60MS_DELAY", + "value": 7, + "description": "Wait for 60 ms." + }, + { + "name": "80MS_DELAY", + "value": 8, + "description": "Wait for 80 ms." + }, + { + "name": "100MS_DELAY", + "value": 9, + "description": "Wait for 100 ms." + }, + { + "name": "120MS_DELAY", + "value": 10, + "description": "Wait for 120 ms." + }, + { + "name": "140MS_DELAY", + "value": 11, + "description": "Wait for 140 ms." + }, + { + "name": "160MS_DELAY", + "value": 12, + "description": "Wait for 160 ms." + }, + { + "name": "180MS_DELAY", + "value": 13, + "description": "Wait for 180 ms." + }, + { + "name": "200MS_DELAY", + "value": 14, + "description": "Wait for 200 ms." + }, + { + "name": "220MS_DELAY", + "value": 15, + "description": "Wait for 220 ms." + } + ] + }, + { + "width": 2, + "id": "fuse16-bits-20-21", + "name": "FLEXSPI_WUP_SEQ", + "description": "Select the flash reset sequence to use for boot from low power mode.", + "values": [ + { + "name": "NO_RESET_PERFORMED", + "value": 0, + "description": "Don't perform any reset." + }, + { + "name": "JEDEC_RESET", + "value": 1, + "description": "The Boot ROM performs a reset sequence according to the JEDEC specification." + }, + { + "name": "RESET_COMMAND", + "value": 2, + "description": "The Boot ROM sends commands for resetting the flash. The sequence is fixed command byte 0x66 (enable reset) followed by command byte 0x99 (reset device) using SPI (single wire)." + }, + { + "name": "WAKEUP_COMMAND", + "value": 3, + "description": "The Boot ROM sends a wakeup command to the flash. The sequence is fixed command byte 0xAB using SPI (single wire). As the wakeup command is using SPI, it has to be ensured that the flash is in a mode where it can accept SPI commands before the system is put to low-power mode." + } + ] + }, + { + "width": 4, + "id": "fuse16-bits-22-25", + "name": "FLEXSPI_WUP_HOLD_TIME", + "description": "Set the time to wait after reset sequence for boot from low power mode.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No additional delay." + }, + { + "name": "100US_DELAY", + "value": 1, + "description": "Wait for 100 us." + }, + { + "name": "500US_DELAY", + "value": 2, + "description": "Wait for 500 us." + }, + { + "name": "1MS_DELAY", + "value": 3, + "description": "Wait for 1 ms." + }, + { + "name": "10MS_DELAY", + "value": 4, + "description": "Wait for 10 ms." + }, + { + "name": "20MS_DELAY", + "value": 5, + "description": "Wait for 20 ms." + }, + { + "name": "40MS_DELAY", + "value": 6, + "description": "Wait for 40 ms." + }, + { + "name": "60MS_DELAY", + "value": 7, + "description": "Wait for 60 ms." + }, + { + "name": "80MS_DELAY", + "value": 8, + "description": "Wait for 80 ms." + }, + { + "name": "100MS_DELAY", + "value": 9, + "description": "Wait for 100 ms." + }, + { + "name": "120MS_DELAY", + "value": 10, + "description": "Wait for 120 ms." + }, + { + "name": "140MS_DELAY", + "value": 11, + "description": "Wait for 140 ms." + }, + { + "name": "160MS_DELAY", + "value": 12, + "description": "Wait for 160 ms." + }, + { + "name": "180MS_DELAY", + "value": 13, + "description": "Wait for 180 ms." + }, + { + "name": "200MS_DELAY", + "value": 14, + "description": "Wait for 200 ms." + }, + { + "name": "220MS_DELAY", + "value": 15, + "description": "Wait for 220 ms." + } + ] + }, + { + "width": 2, + "id": "fuse16-bits-26-27", + "name": "FLEXSPI_HOLD_TIME", + "description": "Wait time before access to Serial Flash.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No additional delay" + }, + { + "name": "500US_DELAY", + "value": 1, + "description": "Wait for 500 us." + }, + { + "name": "3MS_DELAY", + "value": 2, + "description": "Wait for 3 ms." + }, + { + "name": "10MS_DELAY", + "value": 3, + "description": "Wait for 10 ms." + } + ] + }, + { + "width": 4, + "id": "fuse16-bits-28-31", + "name": "FLEXSPI_PWR_HOLD_TIME", + "description": "Delay after POR before accessing Quad/Octal-SPI flash devices in addition to delay defined by QSPI_HOLD TIME field.", + "values": [ + { + "name": "NO_DELAY", + "value": 0, + "description": "No additional delay." + }, + { + "name": "100US_DELAY", + "value": 1, + "description": "Wait for 100 us." + }, + { + "name": "500US_DELAY", + "value": 2, + "description": "Wait for 500 us." + }, + { + "name": "1MS_DELAY", + "value": 3, + "description": "Wait for 1 ms." + }, + { + "name": "10MS_DELAY", + "value": 4, + "description": "Wait for 10 ms." + }, + { + "name": "20MS_DELAY", + "value": 5, + "description": "Wait for 20 ms." + }, + { + "name": "40MS_DELAY", + "value": 6, + "description": "Wait for 40 ms." + }, + { + "name": "60MS_DELAY", + "value": 7, + "description": "Wait for 60 ms." + }, + { + "name": "80MS_DELAY", + "value": 8, + "description": "Wait for 80 ms." + }, + { + "name": "100MS_DELAY", + "value": 9, + "description": "Wait for 100 ms." + }, + { + "name": "120MS_DELAY", + "value": 10, + "description": "Wait for 120 ms." + }, + { + "name": "140MS_DELAY", + "value": 11, + "description": "Wait for 140 ms." + }, + { + "name": "160MS_DELAY", + "value": 12, + "description": "Wait for 160 ms." + }, + { + "name": "180MS_DELAY", + "value": 13, + "description": "Wait for 180 ms." + }, + { + "name": "200MS_DELAY", + "value": 14, + "description": "Wait for 200 ms." + }, + { + "name": "220MS_DELAY", + "value": 15, + "description": "Wait for 220 ms." + } + ] + } + ] + }, + { + "id": "fuse17", + "name": "BOOT_CFG2", + "description": "Boot configuration word specifying settings for FlexSPI image.", + "index_int": "0x0011", + "shadow_reg_offset_int": "0x0044", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse17-bits-0-3", + "name": "FLEXSPI_IMAGE_SIZE", + "description": "The size of the flash memory to use for a boot image.", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "The size of the boot image is considered to be equal to the offset of the second image." + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "Size of remapped area is 768KByte." + } + ] + }, + { + "width": 7, + "id": "fuse17-bits-4-10", + "name": "FLEXSPI_DELAY_CELL_NUM", + "description": "Delay cell numbers for flash read sampling via DQS (either internal loopback or external DQS).\n\ndelay = 1600ps, if value = 0\ndelay = value * 100ps" + }, + { + "width": 10, + "id": "fuse17-bits-11-20", + "name": "FLEXSPI_IMAGE_OFFSET", + "description": "The offset in flash memory where the second boot image starts. The offset to the second image is X * 256 KB." + }, + { + "width": 11 + } + ] + }, + { + "id": "fuse18", + "name": "BOOT_CFG3", + "description": "Boot configuration fuse word 3.", + "index_int": "0x0012", + "shadow_reg_offset_int": "0x0048", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 3, + "id": "fuse18-bits-0-2", + "name": "ROTK0_USAGE", + "description": "RoT key 0 usage properties. ", + "values": [ + { + "name": "All_usage_key", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DebugCA", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "ImageCA_FwCA", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DebugCA_ImageCA_FwCA", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "ImageKey_FwKey", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "ImageKey", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FwKey", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "Unused", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse18-bits-3-5", + "name": "ROTK1_USAGE", + "description": "RoT key 1 usage properties.", + "values": [ + { + "name": "All_usage_key", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DebugCA", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "ImageCA_FwCA", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DebugCA_ImageCA_FwCA", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "ImageKey_FwKey", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "ImageKey", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FwKey", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "Unused", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse18-bits-6-8", + "name": "ROTK2_USAGE", + "description": "RoT key 2 usage properties.", + "values": [ + { + "name": "All_usage_key", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DebugCA", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "ImageCA_FwCA", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DebugCA_ImageCA_FwCA", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "ImageKey_FwKey", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "ImageKey", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FwKey", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "Unused", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 3, + "id": "fuse18-bits-9-11", + "name": "ROTK3_USAGE", + "description": "RoT key 3 usage properties.", + "values": [ + { + "name": "All_usage_key", + "value": 0, + "description": "Usable as debug CA, image CA, FW CA, image and FW key." + }, + { + "name": "DebugCA", + "value": 1, + "description": "Usable as debug CA only." + }, + { + "name": "ImageCA_FwCA", + "value": 2, + "description": "Usable as image (boot and FW) CA only." + }, + { + "name": "DebugCA_ImageCA_FwCA", + "value": 3, + "description": "Usable as debug, boot and FW image CA." + }, + { + "name": "ImageKey_FwKey", + "value": 4, + "description": "Usable as image key and FW update key only." + }, + { + "name": "ImageKey", + "value": 5, + "description": "Usable as boot image key only." + }, + { + "name": "FwKey", + "value": 6, + "description": "Usable as FW update image key only." + }, + { + "name": "Unused", + "value": 7, + "description": "Key slot is not used." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-12-13", + "name": "ENF_CNSA", + "description": "Enforce CNSA (Commercial National Security Algorithm) suite keys.", + "values": [ + { + "name": "P-256_KEY", + "value": 0, + "description": "ECC P-256 keys." + }, + { + "name": "P-384_KEY", + "value": 1, + "description": "ECC P-384 keys." + }, + { + "name": "P-384_KEY_1", + "value": 2, + "description": "ECC P-384 keys." + }, + { + "name": "P-384_KEY_2", + "value": 3, + "description": "ECC P-384 keys." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-14-15", + "name": "ENABLE_CRC_CHECK", + "description": "Enable CRC checks over OTP words.\n\nCRC1 = CRC over OTP fuses from 15 - 21\nCRC2 = CRC over OTP fuses from 00 - 02\nCRC6 = CRC over OTP fuses from 92 - 115", + "values": [ + { + "name": "DISABLE", + "value": 0, + "description": "Disable CRC check over OTPs." + }, + { + "name": "ENABLE_NXP_OTP", + "value": 1, + "description": "Perform CRC check over NXP OTPs." + }, + { + "name": "ENABLE_ALL_OTP", + "value": 2, + "description": "Perform CRC check over NXP and OEM OTPs." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-16-17", + "name": "FIPS_KDF_STEN", + "description": "Enable self-test for CKDF block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-18-19", + "name": "FIPS_CMAC_STEN", + "description": "Enable self-test for CMAC block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-20-21", + "name": "FIPS_DRBG_STEN", + "description": "Enable self-test for DRBG block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-22-23", + "name": "FIPS_ECDSA_STEN", + "description": "Enable self-test for ECDSA block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-24-25", + "name": "FIPS_AES_STEN", + "description": "Enable self-test for AES block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-26-27", + "name": "FIPS_SHA_STEN", + "description": "Enable self-test for SHA2 block on power-up. Needed for FIPS certification. If this field is non-zero run self-test and log result in BOOT_STATE register.", + "values": [ + { + "name": "SKIP_SELF_TEST_RUN", + "value": 0, + "description": "Self-tests run is skipped and results are not included." + }, + { + "name": "INCLUDE_SELF_TEST_RESULTS", + "value": 1, + "description": "On failure continue to boot." + }, + { + "name": "FALL_THROUGH_ISP_ON_FAIL", + "value": 2, + "description": "On failure fall through ISP." + }, + { + "name": "LOCK_DEVICE_ON_FAIL", + "value": 3, + "description": "Stop on execution on fail." + } + ] + }, + { + "width": 2, + "id": "fuse18-bits-28-29", + "name": "SKIP_PM_SIGN_VERIFICATION", + "description": "On boot-up from PM3/PM4, do not run through ECDSA signature verification of the image.", + "values": [ + { + "name": "NO_SKIP", + "value": 0, + "description": "Image verification is not skipped upon wake up from PM3 and PM4." + }, + { + "name": "NO_SKIP_1", + "value": 1, + "description": "Image verification is not skipped upon wake up from PM3 and PM4." + }, + { + "name": "NO_SKIP_2", + "value": 2, + "description": "Image verification is not skipped upon wake up from PM3 and PM4." + }, + { + "name": "SKIP", + "value": 3, + "description": "Image verification is skipped upon wake up from PM3 and PM4." + } + ] + }, + { + "width": 2 + } + ] + }, + { + "id": "fuse19", + "name": "BOOT_CFG4", + "description": "Boot configuration word specifying settings for recovery image.", + "index_int": "0x0013", + "shadow_reg_offset_int": "0x004C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 4, + "id": "fuse19-bits-0-3", + "name": "RECOVERY_IMAGE_SIZE", + "description": "Recovery image size", + "values": [ + { + "name": "SIZE_OFFSET", + "value": 0, + "description": "The size of the boot image is considered to be equal to the offset of the second image." + }, + { + "name": "SIZE_1MB", + "value": 1, + "description": "Size of remapped area is 1MByte." + }, + { + "name": "SIZE_2MB", + "value": 2, + "description": "Size of remapped area is 2MByte." + }, + { + "name": "SIZE_3MB", + "value": 3, + "description": "Size of remapped area is 3MByte." + }, + { + "name": "SIZE_4MB", + "value": 4, + "description": "Size of remapped area is 4MByte." + }, + { + "name": "SIZE_5MB", + "value": 5, + "description": "Size of remapped area is 5MByte." + }, + { + "name": "SIZE_6MB", + "value": 6, + "description": "Size of remapped area is 6MByte." + }, + { + "name": "SIZE_7MB", + "value": 7, + "description": "Size of remapped area is 7MByte." + }, + { + "name": "SIZE_8MB", + "value": 8, + "description": "Size of remapped area is 8MByte." + }, + { + "name": "SIZE_9MB", + "value": 9, + "description": "Size of remapped area is 9MByte." + }, + { + "name": "SIZE_10MB", + "value": 10, + "description": "Size of remapped area is 10MByte." + }, + { + "name": "SIZE_11MB", + "value": 11, + "description": "Size of remapped area is 11MByte." + }, + { + "name": "SIZE_12MB", + "value": 12, + "description": "Size of remapped area is 12MByte." + }, + { + "name": "SIZE_256KB", + "value": 13, + "description": "Size of remapped area is 256KByte." + }, + { + "name": "SIZE_512KB", + "value": 14, + "description": "Size of remapped area is 512KByte." + }, + { + "name": "SIZE_768KB", + "value": 15, + "description": "Size of remapped area is 768KByte." + } + ] + }, + { + "width": 10, + "id": "fuse19-bits-4-13", + "name": "RECOVERY_IMAGE_OFFSET", + "description": "The offset in flash memory where the second boot image starts for recovery image. The offset to the second image is X * 256 kB." + }, + { + "width": 1, + "id": "fuse19-bit-14", + "name": "RECOVERY_BOOT_EN", + "description": "Configures recovery boot flag", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Boot from recovery image is disabled." + }, + { + "name": "ENABLED", + "value": 1, + "description": "Boot from recovery image is enabled." + } + ] + }, + { + "width": 17 + } + ] + }, + { + "id": "fuse20", + "name": "BOOT_CFG5", + "description": "The USB VID and PID can be customized by writing the new values to the USB_VID and USB_PID fields in this fuse word field.", + "index_int": "0x0014", + "shadow_reg_offset_int": "0x0050", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse20-bits-0-15", + "name": "USB_VID", + "description": "Value of USB VID" + }, + { + "width": 16, + "id": "fuse20-bits-16-31", + "name": "USB_PID", + "description": "Value of USB PID" + } + ] + }, + { + "id": "fuse21", + "name": "BOOT_CFG6", + "description": "The SDIO VID and PID can be customized by writing the new values to the SDIO_VID and SDIO_PID fields in this fuse word field.", + "index_int": "0x0015", + "shadow_reg_offset_int": "0x0054", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse21-bits-0-15", + "name": "SDIO_VID", + "description": "Value of SDIO VID" + }, + { + "width": 16, + "id": "fuse21-bits-16-31", + "name": "SDIO_PID", + "description": "Value of SDIO PID" + } + ] + }, + { + "id": "fuse22", + "name": "SEC_BOOT_CFG0", + "description": "Root key revocation fuse word.", + "index_int": "0x0016", + "shadow_reg_offset_int": "0x0058", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 1, + "id": "fuse22-bit-0", + "name": "REVOKE_ROOTKEY0", + "description": "RoT Key 0 enable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "RoT Key is enabled." + }, + { + "name": "REVOKED", + "value": 1, + "description": "RoT Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-1", + "name": "REVOKE_ROOTKEY1", + "description": "RoT Key 1 enable", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "RoT Key is enabled." + }, + { + "name": "REVOKED", + "value": 1, + "description": "RoT Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-2", + "name": "REVOKE_ROOTKEY2", + "description": "RoT Key 2 enable ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "RoT Key is enabled." + }, + { + "name": "REVOKED", + "value": 1, + "description": "RoT Key is revoked." + } + ] + }, + { + "width": 1, + "id": "fuse22-bit-3", + "name": "REVOKE_ROOTKEY3", + "description": "RoT Key 3 enable ", + "values": [ + { + "name": "ENABLED", + "value": 0, + "description": "RoT Key is enabled." + }, + { + "name": "REVOKED", + "value": 1, + "description": "RoT Key is revoked." + } + ] + }, + { + "width": 1 + }, + { + "width": 1, + "id": "fuse22-bit-5", + "name": "NXP_PROV_FW_EXEC_DIS", + "description": "Flag to disable execution of NXP signed provisioning Firmwares", + "values": [ + { + "name": "EXEC_NOT_DISABLED", + "value": 0, + "description": "Execution of NXP provisioning fw is not disabled." + }, + { + "name": "EXEC_DISABLED", + "value": 1, + "description": "Execution of NXP provisioning fw is disabled." + } + ] + }, + { + "width": 10 + } + ] + }, + { + "id": "fuse23", + "name": "SEC_BOOT_CFG1", + "description": "DAP Vendor Usage configurations fuse word.", + "index_int": "0x0017", + "shadow_reg_offset_int": "0x005C", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse23-bits-0-15", + "name": "DAP_VENDOR_USAGE", + "description": "Lower 16-bits of Vendor Usage field in Debug Credentials defined in NXP's Debug Authentication Protocol specifications Version 1.0. " + } + ] + }, + { + "id": "fuse24", + "name": "SEC_BOOT_CFG2", + "description": "Lower 16-bits of revoke Image signing key configuration fuse word.", + "index_int": "0x0018", + "shadow_reg_offset_int": "0x0060", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse24-bits-0-15", + "name": "REVOKE_IMG_KEY", + "description": "Image key revocation bits." + } + ] + }, + { + "id": "fuse25", + "name": "SEC_BOOT_CFG3", + "description": "Upper 16-bits of revoke Image signing key configuration fuse word.", + "index_int": "0x0019", + "shadow_reg_offset_int": "0x0064", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse25-bits-0-15", + "name": "REVOKE_IMG_KEY", + "description": "Image key revocation bits." + } + ] + }, + { + "id": "fuse26", + "name": "SEC_BOOT_CFG4", + "description": "User defined", + "index_int": "0x001A", + "shadow_reg_offset_int": "0x0068", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse26-bits-0-15", + "name": "User", + "description": "User defined" + } + ] + }, + { + "id": "fuse27", + "name": "SEC_BOOT_CFG5", + "description": "User defined", + "index_int": "0x001B", + "shadow_reg_offset_int": "0x006C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse27-bits-0-31", + "name": "SEC_BOOT_CFG5", + "description": "User defined" + } + ] + }, + { + "id": "fuse28", + "name": "SEC_BOOT_CFG6", + "description": "SDIO Block size settings fuse word.", + "index_int": "0x001C", + "shadow_reg_offset_int": "0x0070", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 16, + "id": "fuse28-bits-0-15", + "name": "SDIO_F0_BLOCKSIZE", + "description": "SDIO Block F0 size\n`16b00` = SDIO_F0_BLOCKSIZE will be fixed `0x1`\n`SDIO_F0_BLOCKSIZE` = Fuse value" + }, + { + "width": 16, + "id": "fuse28-bits-16-31", + "name": "SDIO_FN_BLOCKSIZE", + "description": "SDIO Block FN size\n`16b00` = SDIO_FN_BLOCKSIZE will be fixed `0x200`\n`SDIO_FN_BLOCKSIZE` = Fuse value" + } + ] + }, + { + "id": "fuse29", + "name": "SEC_BOOT_CFG7", + "description": "SDIO configuration settings fuse word.", + "index_int": "0x001D", + "shadow_reg_offset_int": "0x0074", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse29-bits-0-7", + "name": "SDIO_REV", + "description": "Configure SDIO version revision.\n`8b00` = SDIO_REV will be fixed `0x30`\n`SDIO_REV ` = Fuse value" + }, + { + "width": 8, + "id": "fuse29-bits-8-15", + "name": "SDIO_SPEED", + "description": "Configure SDIO Speed.\n`8b00` = SDIO_SPEED will be fixed `0xB`\n`SDIO_SPEED` = Fuse value" + }, + { + "width": 16, + "id": "fuse29-bits-16-31", + "name": "SDIO_TIMEOUT", + "description": "Configure SDIO Timeout.\n`16b00` = SDIO_TIMEOUT will be fixed `0x14`\n`SDIO_TIMEOUT` = Fuse value" + } + ] + }, + { + "id": "fuse30", + "name": "SEC_BOOT_CFG8", + "description": "User defined", + "index_int": "0x001E", + "shadow_reg_offset_int": "0x0078", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0008", + "read_lock_int": "0x0020", + "operation_lock_int": "0x0010" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse30-bits-0-31", + "name": "SEC_BOOT_CFG8", + "description": "User defined" + } + ] + }, + { + "id": "fuse31", + "name": "DCFG_CC_SOCU_NS", + "description": "The DCFG_CC_SOCU_NS configuration fields can be used to increase the restriction level specified in DCFG_CC_SOCU. With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only.\n - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug.\n - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used.\n - ROM will use this word to further restrict the debug access.\n - Layout of this word is same as DCFG_CC_SOCU.\n - Combinations of PINNED_xxxEN and DFLT_xxxEN bits and resulting access restriction levels are:\n \n1. PINNED_xxxEN=1,DFLT_xxxEN=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product.\n2. PINNED_xxxEN=0,DFLT_xxxEN=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate.\n3. PINNED_xxxEN=0,DFLT_xxxEN=1: Illegal setting. Part will lock-up if this setting is selected.\n4. PINNED_xxxEN=1,DFLT_xxxEN=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x001F", + "shadow_reg_offset_int": "0x007C", + "default_value_int": "0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse0", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse31-bits-0-7", + "name": "CRC8_NS", + "description": "CRC-8/ITU of upper 3 bytes (bits 8 to 31). Since these fields are security critical, they are constructed with built-in integrity protection to protect from side channel glitch attacks.\nThe lower byte (0 to 7 bits) of these OTP words should be written with CRC-8/ITU of upper 3 bytes (bits 8 to 31). \nThis construction makes the probability of a successful glitch attack to flip the exact control bits extremely difficult.\n The CRC8 calculation should be based on x8 + x2 + x + 1 polynomial. Polynomial=0x07, initial value= 0x00, XorOut=0x55", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse31-bit-8", + "name": "DFLT_NIDEN_NS", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-9", + "name": "DFLT_DBGEN_NS", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-10", + "name": "DFLT_SPNIDEN_NS", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-11", + "name": "DFLT_SPIDEN_NS", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-12", + "name": "DFLT_TAPEN_NS", + "description": "Controls TAP (Test Access Point) controller used for structural integrity testing of silicon by NXP as part of Return Material Analysis (RMA)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-13", + "name": "DFLT_CPU1NIDEN_NS", + "description": "Controls non-Invasive debugging of CPU1.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-14", + "name": "DFLT_CPU1DBGEN_NS", + "description": "Controls invasive debugging of CPU1.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-15", + "name": "DFLT_CPU2NIDEN_NS", + "description": "Controls non-Invasive debugging of CPU2.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-16", + "name": "DFLT_CPU2DBGEN_NS", + "description": "Controls invasive debugging of CPU2.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-17", + "name": "DFLT_ISPCMDEN_NS", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-18", + "name": "DFLT_FACMDEN_NS", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-19", + "name": "PINNED_NIDEN_NS", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-20", + "name": "PINNED_DBGEN_NS", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-21", + "name": "PINNED_SPNIDEN_NS", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-22", + "name": "PINNED_SPIDEN_NS", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-23", + "name": "PINNED_TAPEN_NS", + "description": "Controls TAP (Test Access Point) controller used for structural integrity testing of silicon by NXP as part of Return Material Analysis (RMA)", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-24", + "name": "PINNED_CPU1NIDEN_NS", + "description": "Controls non-Invasive debugging of CPU1", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-25", + "name": "PINNED_CPU1DBGEN_NS", + "description": "Controls invasive debugging of CPU1.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-26", + "name": "PINNED_CPU2NIDEN_NS", + "description": "Controls non-Invasive debugging of CPU2.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-27", + "name": "PINNED_CPU2DBGEN_NS", + "description": "Controls invasive debugging of CPU2.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-28", + "name": "PINNED_ISPCMDEN_NS", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-29", + "name": "PINNED_FACMDEN_NS", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse31-bit-30", + "name": "FORCE_UUID_MATCH_NS", + "description": "When set, debug authentication protocol only accepts Debug Credential certificates (DC) with matching UUID.", + "values": [ + { + "name": "NO_FORCE_UUID_MATCH", + "value": 0, + "description": "Accepts Debug Credential certificates (DC) with any UUID." + }, + { + "name": "FORCE_UUID_MATCH", + "value": 1, + "description": "Accepts Debug Credential certificates (DC) with matching UUID." + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse33", + "name": "DCFG_CC_SOCU", + "description": "The DCFG_CC_SOCU configuration field specifies the debug access restrictions per debug domain. The DCFG_CC_SOCU_NS fields can be used to increase the restriction level specified in DCFG_CC_SOCU but cannot be used to reduce the restriction level.\n - Combinations of PINNED_xxxEN and DFLT_xxxEN bits and resulting access restriction levels are:\n\n 1. PINNED_xxxEN=1,DFLT_xxxEN=1: Restriction level 0. Access to the sub-domain is always enabled. This setting is provided for module use case scenario where DCFG_CC_SOCU_NS would be used to define further access restrictions before final deployment of the product. \n 2. PINNED_xxxEN=0,DFLT_xxxEN=0: Restriction level 1. Access to the sub-domain is disabled at startup. But the access can be enabled through the debug authentication process by providing an appropriate Debug Credential (DC) certificate. \n 3. PINNED_xxxEN=0,DFLT_xxxEN=1: Illegal setting. Part will lock-up if this setting is selected. \n 4. PINNED_xxxEN=1,DFLT_xxxEN=0: Restriction level 2. Access to the sub-domain is permanently disabled and cannot be reversed. This setting offers the highest level of restriction.", + "index_int": "0x0021", + "shadow_reg_offset_int": "0x0084", + "default_value_int": "0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + }, + "bitfields": [ + { + "width": 8, + "id": "fuse33-bits-0-7", + "name": "CRC8", + "description": "CRC-8/ITU of upper 3 bytes (bits 8 to 31). Since these fields are security critical, they are constructed with built-in integrity protection to protect from side channel glitch attacks.\nThe lower byte (0 to 7 bits) of these OTP words should be written with CRC-8/ITU of upper 3 bytes (bits 8 to 31). \nThis construction makes the probability of a successful glitch attack to flip the exact control bits extremely difficult.\n The CRC8 calculation should be based on x8 + x2 + x + 1 polynomial. Polynomial=0x07, initial value= 0x00, XorOut=0x55", + "calculated": "CRC-8/ITU" + }, + { + "width": 1, + "id": "fuse33-bit-8", + "name": "DFLT_NIDEN", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-9", + "name": "DFLT_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-10", + "name": "DFLT_SPNIDEN", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-11", + "name": "DFLT_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-12", + "name": "DFLT_TAPEN", + "description": "Controls TAP (Test Access Point) controller used for structural integrity testing of silicon by NXP as part of Return Material Analysis (RMA)", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-13", + "name": "DFLT_CPU1NIDEN", + "description": "Controls non-Invasive debugging of CPU1.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-14", + "name": "DFLT_CPU1DBGEN", + "description": "Controls invasive debugging of CPU1.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-15", + "name": "DFLT_CPU2NIDEN", + "description": "Controls non-Invasive debugging of CPU2.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-16", + "name": "DFLT_CPU2DBGEN", + "description": "Controls invasive debugging of CPU2.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-17", + "name": "DFLT_ISPCMDEN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-18", + "name": "DFLT_FACMDEN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication", + "values": [ + { + "name": "DISABLED", + "value": 0, + "description": "Disabled" + }, + { + "name": "ENABLED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-19", + "name": "PINNED_NIDEN", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-20", + "name": "PINNED_DBGEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined non-secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-21", + "name": "PINNED_SPNIDEN", + "description": "Controls non-Invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-22", + "name": "PINNED_SPIDEN", + "description": "Controls invasive debugging of TrustZone for Arm8-M defined secure domain of CPU0", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-23", + "name": "PINNED_TAPEN", + "description": "Controls TAP (Test Access Point) controller used for structural integrity testing of silicon by NXP as part of Return Material Analysis (RMA)", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-24", + "name": "PINNED_CPU1NIDEN", + "description": "Controls non-Invasive debugging of CPU1", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-25", + "name": "PINNED_CPU1DBGEN", + "description": "Controls invasive debugging of CPU1.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-26", + "name": "PINNED_CPU2NIDEN", + "description": "Controls non-Invasive debugging of CPU2.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-27", + "name": "PINNED_CPU2DBGEN", + "description": "Controls invasive debugging of CPU2.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-28", + "name": "PINNED_ISPCMDEN", + "description": "Controls whether ISP boot flow DM-AP command (command code: 0x05) can be issued after authentication.", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-29", + "name": "PINNED_FACMDEN", + "description": "Controls whether DM-AP Set FA Mode command (command code: 0x06) can be issued after authentication", + "values": [ + { + "name": "DAR_CC", + "value": 0, + "description": "Debug Authentication Response determines the state." + }, + { + "name": "FIXED", + "value": 1, + "description": "Enabled" + } + ] + }, + { + "width": 1, + "id": "fuse33-bit-30", + "name": "FORCE_UUID_MATCH", + "description": "When set, debug authentication protocol only accepts Debug Credential certificates (DC) with matching UUID.", + "values": [ + { + "name": "NO_FORCE_UUID_MATCH", + "value": 0, + "description": "Accepts Debug Credential certificates (DC) with any UUID." + }, + { + "name": "FORCE_UUID_MATCH", + "value": 1, + "description": "Accepts Debug Credential certificates (DC) with matching UUID." + } + ] + }, + { + "width": 1 + } + ] + }, + { + "id": "fuse34", + "name": "DCFG_CC_SOCU_AP", + "description": "Anti-pole (inverse) value of Debug Configuration word (DCFG_CC_SOCU). DCFG_CC_SOCU_AP should be programmed with the exact anti-pole (inverse value) value of DCFG_CC_SOCU. \nAny mismatch between DCFG_CC_SOCU and DCFG_CC_SOCU_AP is deemed as an attack and device is locked permanently.", + "index_int": "0x0022", + "shadow_reg_offset_int": "0x0088", + "individual_write_lock": "implicit", + "calculated": { + "method": "inverse", + "src_register_id": "fuse33" + }, + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0040", + "read_lock_int": "0x0100", + "operation_lock_int": "0x0080" + } + } + ] + }, + { + "group": { + "name": "Life Cycle Management", + "description": "Life cycle management" + }, + "registers": [ + { + "id": "fuse45", + "name": "LIFE_CYCLE_STATE", + "description": "Life cycle state of rw61x platform.", + "index_int": "0x002D", + "shadow_reg_offset_int": "0x00B4", + "default_value_int": "0x0303", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "reg_width": 16, + "bitfields": [ + { + "width": 8, + "id": "fuse45-bits-0-7", + "name": "LCS", + "description": "Possible values of rw61x lifecycle states", + "values": [ + { + "name": "Blank", + "value": 0, + "description": "Initial state in NXP factory." + }, + { + "name": "Provisioned", + "value": 1, + "description": "NXP provisioned state." + }, + { + "name": "Develop", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "Develop2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "In-Field", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "Field Return OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "Failure Analysis (FA)", + "value": 63, + "description": "NXP field return state (CQC)." + }, + { + "name": "In-Field Locked", + "value": 207, + "description": "Alternative in-field application state that disables debug capability and prevents use of field return/failure analysis states. The rest of the behavior of the device is same as the In-field state." + }, + { + "name": "Shredded", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + }, + { + "width": 8, + "id": "fuse45-bits-8-15", + "name": "LCS_REDUNDANT", + "description": "Repeat values of lifecycle state due to a security", + "values": [ + { + "name": "Blank", + "value": 0, + "description": "Initial state in NXP factory." + }, + { + "name": "Provisioned", + "value": 1, + "description": "NXP provisioned state." + }, + { + "name": "Develop", + "value": 3, + "description": "Initial customer development state after leaving NXP manufacturing." + }, + { + "name": "Develop2", + "value": 7, + "description": "Optional customer development state. Used for development of NS world code." + }, + { + "name": "In-Field", + "value": 15, + "description": "In-field application state for end-customer use." + }, + { + "name": "Field Return OEM", + "value": 31, + "description": "Field return state." + }, + { + "name": "Failure Analysis (FA)", + "value": 63, + "description": "NXP field return state (CQC)." + }, + { + "name": "In-Field Locked", + "value": 207, + "description": "Alternative in-field application state that disables debug capability and prevents use of field return/failure analysis states. The rest of the behavior of the device is same as the In-field state." + }, + { + "name": "Shredded", + "value": 255, + "description": "Bricked state to prevent device use." + } + ] + } + ] + } + ] + }, + { + "group": { + "name": "UUID", + "description": "UUID" + }, + "registers": [ + { + "id": "fuse46", + "name": "UUID[31:0]", + "description": "Universally Unique Identifier 0", + "index_int": "0x002E", + "individual_write_lock": "implicit" + }, + { + "id": "fuse47", + "name": "UUID[63:32]", + "description": "Universally Unique Identifier 1", + "index_int": "0x002F", + "individual_write_lock": "implicit" + }, + { + "id": "fuse48", + "name": "UUID[95:64]", + "description": "Universally Unique Identifier 2", + "index_int": "0x0030", + "individual_write_lock": "implicit" + }, + { + "id": "fuse49", + "name": "UUID[127:96]", + "description": "Universally Unique Identifier 3", + "index_int": "0x0031", + "individual_write_lock": "implicit" + } + ] + }, + { + "group": { + "name": "Firmware Decryption Key", + "description": "Firmware decryption key" + }, + "registers": [ + { + "id": "fuse92", + "name": "CUST_SK_MK[31:0]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x005C", + "shadow_reg_offset_int": "0x0170", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse93", + "name": "CUST_SK_MK[63:32]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x005D", + "shadow_reg_offset_int": "0x0174", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse94", + "name": "CUST_SK_MK[95:64]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x005E", + "shadow_reg_offset_int": "0x0178", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse95", + "name": "CUST_SK_MK[127:96]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x005F", + "shadow_reg_offset_int": "0x017C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse96", + "name": "CUST_SK_MK[159:128]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0060", + "shadow_reg_offset_int": "0x0180", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse97", + "name": "CUST_SK_MK[191:160]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0061", + "shadow_reg_offset_int": "0x0184", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse98", + "name": "CUST_SK_MK[223:192]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0062", + "shadow_reg_offset_int": "0x0188", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse99", + "name": "CUST_SK_MK[255:224]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0063", + "shadow_reg_offset_int": "0x018C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse100", + "name": "CUST_SK_MK[287:256]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0064", + "shadow_reg_offset_int": "0x0190", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse101", + "name": "CUST_SK_MK[319:288]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0065", + "shadow_reg_offset_int": "0x0194", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse102", + "name": "CUST_SK_MK[351:320]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0066", + "shadow_reg_offset_int": "0x0198", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse103", + "name": "CUST_SK_MK[383:352]", + "description": "FW encryption and decryption key wrapped by RFC3394, used for FW decryption", + "index_int": "0x0067", + "shadow_reg_offset_int": "0x019C", + "access": "RO", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + } + ] + }, + { + "group": { + "name": "ROTKH", + "description": "ROTKH" + }, + "registers": [ + { + "id": "fuse104", + "name": "RKTH[383:352]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0068", + "shadow_reg_offset_int": "0x01A0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse105", + "name": "RKTH[351:320]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0069", + "shadow_reg_offset_int": "0x01A4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse106", + "name": "RKTH[319:288]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006A", + "shadow_reg_offset_int": "0x01A8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse107", + "name": "RKTH[287:256]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006B", + "shadow_reg_offset_int": "0x01AC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse108", + "name": "RKTH[255:224]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006C", + "shadow_reg_offset_int": "0x01B0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse109", + "name": "RKTH[223:192]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006D", + "shadow_reg_offset_int": "0x01B4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse110", + "name": "RKTH[191:160]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006E", + "shadow_reg_offset_int": "0x01B8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse111", + "name": "RKTH[159:128]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x006F", + "shadow_reg_offset_int": "0x01BC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse112", + "name": "RKTH[127:96]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0070", + "shadow_reg_offset_int": "0x01C0", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse113", + "name": "RKTH[95:64]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0071", + "shadow_reg_offset_int": "0x01C4", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse114", + "name": "RKTH[63:32]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0072", + "shadow_reg_offset_int": "0x01C8", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + }, + { + "id": "fuse115", + "name": "RKTH[31:0]", + "description": "SHA256 hash digest of hash of four Root Of Trust Keys", + "index_int": "0x0073", + "shadow_reg_offset_int": "0x01CC", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x0001", + "read_lock_int": "0x0004", + "operation_lock_int": "0x0002" + } + } + ] + }, + { + "group": { + "name": "User Space ECC", + "description": "User Space ECC" + }, + "registers": [ + { + "id": "fuse156", + "name": "USER_ECC_0", + "description": "Customer programmable ECC fuse word", + "index_int": "0x009C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse156-bits-0-31", + "name": "USER_ECC_0", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse157", + "name": "USER_ECC_1", + "description": "Customer programmable ECC fuse word", + "index_int": "0x009D", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse157-bits-0-31", + "name": "USER_ECC_1", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse158", + "name": "USER_ECC_2", + "description": "Customer programmable ECC fuse word", + "index_int": "0x009E", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse158-bits-0-31", + "name": "USER_ECC_2", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse159", + "name": "USER_ECC_3", + "description": "Customer programmable ECC fuse word", + "index_int": "0x009F", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse159-bits-0-31", + "name": "USER_ECC_3", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse160", + "name": "USER_ECC_4", + "description": "Customer programmable ECC fuse word", + "index_int": "0x00A0", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse160-bits-0-31", + "name": "USER_ECC_4", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse161", + "name": "USER_ECC_5", + "description": "Customer programmable ECC fuse word", + "index_int": "0x00A1", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse161-bits-0-31", + "name": "USER_ECC_5", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse162", + "name": "USER_ECC_6", + "description": "Customer programmable ECC fuse word", + "index_int": "0x00A2", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse162-bits-0-31", + "name": "USER_ECC_6", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse163", + "name": "USER_ECC_7", + "description": "Customer programmable ECC fuse word", + "index_int": "0x00A3", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse163-bits-0-31", + "name": "USER_ECC_7", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse315", + "name": "USER_ECC_8", + "description": "Customer programmable ECC fuse word", + "index_int": "0x013B", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse315-bits-0-31", + "name": "USER_ECC_8", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse316", + "name": "USER_ECC_9", + "description": "Customer programmable ECC fuse word", + "index_int": "0x013C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse316-bits-0-31", + "name": "USER_ECC_9", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse317", + "name": "USER_ECC_10", + "description": "Customer programmable ECC fuse word", + "index_int": "0x013D", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse317-bits-0-31", + "name": "USER_ECC_10", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse318", + "name": "USER_ECC_11", + "description": "Customer programmable ECC fuse word", + "index_int": "0x013E", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse318-bits-0-31", + "name": "USER_ECC_11", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse319", + "name": "USER_ECC_12", + "description": "Customer programmable ECC fuse word", + "index_int": "0x013F", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse319-bits-0-31", + "name": "USER_ECC_12", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse320", + "name": "USER_ECC_13", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0140", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse320-bits-0-31", + "name": "USER_ECC_13", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse321", + "name": "USER_ECC_14", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0141", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse321-bits-0-31", + "name": "USER_ECC_14", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse322", + "name": "USER_ECC_15", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0142", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse322-bits-0-31", + "name": "USER_ECC_15", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse323", + "name": "USER_ECC_16", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0143", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse323-bits-0-31", + "name": "USER_ECC_16", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse324", + "name": "USER_ECC_17", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0144", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse324-bits-0-31", + "name": "USER_ECC_17", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse325", + "name": "USER_ECC_18", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0145", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse325-bits-0-31", + "name": "USER_ECC_18", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse326", + "name": "USER_ECC_19", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0146", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse326-bits-0-31", + "name": "USER_ECC_19", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse327", + "name": "USER_ECC_20", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0147", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse327-bits-0-31", + "name": "USER_ECC_20", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse328", + "name": "USER_ECC_21", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0148", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse328-bits-0-31", + "name": "USER_ECC_21", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse329", + "name": "USER_ECC_22", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0149", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse329-bits-0-31", + "name": "USER_ECC_22", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse330", + "name": "USER_ECC_23", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014A", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse330-bits-0-31", + "name": "USER_ECC_23", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse331", + "name": "USER_ECC_24", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014B", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse331-bits-0-31", + "name": "USER_ECC_24", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse332", + "name": "USER_ECC_25", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse332-bits-0-31", + "name": "USER_ECC_25", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse333", + "name": "USER_ECC_26", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014D", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse333-bits-0-31", + "name": "USER_ECC_26", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse334", + "name": "USER_ECC_27", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014E", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse334-bits-0-31", + "name": "USER_ECC_27", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse335", + "name": "USER_ECC_28", + "description": "Customer programmable ECC fuse word", + "index_int": "0x014F", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse335-bits-0-31", + "name": "USER_ECC_28", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse336", + "name": "USER_ECC_29", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0150", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse336-bits-0-31", + "name": "USER_ECC_29", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse337", + "name": "USER_ECC_30", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0151", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse337-bits-0-31", + "name": "USER_ECC_30", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse338", + "name": "USER_ECC_31", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0152", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse338-bits-0-31", + "name": "USER_ECC_31", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse339", + "name": "USER_ECC_32", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0153", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse339-bits-0-31", + "name": "USER_ECC_32", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse340", + "name": "USER_ECC_33", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0154", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse340-bits-0-31", + "name": "USER_ECC_33", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse341", + "name": "USER_ECC_34", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0155", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse341-bits-0-31", + "name": "USER_ECC_34", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse342", + "name": "USER_ECC_35", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0156", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse342-bits-0-31", + "name": "USER_ECC_35", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse343", + "name": "USER_ECC_36", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0157", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse343-bits-0-31", + "name": "USER_ECC_36", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse344", + "name": "USER_ECC_37", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0158", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse344-bits-0-31", + "name": "USER_ECC_37", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse345", + "name": "USER_ECC_38", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0159", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse345-bits-0-31", + "name": "USER_ECC_38", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse346", + "name": "USER_ECC_39", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015A", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse346-bits-0-31", + "name": "USER_ECC_39", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse347", + "name": "USER_ECC_40", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015B", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse347-bits-0-31", + "name": "USER_ECC_40", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse348", + "name": "USER_ECC_41", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015C", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse348-bits-0-31", + "name": "USER_ECC_41", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse349", + "name": "USER_ECC_42", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015D", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse349-bits-0-31", + "name": "USER_ECC_42", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse350", + "name": "USER_ECC_43", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015E", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse350-bits-0-31", + "name": "USER_ECC_43", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse351", + "name": "USER_ECC_44", + "description": "Customer programmable ECC fuse word", + "index_int": "0x015F", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse351-bits-0-31", + "name": "USER_ECC_44", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse352", + "name": "USER_ECC_45", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0160", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse352-bits-0-31", + "name": "USER_ECC_45", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse353", + "name": "USER_ECC_46", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0161", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse353-bits-0-31", + "name": "USER_ECC_46", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse354", + "name": "USER_ECC_47", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0162", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse354-bits-0-31", + "name": "USER_ECC_47", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse355", + "name": "USER_ECC_48", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0163", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse355-bits-0-31", + "name": "USER_ECC_48", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse356", + "name": "USER_ECC_49", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0164", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse356-bits-0-31", + "name": "USER_ECC_49", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse357", + "name": "USER_ECC_50", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0165", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse357-bits-0-31", + "name": "USER_ECC_50", + "description": "Customer programmable ECC fuse word" + } + ] + }, + { + "id": "fuse358", + "name": "USER_ECC_51", + "description": "Customer programmable ECC fuse word", + "index_int": "0x0166", + "individual_write_lock": "implicit", + "bitfields": [ + { + "width": 32, + "id": "fuse358-bits-0-31", + "name": "USER_ECC_51", + "description": "Customer programmable ECC fuse word" + } + ] + } + ] + }, + { + "group": { + "name": "CRCx", + "description": "CRCx" + }, + "registers": [ + { + "id": "fuse360", + "name": "CRC0", + "description": "Reserved", + "index_int": "0x0168", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse360-bits-0-31", + "name": "CRC0", + "description": "Reserved" + } + ] + }, + { + "id": "fuse361", + "name": "CRC1", + "description": "CRC32 of BOOT_CFG0-6 configuration data, fuse words 15 to 21.", + "index_int": "0x0169", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse361-bits-0-31", + "name": "CRC1", + "description": "CRC32 of BOOT_CFG0-6 configuration data, fuse words 15 to 21." + } + ] + }, + { + "id": "fuse362", + "name": "CRC2", + "description": "CRC32 of LOCK configuration data, fuse words 0 to 2.", + "index_int": "0x016A", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse362-bits-0-31", + "name": "CRC2", + "description": "CRC32 of LOCK configuration data, fuse words 0 to 2." + } + ] + }, + { + "id": "fuse363", + "name": "CRC3", + "description": "Reserved", + "index_int": "0x016B", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse2", + "write_lock_int": "0x0200", + "read_lock_int": "0x0800", + "operation_lock_int": "0x0400" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse363-bits-0-31", + "name": "CRC3", + "description": "Reserved" + } + ] + }, + { + "id": "fuse364", + "name": "CRC4", + "description": "Reserved", + "index_int": "0x016C", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse364-bits-0-31", + "name": "CRC4", + "description": "Reserved" + } + ] + }, + { + "id": "fuse365", + "name": "CRC5", + "description": "Reserved", + "index_int": "0x016D", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse365-bits-0-31", + "name": "CRC5", + "description": "Reserved" + } + ] + }, + { + "id": "fuse366", + "name": "CRC6", + "description": "CRC32 of OEM programmed keys, fuse words 92 to 115.", + "index_int": "0x016E", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse366-bits-0-31", + "name": "CRC6", + "description": "CRC32 of OEM programmed keys, fuse words 92 to 115." + } + ] + }, + { + "id": "fuse367", + "name": "CRC7", + "description": "Reserved", + "index_int": "0x016F", + "individual_write_lock": "implicit", + "lock": { + "register_id": "fuse1", + "write_lock_int": "0x1000", + "read_lock_int": "0x4000", + "operation_lock_int": "0x2000" + }, + "bitfields": [ + { + "width": 32, + "id": "fuse367-bits-0-31", + "name": "CRC7", + "description": "Reserved" + } + ] + } + ] + }, + { + "group": { + "name": "TZ_NSW_Version", + "description": "Non-Secure firmware version counter" + }, + "registers": [ + { + "id": "fuse368", + "name": "NT_FW_VER0", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0170", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse368-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 0..15" + } + ] + }, + { + "id": "fuse369", + "name": "NT_FW_VER1", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0171", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse369-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 16..31" + } + ] + }, + { + "id": "fuse370", + "name": "NT_FW_VER2", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0172", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse370-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 32..47" + } + ] + }, + { + "id": "fuse371", + "name": "NT_FW_VER3", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0173", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse371-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 48..63" + } + ] + }, + { + "id": "fuse372", + "name": "NT_FW_VER4", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0174", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse372-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 64..79" + } + ] + }, + { + "id": "fuse373", + "name": "NT_FW_VER5", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0175", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse373-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 80..95" + } + ] + }, + { + "id": "fuse374", + "name": "NT_FW_VER6", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0176", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse374-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 96..111" + } + ] + }, + { + "id": "fuse375", + "name": "NT_FW_VER7", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0177", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse375-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 112..127" + } + ] + }, + { + "id": "fuse376", + "name": "NT_FW_VER8", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0178", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse376-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 128..143" + } + ] + }, + { + "id": "fuse377", + "name": "NT_FW_VER9", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0179", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse377-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 144..159" + } + ] + }, + { + "id": "fuse378", + "name": "NT_FW_VER10", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017A", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse378-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 160..175" + } + ] + }, + { + "id": "fuse379", + "name": "NT_FW_VER11", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017B", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse379-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 176..191" + } + ] + }, + { + "id": "fuse380", + "name": "NT_FW_VER12", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017C", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse380-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 192..207" + } + ] + }, + { + "id": "fuse381", + "name": "NT_FW_VER13", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017D", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse381-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 208..223" + } + ] + }, + { + "id": "fuse382", + "name": "NT_FW_VER14", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017E", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse382-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 224..239" + } + ] + }, + { + "id": "fuse383", + "name": "NT_FW_VER15", + "description": "Non-Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x017F", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse383-bits-0-15", + "name": "NT_FW_VER", + "description": "Non-Secure TrustZone firmware version counter, bits 240..255" + } + ] + } + ] + }, + { + "group": { + "name": "TZ_SW_Version", + "description": "Secure firmware version counter" + }, + "registers": [ + { + "id": "fuse384", + "name": "TZ_FW_VER0", + "description": "Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0180", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse384-bits-0-15", + "name": "TZ_FW_VER", + "description": "Secure TrustZone firmware version counter, bits 0..15" + } + ] + }, + { + "id": "fuse385", + "name": "TZ_FW_VER1", + "description": "Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0181", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse385-bits-0-15", + "name": "TZ_FW_VER", + "description": "Secure TrustZone firmware version counter, bits 16..31" + } + ] + }, + { + "id": "fuse386", + "name": "TZ_FW_VER2", + "description": "Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0182", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse386-bits-0-15", + "name": "TZ_FW_VER", + "description": "Secure TrustZone firmware version counter, bits 32.47" + } + ] + }, + { + "id": "fuse387", + "name": "TZ_FW_VER3", + "description": "Secure TrustZone Version. The version is represented by number of set fuse bits.", + "index_int": "0x0183", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse387-bits-0-15", + "name": "TZ_FW_VER", + "description": "Secure TrustZone firmware version counter, bits 48..63" + } + ] + } + ] + }, + { + "group": { + "name": "User Space", + "description": "User Space" + }, + "registers": [ + { + "id": "fuse400", + "name": "USER_RED_0", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0190", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse400-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 0" + } + ] + }, + { + "id": "fuse401", + "name": "USER_RED_1", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0191", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse401-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 1" + } + ] + }, + { + "id": "fuse402", + "name": "USER_RED_2", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0192", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse402-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 2" + } + ] + }, + { + "id": "fuse403", + "name": "USER_RED_3", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0193", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse403-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 3" + } + ] + }, + { + "id": "fuse408", + "name": "USER_RED_4", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0198", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse408-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 4" + } + ] + }, + { + "id": "fuse409", + "name": "USER_RED_5", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x0199", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse409-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 5" + } + ] + }, + { + "id": "fuse410", + "name": "USER_RED_6", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019A", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse410-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 6" + } + ] + }, + { + "id": "fuse411", + "name": "USER_RED_7", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019B", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse411-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 7" + } + ] + }, + { + "id": "fuse412", + "name": "USER_RED_8", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019C", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse412-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 8" + } + ] + }, + { + "id": "fuse413", + "name": "USER_RED_9", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019D", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse413-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 9" + } + ] + }, + { + "id": "fuse414", + "name": "USER_RED_10", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019E", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse414-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 10" + } + ] + }, + { + "id": "fuse415", + "name": "USER_RED_11", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x019F", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse415-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 11" + } + ] + }, + { + "id": "fuse416", + "name": "USER_RED_12", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x01A0", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse416-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 12" + } + ] + }, + { + "id": "fuse417", + "name": "USER_RED_13", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x01A1", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse417-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 13" + } + ] + }, + { + "id": "fuse418", + "name": "USER_RED_14", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x01A2", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse418-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 14" + } + ] + }, + { + "id": "fuse419", + "name": "USER_RED_15", + "description": "Customer Programmable Redundant Fuse Word", + "index_int": "0x01A3", + "reg_width": 16, + "bitfields": [ + { + "width": 16, + "id": "fuse419-bits-0-15", + "name": "User", + "description": "Customer programmable fuse word 15" + } + ] + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/tz.json b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/tz.json new file mode 100644 index 0000000..81ab581 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/devices/rw612/tz.json @@ -0,0 +1,1933 @@ +{ + "cpu": "rw612", + "groups": [ + { + "group": { + "name": "General regs", + "description": "General register generated by SPSDK" + }, + "registers": [ + { + "id": "field000", + "offset_int": "0x0", + "reg_width": 32, + "name": "Start of block (tzm_magic)", + "description": "TrustZone register - Start of block (tzm_magic)", + "default_value_int": "0x4d2d5a54" + }, + { + "id": "field004", + "offset_int": "0x4", + "reg_width": 32, + "name": "CM33 Secure vector table address (cm33_vtor_addr)", + "description": "TrustZone register - CM33 Secure vector table address (cm33_vtor_addr)", + "default_value_int": "0x0" + }, + { + "id": "field008", + "offset_int": "0x8", + "reg_width": 32, + "name": "CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "description": "TrustZone register - CM33 Non-secure vector table address (cm33_vtor_ns_addr)", + "default_value_int": "0x0" + }, + { + "id": "field00C", + "offset_int": "0xc", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 0 (cm33_nvic_itns0)", + "default_value_int": "0x0" + }, + { + "id": "field010", + "offset_int": "0x10", + "reg_width": 32, + "name": "CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "description": "TrustZone register - CM33 Interrupt target non-secure register 1 (cm33_nvic_itns1)", + "default_value_int": "0x0" + }, + { + "id": "field014", + "offset_int": "0x14", + "reg_width": 32, + "name": "Miscellaneous CM33 settings (cm33_misc_ctrl)", + "description": "TrustZone register - Miscellaneous CM33 settings (cm33_misc_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field018", + "offset_int": "0x18", + "reg_width": 32, + "name": "CM33 Non-secure Access Control Register (cm33_nsacr)", + "description": "TrustZone register - CM33 Non-secure Access Control Register (cm33_nsacr)", + "default_value_int": "0x0" + }, + { + "id": "field01C", + "offset_int": "0x1c", + "reg_width": 32, + "name": "CM33 Coprocessor Power Control Register (cm33_cppwr)", + "description": "TrustZone register - CM33 Coprocessor Power Control Register (cm33_cppwr)", + "default_value_int": "0x0" + }, + { + "id": "field020", + "offset_int": "0x20", + "reg_width": 32, + "name": "CM33 Coprocessor Access Control Register (cm33_cpacr)", + "description": "TrustZone register - CM33 Coprocessor Access Control Register (cm33_cpacr)", + "default_value_int": "0x0" + }, + { + "id": "field024", + "offset_int": "0x24", + "reg_width": 32, + "name": "MPU Control Register (cm33_mpu_ctrl)", + "description": "TrustZone register - MPU Control Register (cm33_mpu_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field028", + "offset_int": "0x28", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0)", + "default_value_int": "0x0" + }, + { + "id": "field02C", + "offset_int": "0x2c", + "reg_width": 32, + "name": "MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "description": "TrustZone register - MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1)", + "default_value_int": "0x0" + }, + { + "id": "field030", + "offset_int": "0x30", + "reg_width": 32, + "name": "MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "description": "TrustZone register - MPU Region 0 Base Address Register (cm33_mpu_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field034", + "offset_int": "0x34", + "reg_width": 32, + "name": "MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "description": "TrustZone register - MPU Region 0 Limit Address Register (cm33_mpu_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field038", + "offset_int": "0x38", + "reg_width": 32, + "name": "MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "description": "TrustZone register - MPU Region 1 Base Address Register (cm33_mpu_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field03C", + "offset_int": "0x3c", + "reg_width": 32, + "name": "MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "description": "TrustZone register - MPU Region 1 Limit Address Register (cm33_mpu_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field040", + "offset_int": "0x40", + "reg_width": 32, + "name": "MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "description": "TrustZone register - MPU Region 2 Base Address Register (cm33_mpu_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field044", + "offset_int": "0x44", + "reg_width": 32, + "name": "MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "description": "TrustZone register - MPU Region 2 Limit Address Register (cm33_mpu_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field048", + "offset_int": "0x48", + "reg_width": 32, + "name": "MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "description": "TrustZone register - MPU Region 3 Base Address Register (cm33_mpu_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field04C", + "offset_int": "0x4c", + "reg_width": 32, + "name": "MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "description": "TrustZone register - MPU Region 3 Limit Address Register (cm33_mpu_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field050", + "offset_int": "0x50", + "reg_width": 32, + "name": "MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "description": "TrustZone register - MPU Region 4 Base Address Register (cm33_mpu_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field054", + "offset_int": "0x54", + "reg_width": 32, + "name": "MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "description": "TrustZone register - MPU Region 4 Limit Address Register (cm33_mpu_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field058", + "offset_int": "0x58", + "reg_width": 32, + "name": "MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "description": "TrustZone register - MPU Region 5 Base Address Register (cm33_mpu_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field05C", + "offset_int": "0x5c", + "reg_width": 32, + "name": "MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "description": "TrustZone register - MPU Region 5 Limit Address Register (cm33_mpu_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field060", + "offset_int": "0x60", + "reg_width": 32, + "name": "MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "description": "TrustZone register - MPU Region 6 Base Address Register (cm33_mpu_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field064", + "offset_int": "0x64", + "reg_width": 32, + "name": "MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "description": "TrustZone register - MPU Region 6 Limit Address Register (cm33_mpu_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field068", + "offset_int": "0x68", + "reg_width": 32, + "name": "MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "description": "TrustZone register - MPU Region 7 Base Address Register (cm33_mpu_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field06C", + "offset_int": "0x6c", + "reg_width": 32, + "name": "MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "description": "TrustZone register - MPU Region 7 Limit Address Register (cm33_mpu_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field070", + "offset_int": "0x70", + "reg_width": 32, + "name": "Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "description": "TrustZone register - Non-secure MPU Control Register (cm33_mpu_ctrl_ns)", + "default_value_int": "0x0" + }, + { + "id": "field074", + "offset_int": "0x74", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 0 (cm33_mpu_mair0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field078", + "offset_int": "0x78", + "reg_width": 32, + "name": "Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "description": "TrustZone register - Non-secure MPU Memory Attribute Indirection Register 1 (cm33_mpu_mair1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field07C", + "offset_int": "0x7c", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Base Address Register (cm33_mpu_rbar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field080", + "offset_int": "0x80", + "reg_width": 32, + "name": "Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "description": "TrustZone register - Non-secure MPU Region 0 Limit Address Register (cm33_mpu_rlar0_ns)", + "default_value_int": "0x0" + }, + { + "id": "field084", + "offset_int": "0x84", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Base Address Register (cm33_mpu_rbar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field088", + "offset_int": "0x88", + "reg_width": 32, + "name": "Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "description": "TrustZone register - Non-secure MPU Region 1 Limit Address Register (cm33_mpu_rlar1_ns)", + "default_value_int": "0x0" + }, + { + "id": "field08C", + "offset_int": "0x8c", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Base Address Register (cm33_mpu_rbar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field090", + "offset_int": "0x90", + "reg_width": 32, + "name": "Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "description": "TrustZone register - Non-secure MPU Region 2 Limit Address Register (cm33_mpu_rlar2_ns)", + "default_value_int": "0x0" + }, + { + "id": "field094", + "offset_int": "0x94", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Base Address Register (cm33_mpu_rbar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field098", + "offset_int": "0x98", + "reg_width": 32, + "name": "Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "description": "TrustZone register - Non-secure MPU Region 3 Limit Address Register (cm33_mpu_rlar3_ns)", + "default_value_int": "0x0" + }, + { + "id": "field09C", + "offset_int": "0x9c", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Base Address Register (cm33_mpu_rbar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A0", + "offset_int": "0xa0", + "reg_width": 32, + "name": "Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "description": "TrustZone register - Non-secure MPU Region 4 Limit Address Register (cm33_mpu_rlar4_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A4", + "offset_int": "0xa4", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Base Address Register (cm33_mpu_rbar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0A8", + "offset_int": "0xa8", + "reg_width": 32, + "name": "Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "description": "TrustZone register - Non-secure MPU Region 5 Limit Address Register (cm33_mpu_rlar5_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0AC", + "offset_int": "0xac", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Base Address Register (cm33_mpu_rbar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B0", + "offset_int": "0xb0", + "reg_width": 32, + "name": "Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "description": "TrustZone register - Non-secure MPU Region 6 Limit Address Register (cm33_mpu_rlar6_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B4", + "offset_int": "0xb4", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Base Address Register (cm33_mpu_rbar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0B8", + "offset_int": "0xb8", + "reg_width": 32, + "name": "Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "description": "TrustZone register - Non-secure MPU Region 7 Limit Address Register (cm33_mpu_rlar7_ns)", + "default_value_int": "0x0" + }, + { + "id": "field0BC", + "offset_int": "0xbc", + "reg_width": 32, + "name": "SAU Control Register (cm33_sau_ctrl)", + "description": "TrustZone register - SAU Control Register (cm33_sau_ctrl)", + "default_value_int": "0x0" + }, + { + "id": "field0C0", + "offset_int": "0xc0", + "reg_width": 32, + "name": "SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "description": "TrustZone register - SAU Region 0 Base Address Register (cm33_sau_rbar0)", + "default_value_int": "0x0" + }, + { + "id": "field0C4", + "offset_int": "0xc4", + "reg_width": 32, + "name": "SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "description": "TrustZone register - SAU Region 0 Limit Address Register (cm33_sau_rlar0)", + "default_value_int": "0x0" + }, + { + "id": "field0C8", + "offset_int": "0xc8", + "reg_width": 32, + "name": "SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "description": "TrustZone register - SAU Region 1 Base Address Register (cm33_sau_rbar1)", + "default_value_int": "0x0" + }, + { + "id": "field0CC", + "offset_int": "0xcc", + "reg_width": 32, + "name": "SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "description": "TrustZone register - SAU Region 1 Limit Address Register (cm33_sau_rlar1)", + "default_value_int": "0x0" + }, + { + "id": "field0D0", + "offset_int": "0xd0", + "reg_width": 32, + "name": "SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "description": "TrustZone register - SAU Region 2 Base Address Register (cm33_sau_rbar2)", + "default_value_int": "0x0" + }, + { + "id": "field0D4", + "offset_int": "0xd4", + "reg_width": 32, + "name": "SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "description": "TrustZone register - SAU Region 2 Limit Address Register (cm33_sau_rlar2)", + "default_value_int": "0x0" + }, + { + "id": "field0D8", + "offset_int": "0xd8", + "reg_width": 32, + "name": "SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "description": "TrustZone register - SAU Region 3 Base Address Register (cm33_sau_rbar3)", + "default_value_int": "0x0" + }, + { + "id": "field0DC", + "offset_int": "0xdc", + "reg_width": 32, + "name": "SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "description": "TrustZone register - SAU Region 3 Limit Address Register (cm33_sau_rlar3)", + "default_value_int": "0x0" + }, + { + "id": "field0E0", + "offset_int": "0xe0", + "reg_width": 32, + "name": "SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "description": "TrustZone register - SAU Region 4 Base Address Register (cm33_sau_rbar4)", + "default_value_int": "0x0" + }, + { + "id": "field0E4", + "offset_int": "0xe4", + "reg_width": 32, + "name": "SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "description": "TrustZone register - SAU Region 4 Limit Address Register (cm33_sau_rlar4)", + "default_value_int": "0x0" + }, + { + "id": "field0E8", + "offset_int": "0xe8", + "reg_width": 32, + "name": "SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "description": "TrustZone register - SAU Region 5 Base Address Register (cm33_sau_rbar5)", + "default_value_int": "0x0" + }, + { + "id": "field0EC", + "offset_int": "0xec", + "reg_width": 32, + "name": "SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "description": "TrustZone register - SAU Region 5 Limit Address Register (cm33_sau_rlar5)", + "default_value_int": "0x0" + }, + { + "id": "field0F0", + "offset_int": "0xf0", + "reg_width": 32, + "name": "SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "description": "TrustZone register - SAU Region 6 Base Address Register (cm33_sau_rbar6)", + "default_value_int": "0x0" + }, + { + "id": "field0F4", + "offset_int": "0xf4", + "reg_width": 32, + "name": "SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "description": "TrustZone register - SAU Region 6 Limit Address Register (cm33_sau_rlar6)", + "default_value_int": "0x0" + }, + { + "id": "field0F8", + "offset_int": "0xf8", + "reg_width": 32, + "name": "SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "description": "TrustZone register - SAU Region 7 Base Address Register (cm33_sau_rbar7)", + "default_value_int": "0x0" + }, + { + "id": "field0FC", + "offset_int": "0xfc", + "reg_width": 32, + "name": "SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "description": "TrustZone register - SAU Region 7 Limit Address Register (cm33_sau_rlar7)", + "default_value_int": "0x0" + }, + { + "id": "field100", + "offset_int": "0x100", + "reg_width": 32, + "name": "ROM Memory Rule Register 0 (rom_mem_rule0)", + "description": "TrustZone register - ROM Memory Rule Register 0 (rom_mem_rule0)", + "default_value_int": "0x33333333" + }, + { + "id": "field104", + "offset_int": "0x104", + "reg_width": 32, + "name": "ROM Memory Rule Register 1 (rom_mem_rule1)", + "description": "TrustZone register - ROM Memory Rule Register 1 (rom_mem_rule1)", + "default_value_int": "0x33333333" + }, + { + "id": "field108", + "offset_int": "0x108", + "reg_width": 32, + "name": "ROM Memory Rule Register 2 (rom_mem_rule2)", + "description": "TrustZone register - ROM Memory Rule Register 2 (rom_mem_rule2)", + "default_value_int": "0x33333333" + }, + { + "id": "field10C", + "offset_int": "0x10c", + "reg_width": 32, + "name": "ROM Memory Rule Register 3 (rom_mem_rule3)", + "description": "TrustZone register - ROM Memory Rule Register 3 (rom_mem_rule3)", + "default_value_int": "0x33333333" + }, + { + "id": "field110", + "offset_int": "0x110", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 0 Memory Rule Register 0 (flexspi0_region0_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 0 Memory Rule Register 0 (flexspi0_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field114", + "offset_int": "0x114", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 0 Memory Rule Register 1 (flexspi0_region0_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 0 Memory Rule Register 1 (flexspi0_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field118", + "offset_int": "0x118", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 0 Memory Rule Register 2 (flexspi0_region0_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 0 Memory Rule Register 2 (flexspi0_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field11C", + "offset_int": "0x11c", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 0 Memory Rule Register 3 (flexspi0_region0_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 0 Memory Rule Register 3 (flexspi0_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field120", + "offset_int": "0x120", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 1 Memory Rule Register 0 (flexspi0_region1_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 1 Memory Rule Register 0 (flexspi0_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field124", + "offset_int": "0x124", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 2 Memory Rule Register 1 (flexspi0_region2_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 2 Memory Rule Register 1 (flexspi0_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field128", + "offset_int": "0x128", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 3 Memory Rule Register 2 (flexspi0_region3_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 3 Memory Rule Register 2 (flexspi0_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field12C", + "offset_int": "0x12c", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 4 Memory Rule Register 3 (flexspi0_region4_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 4 Memory Rule Register 3 (flexspi0_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field130", + "offset_int": "0x130", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 5 Memory Rule Register 0 (flexspi0_region5_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 5 Memory Rule Register 0 (flexspi0_region5_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field134", + "offset_int": "0x134", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 5 Memory Rule Register 1 (flexspi0_region5_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 5 Memory Rule Register 1 (flexspi0_region5_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field138", + "offset_int": "0x138", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 5 Memory Rule Register 2 (flexspi0_region5_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 5 Memory Rule Register 2 (flexspi0_region5_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field13C", + "offset_int": "0x13c", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 5 Memory Rule Register 3 (flexspi0_region5_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 5 Memory Rule Register 3 (flexspi0_region5_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field140", + "offset_int": "0x140", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 6 Memory Rule Register 0 (flexspi0_region6_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 6 Memory Rule Register 0 (flexspi0_region6_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field144", + "offset_int": "0x144", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 7 Memory Rule Register 0 (flexspi0_region7_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 7 Memory Rule Register 0 (flexspi0_region7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field148", + "offset_int": "0x148", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 8 Memory Rule Register 0 (flexspi0_region8_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 8 Memory Rule Register 0 (flexspi0_region8_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field14C", + "offset_int": "0x14c", + "reg_width": 32, + "name": "FLEXCOMM SPI 0 region 9 Memory Rule Register 0 (flexspi0_region9_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 0 region 9 Memory Rule Register 0 (flexspi0_region9_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field150", + "offset_int": "0x150", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 0 Memory Rule Register 0 (flexspi1_region0_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 0 Memory Rule Register 0 (flexspi1_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field154", + "offset_int": "0x154", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 0 Memory Rule Register 1 (flexspi1_region0_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 0 Memory Rule Register 1 (flexspi1_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field158", + "offset_int": "0x158", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 0 Memory Rule Register 2 (flexspi1_region0_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 0 Memory Rule Register 2 (flexspi1_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field15C", + "offset_int": "0x15c", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 0 Memory Rule Register 3 (flexspi1_region0_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 0 Memory Rule Register 3 (flexspi1_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field160", + "offset_int": "0x160", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 1 Memory Rule Register 0 (flexspi1_region1_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 1 Memory Rule Register 0 (flexspi1_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field164", + "offset_int": "0x164", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 2 Memory Rule Register 1 (flexspi1_region2_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 2 Memory Rule Register 1 (flexspi1_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field168", + "offset_int": "0x168", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 3 Memory Rule Register 2 (flexspi1_region3_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 3 Memory Rule Register 2 (flexspi1_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field16C", + "offset_int": "0x16c", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 4 Memory Rule Register 3 (flexspi1_region4_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 4 Memory Rule Register 3 (flexspi1_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field170", + "offset_int": "0x170", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 5 Memory Rule Register 0 (flexspi1_region5_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 5 Memory Rule Register 0 (flexspi1_region5_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field174", + "offset_int": "0x174", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 5 Memory Rule Register 1 (flexspi1_region5_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 5 Memory Rule Register 1 (flexspi1_region5_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field178", + "offset_int": "0x178", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 5 Memory Rule Register 2 (flexspi1_region5_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 5 Memory Rule Register 2 (flexspi1_region5_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field17C", + "offset_int": "0x17c", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 5 Memory Rule Register 3 (flexspi1_region5_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 5 Memory Rule Register 3 (flexspi1_region5_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field180", + "offset_int": "0x180", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 6 Memory Rule Register 0 (flexspi1_region6_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 6 Memory Rule Register 0 (flexspi1_region6_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field184", + "offset_int": "0x184", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 7 Memory Rule Register 0 (flexspi1_region7_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 7 Memory Rule Register 0 (flexspi1_region7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field188", + "offset_int": "0x188", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 8 Memory Rule Register 0 (flexspi1_region8_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 8 Memory Rule Register 0 (flexspi1_region8_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field18C", + "offset_int": "0x18c", + "reg_width": 32, + "name": "FLEXCOMM SPI 1 region 9 Memory Rule Register 0 (flexspi1_region9_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 1 region 9 Memory Rule Register 0 (flexspi1_region9_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field190", + "offset_int": "0x190", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 0 Memory Rule Register 0 (flexspi2_region0_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 0 Memory Rule Register 0 (flexspi2_region0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field194", + "offset_int": "0x194", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 0 Memory Rule Register 1 (flexspi2_region0_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 0 Memory Rule Register 1 (flexspi2_region0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field198", + "offset_int": "0x198", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 0 Memory Rule Register 2 (flexspi2_region0_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 0 Memory Rule Register 2 (flexspi2_region0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field19C", + "offset_int": "0x19c", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 0 Memory Rule Register 3 (flexspi2_region0_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 0 Memory Rule Register 3 (flexspi2_region0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1A0", + "offset_int": "0x1a0", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 1 Memory Rule Register 0 (flexspi2_region1_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 1 Memory Rule Register 0 (flexspi2_region1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A4", + "offset_int": "0x1a4", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 2 Memory Rule Register 1 (flexspi2_region2_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 2 Memory Rule Register 1 (flexspi2_region2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1A8", + "offset_int": "0x1a8", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 3 Memory Rule Register 2 (flexspi2_region3_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 3 Memory Rule Register 2 (flexspi2_region3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1AC", + "offset_int": "0x1ac", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 4 Memory Rule Register 3 (flexspi2_region4_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 4 Memory Rule Register 3 (flexspi2_region4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B0", + "offset_int": "0x1b0", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 5 Memory Rule Register 0 (flexspi2_region5_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 5 Memory Rule Register 0 (flexspi2_region5_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1B4", + "offset_int": "0x1b4", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 5 Memory Rule Register 1 (flexspi2_region5_mem_rule1)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 5 Memory Rule Register 1 (flexspi2_region5_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1B8", + "offset_int": "0x1b8", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 5 Memory Rule Register 2 (flexspi2_region5_mem_rule2)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 5 Memory Rule Register 2 (flexspi2_region5_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1BC", + "offset_int": "0x1bc", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 5 Memory Rule Register 3 (flexspi2_region5_mem_rule3)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 5 Memory Rule Register 3 (flexspi2_region5_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1C0", + "offset_int": "0x1c0", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 6 Memory Rule Register 0 (flexspi2_region6_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 6 Memory Rule Register 0 (flexspi2_region6_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C4", + "offset_int": "0x1c4", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 7 Memory Rule Register 0 (flexspi2_region7_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 7 Memory Rule Register 0 (flexspi2_region7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1C8", + "offset_int": "0x1c8", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 8 Memory Rule Register 0 (flexspi2_region8_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 8 Memory Rule Register 0 (flexspi2_region8_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1CC", + "offset_int": "0x1cc", + "reg_width": 32, + "name": "FLEXCOMM SPI 2 region 9 Memory Rule Register 0 (flexspi2_region9_mem_rule0)", + "description": "TrustZone register - FLEXCOMM SPI 2 region 9 Memory Rule Register 0 (flexspi2_region9_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D0", + "offset_int": "0x1d0", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 0 (ram0_mem_rule0)", + "description": "TrustZone register - RAM00 Memory Rule Register 0 (ram0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1D4", + "offset_int": "0x1d4", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 1 (ram0_mem_rule1)", + "description": "TrustZone register - RAM00 Memory Rule Register 1 (ram0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1D8", + "offset_int": "0x1d8", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 2 (ram0_mem_rule2)", + "description": "TrustZone register - RAM00 Memory Rule Register 2 (ram0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1DC", + "offset_int": "0x1dc", + "reg_width": 32, + "name": "RAM00 Memory Rule Register 3 (ram0_mem_rule3)", + "description": "TrustZone register - RAM00 Memory Rule Register 3 (ram0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1E0", + "offset_int": "0x1e0", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 0 (ram1_mem_rule0)", + "description": "TrustZone register - RAM01 Memory Rule Register 0 (ram1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1E4", + "offset_int": "0x1e4", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 1 (ram1_mem_rule1)", + "description": "TrustZone register - RAM01 Memory Rule Register 1 (ram1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1E8", + "offset_int": "0x1e8", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 2 (ram1_mem_rule2)", + "description": "TrustZone register - RAM01 Memory Rule Register 2 (ram1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1EC", + "offset_int": "0x1ec", + "reg_width": 32, + "name": "RAM01 Memory Rule Register 3 (ram1_mem_rule3)", + "description": "TrustZone register - RAM01 Memory Rule Register 3 (ram1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field1F0", + "offset_int": "0x1f0", + "reg_width": 32, + "name": "RAM02 Memory Rule Register 0 (ram2_mem_rule0)", + "description": "TrustZone register - RAM02 Memory Rule Register 0 (ram2_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field1F4", + "offset_int": "0x1f4", + "reg_width": 32, + "name": "RAM02 Memory Rule Register 1 (ram2_mem_rule1)", + "description": "TrustZone register - RAM02 Memory Rule Register 1 (ram2_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field1F8", + "offset_int": "0x1f8", + "reg_width": 32, + "name": "RAM02 Memory Rule Register 2 (ram2_mem_rule2)", + "description": "TrustZone register - RAM02 Memory Rule Register 2 (ram2_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field1FC", + "offset_int": "0x1fc", + "reg_width": 32, + "name": "RAM02 Memory Rule Register 3 (ram2_mem_rule3)", + "description": "TrustZone register - RAM02 Memory Rule Register 3 (ram2_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field200", + "offset_int": "0x200", + "reg_width": 32, + "name": "RAM03 Memory Rule Register 0 (ram3_mem_rule0)", + "description": "TrustZone register - RAM03 Memory Rule Register 0 (ram3_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field204", + "offset_int": "0x204", + "reg_width": 32, + "name": "RAM03 Memory Rule Register 1 (ram3_mem_rule1)", + "description": "TrustZone register - RAM03 Memory Rule Register 1 (ram3_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field208", + "offset_int": "0x208", + "reg_width": 32, + "name": "RAM03 Memory Rule Register 2 (ram3_mem_rule2)", + "description": "TrustZone register - RAM03 Memory Rule Register 2 (ram3_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field20C", + "offset_int": "0x20c", + "reg_width": 32, + "name": "RAM03 Memory Rule Register 3 (ram3_mem_rule3)", + "description": "TrustZone register - RAM03 Memory Rule Register 3 (ram3_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field210", + "offset_int": "0x210", + "reg_width": 32, + "name": "RAM04 Memory Rule Register 0 (ram4_mem_rule0)", + "description": "TrustZone register - RAM04 Memory Rule Register 0 (ram4_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field214", + "offset_int": "0x214", + "reg_width": 32, + "name": "RAM04 Memory Rule Register 1 (ram4_mem_rule1)", + "description": "TrustZone register - RAM04 Memory Rule Register 1 (ram4_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field218", + "offset_int": "0x218", + "reg_width": 32, + "name": "RAM04 Memory Rule Register 2 (ram4_mem_rule2)", + "description": "TrustZone register - RAM04 Memory Rule Register 2 (ram4_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field21C", + "offset_int": "0x21c", + "reg_width": 32, + "name": "RAM04 Memory Rule Register 3 (ram4_mem_rule3)", + "description": "TrustZone register - RAM04 Memory Rule Register 3 (ram4_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field220", + "offset_int": "0x220", + "reg_width": 32, + "name": "RAM05 Memory Rule Register 0 (ram5_mem_rule0)", + "description": "TrustZone register - RAM05 Memory Rule Register 0 (ram5_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field224", + "offset_int": "0x224", + "reg_width": 32, + "name": "RAM05 Memory Rule Register 1 (ram5_mem_rule1)", + "description": "TrustZone register - RAM05 Memory Rule Register 1 (ram5_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field228", + "offset_int": "0x228", + "reg_width": 32, + "name": "RAM05 Memory Rule Register 2 (ram5_mem_rule2)", + "description": "TrustZone register - RAM05 Memory Rule Register 2 (ram5_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field22C", + "offset_int": "0x22c", + "reg_width": 32, + "name": "RAM05 Memory Rule Register 3 (ram5_mem_rule3)", + "description": "TrustZone register - RAM05 Memory Rule Register 3 (ram5_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field230", + "offset_int": "0x230", + "reg_width": 32, + "name": "RAM06 Memory Rule Register 0 (ram6_mem_rule0)", + "description": "TrustZone register - RAM06 Memory Rule Register 0 (ram6_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field234", + "offset_int": "0x234", + "reg_width": 32, + "name": "RAM06 Memory Rule Register 1 (ram6_mem_rule1)", + "description": "TrustZone register - RAM06 Memory Rule Register 1 (ram6_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field238", + "offset_int": "0x238", + "reg_width": 32, + "name": "RAM06 Memory Rule Register 2 (ram6_mem_rule2)", + "description": "TrustZone register - RAM06 Memory Rule Register 2 (ram6_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field23C", + "offset_int": "0x23c", + "reg_width": 32, + "name": "RAM06 Memory Rule Register 3 (ram6_mem_rule3)", + "description": "TrustZone register - RAM06 Memory Rule Register 3 (ram6_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field240", + "offset_int": "0x240", + "reg_width": 32, + "name": "RAM07 Memory Rule Register 0 (ram7_mem_rule0)", + "description": "TrustZone register - RAM07 Memory Rule Register 0 (ram7_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field244", + "offset_int": "0x244", + "reg_width": 32, + "name": "RAM07 Memory Rule Register 1 (ram7_mem_rule1)", + "description": "TrustZone register - RAM07 Memory Rule Register 1 (ram7_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field248", + "offset_int": "0x248", + "reg_width": 32, + "name": "RAM07 Memory Rule Register 2 (ram7_mem_rule2)", + "description": "TrustZone register - RAM07 Memory Rule Register 2 (ram7_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field24C", + "offset_int": "0x24c", + "reg_width": 32, + "name": "RAM07 Memory Rule Register 3 (ram7_mem_rule3)", + "description": "TrustZone register - RAM07 Memory Rule Register 3 (ram7_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field250", + "offset_int": "0x250", + "reg_width": 32, + "name": "RAM08 Memory Rule Register 0 (ram8_mem_rule0)", + "description": "TrustZone register - RAM08 Memory Rule Register 0 (ram8_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field254", + "offset_int": "0x254", + "reg_width": 32, + "name": "RAM08 Memory Rule Register 1 (ram8_mem_rule1)", + "description": "TrustZone register - RAM08 Memory Rule Register 1 (ram8_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field258", + "offset_int": "0x258", + "reg_width": 32, + "name": "RAM08 Memory Rule Register 2 (ram8_mem_rule2)", + "description": "TrustZone register - RAM08 Memory Rule Register 2 (ram8_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field25C", + "offset_int": "0x25c", + "reg_width": 32, + "name": "RAM08 Memory Rule Register 3 (ram8_mem_rule3)", + "description": "TrustZone register - RAM08 Memory Rule Register 3 (ram8_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field260", + "offset_int": "0x260", + "reg_width": 32, + "name": "RAM09 Memory Rule Register 0 (ram9_mem_rule0)", + "description": "TrustZone register - RAM09 Memory Rule Register 0 (ram9_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field264", + "offset_int": "0x264", + "reg_width": 32, + "name": "RAM09 Memory Rule Register 1 (ram9_mem_rule1)", + "description": "TrustZone register - RAM09 Memory Rule Register 1 (ram9_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field268", + "offset_int": "0x268", + "reg_width": 32, + "name": "RAM09 Memory Rule Register 2 (ram9_mem_rule2)", + "description": "TrustZone register - RAM09 Memory Rule Register 2 (ram9_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field26C", + "offset_int": "0x26c", + "reg_width": 32, + "name": "RAM09 Memory Rule Register 3 (ram9_mem_rule3)", + "description": "TrustZone register - RAM09 Memory Rule Register 3 (ram9_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field270", + "offset_int": "0x270", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "description": "TrustZone register - RAM10 Memory Rule Register 0 (ram10_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field274", + "offset_int": "0x274", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "description": "TrustZone register - RAM10 Memory Rule Register 1 (ram10_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field278", + "offset_int": "0x278", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "description": "TrustZone register - RAM10 Memory Rule Register 2 (ram10_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field27C", + "offset_int": "0x27c", + "reg_width": 32, + "name": "RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "description": "TrustZone register - RAM10 Memory Rule Register 3 (ram10_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field280", + "offset_int": "0x280", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "description": "TrustZone register - RAM11 Memory Rule Register 0 (ram11_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field284", + "offset_int": "0x284", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "description": "TrustZone register - RAM11 Memory Rule Register 1 (ram11_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field288", + "offset_int": "0x288", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "description": "TrustZone register - RAM11 Memory Rule Register 2 (ram11_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field28C", + "offset_int": "0x28c", + "reg_width": 32, + "name": "RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "description": "TrustZone register - RAM11 Memory Rule Register 3 (ram11_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field290", + "offset_int": "0x290", + "reg_width": 32, + "name": "RAM12 Memory Rule Register 0 (ram12_mem_rule0)", + "description": "TrustZone register - RAM12 Memory Rule Register 0 (ram12_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field294", + "offset_int": "0x294", + "reg_width": 32, + "name": "RAM12 Memory Rule Register 1 (ram12_mem_rule1)", + "description": "TrustZone register - RAM12 Memory Rule Register 1 (ram12_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field298", + "offset_int": "0x298", + "reg_width": 32, + "name": "RAM12 Memory Rule Register 2 (ram12_mem_rule2)", + "description": "TrustZone register - RAM12 Memory Rule Register 2 (ram12_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field29C", + "offset_int": "0x29c", + "reg_width": 32, + "name": "RAM12 Memory Rule Register 3 (ram12_mem_rule3)", + "description": "TrustZone register - RAM12 Memory Rule Register 3 (ram12_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2A0", + "offset_int": "0x2a0", + "reg_width": 32, + "name": "RAM13 Memory Rule Register 0 (ram13_mem_rule0)", + "description": "TrustZone register - RAM13 Memory Rule Register 0 (ram13_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2A4", + "offset_int": "0x2a4", + "reg_width": 32, + "name": "RAM13 Memory Rule Register 1 (ram13_mem_rule1)", + "description": "TrustZone register - RAM13 Memory Rule Register 1 (ram13_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2A8", + "offset_int": "0x2a8", + "reg_width": 32, + "name": "RAM13 Memory Rule Register 2 (ram13_mem_rule2)", + "description": "TrustZone register - RAM13 Memory Rule Register 2 (ram13_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2AC", + "offset_int": "0x2ac", + "reg_width": 32, + "name": "RAM13 Memory Rule Register 3 (ram13_mem_rule3)", + "description": "TrustZone register - RAM13 Memory Rule Register 3 (ram13_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2B0", + "offset_int": "0x2b0", + "reg_width": 32, + "name": "RAM14 Memory Rule Register 0 (ram14_mem_rule0)", + "description": "TrustZone register - RAM14 Memory Rule Register 0 (ram14_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2B4", + "offset_int": "0x2b4", + "reg_width": 32, + "name": "RAM14 Memory Rule Register 1 (ram14_mem_rule1)", + "description": "TrustZone register - RAM14 Memory Rule Register 1 (ram14_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2B8", + "offset_int": "0x2b8", + "reg_width": 32, + "name": "RAM14 Memory Rule Register 2 (ram14_mem_rule2)", + "description": "TrustZone register - RAM14 Memory Rule Register 2 (ram14_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2BC", + "offset_int": "0x2bc", + "reg_width": 32, + "name": "RAM14 Memory Rule Register 3 (ram14_mem_rule3)", + "description": "TrustZone register - RAM14 Memory Rule Register 3 (ram14_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2C0", + "offset_int": "0x2c0", + "reg_width": 32, + "name": "RAM15 Memory Rule Register 0 (ram15_mem_rule0)", + "description": "TrustZone register - RAM15 Memory Rule Register 0 (ram15_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2C4", + "offset_int": "0x2c4", + "reg_width": 32, + "name": "RAM15 Memory Rule Register 1 (ram15_mem_rule1)", + "description": "TrustZone register - RAM15 Memory Rule Register 1 (ram15_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2C8", + "offset_int": "0x2c8", + "reg_width": 32, + "name": "RAM15 Memory Rule Register 2 (ram15_mem_rule2)", + "description": "TrustZone register - RAM15 Memory Rule Register 2 (ram15_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2CC", + "offset_int": "0x2cc", + "reg_width": 32, + "name": "RAM15 Memory Rule Register 3 (ram15_mem_rule3)", + "description": "TrustZone register - RAM15 Memory Rule Register 3 (ram15_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2D0", + "offset_int": "0x2d0", + "reg_width": 32, + "name": "RAM16 Memory Rule Register 0 (ram16_mem_rule0)", + "description": "TrustZone register - RAM16 Memory Rule Register 0 (ram16_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2D4", + "offset_int": "0x2d4", + "reg_width": 32, + "name": "RAM16 Memory Rule Register 1 (ram16_mem_rule1)", + "description": "TrustZone register - RAM16 Memory Rule Register 1 (ram16_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2D8", + "offset_int": "0x2d8", + "reg_width": 32, + "name": "RAM16 Memory Rule Register 2 (ram16_mem_rule2)", + "description": "TrustZone register - RAM16 Memory Rule Register 2 (ram16_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2DC", + "offset_int": "0x2dc", + "reg_width": 32, + "name": "RAM16 Memory Rule Register 3 (ram16_mem_rule3)", + "description": "TrustZone register - RAM16 Memory Rule Register 3 (ram16_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2E0", + "offset_int": "0x2e0", + "reg_width": 32, + "name": "RAM17 Memory Rule Register 0 (ram17_mem_rule0)", + "description": "TrustZone register - RAM17 Memory Rule Register 0 (ram17_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2E4", + "offset_int": "0x2e4", + "reg_width": 32, + "name": "RAM17 Memory Rule Register 1 (ram17_mem_rule1)", + "description": "TrustZone register - RAM17 Memory Rule Register 1 (ram17_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2E8", + "offset_int": "0x2e8", + "reg_width": 32, + "name": "RAM17 Memory Rule Register 2 (ram17_mem_rule2)", + "description": "TrustZone register - RAM17 Memory Rule Register 2 (ram17_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2EC", + "offset_int": "0x2ec", + "reg_width": 32, + "name": "RAM17 Memory Rule Register 3 (ram17_mem_rule3)", + "description": "TrustZone register - RAM17 Memory Rule Register 3 (ram17_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field2F0", + "offset_int": "0x2f0", + "reg_width": 32, + "name": "RAM18 Memory Rule Register 0 (ram18_mem_rule0)", + "description": "TrustZone register - RAM18 Memory Rule Register 0 (ram18_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field2F4", + "offset_int": "0x2f4", + "reg_width": 32, + "name": "RAM18 Memory Rule Register 1 (ram18_mem_rule1)", + "description": "TrustZone register - RAM18 Memory Rule Register 1 (ram18_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field2F8", + "offset_int": "0x2f8", + "reg_width": 32, + "name": "RAM18 Memory Rule Register 2 (ram18_mem_rule2)", + "description": "TrustZone register - RAM18 Memory Rule Register 2 (ram18_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field2FC", + "offset_int": "0x2fc", + "reg_width": 32, + "name": "RAM18 Memory Rule Register 3 (ram18_mem_rule3)", + "description": "TrustZone register - RAM18 Memory Rule Register 3 (ram18_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field300", + "offset_int": "0x300", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 0 (apb_grp0_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field304", + "offset_int": "0x304", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 1 (apb_grp0_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field308", + "offset_int": "0x308", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 2 (apb_grp0_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field30C", + "offset_int": "0x30c", + "reg_width": 32, + "name": "APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 0 Memory Rule Register 3 (apb_grp0_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field310", + "offset_int": "0x310", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 0 (apb_grp1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field314", + "offset_int": "0x314", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 1 (apb_grp1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field318", + "offset_int": "0x318", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 2 (apb_grp1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field31C", + "offset_int": "0x31c", + "reg_width": 32, + "name": "APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "description": "TrustZone register - APB Bridge Group 1 Memory Rule Register 3 (apb_grp1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field320", + "offset_int": "0x320", + "reg_width": 32, + "name": "AHB Peripherals 0 Slave Rule Register (ahb_periph0_slave_rule)", + "description": "TrustZone register - AHB Peripherals 0 Slave Rule Register (ahb_periph0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field324", + "offset_int": "0x324", + "reg_width": 32, + "name": "AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule)", + "description": "TrustZone register - AHB Peripherals 1 Slave Rule Register (ahb_periph1_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field328", + "offset_int": "0x328", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 0 (aips_bridge_mem_rule0)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 0 (aips_bridge_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field32C", + "offset_int": "0x32c", + "reg_width": 32, + "name": "AIPS bridge 1 Memory Rule Register 1 (aips_bridge_mem_rule1)", + "description": "TrustZone register - AIPS bridge 1 Memory Rule Register 1 (aips_bridge_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field330", + "offset_int": "0x330", + "reg_width": 32, + "name": "AHB Peripherals 2 Slave Rule Register (ahb_periph2_slave_rule)", + "description": "TrustZone register - AHB Peripherals 2 Slave Rule Register (ahb_periph2_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field334", + "offset_int": "0x334", + "reg_width": 32, + "name": "Security control Memory Rule Register (security_ctrl_mem_rule)", + "description": "TrustZone register - Security control Memory Rule Register (security_ctrl_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field338", + "offset_int": "0x338", + "reg_width": 32, + "name": "AHB Peripherals 3 Slave Rule Register (ahb_periph3_slave_rule)", + "description": "TrustZone register - AHB Peripherals 3 Slave Rule Register (ahb_periph3_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field33C", + "offset_int": "0x33c", + "reg_width": 32, + "name": "Always ON Memory Rule Register (aon_mem_rule)", + "description": "TrustZone register - Always ON Memory Rule Register (aon_mem_rule)", + "default_value_int": "0x0" + }, + { + "id": "field340", + "offset_int": "0x340", + "reg_width": 32, + "name": "WLAN Slave Rule register (wlan_s0_slave_rule)", + "description": "TrustZone register - WLAN Slave Rule register (wlan_s0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field344", + "offset_int": "0x344", + "reg_width": 32, + "name": "WLAN Memory Rule Register 0 (wlan_s1_mem_rule0)", + "description": "TrustZone register - WLAN Memory Rule Register 0 (wlan_s1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field348", + "offset_int": "0x348", + "reg_width": 32, + "name": "WLAN Memory Rule Register 1 (wlan_s1_mem_rule1)", + "description": "TrustZone register - WLAN Memory Rule Register 1 (wlan_s1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field34C", + "offset_int": "0x34c", + "reg_width": 32, + "name": "WLAN Memory Rule Register 2 (wlan_s1_mem_rule2)", + "description": "TrustZone register - WLAN Memory Rule Register 2 (wlan_s1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field350", + "offset_int": "0x350", + "reg_width": 32, + "name": "WLAN Memory Rule Register 3 (wlan_s1_mem_rule3)", + "description": "TrustZone register - WLAN Memory Rule Register 3 (wlan_s1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field354", + "offset_int": "0x354", + "reg_width": 32, + "name": "BLE Slave Rule register (ble_s0_slave_rule)", + "description": "TrustZone register - BLE Slave Rule register (ble_s0_slave_rule)", + "default_value_int": "0x0" + }, + { + "id": "field358", + "offset_int": "0x358", + "reg_width": 32, + "name": "BLE Memory Rule Register 0 (ble_s1_mem_rule0)", + "description": "TrustZone register - BLE Memory Rule Register 0 (ble_s1_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field35C", + "offset_int": "0x35c", + "reg_width": 32, + "name": "BLE Memory Rule Register 1 (ble_s1_mem_rule1)", + "description": "TrustZone register - BLE Memory Rule Register 1 (ble_s1_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field360", + "offset_int": "0x360", + "reg_width": 32, + "name": "BLE Memory Rule Register 2 (ble_s1_mem_rule2)", + "description": "TrustZone register - BLE Memory Rule Register 2 (ble_s1_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field364", + "offset_int": "0x364", + "reg_width": 32, + "name": "BLE Memory Rule Register 3 (ble_s1_mem_rule3)", + "description": "TrustZone register - BLE Memory Rule Register 3 (ble_s1_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field368", + "offset_int": "0x368", + "reg_width": 32, + "name": "SOC Top Memory Rule Register 0 (soc_top_mem_rule0)", + "description": "TrustZone register - SOC Top Memory Rule Register 0 (soc_top_mem_rule0)", + "default_value_int": "0x0" + }, + { + "id": "field36C", + "offset_int": "0x36c", + "reg_width": 32, + "name": "SOC Top Memory Rule Register 1 (soc_top_mem_rule1)", + "description": "TrustZone register - SOC Top Memory Rule Register 1 (soc_top_mem_rule1)", + "default_value_int": "0x0" + }, + { + "id": "field370", + "offset_int": "0x370", + "reg_width": 32, + "name": "SOC Top Memory Rule Register 2 (soc_top_mem_rule2)", + "description": "TrustZone register - SOC Top Memory Rule Register 2 (soc_top_mem_rule2)", + "default_value_int": "0x0" + }, + { + "id": "field374", + "offset_int": "0x374", + "reg_width": 32, + "name": "SOC Top Memory Rule Register 3 (soc_top_mem_rule3)", + "description": "TrustZone register - SOC Top Memory Rule Register 3 (soc_top_mem_rule3)", + "default_value_int": "0x0" + }, + { + "id": "field378", + "offset_int": "0x378", + "reg_width": 32, + "name": "Security violation address/information registers valid flags (sec_vio_info_valid)", + "description": "TrustZone register - Security violation address/information registers valid flags (sec_vio_info_valid)", + "default_value_int": "0x0" + }, + { + "id": "field37C", + "offset_int": "0x37c", + "reg_width": 32, + "name": "Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "description": "TrustZone register - Secure GPIO Mask Register 0 (sec_gpio_mask0)", + "default_value_int": "0xffffffff" + }, + { + "id": "field380", + "offset_int": "0x380", + "reg_width": 32, + "name": "Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "description": "TrustZone register - Secure GPIO Mask Register 1 (sec_gpio_mask1)", + "default_value_int": "0xffffffff" + }, + { + "id": "field384", + "offset_int": "0x384", + "reg_width": 32, + "name": "Secure GPIO Mask Lock Register (sec_gpio_mask_lock)", + "description": "TrustZone register - Secure GPIO Mask Lock Register (sec_gpio_mask_lock)", + "default_value_int": "0xa" + }, + { + "id": "field388", + "offset_int": "0x388", + "reg_width": 32, + "name": "Master Secure Level Register (master_sec_reg)", + "description": "TrustZone register - Master Secure Level Register (master_sec_reg)", + "default_value_int": "0x80000000" + }, + { + "id": "field38C", + "offset_int": "0x38c", + "reg_width": 32, + "name": "Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "description": "TrustZone register - Master Secure Level Anti-pole Register (master_sec_anti_pol_reg)", + "default_value_int": "0xbfffffff" + }, + { + "id": "field390", + "offset_int": "0x390", + "reg_width": 32, + "name": "M33 Lock Control Register (cm33_lock_reg)", + "description": "TrustZone register - M33 Lock Control Register (cm33_lock_reg)", + "default_value_int": "0x800002aa" + }, + { + "id": "field394", + "offset_int": "0x394", + "reg_width": 32, + "name": "Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "description": "TrustZone register - Secure Control Duplicate Register (misc_ctrl_dp_reg)", + "default_value_int": "0x86a2" + }, + { + "id": "field398", + "offset_int": "0x398", + "reg_width": 32, + "name": "Secure Control Register (misc_ctrl_reg)", + "description": "TrustZone register - Secure Control Register (misc_ctrl_reg)", + "default_value_int": "0x86a2" + }, + { + "id": "field39C", + "offset_int": "0x39c", + "reg_width": 32, + "name": "ITRC IRQ Trigger source low selector register 0 (itrc_irq_lo_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source low selector register 0 (itrc_irq_lo_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3A0", + "offset_int": "0x3a0", + "reg_width": 32, + "name": "ITRC IRQ Trigger source low selector register 1 (itrc_irq_lo_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source low selector register 1 (itrc_irq_lo_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3A4", + "offset_int": "0x3a4", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger low source selector register 0 (itrc_chip_reset_lo_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger low source selector register 0 (itrc_chip_reset_lo_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3A8", + "offset_int": "0x3a8", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger low source selector register 1 (itrc_chip_reset_lo_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger low source selector register 1 (itrc_chip_reset_lo_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3AC", + "offset_int": "0x3ac", + "reg_width": 32, + "name": "ITRC IRQ Trigger source high selector register 0 (itrc_irq_hi_sel0)", + "description": "TrustZone register - ITRC IRQ Trigger source high selector register 0 (itrc_irq_hi_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3B0", + "offset_int": "0x3b0", + "reg_width": 32, + "name": "ITRC IRQ Trigger source high selector register 1 (itrc_irq_hi_sel1)", + "description": "TrustZone register - ITRC IRQ Trigger source high selector register 1 (itrc_irq_hi_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3B4", + "offset_int": "0x3b4", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger high source selector register 0 (itrc_chip_reset_hi_sel0)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger high source selector register 0 (itrc_chip_reset_hi_sel0)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3B8", + "offset_int": "0x3b8", + "reg_width": 32, + "name": "ITRC CHIP_RESET Trigger high source selector register 1 (itrc_chip_reset_hi_sel1)", + "description": "TrustZone register - ITRC CHIP_RESET Trigger high source selector register 1 (itrc_chip_reset_hi_sel1)", + "default_value_int": "0xaaaaaaaa" + }, + { + "id": "field3BC", + "offset_int": "0x3bc", + "reg_width": 32, + "name": "Miscellaneous TZM settings (misc_tzm_settings)", + "description": "TrustZone register - Miscellaneous TZM settings (misc_tzm_settings)", + "default_value_int": "0x0" + } + ] + } + ] +} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_ahab.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_ahab.yaml new file mode 100644 index 0000000..6686805 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_ahab.yaml @@ -0,0 +1,882 @@ +# Copyright 2023-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +--- +whole_ahab_image: + type: object + required: + - containers + - output + properties: + target_memory: + type: string + title: Target memory + description: Target memory for AHAB container + enum: [standard, nor, serial_downloader, nand_2k, nand_4k, sd_emmc] + enum_template: [serial_downloader, standard, nand_2k, nand_4k, sd_emmc] + template_value: standard + output: + type: string + title: Output file name + description: Output AHAB file name + format: file_name + template_value: generated_ahab.bin + output_format: + type: string + title: Output file format + description: Output file format for AHAB image + enum: [bin, hex, srec, sparse] + template_value: bin + output_offset: + type: [string, number] + title: Base offset for the output file + description: Base offset where the AHAB image will be placed in target memory. (primarily when using SREC/HEX output_format) + template_value: 0 + format: number + container_version: + type: number + title: Container version + description: + Force container version, if not specified the default version is used. + This configuration option is valid only for chips that supports both AHAB container versions. Possible options <2, 1> + minimal: 1 + maximal: 2 + template_value: 2 + skip_in_template: True + + containers: + title: List of containers present in AHAB + description: The order of containers in the list defines the order in AHAB. + type: array + minItems: 1 + items: + oneOf: + - type: object + required: [binary_container] + properties: + binary_container: + type: object + title: Binary AHAB container + description: Binary Container format to add to AHAB image, Typically it could be used to add ELE Firmware. + required: [path] + properties: + path: + type: string + title: The AHAB container binary file + description: The binary file that contains AHAB "my_binary_container.bin + template_value: my_ahab_container.bin + - type: object + required: [container] + properties: + container: + type: object + title: AHAB Container + description: Configurable Container format to add to AHAB image. This allow to configure all aspects of the AHAB container. + required: [srk_set, images] + if: + properties: + srk_set: + const: none + then: + required: [] + else: + required: [srk_table, used_srk_id] + properties: + srk_set: + type: string + title: Super Root Key (SRK) set + description: Defines which set is used to authenticate the container. + enum: [none, oem, nxp] + template_value: none + used_srk_id: + type: [number, string] + title: Used SRK + description: Which key from SRK set is being used. + format: number + template_value: 0 + srk_revoke_mask: + type: [number, string] + title: SRK revoke mask + description: + Bit-mask to indicate which SRKs to revoke. Bit set to 1 means revoke + key. Bit 0 = revoke SRK_0, bit 1 = revoke SRK_1 etc. + Example of revocation SRK_0 and SRK_1 - the value should be 0x03 + format: number + template_value: "0x00" + gdet_runtime_behavior: + type: string + title: GDET runtime behavior + description: + "This option defines runtime behavior of Glitch detector. Not supported by all devices and their ELE firmware.\n + - disabled: GDET is disabled after the first OEM container has been authenticated (default behavior)\n + - enabled_eleapi: Automatically enable GDET during all ELE API calls\n + - enabled: Leave GDET enabled" + enum: [disabled, enabled_eleapi, enabled] + template_value: disabled + check_all_signatures: + type: string + title: Check all signatures + description: + "This option overrides a fuse to select verification mode.\n + - default: Apply default fuse policy.\n + - check_all_signatures: Force verification of all present signatures." + enum: [default, check_all_signatures] + template_value: default + skip_in_template: True + fast_boot: + type: string + title: Fast boot + description: "This option enables fast boot mode.\n + - disabled: Fast boot disabled.\n + - hash_and_copy: ELE will do the hash and copy (when disabled, BootROM will do the copy).\n + - external_accelerator: Use external accelerator for authentication (e.g. V2X on i.MX95B0, i.MX943 and i.MX952).\n + - hash_and_copy_with_external_accelerator:ELE will do hash and copy, and use external accelerator for authentication." + enum: + [ + disabled, + hash_and_copy, + external_accelerator, + hash_and_copy_with_external_accelerator, + ] + skip_in_template: True + template_value: disabled + fuse_version: + type: [number, string] + title: Fuse version + description: + The value must be equal or greater than the version stored in fuses + to allow loading this container. + format: number + template_value: 0 + sw_version: + type: [number, string] + title: Software version + description: + Number used by Privileged Host Boot Companion (PHBC) to select between + multiple images with same Fuse version field. + format: number + template_value: 0 + signer: + type: string + title: AHAB container signer + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for sign the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + signer_#2: + type: string + title: AHAB container signer for second signature (PQC only) + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for second sign (PQC only) of the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + skip_in_template: True + images: + type: array + title: Image array + description: Array of image entries. + template_title: Configuration of AHAB Container images (array of multiple images) + minItems: 1 + maxItems: 8 + items: + oneOf: + - type: object + template_title: SPL with optional DDR tunning images + image_identifier: spl_ddr + skip_in_template: True + description: U-Boot SPL with optional DDR PHY tunning images + required: + [ + spl_ddr, + lpddr_imem_1d, + lpddr_imem_2d, + lpddr_dmem_1d, + lpddr_dmem_2d, + ] + properties: + lpddr_imem_1d: + type: string + title: LPDDR memory FW in 1D mode + description: Firmware for LPDDR4/5 memory in 1D mode. + template_value: lpddr_imem_1d.bin + format: file + lpddr_imem_2d: + type: string + title: LPDDR memory FW in 2D mode + description: Firmware for LPDDR4/5 memory in 2D mode. + template_value: lpddr_imem_2d.bin + format: file + lpddr_dmem_1d: + type: string + title: LPDDR memory data in 1D mode + description: Data for LPDDR4/5 memory in 1D mode. + template_value: lpddr_dmem_1d.bin + format: file + lpddr_dmem_2d: + type: string + title: LPDDR memory data in 2D mode + description: Data for LPDDR4/5 memory in 2D mode. + template_value: lpddr_dmem_2d.bin + format: file + spl_ddr: + type: string + title: SPL + description: SPL firmware + template_value: spl.bin + format: file + + - type: object + template_title: OEI with DDR tunning images + image_identifier: oei_ddr + skip_in_template: True + description: OEI with DDR PHY tunning images + required: [oei_ddr, lpddr_imem, lpddr_dmem] + properties: + lpddr_imem: + type: string + title: LPDDR memory FW + description: Firmware for LPDDR4/5 memory. + template_value: lpddr_imem.bin + format: file + lpddr_imem_qb: + type: string + title: LPDDR memory FW for quick boot + description: Firmware for LPDDR4/5 for quick boot. + template_value: lpddr_imem_qb.bin + format: file + lpddr_dmem: + type: string + title: LPDDR memory data + description: Data for LPDDR4/5 memory. + template_value: lpddr_dmem.bin + format: file + lpddr_dmem_qb: + type: string + title: LPDDR memory data for quick boot + description: Data for LPDDR4/5 memory in quick boot. + template_value: lpddr_dmem_qb.bin + format: file + oei_ddr: + type: string + title: OEI + description: OEI - Optional Executable Image firmware + template_value: oei_ddr.bin + format: file + qb_data: + type: string + title: Quick Boot Data + description: QB data - Optional Quick boot data, if defined a new empty record will be added just behind DDR FW entry + template_value: qb_data.bin + format: file + + - type: object + template_title: OEI with DDR tunning images + image_identifier: oei_ddr_no_qb + skip_in_template: True + description: OEI with DDR PHY tunning images + required: [oei_ddr, lpddr_imem, lpddr_dmem] + properties: + lpddr_imem: + type: string + title: LPDDR memory FW + description: Firmware for LPDDR4/5 memory. + template_value: lpddr4x_imem_v202409.bin + format: file + lpddr_imem_qb: + type: string + title: LPDDR memory FW for quick boot + description: Firmware for LPDDR4/5 for quick boot. + template_value: lpddr4x_imem_qb_v202409.bin + format: file + lpddr_dmem: + type: string + title: LPDDR memory data + description: Data for LPDDR4/5 memory. + template_value: lpddr4x_dmem_v202409.bin + format: file + lpddr_dmem_qb: + type: string + title: LPDDR memory data for quick boot + description: Data for LPDDR4/5 memory in quick boot. + template_value: lpddr4x_dmem_qb_v202409.bin + format: file + oei_ddr: + type: string + title: OEI + description: OEI - Optional Executable Image firmware + template_value: oei-m33-ddr.bin + format: file + + - type: object + template_title: OEI TCM Settings (ECC configuration etc.) + image_identifier: oei_tcm + skip_in_template: True + description: OEI TCM settings (ECC etc.) + required: [oei_tcm] + properties: + oei_tcm: + type: string + title: OEI TCM FW + description: OEI(Optional Executable Image) TCM settings binary file. + template_value: oei_tcm.bin + format: file + + - type: object + template_title: Double Authentication of NXP Firmwares + image_identifier: double_authentication + skip_in_template: True + description: Double Authentication of NXP firmwares + required: [double_authentication] + properties: + double_authentication: + type: string + title: NXP ELE FW + description: NXP ELE firmware, that should be also signed by OEM keys binary file. + template_value: nxp_ele.bin + format: file + + - type: object + template_title: Boot system manager + image_identifier: system_manager + skip_in_template: True + description: System booting image + required: [system_manager] + properties: + system_manager: + type: string + title: Boot system manager + description: System manager booting image + template_value: system_manager.bin + format: file + + - type: object + template_title: Cortex M7 additional application + image_identifier: cortex_m7_app + skip_in_template: True + description: Cortex M7 additional application + required: [cortex_m7_app] + properties: + cortex_m7_app: + type: string + title: Cortex M7 additional application + description: Cortex M7 additional application + template_value: cortex_m7_app.bin + format: file + + - type: object + template_title: Cortex M7 second core additional application + image_identifier: cortex_m7_2_app + skip_in_template: True + description: Cortex M7 second core additional application + required: [cortex_m7_2_app] + properties: + cortex_m7_2_app: + type: string + title: Cortex M7 second core additional application + description: Cortex M7 second core additional application + template_value: cortex_m7_2_app.bin + format: file + + - type: object + template_title: Cortex M33 second core additional application + image_identifier: cortex_m33_2_app + skip_in_template: True + description: Cortex M33 second core additional application + required: [cortex_m33_2_app] + properties: + cortex_m33_2_app: + type: string + title: Cortex M33 second core additional application + description: Cortex M33 second core additional application + template_value: cortex_m33_2_app.bin + format: file + + - type: object + template_title: TEE Trusted Execution Environment + image_identifier: tee + skip_in_template: True + description: + A TEE (Trusted Execution Environment) is a trusted OS running in some + secure environment, for example, TrustZone on ARM CPUs, or a separate + secure co-processor etc. A TEE driver handles the details needed to + communicate with the TEE. + required: [tee] + properties: + tee: + type: string + title: TEE + description: TEE - Trusted Execution Environment binary + template_value: tee.bin + format: file + + - type: object + template_title: uPower + image_identifier: upower + skip_in_template: True + description: uPower firmware + required: [upower] + properties: + upower: + type: string + title: uPower + description: uPower firmware + template_value: upower.bin + format: file + + - type: object + template_title: MCU Image + image_identifier: mcu + skip_in_template: True + description: MCU Image + required: [mcu] + properties: + mcu: + type: string + title: MCU Image + description: MCU Image + template_value: m33_image.bin + format: file + + - type: object + template_title: SPL + image_identifier: spl + skip_in_template: True + description: U-Boot SPL (Secondary program loader) + required: [spl] + properties: + spl: + type: string + title: SPL + description: SPL firmware + template_value: spl.bin + format: file + + - type: object + template_title: Uboot ATF + image_identifier: atf + skip_in_template: True + description: U-Boot ATF container definition + required: [atf] + properties: + atf: + type: string + title: ATF binary + description: ARM Trusted Firmware binary file. + template_value: bl31.bin + format: file + + - type: object + template_title: Linux Kernel Image + image_identifier: kernel + skip_in_template: True + description: Linux kernel Image container definition + required: [kernel] + properties: + kernel: + type: string + title: Linux Kernel Image Binary + description: Linux kernel executable Image binary file (typically Image.bin) + template_value: Image.bin + format: file + + - type: object + template_title: Device Tree Blob + image_identifier: dtb + skip_in_template: True + description: Device Tree Blob (DTB) container definition + required: [dtb] + properties: + dtb: + type: string + title: Device Tree Blob Binary + description: Device Tree Blob (DTB) binary file containing hardware description + template_value: device-tree.dtb + format: file + + - type: object + template_title: Uboot + image_identifier: uboot + skip_in_template: True + description: U-Boot container definition + required: [uboot] + properties: + uboot: + type: string + title: U-Boot binary + description: U-Boot binary file. + template_value: u-boot.bin + format: file + + - type: object + template_title: V2X Dummy + image_identifier: v2x_dummy + skip_in_template: True + description: V2X dummy image container definition + required: [v2x_dummy] + properties: + v2x_dummy: + type: boolean + title: V2X Dummy + description: If Present, V2X dummy image will be added to Image Array Entry (no data record) + template_value: True + + - type: object + template_title: General Image Entry + image_identifier: general_image + description: General Image Entry + required: + - load_address + - entry_point + - image_type + - core_id + properties: + image_path: + type: string + title: Image path + description: + Path to image binary (absolute/relative). In case that only Image Array entry without any data image is needed, Just do not use the image path. + In case that the image size in container should be aligned differently then SPSDK do (4 bytes for ELE images, 1 byte otherwise), there is hidden option + 'image_size_alignment' where could be override image size by any custom value. + format: file + template_value: my_image.bin + image_size_alignment: + type: number + title: Image size alignment. + description: As a standard is use 1 byte in general and for ELE image 4 bytes. + template_value: 1 + skip_in_template: True + image_offset: + type: [number, string] + title: Image offset in AHAB container + description: + Offset in bytes from start of container header to beginning of the image. + Zero value means automatic placing the image with proper alignment after previous one, this is recommended + for serial_downloader mode. + In case of XiP type of AHAB image, the load_address and entry_point must correspond to this values. + Example of setting of load_address - AHAB_IMAGE_ADDRESS+IMAGE_OFFSET=LOAD_ADDRESS. + The Booting core images must be located after the other ones + format: number + template_value: 0 + default: 0 + load_address: + type: [number, string] + title: Image destination address + description: + Address the image is written to in memory (absolute address in + system memory). + format: number + template_value: "0x1FFC_0000" + entry_point: + type: [number, string] + title: Image entry point + description: + Image entry point (absolute address). Valid only for executable + image types. + format: number + template_value: "0x1FFC_0000" + image_type: + type: string + title: Image type + description: Kind of image. + template_value: executable + core_id: + type: string + title: Core ID + description: Defines the core the image is dedicated for. Not all cores are supported for all families. + template_value: cortex-m33 + is_encrypted: + type: boolean + title: Image encryption + description: Determines, whether image is encrypted or not. + template_value: false + default: false + is_image_descriptor: + type: boolean + title: Image Descriptor + description: Determines, whether image is descriptor or not. + template_value: false + default: false + boot_flags: + type: [number, string] + title: Boot flags + description: Boot flags controlling SCFW boot. + template_value: 0x00 + meta_data_start_cpu_id: + type: [number, string] + title: Start CPU ID + description: Resource ID of CPU to be started + format: number + template_value: 0 + meta_data_mu_cpu_id: + type: [number, string] + title: CPU memory unit start ID + description: Resource ID of the MU associated with the CPU + format: number + template_value: 0 + meta_data_start_partition_id: + type: [number, string] + title: Start partition ID + description: Partition ID of the partition to start + format: number + template_value: 0 + hash_type: + type: string + title: Images HASH type + description: HASH type of image. + enum: [] + template_value: sha512 + gap_after_image: + type: number + title: Size of gap + description: Size of empty gap just behind the image in AHAB container + template_value: 0 + default: 0 + skip_in_template: True + srk_table: + type: object + title: SRK Table + template_title: Configuration of AHAB SRK table + description: "SRK (Super Root key) table definition." + required: [srk_array] + properties: + flag_ca: + type: boolean + title: CA Flag + description: + "CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys. + In AHAB CA Flag only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing process itself. + This option exists only for compatibility with systems where fuses are already programmed. In most cases, this should remain false." + template_value: false + hash_algorithm: + type: string + title: Hash Algorithm + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: + &ahab_hash_algorithms [ + default, + sha256, + sha384, + sha512, + sha3_256, + sha3_384, + sha3_512, + shake_128_256, + shake_256_512, + sm3, + ] + template_value: default + rsa_exponent_legacy_size: + type: boolean + title: RSA exponent legacy size (4 bytes) + description: + "Force RSA exponent to use legacy 4-byte size instead of actual exponent size. + This option provides backward compatibility with older SPSDK versions that always used 4 bytes for RSA exponents. + Only enable this if you need compatibility with containers generated by older SPSDK versions." + template_value: false + default: false + skip_in_template: true + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK records. All SRKs must be of the same + type. Supported signing algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: + sha256, sha384, sha512, sha3_256, sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, + rsa2048, rsa4096, dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just + in new type of AHAB container" + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + srk_table_#2: + type: object + title: Second SRK Table + template_title: Configuration of AHAB SRK table in case that the double signing (ECC + PQC) + required: [srk_array] + skip_in_template: True + properties: + flag_ca: + type: boolean + title: CA Flag + description: + "CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. + In AHAB CA Flag only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing process itself. + This option exists only for compatibility with systems where fuses are already programmed. In most cases, this should remain false." + template_value: false + hash_algorithm: + type: string + title: Hash Algorithm + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: *ahab_hash_algorithms + template_value: default + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK Dilithium records. All SRKs must be of the same + type. Supported signing algorithms are: Dilithium level 3. Supported hash algorithms: + sha3_256, sha3_384, sha3_512. Certificate may be of Certificate Authority." + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + + certificate: + type: string + title: The AHAB certificate + template_title: Optional configuration of AHAB Container Certificate (if not used, erase the section) + description: + The file that contains AHAB certificate. It could be used already prepared binary form signed by SRK, or it is possible to + use configuration YAML file of certificate and the AHAB export process it will export it itself. + format: file + template_value: my_ahab_certificate.bin + + blob: + type: object + title: Encryption blob + description: Encryption blob container definition + template_title: Optional configuration of AHAB Container Encryption blob (if not used, erase the section) + required: [key_identifier, dek_key_size, dek_key] + properties: + key_identifier: + type: [number, string] + title: Key identifier + description: The key identifier that has been used to generate DEK keyblob. + format: number + template_value: 0 + dek_key_size: + type: [number, string] + title: DEK key size + description: Data Encryption key size. Used for AES CBC-MAC (128/192/256 size) + enum: [128, 192, 256] + format: number + template_value: 128 + dek_key: + type: string + title: DEK key + description: Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted + template_value: my_dek_key.txt + format: file-or-hex-value + dek_keyblob: + type: string + title: DEK keyblob + description: Wrapped Data Encryption key. Used for AES CBC-MAC (128/192/256 size). The HEX format is accepted. If NOT used, the empty keyblob is inserted into container and need to be updated later. + template_value: my_wrapped_key.txt + format: file-or-hex-value + +ahab_certificate: + type: object + title: Configuration of AHAB Container Certificate + description: Certificate container definition." + required: [public_key_0, permissions, signer_0] + properties: + permissions: + type: array + title: Certificate permissions + description: Permissions used to indicate what a certificate can be used for + items: + type: string + enum: + - container + - debug + - secure_fuse + - return_life_cycle + - patch_fuses + template_value: + - container + - debug + permission_data: + type: [number, string] + title: Permission data + description: (Optional) Complementary information for debug auth feature 96-bits + format: number + template_value: "0x00001111aaaabbbb22223333" + uuid: + type: string + title: Device UUID + description: Optional 128-bit IETF RFC4122 compliant non-sequential Universally Unique Identifier (UUID) + format: hex_value + template_value: "00000000000000000000000000000000" + fuse_version: + type: [number, string] + title: Fuse/PFR monotonic counter version + description: | + The fuse version serves as a monotonic counter for anti-rollback protection, but its exact + implementation and validation mechanism depends on the target device type and certification purpose. + + **For MPU devices (i.MX series):** + The fuse version is compared against a monotonic counter implemented directly in hardware fuses. + The value must be equal to or greater than the version stored in fuses to allow loading this container. + + **For MCU devices (e.g., MCXN556S):** + The fuse version validation depends on the specific feature being certified: + + - **Debug Authentication:** The fuse version is validated against the monotonic counter + "Vendor usage" located in the CFPA (Customer Field Programmable Area) PFR page. + + - **Bootable Image Certification:** The fuse version is validated against the + IMAGE_KEY_REVOCATION_ID, which is a combination of both CFPA and OTP fuse data: + `CFPA.IMAGE_KEY_REVOKE[23:0] | OTP.IMAGE_KEY_REVOKE[7:0] << 24` + This creates a 32-bit revocation ID where the lower 24 bits come from CFPA and + the upper 8 bits come from OTP fuses. + + **Note:** Despite these different validation mechanisms across device types and use cases, + a single "fuse_version" field name is used for consistency and simplicity in the configuration + schema, as all scenarios serve the same fundamental purpose of preventing rollback attacks + through monotonic counter validation. + format: number + template_value: 0 + public_key_0: + type: string + title: Certificate public key 0 + description: Path to Public key 0 file. + format: file + template_value: my_cert_public_key0.pem + signer_0: + type: string + title: Signer 0 + description: Signature provider configuration in format 'type=;=;=' or the private key 0 used for signing the certificate container. + template_value: type=file;file_path=my_prv_key0.pem + hash_algorithm_0: + type: string + title: Hash Algorithm 0 + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: *ahab_hash_algorithms + template_value: default + + public_key_1: + type: string + title: Certificate public key 1 + description: Path to Public key 1 file. + format: file + template_value: my_cert_public_key1.pem + signer_1: + type: string + title: Signer 1 + description: Signature provider configuration in format 'type=;=;=' or the private key 1 used for signing the certificate container. + template_value: type=file;file_path=my_prv_key0.pem + hash_algorithm_1: + type: string + title: Hash Algorithm 1 + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: *ahab_hash_algorithms + template_value: default diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bca.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bca.yaml new file mode 100644 index 0000000..1ea9214 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bca.yaml @@ -0,0 +1,14 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +bca: + type: object + properties: + bca: + type: object + title: Settings of BCA + description: BCA settings. + # properties will be added in runtime + + required: [bca] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bee.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bee.yaml new file mode 100644 index 0000000..a816596 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bee.yaml @@ -0,0 +1,149 @@ +# Copyright 2022-2023,2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +bee_output: + type: object + title: Basic Settings + properties: + output_folder: + type: string + title: BEE output folder + description: Folder name to store generated BEE output + template_value: bee_output + + output_name: + type: string + title: Output binary file name + description: File name of the encrypted file, output_folder/output_name or full path (.bin will be appended) + template_value: "encrypted" + + header_name: + type: string + title: File name of the exported BEE region headers + description: output_folder/header_name or full path + index will be appended (.bin will be appended) + template_value: "bee_ehdr" + + # Add data_blobs configuration similar to OTFAD + data_blobs: + type: array + title: Data blobs list + description: List of all data blobs to be encrypted + items: + type: object + required: [data, address] + properties: + data: + type: string + title: Plain Text data blob + description: Path to binary file with plain text data to be encrypted + format: file + template_value: my_data.bin + + address: + type: [number, string] + title: Data blob address + description: Data blob address where the data should be loaded + format: number + template_value: "0x60001000" + + required: [output_folder] +bee: + type: object + title: BEE Settings + required: [engine_selection, engine_key_selection, bee_engine] + properties: + engine_selection: + type: string + title: Engine selection + description: BEE Engine Selection, engine0, engine1 or both engines + enum: ["engine0", "engine1", "both"] + template_value: "engine0" + + engine_key_selection: + type: string + title: Engine Key selection + description: Random Key or Zero key + enum: ["random", "zero"] + template_value: "random" + + bee_engine: + title: Bee engines + description: Configuration of BEE engines + type: array + minItems: 1 + maxItems: 2 + items: + oneOf: + - type: object + title: Engine Config + description: BEE engine configuration + required: [bee_cfg] + properties: + bee_cfg: + type: object + required: [user_key] + properties: + user_key: + type: [string, number] + title: User AES-128 key + description: AES key for encryption + format: number + template_value: "0x0123456789abcdeffedcba9876543210" + + # aes_mode: + # type: string + # title: AES mode + # description: AES mode - counter or ECB + # enum: ["CTR", "ECB"] + # template_value: "CTR" + + protected_region: + title: Protected region + description: List of protected regions, up to four regions + type: array + items: + type: object + required: [start_address, length, protected_level] + properties: + start_address: + type: [string, number] + title: Start address of protected region + description: Start address of protected region, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x60001000" + + length: + type: [string, number] + title: Length of protected region + description: Length of protected region, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x4400" + + protected_level: + type: number + title: Protected level + description: Protected level (0/1/2/3), 0 is default + format: number + template_value: 0 + - type: object + title: Engine BinConfig + description: BEE engine configuration with binary header + required: [bee_binary_cfg] + properties: + bee_binary_cfg: + type: object + required: [header_path, user_key] + properties: + header_path: + type: string + title: BEE header path + description: Path to the existing BEE header in binary form + template_value: bee_ehdr0.bin + + user_key: + type: [string, number] + title: User AES-128 key + description: AES key that was used for header encryption + format: number + template_value: "0x0123456789abcdeffedcba9876543210" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_binary.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_binary.yaml new file mode 100644 index 0000000..99cde3e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_binary.yaml @@ -0,0 +1,113 @@ +# Copyright 2021-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +type: object +required: [name, regions] +properties: + name: + type: string + title: Image name + description: The optional image name used just during prints to console during merging. + template_value: My super binary image + size: + type: [string, number] + title: Overall size of image + description: The overall size of merged image. If the size of merged blocks exceeds this size the merge failed, otherwise the merged blocks will be padded with defined pattern. + format: number + template_value: 1024 + pattern: + title: Pattern defined as number or special values + description: > + The pattern that will be used to fill up gaps between defined regions. String or number or choose from predefined patterns - [rand, zeros, ones, inc] + - any number pattern: The defined number pattern, that will be repeated to fill up gaps between blocks. + - rand: Random pattern + - zeros: The zeros pattern 0x0000000.... + - ones: The 'ones' pattern 0xfffffff.... + - inc: The byte incremental pattern 0x00010203.....fdfeff00010203.... + template_value: zeros + oneOf: + - type: [string, number] + format: number + - type: string + enum: [rand, zeros, ones, inc] + alignment: + type: [string, number] + title: Regions alignment + description: The region alignment that will be used in case that offset is not specified. + format: number + template_value: 1 + regions: + type: array + title: Array of defined binary regions + description: The array of individual regions to merge into final image. + template_title: Binary images to merge + items: + oneOf: + - type: object + required: [binary_file] + properties: + binary_file: + type: object + title: Binary file + required: [path] + properties: + name: + type: string + title: Image name + description: The optional image name used just during prints to console during merging. + template_value: My super binary image + path: + type: string + title: Binary file + description: The path to binary file to merge into final image + format: file + template_value: my_binary_to_merge.bin + offset: + type: [string, number] + title: Offset of image in merged block + description: The offset of image to be merged on. The offset could be also negative - for example to 'erase' security bit from address. + In case that offset definition is omitted, the block will be placed after previous one with defined alignment. + format: number + template_value: 1024 + - type: object + required: [binary_block] + properties: + binary_block: + type: object + title: Binary block + required: [pattern, size] + properties: + name: + type: string + title: Image name + description: The optional image name used just during prints to console during merging. + template_value: My super binary block + size: + type: [string, number] + title: Binary block size + description: The size of binary block + format: number + template_value: 0x200 + offset: + type: [string, number] + title: Offset of binary block in merged block + description: The offset of binary block to be merged on. The offset could be also negative. + In case that offset definition is omitted, the block will be placed after previous one with defined alignment. + format: number + template_value: 1024 + pattern: + title: Pattern defined as number or special values + description: > + The pattern that will be used to fill up binary block. Number or choose from predefined patterns - [rand, zeros, ones, inc] + - any number pattern: The defined number pattern, that will be repeated to fill up binary block. + - rand: Random pattern + - zeros: The zeros pattern 0x0000000.... + - ones: The 'ones' pattern 0xfffffff.... + - inc: The byte incremental pattern 0x00010203.....fdfeff00010203.... + template_value: zeros + oneOf: + - type: [string, number] + format: number + - type: string + enum: [rand, zeros, ones, inc] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bootable_image.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bootable_image.yaml new file mode 100644 index 0000000..4152b39 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_bootable_image.yaml @@ -0,0 +1,277 @@ +# Copyright 2022-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +memory_type: + type: object + required: [memory_type] + properties: + memory_type: + type: string + title: Memory type + description: Specify type of memory used by bootable image description. + template_value: flexspi_nor + +init_offset: + properties: + init_offset: + type: [number, string] + format: number + title: Initial segment + description: The segment name or the index of initial segment in exported image + template_value: 0 + +output_definition: + properties: + output: + type: string + title: Output file name + description: Bootable image output file name + format: file_name + template_value: bootable_image.bin + output_format: + type: string + title: Output file format + description: Output file format for Bootable image + enum: [bin, hex, srec, sparse] + template_value: bin + +keyblob: + title: Bootable Segments definition + properties: + keyblob: + type: string + format: optional_file + title: Key Blob block path + description: Key blob block path + template_value: keyblob.bin + +fcb: + title: Bootable Segments definition + properties: + fcb: + type: string + title: FCB block path + format: optional_file + description: + Flash Configuration block Image path. It could be used as pre-prepared binary form of FCB and also YAML configuration file for FCB. + In case that YAML configuration file is used, the Bootable image tool build the FCB itself. + template_value: fcb.bin + +image_version: + title: Bootable Segments definition + properties: + image_version: + type: [number, string] + title: Image version + format: number + description: Image version + template_value: 0x00 + +image_version_ap: + title: Bootable Segments definition + properties: + image_version: + type: [number, string] + title: Image version + format: number + description: Image version + template_value: 0x00 + +keystore: + title: Bootable Segments definition + properties: + keystore: + type: string + format: optional_file + title: Key Store block path + description: Key store block path + template_value: keystore.bin + +bee_header_0: + title: Bootable Segments definition + properties: + bee_header_0: + type: string + title: BEE encryption header 0 + format: optional_file + description: BEE encryption header 0 path + template_value: bee_header_0.bin + +bee_header_1: + title: Bootable Segments definition + properties: + bee_header_1: + type: string + title: BEE encryption header 1 + format: optional_file + description: BEE encryption header 1 path + template_value: bee_header_1.bin + +xmcd: + title: Bootable Segments definition + properties: + xmcd: + type: string + title: XMCD block path + format: optional_file + description: + External Memory Configuration Data Segment Image path. It could be used as pre-prepared binary form of XMCD and also YAML configuration file for XMCD. + In case that YAML configuration file is used, the Bootable image tool build the XMCD itself. + template_value: xmcd.bin + +mbi: + title: Executable Segment definition + properties: + mbi: + type: string + format: file + title: Master Boot Image + description: + Master Boot Image path. It could be used as pre-prepared binary form of MBI and also YAML configuration file for MBI. + In case that YAML configuration file is used, the Bootable image tool build the MBI itself. + template_value: mbi.bin + application: + type: string + format: file + title: Application + description: Application image path + template_value: application.yaml + skip_in_template: True + +hab_container: + title: Executable Segment definition + properties: + hab_container: + type: string + title: HAB container + format: file + description: + HAB container image path. It could be used as pre-prepared binary form of HAB and also YAML configuration file for HAB. + In case that YAML configuration file is used, the Bootable image tool build the HAB itself. + template_value: hab_container.yaml + +ahab_container: + title: Executable Segment definition + properties: + ahab_container: + type: string + title: AHAB container + format: file + description: + AHAB container image path. It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. + In case that YAML configuration file is used, the Bootable image tool build the AHAB itself. + template_value: ahab_container.yaml + +primary_image_container_set: + title: Primary Executable Segment definition + properties: + spl: + type: string + title: Primary Image Container Set + format: file + description: + This is primary Image Container Set that is validated by ROM and usually contains DDR initialization and SPL code. + It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. + In case that YAML configuration file is used, the Bootable image tool build the AHAB itself. + template_value: spl.yaml + primary_image_container_set: + type: string + title: Primary Image Container Set + format: file + description: + This is primary Image Container Set that is validated by ROM and usually contains DDR initialization and SPL code. + It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. + In case that YAML configuration file is used, the Bootable image tool build the AHAB itself. + template_value: spl.yaml + skip_in_template: True + +secondary_image_container_set: + title: Secondary Executable Segment definition + properties: + uboot: + oneOf: + - type: string + title: Secondary Image Container Set + format: file + description: > + This is secondary AHAB image that is validated by SPL from primary image. + It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. + In case that YAML configuration file is used, the Bootable image tool build the AHAB itself. + template_value: uboot.yaml + - type: object + title: Secondary Image Container Set with custom offset + properties: + path: + type: string + title: Secondary Image Container Set path + format: file + description: > + Path to the secondary AHAB image that is validated by SPL from primary image. + offset: + type: [number, string] + title: Custom offset + format: number + description: Custom offset for the secondary image container set + required: ["path"] + skip_in_template: True + secondary_image_container_set: + skip_in_template: True + oneOf: + - type: string + title: Secondary Image Container Set + format: file + description: > + This is secondary AHAB image that is validated by SPL from primary image. + It could be used as pre-prepared binary form of AHAB and also YAML configuration file for AHAB. + In case that YAML configuration file is used, the Bootable image tool build the AHAB itself. + template_value: uboot.yaml + - type: object + title: Secondary Image Container Set with custom offset + properties: + path: + type: string + title: Secondary Image Container Set path + format: file + description: > + Path to the secondary AHAB image that is validated by SPL from primary image. + offset: + type: [number, string] + title: Custom offset + format: number + description: Custom offset for the secondary image container set + required: ["path"] + skip_in_template: True + +sb21: + title: Secure Binary Executable Segment definition + properties: + sb21: + type: string + title: Secure Binary v2.1 + format: file + description: + Secure Binary v2.1 image path. It could be used as pre-prepared binary form of Secure Binary v2.1 and also YAML configuration file for Secure Binary v2.1. + In case that YAML configuration file is used, the Bootable image tool build the Secure Binary v2.1 itself. + template_value: secure_binary_21.yaml + +sb31: + title: Secure Binary Executable Segment definition + properties: + sb31: + type: string + title: Secure Binary v3.1 + format: file + description: + Secure Binary v3.1 image path. It could be used as pre-prepared binary form of Secure Binary v3.1 and also YAML configuration file for Secure Binary v3.1. + In case that YAML configuration file is used, the Bootable image tool build the Secure Binary v3.1 itself. + template_value: secure_binary_21.yaml + +post_export: + title: General Options + properties: + post_export: + type: string + title: Path to directory for post export + description: Path to directory where post export artifacts like fuse scripts, keyblobs etc. will be exported + template_value: output diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_cert_block.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_cert_block.yaml new file mode 100644 index 0000000..a4d0942 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_cert_block.yaml @@ -0,0 +1,282 @@ +# Copyright 2021-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +certificate_v1: + type: object + title: Certificate V1 Settings + properties: + imageBuildNumber: + type: [number, string] + title: Image Build Number + description: If it's omitted, it will be used 0 as default value. + format: number + template_value: 0 + + chainCertificate0File0: + type: string + title: Chain certificate 0 for root 0 + description: Chain certificate 0 for root certificate 0 + format: optional_file + template_value: chain_certificate0_depth0.pem + chainCertificate0File1: + type: string + title: Chain certificate 1 for root 0 + description: Chain certificate 1 for root certificate 0 + format: optional_file + template_value: chain_certificate0_depth1.pem + chainCertificate0File2: + type: string + title: Chain certificate 2 for root 0 + description: Chain certificate 2 for root certificate 0 + format: optional_file + template_value: chain_certificate0_depth2.pem + chainCertificate0File3: + type: string + title: Chain certificate 3 for root 0 + description: Chain certificate 3 for root certificate 0 + format: optional_file + template_value: chain_certificate0_depth3.pem + + chainCertificate1File0: + type: string + title: Chain certificate 0 for root 1 + description: Chain certificate 0 for root certificate 1 + format: optional_file + template_value: chain_certificate1_depth0.pem + chainCertificate1File1: + type: string + title: Chain certificate 1 for root 1 + description: Chain certificate 1 for root certificate 1 + format: optional_file + template_value: chain_certificate1_depth1.pem + chainCertificate1File2: + type: string + title: Chain certificate 2 for root 1 + description: Chain certificate 2 for root certificate 1 + format: optional_file + template_value: chain_certificate1_depth2.pem + chainCertificate1File3: + type: string + title: Chain certificate 3 for root 1 + description: Chain certificate 3 for root certificate 1 + format: optional_file + template_value: chain_certificate1_depth3.pem + + chainCertificate2File0: + type: string + title: Chain certificate 0 for root 2 + description: Chain certificate 0 for root certificate 2 + format: optional_file + template_value: chain_certificate2_depth0.pem + chainCertificate2File1: + type: string + title: Chain certificate 1 for root 2 + description: Chain certificate 1 for root certificate 2 + format: optional_file + template_value: chain_certificate2_depth1.pem + chainCertificate2File2: + type: string + title: Chain certificate 2 for root 2 + description: Chain certificate 2 for root certificate 2 + format: optional_file + template_value: chain_certificate2_depth2.pem + chainCertificate2File3: + type: string + title: Chain certificate 3 for root 2 + description: Chain certificate 3 for root certificate 2 + format: optional_file + template_value: chain_certificate2_depth3.pem + + chainCertificate3File0: + type: string + title: Chain certificate 0 for root 3 + description: Chain certificate 0 for root certificate 3 + format: optional_file + template_value: chain_certificate3_depth0.pem + chainCertificate3File1: + type: string + title: Chain certificate 1 for root 3 + description: Chain certificate 1 for root certificate 3 + format: optional_file + template_value: chain_certificate3_depth1.pem + chainCertificate3File2: + type: string + title: Chain certificate 2 for root 3 + description: Chain certificate 2 for root certificate 3 + format: optional_file + template_value: chain_certificate3_depth2.pem + chainCertificate3File3: + type: string + title: Chain certificate 3 for root 3 + description: Chain certificate 3 for root certificate 3 + format: optional_file + template_value: chain_certificate3_depth3.pem + +certificate_v21: + type: object + title: ISK (Image signing key) Certificate Settings + properties: + useIsk: + type: boolean + title: Use ISK for signature certification + description: Enable ISK type of signature certification. + template_value: false + + signingCertificateFile: + type: string + title: ISK public key + description: Path to ISK public key. + format: file + template_value: sign_cert.pub + skip_in_template: true + iskPublicKey: + type: string + title: ISK public key + description: Path to ISK public key. + format: file + template_value: sign_cert.pub + + signingCertificateConstraint: + type: [string, number] + title: ISK certificate constraint + description: Constraint is certificate version, compared with monotonic counter in fuses. + format: number + default: 0 + template_value: 0 + skip_in_template: true + iskCertificateConstraint: + type: [string, number] + title: ISK certificate constraint + description: Constraint is certificate version, compared with monotonic counter in fuses. + format: number + default: 0 + template_value: 0 + + signCertData: + type: string + title: ISK certificate user data + description: Path to user data. + format: optional_file + template_value: user_cert_data.bin + skip_in_template: true + iskCertData: + type: string + title: ISK certificate user data + description: Path to user data. + format: optional_file + template_value: user_cert_data.bin + signer: + type: string + title: Signer configuration + description: Signature provider configuration in format 'type=;=;=' or path to a private key. + template_value: type=file;file_path=root_prv_key.pem + required: [useIsk] + allOf: # Global all of group - this is main concatenation group for all sub rules + - if: + properties: + useIsk: + const: True + then: + allOf: + - oneOf: + - required: [signingCertificateFile] + - required: [iskPublicKey] + required: [signer] + +certificate_vx: + type: object + title: ISK Certificate Settings + properties: + selfSigned: + type: boolean + title: True if certificate is self signed, false for NXP Signed certificate + description: NXP Signed = false, Self signed = true + template_value: true + signingCertificateFile: + type: string + title: ISK public key + description: Path to ISK public key. + format: file + template_value: sign_cert.pub + skip_in_template: true + iskPublicKey: + type: string + title: ISK public key + description: Path to ISK public key. + format: file + template_value: sign_cert.pub + signer: + type: string + title: Signature Provider + description: Signature provider configuration in format 'type=;=;=' a path to a Main root Certification Private Key. + template_value: type=file;file_path=root_prv_key.pem + + allOf: # Global all of group - this is main concatenation group for all sub rules + - if: + properties: + useIsk: + const: True + then: + allOf: + - oneOf: + - required: [signingCertificateFile] + - required: [iskPublicKey] + required: [signer] + +cert_block_output: + type: object + title: Basic Settings + properties: + containerOutputFile: + type: string + title: cert block filename + description: Generated cert block filename. + template_value: cert_block.bin + required: [containerOutputFile] + +certificate_root_keys: + type: object + title: Root Keys Settings + properties: + rootCertificate0File: + type: string + title: Root Certificate File 0 + description: Root certificate file index 0. + format: file + template_value: my_certificate0.pub + rootCertificate1File: + type: string + title: Root Certificate File 1 + description: Root certificate file index 1. + format: optional_file + template_value: my_certificate1.pub + rootCertificate2File: + type: string + title: Root Certificate File 2 + description: Root certificate file index 2. + format: optional_file + template_value: my_certificate2.pub + rootCertificate3File: + type: string + title: Root Certificate File 3 + description: Root certificate file index 3. + format: optional_file + template_value: my_certificate3.pub + + mainRootCertId: + type: [number, string] + title: Main Certificate Index + description: Index of certificate that is used as a main. If not defined, the certificate matching private key will be selected. + format: number + template_value: 0 + + allOf: # Global all of group - this is main concatenation group for all sub rules + - oneOf: + - required: [binaryCertificateBlock] + - allOf: + - required: [rootCertificate0File] + - anyOf: + - required: [signer] + - required: [mainRootCertId] + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_dat.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_dat.yaml new file mode 100644 index 0000000..09b7933 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_dat.yaml @@ -0,0 +1,308 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +--- +dc_content: + allOf: + - required: [signer] + - oneOf: + - required: [family] + - required: [socc] + required: + - uuid + - cc_socu + - cc_vu + - cc_beacon + - rot_meta + - rot_id + - dck + + type: object + title: Debug Credential Content + properties: + socc: + type: [string, integer] + title: Device SoC Class + description: + A unique identifier for a set of SoCs that require no SoC-specific differentiation in + their debug authentication. The main usage is to allow a different set of debug + domains and options to be negotiated between the device configuration and + credentials. A class can contain just a single revision of a single SoC model, if the + granularity of debug control warrants it. + format: number + template_value: 6 + skip_in_template: true + uuid: + type: string + title: Device UUID + description: 128-bit IETF RFC4122 compliant non-sequential Universally Unique Identifier (UUID) + format: hex_value + template_value: "00000000000000000000000000000000" + cc_socu: + type: [string, integer] + title: SoC Usage + description: + A CC (constraint) value that is a bit mask, and whose bits are used in an + SoCC-specific manner. These bits are typically used for controlling which debug + domains are accessed via the authentication protocol, but device-specific debug + options can be managed in this way also. + format: number + template_value: "0x0FFF" + cc_vu: + type: [string, integer] + title: Vendor Usage + description: + A CC (constraint) value that is opaque to the debug authentication protocol itself but + which can be leveraged by vendors in product-specific ways. + format: number + template_value: 0 + cc_beacon: + type: [string, integer] + title: Credential Beacon + description: + A value that is passed through the authentication protocol, which is not interpreted + by the protocol but is instead made visible to the application being debugged. A + credential beacon is associated with a DC and is therefore vendor/RoT-signed. An + authentication beacon is provided and signed by the debugger during the + authentication process. + format: number + template_value: 0 + rot_meta: + type: array + title: RoT meta-data + description: + The RoT meta-data required by the device to corroborate; the ROTID sent in the + DAC, the field in this DC, and any additional RoT state that is not stored within the + device. This allows different RoT identification, management and revocation + solutions to be handled. + minItems: 1 + maxItems: 4 + items: + type: string + format: file + template_value: + - ./rotk0.pub + - ./rotk1.pub + - ./rotk2.pub + - ./rotk3.pub + rot_id: + type: [string, integer] + title: RoT Identifier + description: + RoTID allows the debugger to infer which RoT public key(s) are acceptable to the + device. If the debugger cannot or does not provide such a credential, the + authentication process will fail. + minimum: 0 + maximum: 100 + format: number + template_value: 0 + dck: + type: string + title: Debug Credential Key + description: + A user-owned key pair. The public part of the key is associated with a DC, the + private part is held by the user and used to produce signatures during + authentication. + format: file + template_value: dck.pub + signer: + type: string + title: Signer + description: Signature provider configuration in format 'type=;key_number=' or a private key for the RoT meta chosen by rot_id to sign the image. + template_value: type=sasp;key_number=0 + rot_config: + type: string + format: file + title: Rot Config + description: Path to a cert block binary/cert block configuration of MBI configuration. + template_value: cert_block.yaml + skip_in_template: true + +dc_srk_ca_flag: + type: object + title: Debug Credential Signature part + properties: + flag_ca: + type: boolean + title: CA Flag + description: + "CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys. + In AHAB CA Flag only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing process itself. + This option exists only for compatibility with systems where fuses are already programmed. In most cases, this should remain false." + template_value: false + +main_note: "\nDebug credential file has following binary structure:\n + ============================================\n + ============================================\n + === Version ===\n + ============================================\n + === Soc Class ===\n + ============================================\n + === UUID ===\n + ============================================\n + === RoT Meta SHA256 of following: ===\n + === RoT Key0 SHA256 ===\n + === RoT Key1 SHA256 ===\n + === RoT Key2 SHA256 ===\n + === RoT Key3 SHA256 ===\n + ============================================\n + === Debugger Key DCK (Pub): ===\n + === ===\n + ============================================\n + === CC SOCU ===\n + ============================================\n + === CC VU ===\n + ============================================\n + === CB ===\n + ============================================\n + === RoT Key (pub) ===\n + === ===\n + ============================================\n + ============================================\n + === Signature of all block ===\n + === SHA256 of whole block => Sign(RoTK) ===\n + ============================================\n + ============================================\n + \n\n + ============================================\n + Debug Credential Signature\n + ============================================\n + There are two ways how sign the final DC data blob.\n + \n + 1. The 'signer' option is available to specify the signature provider configuration or path to a private key. \n + The 'signer' option provides a standardized interface for external signing solutions that works \n + consistently across all SPSDK applications. \n + Previous options like 'rotk' and 'sign_provider'/'signProvider' are no longer supported \n + \n + 2. For case that Debug Credential files are generated in untrusted environment (without access to RoT private keys),\n + there is option to use plugin (example how to create own plugin is in: ./SPSDK/examples/dat/hsm/). The plugin\n + has simple interface that allows handle DC data blob into plugin with index of RoT meta public key to get back signed\n + DC image.\n + \n + Those options are exclusive, so only one option could be used to sign the DC.\n + \n + " + +ele_socu: + required: + - cc_socu + + type: object + title: Debug Credential Content + properties: + cc_socu: + type: [string, integer] + title: SoC Usage + description: + A CC (constraint) value that is a bit mask, and whose bits are used in an + SoCC-specific manner. These bits are typically used for controlling which debug + domains are accessed via the authentication protocol, but device-specific debug + options can be managed in this way also. + format: number + template_value: "0x0FFF" + +ele_dc_beacon: + type: object + title: Debug Credential Content + properties: + cc_beacon: + type: [string, integer] + title: Credential Beacon + description: + A value that is passed through the authentication protocol, which is not interpreted + by the protocol but is instead made visible to the application being debugged. A + credential beacon is associated with a DC and is therefore vendor/RoT-signed. An + authentication beacon is provided and signed by the debugger during the + authentication process. + format: number + template_value: 0 + +ele_auth_beacon: + type: object + title: Debug Credential Content + properties: + beacon: + type: [string, integer] + title: Authentication beacon + description: + Debug authentication process can be extended with beacons. DEBUG_AUTH_BEACON (this field) contain + information from debug authentication after debugger is successfully authenticated. This register contain + data from Authentication beacon [31:16] which is defined during authentication session and + Credential beacon [15:0] which is defined on RoT keys owner side during debug credential file + generation and signing. + When credential beacon non-zero value is used in this field, ROM defers opening debug access to user + application. The result of the authentication process is written to DBG_FEATURES register while the + user application after doing its extended processing, such as clean-up of critical keys and secrets, should + copy the value to DBG_FEATURES_DP register to enable the debug access. + format: number + template_value: 0 + +ahab_certificate_vendor_usage: + type: object + title: Debug Credential Content + properties: + cc_vendor_usage: + type: [number, string] + title: Vendor Usage version + description: The value must be equal to VU stored in fuses to allow loading this certificate. + format: number + template_value: 0 + +ahab_debug_certificate: + type: object + properties: + certificate: + type: string + title: The AHAB Debug Certificate file + template_title: AHAB Debug Certificate + description: + The file that contains AHAB Debug Certificate. It could be used already prepared binary form signed by SRK, or it is possible to + use configuration YAML file of debug certificate. + format: file + template_value: my_ahab_dc.bin + required: [certificate] + +dat_classic: + allOf: + - required: [signer] + required: + - certificate + - beacon + + type: object + title: Debug Authentication Content + properties: + certificate: + type: string + title: Debug Credential Certificate file + description: A debug credential binary file provided by owner of Root Keys. The file could be created by 'dc' group of commands. + format: file + template_value: dc.bin + beacon: + type: [string, integer] + title: Authentication beacon + description: + Debug authentication process can be extended with beacons. DEBUG_AUTH_BEACON (this field) contain + information from debug authentication after debugger is successfully authenticated. This register contain + data from Authentication beacon [31:16] which is defined during authentication session and + Credential beacon [15:0] which is defined on RoT keys owner side during debug credential file + generation and signing. + When credential beacon non-zero value is used in this field, ROM defers opening debug access to user + application. The result of the authentication process is written to DBG_FEATURES register while the + user application after doing its extended processing, such as clean-up of critical keys and secrets, should + copy the value to DBG_FEATURES_DP register to enable the debug access. + format: number + template_value: 0 + srk_set: + type: string + title: Keys set + description: Selection of keys origin. + enum: [oem, nxp] + default: oem + template_value: oem + signer: + type: string + title: Signer + description: Signature provider configuration in format 'type=;key_number=' or a Private key that match the public key in debug credential file, to sign Debug Authentication response. + template_value: type=sasp;key_number=0 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_devhsm.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_devhsm.yaml new file mode 100644 index 0000000..230dde8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_devhsm.yaml @@ -0,0 +1,122 @@ +# Copyright 2021-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +common: + type: object + title: Common DevHSM settings + if: + properties: oemEncMasterShare + then: + required: [oemRandomShare] + + required: [containerOutputFile] + properties: + oemRandomShare: + type: string + title: OEM Random Share input + description: > + Path to a file containing 16B of random seed data. If not specified, random seed will be generated. In case that 'oemEncMasterShare' is defined, the 'oemRandomShare' + must be defined with the original random seed that has been used to create OEM Encrypted master share. + template_value: oem_seed.bin + format: optional_file + oemEncMasterShare: + type: string + title: OEM Encrypted Master Share + description: Path to a file containing encrypted OEM Master Share to restore a secure session + template_value: oem_enc_master_share.bin + format: optional_file + oemEncShare: + type: string + title: OEM Encrypted Share + description: Path to a file containing encrypted OEM Share to restore a secure session + template_value: oem_enc_share.bin + format: optional_file + initialReset: + type: boolean + title: Initial device reset + description: Reset the device before starting the DevHSM operation + template_value: false + finalReset: + type: boolean + title: Final device reset + description: Reset the device after the DevHSM operation + template_value: true + workspace: + type: string + title: Development/debug workspace + description: Path to a folder where to store intermediate artifacts for development/debugging purposes + template_value: wsp + format: dir_name + bufferAddress: + type: [string, number] + format: number + title: Communication buffer address + description: Address to override default communication buffer address + template_value: + containerOutputFile: + type: string + title: Output file path + description: Path where to store generated DevHSM SB file + template_value: devhsm.sb + format: file_name + +cust_mk_sk: + type: object + properties: + containerKeyBlobEncryptionKey: + type: string + title: Part Common Key + description: Path to PCK/NPK/CUST_MK_SK/SB_KEK 256 or 128 bit key in plain hex string format or path to binary file or hex string. + template_value: cust_mk_sk.bin + format: file-or-hex-value + +subTitle: | + # ================================= Minimal steps to perform DevHSM Trust Provisioning ================================= + commands: + +programLifeCycleFuse: >2 + # Advance Life-cycle to Production + - programFuses: + address: {address} + values: {value:#_x} + +loadCMPA: >2 + # Load CMPA + - load: + address: {address:#_x} + file: cmpa.bin + +loadCFPA: >2 + # Load CFPA + - load: + address: {address:#_x} + file: cfpa.bin + +loadKeyBlob: >2 + # In case you have the encryption key in plain (set via containerKeyBlobEncryptionKey) + # a default loadKeyBlob command will be injected automatically + # However, if you'd like to customize the command, use the following command. + # Please note the `plainInput` parameter + # - loadKeyBlob: + # offset: {offset:#_x} + # wrappingKeyId: NXP_CUST_KEK_EXT_SK + # file: cust_mk_sk.bin + # plainInput: bin + # + # if you already have a wrapped encryption key use loadKeyBlob command + # you may wrap the key using `nxpdevhsm wrap-cust-mk-sk` command + # in such case comment-out the `containerKeyBlobEncryptionKey` field + # - loadKeyBlob: + # offset: {offset:#_x} + # wrappingKeyId: NXP_CUST_KEK_EXT_SK + # file: wrapped_key_blob.bin + # + +writeIFR: >2 + # Write IFR command - IMPORTANT: This command must ALWAYS be placed after loadKeyBlob + # This command instructs the ROM to write the generated key blob to the flash + # The type must be set to CFPA_AND_CMPA to ensure both CFPA and CMPA regions are written + # - writeIFR: + # type: CFPA_AND_CMPA + # file: ifr_data.bin diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_el2go_tp.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_el2go_tp.yaml new file mode 100644 index 0000000..fc56fe4 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_el2go_tp.yaml @@ -0,0 +1,182 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +el2go_tp: + type: object + properties: + url: + type: string + title: EdgeLock 2GO API URL + description: Base URL of the EdgeLock 2GO backend API without an / at the end + template_value: https://api.edgelock2go.com + api_key: + type: string + title: EdgeLock 2GO API Key + description: "REST API key used for user authentication in EdgeLock 2GO. + You may use: + 1) path to a file with the key on the first line: ~/.el2go/wpc_token.txt (~ is interpreted as your HOME) + 2) environment variable with the key: $MY_EL2GO_KEY + 3) environment variable containing a path to the key file: $MY_KEY_FILE + 4) directly your API key in plain text (not recommended)" + template_value: abcxyz123 + device_group_id: + type: number + title: Device Group ID + description: Device Group ID in which the connected secure element needs to be assigned + template_value: 49 + nc12: + type: number + title: Product 12NC + description: Product 12NC registered in EdgeLock 2GO + template_value: 123456789012 + domains: + type: array + title: Secure Objects Domains + description: List of the EdgeLock 2GO Secure Objects Domains to download. + items: + type: string + enum: [RTP, MATTER] + template_value: [RTP, MATTER] + enum_template: [RTP, MATTER] + delay: + type: number + title: Delay between EdgeLock 2GO's API calls + description: Delay in seconds between EdgeLock 2GO API requests regarding Secure Objects generation status. Default value is 5 seconds + template_value: 5 + timeout: + type: number + title: Timeout for EdgeLock 2GO API + description: Timeout in seconds of downloading Secure Objects through EdgeLock 2GO API operation. Default is 60 seconds + template_value: 60 + download_timeout: + type: number + title: Download Timeout + description: Timeout for overall download process including waiting for Secure Objects creation + template_value: 300 + + required: [api_key, device_group_id, nc12] + +prov_fw_path: + properties: + prov_fw_path: + type: string + format: file + title: NXP EL2GO Provisioning FW path + description: Path to NXP EL2GO Provisioning Firmware SB file. If you don't want to use the Provisioning FW, please comment out the line below + template_value: oem_tp_fw.sb + required: [] + +uboot_path: + properties: + uboot_path: + type: string + format: optional_file + title: Path to U-Boot binary + description: Path to U-Boot binary that will be used for writing assets to EMMC/SD + template_value: u-boot.bin + skip_in_template: True + +imx_bootloader_path: + properties: + imx_bootloader_path: + type: string + format: optional_file + title: Path to imx-bootloader + description: Path to imx-bootloader binary that will be used for writing assets to EMMC/SD. This bootloader will be loaded using the SDPS protocol as part of the preparation step. + template_value: flash.bin + +fw_load_address: + properties: + fw_load_address: + type: number + title: Address for loading the Provisioning Firmware + description: Address where to store the Provisioning Firmware. + Please note, that if you're using external memory, you have to configure the memory first. + template_value: 1234 + required: ["fw_load_address"] + +additional_data_address: + properties: + secure_objects_address: + type: number + title: Address for External (user-defined) Secure Objects + description: + Address where to store External (user-defined) Secure Objects obtained from EL2GO. + External Secure Objects refers to Secure Objects other than OEM FW Authentication Key Hash, and OEM FW Decryption Key. + Please note that the FW will always erase 8K memory block (flash page size) in the destination address, + so any data previously stored at that flash location will be gone. + If you don't use any External Secure Objects, this setting has no effect + template_value: 123456 + required: ["secure_objects_address"] + +secure_objects_address: + properties: + secure_objects_address: + type: number + title: Secure Objects address + description: Address where to store Secure Objects obtained from EL2GO. + Please note, that if you're using external memory, you have to configure the memory first. + template_value: 123456 + required: ["secure_objects_address"] + +prov_report_address: + properties: + prov_report_address: + type: number + title: Trust Provisioning Report address + description: + Address where to put the provisioning report. If you don't want to store TP Report in memory, + leave the address empty, or comment out this setting, or set to 0xFFFF_FFFF. + template_value: 0xFFFF_FFFF + required: [] + +fatwrite: + properties: + fatwrite_filename: + type: string + title: Filename of the secure objects stored in partition + description: Filename of the secure objects stored in partition. Passed to U-Boot fatwrite command. + template_value: secure_objects.bin + default: secure_objects.bin + fatwrite_interface: + type: string + title: Interface for storing the secure objects + description: Interface for storing the secure objects, passed to U-Boot fatwrite command. + template_value: mmc + default: mmc + fatwrite_device_partition: + type: string + title: Device and partition for writing the secure objects. + description: Device and partition for writing the secure objects, separated by colon. Passed to U-Boot fatwrite command. Enclose in quotes. + template_value: "0:1" + default: "0:1" + oem_provisioning_config_filename: + type: string + title: Filename of the configuration file for OEM Provisioning App + description: Filename of the configuration file for OEM Provisioning App that will be stored in partition together with the secure objects. + template_value: config.yaml + default: config.yaml + +linux_boot: + properties: + boot_linux: + type: boolean + title: Boot Linux + description: Boot Linux after provisioning + template_value: true + default: true + linux_boot_sequence: + type: array + title: Linux boot sequence + description: List of UUU commands to execute to boot Linux + items: + type: string + template_value: + [ + "setenv mmcdev 0", + "setenv mmcpart 1", + "setenv mmcroot /dev/mmcblk0p2 rootwait rw", + "run loadimage", + "run loadfdt", + "run bsp_bootcmd", + ] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcb.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcb.yaml new file mode 100644 index 0000000..17a611d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcb.yaml @@ -0,0 +1,25 @@ +# Copyright 2022-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +memory_type: + type: object + required: [type] + properties: + type: + type: string + title: Memory type + description: Specify type of memory used by FCB description. + # enum: [flexspi_nor] This field will be added in run time + template_value: flexspi_nor + +fcb: + type: object + properties: + fcb_settings: + type: object + title: Settings of FCB + description: Flash Configuration settings for selected MCU. + # properties will be added in runtime + + required: [fcb_settings] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcf.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcf.yaml new file mode 100644 index 0000000..03da6ea --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fcf.yaml @@ -0,0 +1,14 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +fcf: + type: object + properties: + fcf: + type: object + title: Settings of FCF + description: FCF settings. + # properties will be added in runtime + + required: [fcf] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fuses.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fuses.yaml new file mode 100644 index 0000000..47b7273 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_fuses.yaml @@ -0,0 +1,11 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +fuses: + type: object + required: [registers] + properties: + registers: + type: object + title: Fuses Settings diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_general.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_general.yaml new file mode 100644 index 0000000..6f5f642 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_general.yaml @@ -0,0 +1,20 @@ +# Copyright 2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +--- +family: + type: object + required: + - family + properties: + family: + type: string + title: The chip family name + description: + NXP chip family identifier. + template_value: mimxrt1189 + revision: + type: string + title: MCU revision + description: Revision of silicon. The 'latest' name, means most current revision. + template_value: latest diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hab.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hab.yaml new file mode 100644 index 0000000..ce62c6f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hab.yaml @@ -0,0 +1,559 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +hab_input: + type: object + title: HAB Input + properties: + inputImageFile: + type: string + title: Plain application image + description: The input application image in plain BIN, S-REC or ELF. + format: file_name + template_value: my_application.bin + required: ["inputImageFile"] + +hab: + type: object + required: [options] + properties: + options: + type: object + title: HAB Options + description: An options block contains zero or more name/value pairs and the option settings that assign values to global options used by the nxpimage to control the generation of the output file. + allOf: + - required: [family, flags, startAddress] + - oneOf: + - required: [ivtOffset, initialLoadSize] + - required: [bootDevice] + properties: + flags: + type: + - number + - string + title: HAB flags + description: HAB flags. 0x0 for unsigned, 0x08 signed, 0x0C encrypted. + template_value: 0x8 + startAddress: + type: + - number + - string + title: Image start address + description: "First address of the bootable image in the target memory." + template_value: 0x60000000 + ivtOffset: + type: + - number + - string + title: IVT Offset + description: "Offset of IVT table(beginning of HAB container) from startAddress. This option can be omitted if family and bootDevice are specified." + template_value: 0x1000 + initialLoadSize: + type: + - number + - string + title: Initial Load size + description: "Size of the segments(such as IVT, BDT, DCD, XMCD) placed before the actual application image. The value is specific per boot device type. This option can be omitted if family and bootDevice are specified." + template_value: 0x2000 + entryPointAddress: + type: + - number + - string + title: Entry Point address + description: "Reset vector of the application. If not specified, the vector will be automatically detected from the input image." + template_value: 0x800041f5 + family: + type: string + title: Family + description: "Processor family" + template_value: mimxrt1010 + bootDevice: + type: string + title: Boot device + description: "Boot device memory where the image is booted from. If not specified, the ivtOffset and initialLoadSize must be defined." + template_value: flexspi_nor + signatureTimestamp: + type: string + title: Timestamp of the signature + description: "Date and time when the signature was created. Format: day/month/year hour:minute:second (DD/MM/YYYY HH:MM:SS)" + template_value: "31/05/2023 11:22:33" + DCDFilePath: + type: string + title: DCD file path + description: "Optional path to DCD data." + template_value: "dcd.bin" + XMCDFilePath: + type: string + title: XMCD file path + description: "Optional path to XMCD data." + template_value: "xmcd.bin" + +hab_sections: + type: object + title: CSF Sections + properties: + sections: + type: array + title: CSF Sections + description: CSF Sections. + items: + oneOf: + - type: object + required: + - Header + properties: + Header: + type: object + title: Header + description: >- + The Header command contains data used in the CSF header as well as default values used by the CST for other commands throughout the remaining CSF. + There must be exactly one Header command and it must appear first in the CSF. + properties: + Header_Version: + type: + - string + - number + title: Version + description: Version of HAB. + template_value: "4.2" + Header_HashAlgorithm: + type: + - string + title: Hash algorithm + description: Default hash algorithm. + template_value: "sha256" + enum: ["sha256"] + Header_Engine: + type: string + title: Engine + description: Default engine. + template_value: "ANY" + enum: + - ANY + - SAHARA + - RTIC + - DCP + - CAAM + - SW + Header_EngineConfiguration: + type: + - string + - number + title: Engine configuration + description: Default engine configuration. See the CST manual for more info. + template_value: 0 + Header_CertificateFormat: + type: + - string + title: Certificate format + description: Default certificate format. + template_value: "x509" + enum: + - x509 + - WTLS + Header_SignatureFormat: + type: + - string + - number + title: Signature format + description: Default signature format. + template_value: "CMS" + enum: + - PKCS1 + - CMS + required: + - Header_Version + - type: object + required: + - InstallSRK + properties: + InstallSRK: + type: object + title: Install SRK + description: >- + The Install SRK command authenticates and installs the root public key for use in subsequent Install CSFK (HAB only) or Install Key (HAB4 only) commands. + HAB or AHAB authenticates the SRK using the SRK hash (SRK_HASH) fuses. HAB4 or AHAB allows revocation of individual keys within the SRK table using the SRK revocation (SRK_REVOKE) fuses. + HAB installs the SRK in slot 0 of its internal public key store. + There must be exactly one Install SRK command in a CSF, and it must occur before the Install + CSFK (HAB only) command. + properties: + InstallSRK_Table: + type: string + title: SRK table binary file + description: Valid file path + template_value: "srk_table.bin" + InstallSRK_SourceIndex: + type: number + title: InstallSRK SourceIndex + description: SRK index within SRK table. Installation fails if the SRK revocation fuse with this index is burned. + enum: + - 0 + - 1 + - 2 + - 3 + template_value: 0 + required: + - InstallSRK_Table + - InstallSRK_SourceIndex + - type: object + required: + - InstallCSFK + properties: + InstallCSFK: + type: object + title: Install CSFK + description: + The Install CSFK command authenticates and installs a public key for use in subsequent Install Key (HAB3 only) or Authenticate CSF commands. + HAB authenticates the CSFK from the CSFK certificate using the SRK. + HAB installs the CSFK in slot 1 of its internal public key store. + There must be exactly one Install CSFK command in a CSF, and it must occur before the Authenticate CSF command. + properties: + InstallCSFK_File: + type: string + title: CSFK Certificate + description: Valid path. + template_value: "csf.der" + InstallCSFK_CertificateFormat: + type: string + title: Certificate Format + description: CSFK certificate format. + enum: + - x509 + - WTLS + template_value: x509 + required: + - InstallCSFK_File + - type: object + required: + - InstallNOCAK + properties: + InstallNOCAK: + type: object + title: Install NOCAK + description: + The Install NOCAK command authenticates and installs a public key for use with the fast authentication mechanism (HAB 4.1.2 and later only). With this mechanism, one key is used for all signatures. + HAB installs the no-CA key in slot 1 of its internal public key store. + There must be exactly one Install NOCAK command in a CSF, and it must occur before the Authenticate CSF command and there must be no Install Key commands. + properties: + InstallNOCAK_File: + type: string + title: NOCAK Certificate + description: Valid path. + template_value: "srk.pem" + InstallNOCAK_CertificateFormat: + type: string + title: Certificate Format + description: NOCAK certificate format. + enum: + - x509 + - WTLS + template_value: x509 + required: + - InstallNOCAK_File + - type: object + required: + - AuthenticateCSF + properties: + AuthenticateCSF: + type: object + title: Authenticate CSF + description: + The Authenticate CSF command authenticates the CSF from which it is executed. + HAB authenticates the CSF using the CSFK public key, from a digital signature generated automatically by the CST. + There must be exactly one Authenticate CSF command in a CSF file, and it must occur after the Install CSFK command. Most other CSF commands are allowed only after the Authenticate CSF command. + properties: + AuthenticateCSF_EngineConfiguration: + type: + - string + - number + title: Engine configuration + description: Default engine configuration. See the CST manual for more info. + template_value: 0 + AuthenticateCSF_CertificateFormat: + type: + - string + title: Certificate format + description: Default certificate format. + template_value: "x509" + enum: + - x509 + - WTLS + AuthenticateCSF_SignatureFormat: + type: + - string + - number + title: Signature format + description: Default signature format. + template_value: "CMS" + enum: + - PKCS1 + - CMS + Signer: + type: + - string + title: Signer + description: Signature provider configuration string or a path to authenticate CSF private key file. + template_value: "type=file;file_path=keys/CSF1_1_sha256_2048_65537_v3_usr_key.pem;password=PrivateKeyPwd" + - type: object + required: + - InstallKey + properties: + InstallKey: + type: object + title: Install Key + description: + The Install Key command authenticates and installs a public key for use in subsequent Install Key or Authenticate Data commands. + HAB authenticates a public key from a public key certificate using a previously installed verifying key and a hash of the public key certificate. + HAB installs the authenticated public key in an internal public key store with a zero-based array of key slots. + The CSF author is responsible for managing the key slots in the internal public key store to establish the desired public key hierarchy and determine the keys used in authentication operations. Overwriting occupied key slots is not allowed, although a repeat command to re- install the same public key occupying the target slot will be skipped and not generate an error. + properties: + InstallKey_File: + type: string + title: Public key certificate + description: Valid file path. + template_value: "imgk.pem" + InstallKey_VerificationIndex: + type: number + title: Verification Index + description: Verification key index in key store. CSFK not supported. + enum: + - 0 + - 2 + - 4 + template_value: 0 + InstallKey_TargetIndex: + type: number + title: Target Index + description: Target key index in key store. SRK, CSFK slots reserved. + enum: + - 2 + - 4 + template_value: 2 + required: + - InstallKey_File + - InstallKey_VerificationIndex + - InstallKey_TargetIndex + - type: object + required: + - AuthenticateData + properties: + AuthenticateData: + type: object + title: Authenticate Data + description: + The Authenticate Data command verifies the authenticity of pre-loaded data in memory. The data may include executable SW instructions and may be spread across multiple non-contiguous address ranges drawn from multiple object files. + HAB authenticates the pre-loaded data using a previously installed public key from a digital signature generated automatically by the CST. + properties: + AuthenticateData_VerificationIndex: + type: number + title: Verification Index + description: Verification key index in key store. SRK, CSFK not supported. NOTE For HAB4 Fast Authentication, this must be 0 + enum: + - 0 + - 2 + - 4 + template_value: 2 + AuthenticateData_Engine: + type: string + title: Engine + description: Data signature hash engine. + enum: + - ANY + - SAHARA + - RTIC + - DCP + - CAAM + - SW + template_value: ANY + AuthenticateData_EngineConfiguration: + type: + - string + - number + title: Engine Configuration + description: Configuration flags for the engine. See the CSF manual. + template_value: 0 + Signer: + type: + - string + title: Signer + description: Signature provider configuration string or a path to authenticate IMG private key file. + template_value: "type=file;file_path=keys/IMG1_1_sha256_2048_65537_v3_usr_key.pem;password=PrivateKeyPwd" + required: + - AuthenticateData_VerificationIndex + - type: object + required: + - SetEngine + properties: + SetEngine: + type: object + title: Set Engine + description: + The Set Engine command selects the default engine and engine configuration for a given algorithm. HAB3 does not support the Set Engine command. + Some CSF commands allow the CSF author to select the engine used for an algorithm by specifying an argument other than ANY. However, if the engine argument is ANY, then HAB selects the engine to use based on internal criteria. The Set Engine command overrides the HAB internal criteria and selects the engine and configuration to use when ANY is specified. + + Some algorithm types do not have an associated engine argument in the CSF commands (e.g. the signature algorithm in Authenticate Data commands). By default, HAB selects the engine to use for such algorithms based on internal criteria. The Set Engine command overrides the HAB internal criteria in such cases as well. + Multiple Set Engine commands may appear anywhere in a CSF after the Header command. Subsequent commands use the engine selected by the most recent Set Engine command + properties: + SetEngine_HashAlgorithm: + type: string + title: Hash Algorithm + description: Hash algorithm. + enum: + - sha256 + template_value: sha256 + SetEngine_Engine: + type: string + title: Engine + description: Engine, use ANY to restore internal HAB criteria. + template_value: "ANY" + enum: + - ANY + - SAHARA + - RTIC + - DCP + - CAAM + - SW + SetEngine_EngineConfiguration: + type: + - string + - number + title: Engine configuration + description: Default engine configuration. See the CST manual for more info. + template_value: 0 + required: + - SetEngine_HashAlgorithm + - SetEngine_Engine + - type: object + required: + - Unlock + properties: + Unlock: + type: object + title: Unlock + description: + The Unlock command prevents specified engine features from being locked when exiting the internal boot ROM. HAB3 does not support the Unlock command. + Multiple Unlock commands may appear after the Authenticate CSF command. A feature will be unlocked if specified in one or more Unlock commands. + properties: + Unlock_Engine: + type: string + title: Engine + description: Engine to unlock. + enum: + - SRTC + - CAAM + - SNVS + - OCOTP + template_value: OCOTP + Unlock_Features: + type: [string, array] + title: Features + description: Comma-separated list of features to unlock. + template_value: ['JTAG', 'SRK REVOKE'] + Unlock_UID: + type: [string, array] + title: Unlock UID + description: List of UIDs. + template_value: [0x1, 0x23, 0x45, 0x67] + - type: object + required: + - SecretKey + properties: + SecretKey: + type: object + title: Install Secret Key + description: This command is applicable from HAB 4.1 onwards and only on processors which include CAAM and SNVS. Each instance of this command generates a CSF command to install a secret key in CAAM's secret key store. + properties: + SecretKey_Name: + type: string + title: Key + description: CMS encrypted data encryption key. + template_value: "dek.bin" + SecretKey_Length: + type: number + title: Key length + description: Key length in bits + enum: + - 128 + - 192 + - 256 + template_value: 128 + SecretKey_VerifyIndex: + type: number + title: Verification index + description: Master KEK index. 0 or 1 OTPMK from fuses. 2 ZMK from SNVS, 3 CMK from SNVS. + enum: + - 0 + - 1 + - 2 + - 3 + template_value: 0 + SecretKey_TargetIndex: + type: number + title: Target index + description: Target secret key store index. + enum: + - 0 + - 1 + - 2 + - 3 + template_value: 0 + SecretKey_ReuseDek: + type: + - boolean + - number + title: Reuse DEK + description: If set, the secret key from SecretKey_Name parameter will be used. If not, a random key will be generated and stored. + template_value: false + required: + - SecretKey_Name + - SecretKey_TargetIndex + - type: object + required: + - Decrypt + properties: + Decrypt: + type: object + title: Decrypt Data + description: This command is applicable from HAB4.1 onwards. Each instance generates a CSF command to decrypt and authenticate a list of code/data blocks using secret key stored in the secret key store. CST will generate a corresponding AUT_DAT command. CST will encrypt the data blocks in- place in the given files using a secret key and generate MAC data which is appended to the CSF. The secret key index must have been the target key index in a preceding Install Secret Key command. The same secret key must never be used more than once. The secret key used is removed from the secret key store by the Decrypt Data command. A separate Install Secret Key command (which generates a fresh secret key) is required for another Decrypt Data command. + properties: + Decrypt_VerifyIndex: + type: number + title: Verification Index + description: Secret key index in Secret key store. + enum: + - 0 + - 1 + - 2 + - 4 + template_value: 0 + Decrypt_Engine: + type: string + title: Engine + description: MAC Engine. + enum: + - ANY + - CAAM + - DCP + template_value: ANY + Decrypt_EngineConfiguration: + type: + - string + - number + title: Engine Configuration + description: Configuration flags for the engine. See the CSF manual. + template_value: 0 + Decrypt_MacBytes: + type: + - string + - number + title: Mac Bytes + description: Size of MAC in bytes. Even value between 4 and 16. + template_value: 16 + Decrypt_Nonce: + type: string + title: Nonce + description: If set, the nonce from the given file will be used. If not, a random nonce will be generated. + template_value: "nonce.bin" + required: + - Decrypt_VerifyIndex diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hse.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hse.yaml new file mode 100644 index 0000000..dae89e5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_hse.yaml @@ -0,0 +1,620 @@ +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +key_info: + type: object + title: HSE Key Information + required: [output, keyType, keyBitLen] + properties: + output: + type: string + title: Output file name + description: Output Key Info file name + format: file_name + template_value: key_info.bin + + keyType: + type: string + title: Key Type + description: Type of the cryptographic key + enum: [SHE, AES, HMAC, SHARED_SECRET, SIPHASH, ECC_PAIR, ECC_PUB, ECC_PUB_EXT, + RSA_PAIR, RSA_PUB, RSA_PUB_EXT, DH_PAIR, DH_PUB] + template_value: AES + + keyBitLen: + type: number + title: Key Bit Length + description: Length of the key in bits + format: number + enum: [0, 64, 128, 160, 192, 224, 240, 256, 320, 384, 512, 521, 638, 1024, 2048, 3072, 4096] + template_value: 256 + + keyCounter: + type: [number, string] + title: Key Counter + description: Counter value for rollback protection (0 to 0xFFFFFFFE) + format: number + minimum: 0 + maximum: 0xFFFFFFFE + template_value: 0 + + keyFlags: + type: array + title: Key Flags + description: | + Flags defining key properties and usage restrictions: + - USAGE_ENCRYPT: Key is used to encrypt data (including keys if USAGE_KEY_PROVISION is set) + - USAGE_DECRYPT: Key is used to decrypt data (including keys if USAGE_KEY_PROVISION is set) + - USAGE_SIGN: Key is used to generate digital signatures or MACs of any data (including keys if USAGE_KEY_PROVISION is set) + - USAGE_VERIFY: Key is used to verify digital signatures or MACs of any data (including keys if USAGE_KEY_PROVISION is set) + - USAGE_EXCHANGE: Key may be used for key exchange operations + - USAGE_DERIVE: Key may be used as a base key for deriving other keys + - USAGE_KEY_PROVISION: Key used for key provisioning operation. Provision keys can only be NVM keys. This flag along with encrypt/decrypt/sign/verify flags specifies which operations can be performed on a key using this provisioning key + - USAGE_AUTHORIZATION: Key can be used for system authorization. Can be set only for NVM keys. This key should have the verify flag set, but the sign flag NOT set + - USAGE_SMR_DECRYPT: The key is used for SMR decryption. If this flag is set during key installation, HSE will set the USAGE_DECRYPT flag to zero + - ACCESS_WRITE_PROT: The key is write protected and cannot change anymore. For RAM keys, this flag is forced to zero + - ACCESS_DEBUG_PROT: The key is disabled when a debugger is attached. For RAM keys, this flag is forced to zero + - ACCESS_EXPORTABLE: The key can be exported in any format. Ignored when used in combination with USAGE_KEY_PROVISION or USAGE_AUTHORIZATION (provision/authorization keys are NOT exportable) + - USAGE_XTS_TWEAK: This is used as a tweak key in XTS AES encryption; no other flag shall be set + - USAGE_OTFAD_DECRYPT: The key is used just in OTFAD decryption; no other flag shall be set + items: + type: string + enum: [USAGE_ENCRYPT, USAGE_DECRYPT, USAGE_SIGN, USAGE_VERIFY, USAGE_EXCHANGE, + USAGE_DERIVE, USAGE_KEY_PROVISION, USAGE_AUTHORIZATION, USAGE_SMR_DECRYPT, + ACCESS_WRITE_PROT, ACCESS_DEBUG_PROT, ACCESS_EXPORTABLE, USAGE_XTS_TWEAK, + USAGE_OTFAD_DECRYPT] + template_value: [USAGE_ENCRYPT, USAGE_DECRYPT] + enum_template: [USAGE_ENCRYPT, USAGE_DECRYPT, USAGE_SIGN, USAGE_VERIFY, USAGE_EXCHANGE, + USAGE_DERIVE, USAGE_KEY_PROVISION, USAGE_AUTHORIZATION, USAGE_SMR_DECRYPT, + ACCESS_WRITE_PROT, ACCESS_DEBUG_PROT, ACCESS_EXPORTABLE, USAGE_XTS_TWEAK, + USAGE_OTFAD_DECRYPT] + + smrFlags: + type: array + title: SMR Flags + description: Secure Memory Region flags that must be verified before key usage + items: + type: integer + minimum: 0 + maximum: 31 + minItems: 1 # At least one item + maxItems: 32 # At most 32 items (since range is 0-31) + uniqueItems: true # No duplicates allowed + template_value: [] + enum_template: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] + + specificData: + title: Key-Specific Data + description: Additional data specific to the key type + oneOf: + - type: object + title: ECC Key Specific Data + description: Specific data for ECC keys + required: [eccCurveId] + properties: + eccCurveId: + type: string + title: ECC Curve ID + description: Elliptic curve to use with ECC keys + enum: [NONE, SEC_SECP256R1, SEC_SECP384R1, SEC_SECP521R1, BRAINPOOL_P256R1, + BRAINPOOL_P320R1, BRAINPOOL_P384R1, BRAINPOOL_P512R1, + ED25519, CURVE25519, ED448, CURVE448, USER_CURVE1, USER_CURVE2, USER_CURVE3] + template_value: SEC_SECP256R1 + + - type: object + title: RSA Key Specific Data + description: Specific data for RSA keys + required: [pubExponentSize] + properties: + pubExponentSize: + type: [number, string] + title: RSA Public Exponent Size + description: Size of RSA public exponent in bytes (must be less than 16) + format: number + template_value: 3 + + - type: object + title: AES Key Specific Data + description: Specific data for AES keys + required: [aesBlockModeMask] + properties: + aesBlockModeMask: + type: array + title: AES Block Mode Mask + description: Allowed block modes for AES keys + items: + type: string + enum: [BLOCK_MODE_XTS, BLOCK_MODE_CTR, BLOCK_MODE_CBC, BLOCK_MODE_ECB, + BLOCK_MODE_CFB, BLOCK_MODE_OFB, BLOCK_MODE_CCM, BLOCK_MODE_GCM] + template_value: [BLOCK_MODE_CBC, BLOCK_MODE_CTR] + +key_catalog: + type: object + title: HSE Key Catalog Configuration + required: [output, nvmKeyGroups, ramKeyGroups] + properties: + output: + type: string + title: Output file name + description: Output Key Catalog Configuration file name + format: file_name + template_value: key_catalog.bin + + nvmKeyGroups: + type: array + title: NVM Key Groups + description: Configuration for NVM key groups + minItems: 1 + items: + type: object + properties: + muMask: + type: string + title: MU Mask + description: Specifies which Message Units can access this key group + enum: [NONE, MU0, MU1, MU2, MU3, ALL] + default: ALL + template_value: ALL + + groupOwner: + type: string + title: Group Owner + description: Specifies the owner of the key group + enum: [ANY, CUST, OEM] + default: ANY + template_value: ANY + + keyType: + type: string + title: Key Type + description: Type of keys in this group + enum: [SHE, AES, HMAC, SHARED_SECRET, SIPHASH, ECC_PAIR, ECC_PUB, ECC_PUB_EXT, + RSA_PAIR, RSA_PUB, RSA_PUB_EXT, DH_PAIR, DH_PUB] + template_value: AES + + numOfKeySlots: + type: [number, string] + title: Number of Key Slots + description: Number of key slots in this group + format: number + minimum: 1 + maximum: 254 + template_value: 10 + + maxKeyBitLen: + type: [string, number] + title: Maximum Key Bit Length + description: Maximum bit length for keys in this group + format: number + enum: [0, 64, 128, 160, 192, 224, 240, 256, 320, 384, 512, 521, 638, 1024, 2048, 3072, 4096] + template_value: 256 + required: [keyType, numOfKeySlots, maxKeyBitLen] + template_value: + - muMask: ALL + groupOwner: ANY + keyType: SHE + numOfKeySlots: 10 + maxKeyBitLen: 256 + - muMask: ALL + groupOwner: CUST + keyType: AES + numOfKeySlots: 5 + maxKeyBitLen: 256 + + ramKeyGroups: + type: array + title: RAM Key Groups + description: Configuration for RAM key groups + minItems: 1 + items: + type: object + properties: + muMask: + type: string + title: MU Mask + description: Specifies which Message Units can access this key group + enum: [NONE, MU0, MU1, MU2, MU3, ALL] + default: ALL + template_value: ALL + + groupOwner: + type: string + title: Group Owner + description: Specifies the owner of the key group + enum: [ANY, CUST, OEM] + default: ANY + template_value: ANY + + keyType: + type: string + title: Key Type + description: Type of keys in this group + enum: [SHE, AES, HMAC, SHARED_SECRET, SIPHASH, ECC_PAIR, ECC_PUB, ECC_PUB_EXT, + RSA_PAIR, RSA_PUB, RSA_PUB_EXT, DH_PAIR, DH_PUB] + template_value: AES + + numOfKeySlots: + type: [number, string] + title: Number of Key Slots + description: Number of key slots in this group + format: number + minimum: 1 + maximum: 254 + template_value: 10 + + maxKeyBitLen: + type: [string, number] + title: Maximum Key Bit Length + description: Maximum bit length for keys in this group + format: number + enum: [0, 64, 128, 160, 192, 224, 240, 256, 320, 384, 512, 521, 638, 1024, 2048, 3072, 4096] + template_value: 256 + required: [keyType, numOfKeySlots, maxKeyBitLen] + template_value: + - muMask: ALL + groupOwner: ANY + keyType: SHE + numOfKeySlots: 5 + maxKeyBitLen: 256 + - muMask: ALL + groupOwner: ANY + keyType: AES + numOfKeySlots: 5 + maxKeyBitLen: 256 + +smr: + type: object + title: HSE Secure Memory Region Entry + description: Configuration for a Secure Memory Region (SMR) entry that defines memory regions to be verified during boot or runtime + required: [output,smrSrcAddr, smrSize, authKeyHandle, authScheme] + properties: + output: + type: string + title: Output file name + description: Output SME entry file name + format: file_name + template_value: emr_entry.bin + smrSrcAddr: + type: [number, string] + title: SMR Source Address + description: Source address where the SMR needs to be loaded from. This address must be an absolute address. + format: number + template_value: "0x0040_0000" + + smrSize: + type: [number, string] + title: SMR Size + description: The size in bytes of the SMR to be loaded/verified + format: number + minimum: 1 + template_value: "0x0001_0000" + + smrDest: + type: [number, string] + title: SMR Destination Address + description: | + Destination address of SMR (where to copy the SMR after authentication). + For HSE_B, if specified (non-zero), smrDest and (smrDest + smrSize) must be aligned to 16 bytes. + Set to 0 if no copy is needed. + format: number + template_value: "0x0" + + configFlags: + type: string + title: Configuration Flags + description: Configuration flags of SMR entry + enum: [QSPI_FLASH, SD_FLASH, MMC_FLASH, INSTALL_AUTH, AUTH_AAD] + template_value: QSPI_FLASH + + checkPeriod: + type: [number, string] + title: Check Period + description: | + If non-zero, HSE verifies the SMR entry periodically (in background). + Specifies the verification period in x100 milliseconds when HSE is running at maximum frequency. + The value 0xFFFFFFFF is invalid; the checkPeriod max value must be [MAX_UNSIGNED32_INT - 1]. + If checkPeriod is non-zero, smrDest must be non-zero and configFlags must be zero. + Set to 0 to disable periodic verification. + format: number + minimum: 0 + maximum: 0xFFFFFFFE + template_value: "0x0" + + authKeyHandle: + type: object + title: Authentication Key Handle + description: | + The key handle used to check the authenticity of the plaintext SMR. + If INSTALL_AUTH flag is cleared, the authKeyHandle is used only in the Installation Phase. + The key flags must be configured with USAGE_VERIFY set and USAGE_SIGN NOT set. + required: [catalogId, groupIdx, slotIdx] + properties: + catalogId: + type: string + title: Key Catalog ID + description: Key catalog type (ROM, NVM, or RAM) + enum: [ROM, NVM, RAM] + template_value: NVM + + groupIdx: + type: [number, string] + title: Group Index + description: Group index in catalog + format: number + minimum: 0 + maximum: 254 + template_value: 0 + + slotIdx: + type: [number, string] + title: Slot Index + description: Key slot index within the group + format: number + minimum: 0 + maximum: 254 + template_value: 0 + + authScheme: + title: Authentication Scheme + description: | + The authentication scheme used to verify the SMR either during the Installation Phase or Verification phase. + If INSTALL_AUTH flag is set, the same authentication scheme (installation TAG) can be used + to verify the authenticity of SMR during verification phase too; otherwise an internal authentication scheme is used. + oneOf: + - type: object + title: ECDSA Signature Scheme + description: ECDSA signature scheme for SMR authentication + required: [ecdsa] + properties: + ecdsa: + type: object + title: ECDSA Parameters + required: [hashAlgo] + properties: + hashAlgo: + type: string + title: Hash Algorithm + description: Hash algorithm for ECDSA signature + enum: [SHA_1, SHA224, SHA256, SHA384, SHA512, SHA512_224, SHA512_256, + SHA3_224, SHA3_256, SHA3_384, SHA3_512, MP] + template_value: SHA256 + + - type: object + title: EdDSA Signature Scheme + description: EdDSA signature scheme for SMR authentication + required: [eddsa] + properties: + eddsa: + type: object + title: EdDSA Parameters + properties: + preHashEddsa: + type: boolean + title: Pre-hash EdDSA + description: Use pre-hashing for EdDSA scheme + template_value: false + + contextLength: + type: [number, string] + title: Context Length + description: Length of context for EdDSA (0-255 bytes, maximum 16 bytes for SMR) + format: number + minimum: 0 + maximum: 16 + template_value: 0 + + contextAddr: + type: [number, string] + title: Context Address + description: Address of context data for EdDSA (required if contextLength > 0) + format: number + template_value: 0 + + - type: object + title: RSASSA-PSS Signature Scheme + description: RSASSA-PSS signature scheme for SMR authentication + required: [rsassa_pss] + properties: + rsassa_pss: + type: object + title: RSASSA-PSS Parameters + required: [hashAlgo] + properties: + hashAlgo: + type: string + title: Hash Algorithm + description: Hash algorithm for RSASSA-PSS signature + enum: [SHA_1, SHA224, SHA256, SHA384, SHA512, SHA512_224, SHA512_256, + SHA3_224, SHA3_256, SHA3_384, SHA3_512, MP] + template_value: SHA256 + + saltLength: + type: [number, string] + title: Salt Length + description: Salt length for RSASSA-PSS scheme + format: number + minimum: 0 + template_value: 32 + + - type: object + title: RSASSA-PKCS1-v1.5 Signature Scheme + description: RSASSA-PKCS1-v1.5 signature scheme for SMR authentication + required: [rsassa_pkcs1_v15] + properties: + rsassa_pkcs1_v15: + type: object + title: RSASSA-PKCS1-v1.5 Parameters + required: [hashAlgo] + properties: + hashAlgo: + type: string + title: Hash Algorithm + description: Hash algorithm for RSASSA-PKCS1-v1.5 signature + enum: [SHA_1, SHA224, SHA256, SHA384, SHA512, SHA512_224, SHA512_256, + SHA3_224, SHA3_256, SHA3_384, SHA3_512, MP] + template_value: SHA256 + + - type: object + title: CMAC Scheme + description: CMAC (AES-based) authentication scheme for SMR + required: [cmac] + properties: + cmac: + type: object + title: CMAC Parameters + properties: + cipherAlgo: + type: string + title: Cipher Algorithm + description: Cipher algorithm for CMAC scheme (only AES is supported) + enum: [AES] + template_value: AES + default: AES + + - type: object + title: GMAC Scheme + description: GMAC (AES-GCM based) authentication scheme for SMR + required: [gmac] + properties: + gmac: + type: object + title: GMAC Parameters + required: [ivLength, ivAddr] + properties: + ivLength: + type: [number, string] + title: IV Length + description: Length of initialization vector for GMAC scheme + format: number + minimum: 1 + template_value: 12 + + ivAddr: + type: [number, string] + title: IV Address + description: Address of initialization vector for GMAC scheme + format: number + template_value: "0x0050_0000" + + - type: object + title: XCBC-MAC Scheme + description: XCBC-MAC (AES128-based) authentication scheme for SMR + required: [xcbc_mac] + properties: + xcbc_mac: + type: object + title: XCBC-MAC Parameters + properties: {} + + - type: object + title: HMAC Scheme + description: HMAC authentication scheme for SMR + required: [hmac] + properties: + hmac: + type: object + title: HMAC Parameters + required: [hashAlgo] + properties: + hashAlgo: + type: string + title: Hash Algorithm + description: Hash algorithm for HMAC + enum: [SHA_1, SHA224, SHA256, SHA384, SHA512, SHA512_224, SHA512_256, + SHA3_224, SHA3_256, SHA3_384, SHA3_512, MP] + template_value: SHA256 + + instAuthTagAddrs: + type: array + title: Installation Authentication Tag Addresses + description: | + Optional - The location in external flash of the initial proof of authenticity over SMR. + If INSTALL_AUTH flag is set, specifies the address(es) where the SMR original authentication TAG is located. + For MAC and RSA signature, only first address is used. + Both addresses are used for ECDSA and EDDSA signatures (r at index 0, s at index 1). + minItems: 2 + maxItems: 2 + items: + type: [number, string] + format: number + template_value: [0, 0] + + smrDecrypt: + type: object + title: SMR Decryption Parameters + description: Specifies the parameters for SMR decryption (optional) + if: + properties: + aadLength: + not: + const: 0 + then: + required: [decryptKeyHandle, aadAddr] + else: + required: [decryptKeyHandle] + properties: + decryptKeyHandle: + type: object + title: Decryption Key Handle + description: The key handle referencing the decryption key + required: [catalogId, groupIdx, slotIdx] + properties: + catalogId: + type: string + title: Key catalog type (ROM, NVM, or RAM) + enum: [ROM, NVM, RAM] + template_value: NVM + + groupIdx: + type: [number, string] + title: Group Index + format: number + minimum: 0 + maximum: 254 + template_value: 0 + + slotIdx: + type: [number, string] + title: Key slot index within the group + format: number + minimum: 0 + maximum: 254 + template_value: 0 + + gmacTagAddr: + type: [number, string] + title: GMAC Tag Address + description: Address of the Tag used for GCM. If set to 0, AES-CTR is used for decryption. + format: number + template_value: 0 + + aadLength: + type: [number, string] + title: AAD Length + description: The length in bytes of the Authenticated Additional Data (AAD). Must be 0, 64, or 128 bytes. + format: number + enum: [0, 64, 128] + template_value: 0 + + aadAddr: + type: [number, string] + title: AAD Address + description: The address of AAD used for AEAD (required if aadLength > 0) + format: number + template_value: 0 + + versionOffset: + type: [number, string] + title: Version Offset + description: | + Optional - The offset in SMR where the image version can be found. + Provides anti-rollback protection for the image against attacks during update. + Set to 0 to disable version checking. + If used, must be a valid offset within the SMR in range [4, smrSize - 4]. + Must be aligned to 4 bytes. + Once used, all subsequent updates must have a version GREATER than the previous one. + Not used for SHE based secure boot. + format: number + minimum: 0 + template_value: 0 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_iee.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_iee.yaml new file mode 100644 index 0000000..dffab1c --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_iee.yaml @@ -0,0 +1,260 @@ +# Copyright 2022-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +iee_output: + type: object + title: Basic Settings + properties: + output_folder: + type: string + title: IEE output directory + description: Path to directory where the IEE output will be generated + template_value: "iee_output" + + output_format: + type: string + title: Output data file format's + description: Output file format for IEE image(s) + enum: [bin, hex, srec, sparse] + template_value: bin + + output_name: + type: string + title: Output binary image filename + description: Filename of the output image containing keyblobs and encrypted data blobs without file extension (.bin will be appended) + template_value: "iee_full_image" + default: "iee_full_image" + + keyblob_name: + type: string + title: Keyblob filename + description: Filename of the keyblob without file extension (.bin will be appended) + template_value: "iee_keyblob" + default: "iee_keyblob" + + encrypted_name: + type: string + title: Encrypted name + description: filename of the encrypted datablobs without file extension (.bin will be appended) + template_value: "encrypted_blob" + default: "encrypted_blob" + + generate_readme: + type: boolean + title: Generate readme.txt + description: Readme file contains information about image layout + template_value: true + default: true + + generate_fuses_script: + type: boolean + title: Generate blhost batch file to burn fuses + description: BCF file with fuses configuration + template_value: true + default: true + required: [output_folder] + +iee: + type: object + title: IEE Settings + required: [keyblob_address] + properties: + keyblob_address: + type: [string, number] + title: Base address of the IEE keyblob + description: Should be aligned to 1 kB + format: number + template_value: "0x30000000" + + data_blobs: + type: array + title: Data blobs list + description: List of all data blobs that will be encrypted + items: + type: object + required: [data] + properties: + data: + type: string + title: Binary data blob + description: Path to binary file with plain text data to be encrypted + format: file + template_value: my_data.bin + + address: + type: [number, string] + title: Data blob address + description: Data blob address, it doesn't have to be specified for S-REC + format: number + template_value: "0x30001000" + +ibkek: + type: object + title: Keyblob Encryption Key + required: [ibkek1, ibkek2] + properties: + ibkek1: + type: [string, number] + title: IBKEK1 AES-XTS 256-bit key + description: IBKEK1 AES-XTS key for keyblob encryption + format: number + template_value: "0x000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F" + + ibkek2: + type: [string, number] + title: IBKEK2 AES-XTS 256-bit key + description: IBKEK2 AES-XTS key for keyblob encryption + format: number + template_value: "0x202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F" + +key_blobs: + type: object + title: List of Key Blobs used by IEE + required: [key_blobs] + properties: + key_blobs: + description: The list of definition of individual key blobs including plain data. Add other array items as you need and device allows + type: array + minItems: 1 + maxItems: 4 + items: + type: object + required: [key1, key2, aes_mode, key_size, start_address, end_address] + properties: + region_lock: + type: boolean + title: Keyblob lock attribute + description: Determines if the ROM will lock the IEE configuration to prevent later changes. + template_value: False + default: False + + aes_mode: + type: string + title: AES mode + description: AES mode, Encryption bypass, AES-XTS, AES-CTR (with or without address binding) or AES-CTR keystream only + enum: + [ + "Bypass", + "AesXTS", + "AesCTRWAddress", + "AesCTRWOAddress", + "AesCTRkeystream", + ] + template_value: "AesXTS" + + key_size: + type: string + title: AES key size, 128/256 for AES-CTR or 256/512 for AES-XTS + description: AES mode, AES-XTS or AES-CTR + enum: ["CTR256XTS512", "CTR128XTS256"] + template_value: "CTR256XTS512" + + page_offset: + type: number + title: Page offset + description: Page offset, IEE_REG0PO value + format: number + template_value: 0 + default: 0 + + key1: + type: [number, string] + title: AES-XTS key1 / AES-CTR key + description: AES key for the key blob, size depends on key_size + format: number + template_value: "0x000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F" + + key2: + type: [number, string] + title: AES-CTR Counter value or AES-XTS key2 + description: AES key for the key blob, size depends on key_size + format: number + template_value: "0x202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F" + + start_address: + type: [number, string] + title: Start address of key blob data + description: Start address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x30001000" + + end_address: + type: [number, string] + title: End address of key blob data + description: End address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x30008000" + +key_blobs_with_ele: + type: object + title: MIMXRT118x Keyblob Configuration + properties: + key_blob: + description: Keyblob configuration, keyblob won't be generated. + type: object + required: [key1, key2, aes_mode, key_size, start_address, end_address] + properties: + region_lock: + type: boolean + title: Keyblob lock attribute + description: Determines if the ROM will lock the IEE configuration to prevent later changes. + template_value: False + default: False + + aes_mode: + type: string + title: AES mode + description: AES mode, Encryption bypass, AES-XTS, AES-CTR (with or without address binding) or AES-CTR keystream only + enum: + [ + "Bypass", + "AesXTS", + "AesCTRWAddress", + "AesCTRWOAddress", + "AesCTRkeystream", + ] + template_value: "AesXTS" + + key_size: + type: string + title: AES key size, 128/256 for AES-CTR or 256/512 for AES-XTS + description: AES mode, AES-XTS or AES-CTR + enum: ["CTR256XTS512", "CTR128XTS256"] + template_value: "CTR256XTS512" + + page_offset: + type: number + title: Page offset + description: Page offset, IEE_REG0PO value + format: number + template_value: 0 + default: 0 + + key1: + type: [number, string] + title: AES-XTS key1 / AES-CTR key + description: AES key for the key blob, size depends on key_size + format: number + template_value: "0x000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F" + + key2: + type: [number, string] + title: AES-CTR Counter value or AES-XTS key2 + description: AES key for the key blob, size depends on key_size + format: number + template_value: "0x202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F" + + start_address: + type: [number, string] + title: Start address of key blob data + description: Start address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x04001000" + + end_address: + type: [number, string] + title: End address of key blob data + description: End address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x04008000" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_mbi.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_mbi.yaml new file mode 100644 index 0000000..3862ceb --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_mbi.yaml @@ -0,0 +1,584 @@ +# Copyright 2021-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +app: + type: object + title: Basic Settings + properties: + inputImageFile: + type: string + title: Plain application image + description: The input application image to by modified to Master Boot Image. + format: file + template_value: my_application.bin + required: [inputImageFile] + +output_file: + type: object + title: Basic Settings + properties: + masterBootOutputFile: + type: string + title: Output Image name + description: The path for result binary file. + format: file_name + template_value: my_mbi.bin + required: [masterBootOutputFile] + +trust_zone: + type: object + title: Trust Zone Settings + properties: + enableTrustZone: + type: boolean + title: TrustZone enable option + description: If not specified, the Trust zone is disabled. + template_value: false + trustZonePresetFile: + type: string + title: TrustZone Customization file + description: If not specified, but TrustZone is enabled(enableTrustZone) the default values are used. + template_value: my_tz_custom.yaml + format: optional_file + +trust_zone_mandatory: + type: object + title: Trust Zone Settings + properties: + trustZonePresetFile: + type: string + title: TrustZone Customization file + description: If not specified the default values are used. + template_value: my_tz_custom.yaml + format: optional_file + +trust_zone_2: + type: object + title: Trust Zone Settings + properties: + trustZonePresetFile: + type: string + title: TrustZone Customization file in version 2 + description: Specification of Trust Zone configuration file for advanced settings. It could be as YAML TrustZone configuration file as pre-prepared binary TrustZone configuration. + template_value: my_tz_custom.yaml + format: optional_file + +load_addr: + type: object + title: Basic Settings + properties: + outputImageExecutionAddress: + type: [number, string] + title: Loading address of application + description: Application loading address in RAM if not XiP, otherwise address of load in XiP. + template_value: 0 + +firmware_version: + type: object + title: Basic Settings + properties: + firmwareVersion: + type: [number, string] + title: Firmware version. + description: Value compared with Secure_FW_Version monotonic counter value stored in protected memory (MCU specific). If value is lower than value in protected memory, then is image rejected (rollback protection). + format: number + template_value: 0 + +firmware_version_vx: + type: object + title: Basic Settings + properties: + firmwareVersion: + type: [number, string] + title: Firmware version. + description: Used for anti-rollback protection. New firmware must have the same or higher FW version. This value is the minimum firmware version will be stored in BCA and the firmware version specified in SBX file is then compared with this value. + format: number + template_value: 0 + +image_version: + type: object + title: Basic Settings + properties: + imageVersion: + type: [number, string] + title: Image version. + description: Image version is used for dual boot. The boot ROM decides which image to boot first based on the image version. It boots the one with the newer image version first, and in case of a failure, it boots the older one. + format: number + template_value: 0 + +image_subtype: + type: object + title: Basic Settings + properties: + outputImageSubtype: + type: string + title: Image SubType + description: Image subtype determine the image use in MCU. "main" for main application, "nbu" for Narrow Band Unit image and "recovery" for recovery image type + enum: [main, nbu, recovery] + template_value: main + +cert_block_v1: + type: object + title: Certificate Block V1 + properties: + certBlock: + type: string + title: Certificate Block binary/config file + description: Path to certificate block binary or config file. + template_value: cert_block.yaml + format: file + required: [certBlock] + +cert_block_v21: + type: object + title: Certificate Block V2.1 + properties: + certBlock: + type: string + title: Certificate Block binary/config file + description: Path to certificate block binary or config file. + template_value: cert_block.yaml + format: file + required: [certBlock] + + +ahab_sign_support: + type: object + title: AHAB Container format to add to ECC + PQC sign. + required: [srk_set, srk_table, used_srk_id] + properties: + srk_set: + type: string + title: Super Root Key (SRK) set + description: Defines which set is used to authenticate the container. + enum: [oem, nxp] + template_value: oem + used_srk_id: + type: [number, string] + title: Used SRK + description: Which key from SRK set is being used. + format: number + template_value: 0 + signer: + type: string + title: AHAB container signer + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for sign the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + signer_#2: + type: string + title: AHAB container signer for second signature (PQC only) + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for second sign (PQC only) of the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + srk_table: + type: object + title: SRK Table + template_title: Configuration of AHAB SRK table + description: "SRK (Super Root key) table definition." + required: [srk_array] + properties: + flag_ca: + type: boolean + title: CA Flag + description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys + template_value: false + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK records. All SRKs must be of the same + type. Supported signing algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: + sha256, sha384, sha512, sha3_256, sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, + rsa2048, rsa4096, dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just + in new type of AHAB container" + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + srk_table_#2: + type: object + title: Second SRK Table + template_title: Configuration of AHAB SRK table in case that the double signing (ECC + PQC) + required: [srk_array] + properties: + flag_ca: + type: boolean + title: CA Flag + description: CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys + template_value: false + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK Dilithium records. All SRKs must be of the same + type. Supported signing algorithms are: Dilithium level 3. Supported hash algorithms: + sha3_256, sha3_384, sha3_512. Certificate may be of Certificate Authority." + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + certificate: + type: string + title: The AHAB certificate + template_title: Optional configuration of AHAB Container Certificate (if not used, erase the section) + description: + The file that contains AHAB certificate. It could be used already prepared binary form signed by SRK, or it is possible to + use configuration YAML file of certificate and the AHAB export process it will export it itself. + format: file + template_value: my_ahab_certificate.bin + +ahab_sign_support_add_image_hash_type: + type: object + title: AHAB Container format to add to ECC + PQC sign. + properties: + image_hash_type: + type: string + title: Images HASH type + description: HASH type of image. + enum: [sha256, sha384, sha512] + template_value: sha512 + +ahab_sign_support_add_core_id: + type: object + title: AHAB Container format to add to ECC + PQC sign. + properties: + core_id: + type: string + title: Target Core ID + description: Target core id to select kind of image. + enum: [cortex-m33, nbu] + template_value: cortex-m33 + +ahab_sign_support_add_crc: + type: object + title: Additional Checks. + properties: + add_crc_check: + type: boolean + title: The additional CRC images check + description: + If true, add additional CRC image that is computed from all data execution mage and optionally TrustZone. + template_value: false + +cert_block_vX: + type: object + title: Certificate Block vX + properties: + certBlock: + type: string + title: Certificate Block binary file + description: Path to certificate block. + template_value: cert_block.bin + format: file + addCertHash: + type: boolean + title: True to append SHA256 hash [0:127] at the end of certificate block + description: Not mandatory if the hash is written in OTP + template_value: true + + required: [certBlock] + +signer: + type: object + title: Image Signing Settings + properties: + signer: + type: string + title: Signer configuration + description: Signature provider configuration in format 'type=;=;=' or path to a private key. + template_value: type=file;file_path=root_prv_key.pem + required: [signer] + +hw_key: + type: object + title: Basic Settings + properties: + enableHwUserModeKeys: + type: [boolean, string] + title: Enable User HW key sharing + description: Controlling secure hardware key bus. If enabled(1), then it is possible to access keys on hardware secure bus from non-secure application, else non-secure application will read zeros. + template_value: false + required: [enableHwUserModeKeys] + +key_store: + type: object + title: Encryption Settings + properties: + keyStoreFile: + type: string + title: The Key store data file + description: Optional KeyStore data file for included keystore in LoadToRam images. If defined the KeyStore is added into MBI. + format: optional_file + template_value: my_key_store_data.bin + +hmac: + type: object + title: Encryption Settings + properties: + outputImageEncryptionKeyFile: + type: string + title: OTP Master key (HMAC Key) + description: + The OTP Master key that is used to compute HMAC encryption key. + Could be defined as hex number and also as hex/binary file.\n + Used algorithm by tool the get HMAC Key; AES_ENCRYPT (OTP_MASTER_KEK, 0x00000000000000000000000000000000) + template_value: otp_master_key.bin + format: file-or-hex-value + +hmac_mandatory: + type: object + title: Encryption Settings + properties: + outputImageEncryptionKeyFile: + type: string + title: OTP Master key (HMAC Key) + description: + The OTP Master key that is used to compute HMAC encryption key. + Could be defined as hex number and also as hex/binary file.\n + Used algorithm by tool the get HMAC Key; AES_ENCRYPT (OTP_MASTER_KEK, 0x00000000000000000000000000000000) + template_value: otp_master_key.bin + format: file-or-hex-value + required: [outputImageEncryptionKeyFile] + +ctr_init_vector: + type: object + title: Encryption Settings + properties: + CtrInitVector: + type: string + title: The output image encryption initial vector for encryption counter + description: The initial vector for encryption counter. Could be defined as hex number and also as hex/binary file + template_value: "0xc3df2316fd40b15586cb5ae49483aee2" + format: file-or-hex-value + +app_table: + type: object + title: Basic Settings + properties: + applicationTable: + type: array + title: The list of additional binaries + description: This is software feature of RTxxx family that NXP SDK startup code (not ROM) could load additional images. + items: + type: object + required: [binary, destAddress, load] + properties: + binary: + type: string + title: Binary file + description: The binary file to be added to final application. + format: file + template_value: my_additional_binary.bin + destAddress: + type: [string, number] + title: Destination address + description: Destination address in RAM of additional binary. + format: number + template_value: 0x20000000 + load: + type: boolean + title: Enable load + description: Enabler to load/use the image. + template_value: true + +image_type: + type: object + title: Basic Settings + properties: + outputImageExecutionTarget: + type: string + title: Application target + description: Definition if application is Execute in Place(XiP) or loaded to RAM during reset sequence. + enum: + [ + "xip", + "load-to-ram", + "Internal flash (XIP)", + "External flash (XIP)", + "Internal Flash (XIP)", + "External Flash (XIP)", + "RAM", + "ram", + ] + enum_template: ["xip", "load-to-ram"] + template_value: xip + + outputImageAuthenticationType: + type: string + title: Type of boot image authentication + description: Specification of final master boot image authentication. + enum: + [ + plain, + crc, + signed, + signed-encrypted, + signed-nxp, + nxp_signed, + nbu-signed, + Plain, + CRC, + Signed, + Encrypted + Signed, + NXP Signed, + NXP signed, + NBU Signed, + encrypted, + ] + enum_template: + ["plain", "crc", "signed", "signed-encrypted", "signed-nxp","nbu-signed"] + template_value: plain + + required: [outputImageExecutionTarget, outputImageAuthenticationType] + +lifecycle: + type: object + title: Basic Settings + properties: + lifeCycle: + type: string + title: Life cycle state + description: + life cycle state model to protect code from reading from the device internal flash, which is called code + read protection feature. There are different levels of protections in the system, so that access to the on-chip flash and use of ISP + can be restricted. Four levels of Read Out Protection (ROP) are supported. This read out protection is a mechanism that allows user to enable + different levels of protection in the system. It is a 8-bit field FTFA_FSEC associated with flash security byte (0x40c byte address). + It can be programmed by customer. Check the SRM for more information. If not provided, value in application will be used. + enum: + [ + "NOT_SET", + "OEM_OPEN", + "OEM_CLOSED_ROP1", + "OEM_CLOSED_ROP2", + "OEM_CLOSED_ROP3", + "OEM_CLOSED_NO_RETURN", + ] + template_value: NOT_SET + +just_header: + type: object + title: Basic Settings + properties: + justHeader: + type: boolean + title: Generate only header + description: + Build only the boot headers (Vector table, BCA, FCB) 0x0..0x800 binary without the application. + This is needed for device HSM provisioning file in case the user set ROP2, ROP3. + template_value: false + +bca: + type: object + title: Bootloader Configuration Area (BCA) + properties: + bca: + type: string + title: BCA binary/config file + description: Path to bca binary or config file. + template_value: bca.yaml + format: file + +fcf: + type: object + title: Flash Configuration Fields + properties: + fcf: + type: string + title: FCF binary/config file + description: Path to FCF binary or config file. + template_value: fcf.yaml + format: file + +hse_ivt: + type: object + title: HSE IVT Settings + description: "HSE Interrupt Vector Table configuration settings" + properties: + appSwtInit: + type: boolean + title: APP SWT Init + description: "Application Software Tamper initialization" + template_value: false + appStartAddress: + type: [number, string] + title: Application Start Address + description: "Start address for CM7_0 core application" + format: number + template_value: "0x00400200" + lcConfigAddr: + type: [number, string] + title: Lifecycle Configuration Address + description: "Address of lifecycle configuration data. If not set, the LC configuration will be placed after application." + format: number + template_value: "0x0" + hseFwAddr: + type: [number, string] + title: HSE Firmware Address + description: "Address of HSE firmware" + format: number + template_value: "0x0" + +hse_app_boot_header: + type: object + title: Application Boot Header Settings + description: "Configuration for the Application Boot" + properties: + appStartAddress: + type: [number, string] + title: Start Address + description: "Start address of the application" + format: number + template_value: "0x00400200" + +hse_signature: + type: object + title: HSE Signature settings + description: "Configuration of HSE signature" + properties: + initialVector: + type: string + title: Initial Vector + description: "Initial vector for encryption (12 bytes hexadecimal). If not specified, random value will be generated." + format: file-or-hex-value + template_value: "000102030405060708090A0B" + adkp: + type: string + title: Application Debug/Key Password + description: "Key used for encryption (16 bytes hexadecimal)" + format: file-or-hex-value + template_value: "000102030405060708090A0B0C0D0E0F" + required: [adkp] + +hse_lifecycle: + type: object + title: Lifecycle Configuration + description: "Configuration for HSE lifecycle state. The lifecycle state determines the security level and available features of the device. Each state has specific implications for device functionality and security." + properties: + lifecycle: + type: string + title: Lifecycle State + description: "Defines the lifecycle state of the device: 'none' - default state with no lifecycle change, 'oem_prod' - OEM production state with increased security, 'in_field' - deployed state with highest security level and restricted debug access." + enum: ["none", "oem_prod", "in_field"] + template_value: "none" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_memcfg.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_memcfg.yaml new file mode 100644 index 0000000..62aae2d --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_memcfg.yaml @@ -0,0 +1,31 @@ +# Copyright 2021-2024 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +base: + type: object + required: [peripheral] + properties: + peripheral: + type: string + title: Peripheral name + # enum: [] + description: Name of the external memory support peripheral + template_value: spi_nor + + interface: + type: string + title: Interface name + # enum: [] + description: Interface name of some other details about connection + template_value: quad_spi + +settings: + type: object + required: [settings] + properties: + settings: + type: object + title: Option words settings + description: The The option word settings + properties: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_otfad.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_otfad.yaml new file mode 100644 index 0000000..76d2b1f --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_otfad.yaml @@ -0,0 +1,182 @@ +# Copyright 2022-2023,2025-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +otfad_family: + type: object + title: Basic Settings + properties: + family: + type: string + title: MCU family + description: MCU family name. + enum: [place_holder] + template_value: rt5xx + required: [family] + +otfad_output: + type: object + title: Basic Settings + properties: + output_folder: + type: string + title: OTFAD output folder + description: Path to directory where the OTFAD output will be generated + template_value: "otfad_output" + + output_format: + type: string + title: Output data file format's + description: Output file format for OTFAD image(s) + enum: [bin, hex, srec, sparse] + template_value: bin + + output_name: + type: string + title: Output binary image file name + description: Filename of the output image containing keyblobs and encrypted data blobs without file extension (.bin will be appended) + template_value: "otfad_whole_image" + default: "otfad_whole_image" + + keyblob_name: + type: string + title: Keyblob file name + description: Filename of the keyblob without file extension (.bin will be appended) + template_value: "OTFAD_Table" + default: "OTFAD_Table" + + encrypted_name: + type: string + title: Encrypted name + description: filename of the encrypted datablobs without file extension (.bin will be appended) + template_value: "encrypted_blob" + default: "encrypted_blob" + + generate_readme: + type: boolean + title: Generate readme.txt + description: Readme file contains information about image layout + template_value: true + default: true + + required: [output_folder] + +otfad: + type: object + title: OTFAD Settings + required: [key_blobs, kek, otfad_table_address] + properties: + kek: + type: string + title: KEK + description: OTFAD Key Encryption Key to encrypt OTFAD table. Might be provided as a path to binary file containing KEK or as a string or number + template_value: my_secret_kek.bin + + otfad_table_address: + type: [number, string] + title: OTFAD key blobs table address + description: The base address of key blob table, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x08000000" + + data_blobs: + type: array + title: Data blobs list + description: List of all data blobs included in this key blob + items: + type: object + required: [data, address] + properties: + data: + type: string + title: Plain Text data blob + description: Path to binary file with plain text data to be encrypted if desired + format: file + template_value: my_data.bin + + address: + type: [number, string] + title: Data blob address + description: Data blob address, it could be omitted if data blob starts at start_address + format: number + template_value: "0x08001000" + + key_blobs: + title: List of Key Blobs used by OTFAD + description: The list of definition of individual key blobs including plain data. Add other array items as you need and device allows + type: array + minItems: 1 + items: + type: object + required: [aes_key, aes_ctr, start_address, end_address] + properties: + aes_key: + type: [number, string] + title: AES key + description: AES key for the key blob + format: number + template_value: "0xB1A0C56AF31E98CD6936A79D9E6F829D" + + aes_ctr: + type: [number, string] + title: AES Counter value + description: AES counter value for the key blob + format: number + template_value: "0x5689fab8b4bfb264" + + start_address: + type: [number, string] + title: Start address of key blob data + description: Start address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x08001000" + + end_address: + type: [number, string] + title: End address of key blob data + description: End address of key blob data, it should be aligned to 1 KB (1024 B) + format: number + template_value: "0x08010000" + + aes_decryption_enable: + type: boolean + title: AES decryption enable flag + description: For accesses hitting in a valid context, this bit indicates if the fetched data is to be decrypted or simply bypassed + template_value: True + default: True + + valid: + type: boolean + title: Valid flag + description: This field signals if the context is valid or not + template_value: True + default: True + + read_only: + type: boolean + title: Read Only flag + description: This field signals if the context is Read only or not + template_value: True + default: True + +otfad_scramble: + type: object + title: OTFAD Key Scrambling Settings + properties: + key_scramble: + type: object + description: If Key scrambling is not required, this section must be commented out + required: [key_scramble_mask, key_scramble_align] + properties: + key_scramble_mask: + type: [number, string] + title: Key Scramble + description: OTFAD Key Scramble mask (4 bytes size) + format: number + template_value: "0x12345678" + key_scramble_align: + type: [number, string] + title: Key Scramble Align + description: OTFAD Key scramble mask align (1 byte size) + format: number + template_value: "0x72" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_pfr.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_pfr.yaml new file mode 100644 index 0000000..5ccd087 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_pfr.yaml @@ -0,0 +1,31 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +pfr_base: + type: object + required: [type] + properties: + type: + type: string + title: Configuration area type + description: PFR / IFR type + template_value: CMPA + +pfr_settings: + type: object + required: [settings] + properties: + settings: + type: object + title: Configuration area Settings + +pfr_additional_data: + type: object + properties: + additional_data: + type: string + title: Customer defined data + description: Custom configuration area for customer-specific data. If not specified, the data won't be added to the binary. + template_value: customer-data.bin + format: file-or-hex-value diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb21.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb21.yaml new file mode 100644 index 0000000..45c36e8 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb21.yaml @@ -0,0 +1,611 @@ +# Copyright 2023-2024,2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +common: + type: object + title: Basic Setting + properties: + containerKeyBlobEncryptionKey: + type: string + title: SB2.1 SBKEK + description: Path to SB key encryption key (AES-128). It might be provided in text file or binary file or as a hex string in the configuration. + template_value: sbkek.txt + format: file-or-hex-value + RKTHOutputPath: + type: string + title: Path to file where the hash of hashes will be stored + description: Path to output hash of hashes of root keys + template_value: hash.bin + format: file_name + required: [containerKeyBlobEncryptionKey] + +sb2_family: + type: object + title: Basic Settings + properties: + family: + type: string + title: MCU family + description: MCU family name. + enum: [] # Just placeholder to keep this record that will be fulfilled in runtime + template_value: lpc55s6x + required: [family] + +sb2_output: + type: object + title: SB2.1 Output + properties: + containerOutputFile: + type: string + title: SB2 filename + description: Generated SB2 container filename. + template_value: my_new.sb + format: file_name + required: [containerOutputFile] + +sb2: + type: object + required: [options] + properties: + options: + type: object + title: SB2.1 Options + description: An options block contains zero or more name/value pairs and the option settings that assign values to global options used by the nxpimage to control the generation of the output file. + required: + - flags + properties: + flags: + type: + - number + - string + title: SB2.1 flags + description: For SB2.1 use only 0x8 encrypted + signed. + template_value: 0x8 + buildNumber: + type: + - number + - string + title: SB2.1 build number + description: Build number. + template_value: 0x1 + productVersion: + type: + - number + - string + title: Product version + description: Version string as "xxx.yyy.zzz". + template_value: "1.00.00" + componentVersion: + type: + - number + - string + title: Component version + description: Component version string as "xxx.yyy.zzz". + template_value: "1.00.00" + secureBinaryVersion: + type: + - number + - string + title: SB Version + description: Used to specify version of SB2 file. + template_value: "2.1" + +keyblobs: + type: object + title: SB 2.1 Keyblobs + properties: + keyblobs: + type: array + title: SB2.1 Keyblobs + description: Section with keyblobs + items: + type: object + required: + - keyblob_id + - keyblob_content + properties: + keyblob_id: + type: number + title: Keyblob ID + description: >- + ID referenced by keywrap and encrypt commands + template_value: 0 + keyblob_content: + type: array + title: Keyblob Content + description: >- + Definition of keyblobs + items: + type: object + required: + - start + - end + - key + - counter + properties: + start: + type: + - string + - number + title: Start address + description: >- + Start address of keyblob + template_value: "0x08008000" + end: + type: + - string + - number + title: End address + description: >- + End address of keyblob. last bits must be 0x3ff to have the AES enabled, bit ADE = 1 + template_value: "0x087983ff" + key: + type: string + title: AES key + description: >- + Random user defined key + template_value: "000102030405060708090A0B0C0D0E0F" + minLength: 32 + maxLength: 64 + counter: + type: string + title: AES seed value + description: >- + Counter value + template_value: "0123456789ABCDEF" + minLength: 16 + maxLength: 16 + noByteSwap: + type: number + title: Byte swap + description: >- + RT500, RT600: noByteSwap = 1 (default) + template_value: 1 +sb2_test: + type: object + title: Secure Binary v2.1 Testing Settings + skip_in_template: true + properties: + options: + type: object + title: SB2.1 Options + description: An options block contains zero or more name/value pairs and the option settings that assign values to global options used by the nxpimage to control the generation of the output file. + properties: + dek: + type: string + title: DEK key + description: 32 bytes DEK key for SB 2.1 + template_value: "0000000000000000000000000000000000000000000000000000000000000000" + minLength: 64 + maxLength: 64 + skip_in_template: true + mac: + type: string + title: MAC key + description: 32 bytes MAC key for SB 2.1 + template_value: "0000000000000000000000000000000000000000000000000000000000000000" + minLength: 64 + maxLength: 64 + skip_in_template: true + nonce: + type: string + title: Nonce + description: Nonce for SB 2.1, clear bits at offset 31 and 63. 16 bytes. + template_value: "00000000000000000000000000000000" + minLength: 32 + maxLength: 32 + skip_in_template: true + zeroPadding: + type: [string, boolean] + title: Enable zero padding instead of random padding + description: Zero padding instead of random padding is useful if you want to binary compare two SB 2.1 files. + template_value: false + skip_in_template: true + timestamp: + type: [string, number] + title: SB 2.1 file force timestamp + description: For testing purposes. This option can override real timestamp of SB 2.1 file. + format: number + template_value: 1234567890 + skip_in_template: true + +sb2_sections: + type: object + title: SB 2.1 Sections and commands + required: [sections] + properties: + sections: + type: array + title: SB2.1 Sections + description: Secure Binary v2.1 section blocks + items: + type: object + properties: + section_id: + type: number + title: Section ID + description: >- + ID of the section + template_value: 0 + skip_in_template: True + commands: + type: array + title: SB2.1 Commands + description: >- + Secure Binary v2.1 commands block, list of all possible options - + Modify it according to your application + items: + oneOf: + - type: object + required: + - erase + properties: + erase: + type: object + title: Erase + description: >- + Performs a flash erase of the given address range. The + erase will be rounded up to the sector size. + properties: + address: + type: + - string + - number + title: Address + description: Address of memory block to be erased. + template_value: 0 + length: + type: + - string + - number + title: Size + description: Size of memory block to be erased. + template_value: 4096 + mem_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be erased. + template_value: 0 + flags: + type: number + title: Flags + description: For erase all, flags=1, for erase unsecure all -> 2 + template_value: 0 + required: + - address + - type: object + required: + - load + properties: + load: + type: object + title: Load + description: >- + If set, then the data to write immediately follows the + range header. The length field contains the actual data + length + properties: + address: + type: + - string + - number + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0 + load_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be loaded. + template_value: 0 + file: + type: string + title: Binary file. + description: Binary file to be loaded. + format: file + template_value: my_binary.bin + pattern: + type: + - string + - number + title: Value for fuse programming + description: Fill the 32bit integer value of fuse to be programmed. Legacy way of programming fuses. ProgramFuses is recommended in new projects. + format: number + template_value: 1 + values: + type: + - string + - number + title: Binary values. + description: Binary values delimited by comma to be loaded. + template_value: 0x1224, 0x5678, 0, 12245678 + required: + - address + - type: object + required: + - enable + properties: + enable: + type: object + title: Configure memory + description: >- + initialization of external memories using a parameter + block that was previously loaded to RAM. + properties: + address: + type: + - string + - number + title: Address + description: Configuration address. + format: number + template_value: 0 + mem_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be configured. + template_value: 0 + required: + - address + - type: object + required: + - keywrap + properties: + keywrap: + type: object + title: Keywrap + description: >- + Keywrap holds keyblob ID to be encoded by a value stored in load command and + stored to address defined in the load command. + properties: + keyblob_id: + type: number + title: Address + description: ID of the keyblob. + format: number + template_value: 0 + address: + type: + - string + - number + title: Address + description: Address of keyblob. + format: number + template_value: 0 + values: + type: string + title: Key. + description: Key encryption key. + minLength: 32 + maxLength: 64 + template_value: "000102030405060708090A0B0C0D0E0F" + required: + - keyblob_id + - address + - values + - type: object + required: + - encrypt + properties: + encrypt: + type: object + title: Encrypt with keyblob + description: >- + Encrypt holds an ID, which is a reference to keyblob to be used for + encryption. So the encrypt command requires a list of keyblobs, the keyblob + ID and load command. + properties: + keyblob_id: + type: number + title: Address + description: ID of the keyblob. + format: number + template_value: 0 + address: + type: + - string + - number + title: Address + description: Where the data will be loaded. + format: number + template_value: 0 + values: + type: string + title: Datablob. + description: Encrypt data blob, choose either file or datablob. + template_value: "000102030405060708090A0B0C0D0E0F" + file: + type: string + title: Binary file. + description: Binary file to be encrypted. + format: file + template_value: my_binary.bin + required: + - keyblob_id + - address + - type: object + required: + - fill + properties: + fill: + type: object + title: Fill memory + description: Used for filling of the memory range by repeated pattern. + properties: + address: + type: + - string + - number + title: Address + description: Address of memory block to be filled. + format: number + template_value: 0 + pattern: + type: + - string + - number + title: Pattern + description: Pattern which will be used to fill memory. + format: number + template_value: 2779096485 + required: + - address + - pattern + - type: object + required: + - jump + properties: + jump: + type: object + title: Jump to address + description: The jump command produces the ROM_JUMP_CMD command. Optionally set SP and call argument. + properties: + address: + type: + - string + - number + title: Address + description: Jump to fixed address. + format: number + template_value: 0 + spreg: + type: + - string + - number + title: Stack pointer value + description: Sets the stack pointer before jumping. + template_value: 0x20000e00 + argument: + type: + - string + - number + title: Call argument + description: Argument to the function being jumped to. + template_value: 0x5a5a5a5a + required: + - address + - type: object + required: + - version_check + properties: + version_check: + type: object + title: Check firmware version + description: >- + Used to execute check of provided counter value with value + stored in specified monotonous counter in device. If + values are not same, SB file is rejected. + properties: + ver_type: + type: number + title: Version type + description: 0 for secure, 1 for non secure. + format: number + template_value: 0 + fw_version: + type: number + title: FW version + description: FW version to be checked. + format: number + template_value: 1 + required: + - ver_type + - fw_version + - type: object + required: + - keystore_to_nv + properties: + keystore_to_nv: + type: object + title: Load keystore to memory + description: >- + The keystore_to_nv statement instructs the bootloader to load the backed up + keystore values back into keystore memory region on non-volatile memory. + properties: + address: + type: + - string + - number + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0 + mem_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be loaded. + template_value: 0 + required: + - address + - mem_opt + - type: object + required: + - keystore_from_nv + properties: + keystore_from_nv: + type: object + title: Load keystore from memory + description: >- + The keystore_to_nv statement instructs the bootloader to load the backed up + keystore values back into keystore memory. + properties: + address: + type: + - string + - number + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0 + mem_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be loaded. + template_value: 0 + required: + - address + - mem_opt + - type: object + required: [programFuses] + properties: + programFuses: + type: object + title: Program Fuses + description: Address is OTP index of fuses to be programmed (Check the reference manual for more information). Values is a comma separated list of 32bit values. + properties: + address: + type: [string, number] + title: Address + description: OTP Index of fuses to be programmed. Depends on the chip ROM. + format: number + template_value: 0x0 + values: + type: string + title: Binary values + description: Binary blob either 4 or 8 bytes. + template_value: "aabbccdd" + pattern: + type: [string, number] + title: Integer values + description: values provided as integer e.g. 0x1000 represents data_word1. Choose only one way. + template_value: 0x1000 + load_opt: + type: + - string + - number + title: Memory ID + description: ID of memory block to be loaded. Default memory ID for fuses is 4. + template_value: 4 + skip_in_template: True + required: [address] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb31.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb31.yaml new file mode 100644 index 0000000..1bf75cf --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb31.yaml @@ -0,0 +1,579 @@ +# Copyright 2021-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +sb3_output: + type: object + title: Basic Settings + properties: + containerOutputFile: + type: string + title: SB3 filename + description: Generated SB3 container filename. + template_value: my_new.sb3 + required: [containerOutputFile] + +sb3_description: + type: object + title: Secure Binary v3.1 Settings + properties: + description: + type: string + title: Description + description: Description up to 16 characters, longer will be truncated. Stored in SB3.1 manifest. + template_value: My SB file +sb3: + type: object + title: Secure Binary v3.1 Settings + properties: + containerKeyBlobEncryptionKey: + type: string + title: Part Common Key + description: Path to PCK/NPK 256 or 128 bit key in plain hex string format or path to binary file or hex string. + template_value: my_pck.txt + format: file-or-hex-value-or-config-string + isNxpContainer: + type: boolean + title: Enable NXP Container format + description: Internal usage only, used for generating SB files with NXP content e.g. provisioning firmware, etc... + template_value: false + kdkAccessRights: + type: number + title: KDK access rights + description: Accepted values are 0, 1, 2 and 3. Value used as key properties for key derivation process, more details can be found in CSSv2 manual. + enum: [0, 1, 2, 3] + template_value: 0 + containerConfigurationWord: + type: [string, number] + title: Container configuration word + description: Flag value in SB3.1 manifest, not used by silicons with LPC55S3x ROM. Value can be kept 0, or it can be removed from the configuration file. + format: number + template_value: 0x0 + allOf: + - if: + properties: + isEncrypted: + enum: [true, null] + then: + required: [containerKeyBlobEncryptionKey] + else: + required: [] + +sb3_test: + type: object + title: Secure Binary v3.1 Testing Settings + skip_in_template: true + properties: + isEncrypted: + type: boolean + title: Enable NXP Container encryption + description: If false, generated SB3.1 blocks are not encrypted, only for testing, ROM won't accept unencrypted SB3.1 file. If option is missing, SB3.1 file is automatically encrypted. + template_value: true + skip_in_template: true + timestamp: + type: [string, number] + title: SB3 file force timestamp + description: For testing purposes. This option can override real timestamp of SB3 file. + format: number + template_value: 1234567890 + skip_in_template: true + +sb3_commands: + type: object + title: Secure Binary v3.1 / v4.0 Commands Settings + required: [commands] + properties: + commands: + type: array + title: SB3.1 Commands + description: Secure Binary v3.1 commands block, list of all possible options - Modify it according to your application + items: + oneOf: + - type: object + required: [erase] + properties: + erase: + type: object + title: Erase + description: Performs a flash erase of the given address range. The erase will be rounded up to the sector size. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be erased. + format: number + template_value: 0x0 + size: + type: [string, number] + title: Size + description: Size of memory block to be erased. + format: number + template_value: 4096 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be erased. + format: number + template_value: 0 + required: [address, size] + + - type: object + required: [load] + properties: + load: + type: object + title: Load + description: If set, then the data to write immediately follows the range header. The length field contains the actual data length + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be loaded. + format: number + template_value: 0 + file: + type: string + title: Binary file. + format: file + skip_in_template: True + values: + type: [string, number, array] + title: 32-bit binary values delimited by comma to be programmed or a list with multiple values as integers or 32-bit binary values. + skip_in_template: True + value: + type: [string, number] + title: Binary value + skip_in_template: True + data: + type: [string, number, array] + title: Data to be loaded + description: > + The data to be loaded, it could be defined in following formats: + - 32-bit value. Value will be converted to binary in little endian format. Example: '0xB38AA899' or '0b111000' + - Array of 32-bit binary values delimited by comma to be loaded. Individual 32-bit values will be stored in little endian format. Example: 0x1234, 0x5678, 0, 12345678 + - List of integers passed as an array. + - Path to binary file. Example: my_binary.bin + template_value: my_binary.bin + compress: + type: boolean + title: Data compression + description: Use LZMA compression of date before loading onto the target + template_value: false + sectorSize: + type: [string, number] + title: Memory sector size + description: Size of memory sector where data should be loaded. + format: number + template_value: 8_192 + required: [address] + oneOf: + - required: [data] + - required: [file] + - required: [value] + - required: [values] + allOf: + - if: + properties: + compress: + enum: [false, no, null] + then: + required: [] + else: + required: [sectorSize] + - if: + properties: + data: + type: string + # Check if it doesn't start with 0x or 0b and doesn't contain commas + not: + pattern: "^(0x|0b)|,|^[0-9]+$" + required: [data] + then: + properties: + data: + format: file + - type: object + required: [execute] + properties: + execute: + type: object + title: Execute + description: Address is the jump-to address. No further processing of SB after jump, ROM do not expect to return. + properties: + address: + type: [string, number] + title: Address + description: Jump-to address to start execute code. + format: number + template_value: 0x0 + required: [address] + + - type: object + required: [call] + properties: + call: + type: object + title: Call + description: Address is address to jump. However, the state machine should expect a return to the next statement to continue processing the SB file + properties: + address: + type: [string, number] + title: Address + description: Jump-to address to start execute code. + format: number + template_value: 0x0 + required: [address] + + - type: object + required: [programFuses] + properties: + programFuses: + type: object + title: Program Fuses + description: Address is OTP index of fuses to be programmed (Check the reference manual for more information). Values is a comma separated list of 32bit values. + properties: + address: + type: [string, number] + title: Address + description: OTP Index of fuses to be programmed. Depends on the chip ROM. + format: number + template_value: 0x0 + values: + type: [string, number] + title: Binary values + description: 32bit binary values delimited by comma or one 32 bit integer to be programmed. + template_value: 0x1234, 0x5678, 0, 12345678 + required: [address, values] + + - type: object + required: [programIFR] + properties: + programIFR: + type: object + title: Program IFR + description: The startAddress will be the address into the IFR region, length will be in number of bytes to write to IFR region. The data to write to IFR region at the given address will immediately follow the header + properties: + address: + type: [string, number] + title: Address + description: Address of IFR region to be programmed. + format: number + template_value: 0x0 + file: + type: string + title: Binary file. + format: file + skip_in_template: True + values: + type: [string, number, array] + title: 32-bit binary values delimited by comma to be programmed or a list with multiple values as integer or 32-bit binary values. + skip_in_template: True + value: + type: [string, number] + title: Binary value + skip_in_template: True + data: + type: [string, number, array] + title: Data to be loaded + description: > + The data to be loaded, it could be defined in following formats: + - 32-bit value. Value will be converted to binary in little endian format. Example: '0xB38AA899' or '0b111000' + - Array of 32-bit binary values delimited by comma to be loaded. Individual 32-bit values will be stored in little endian format. Example: 0x1234, 0x5678, 0, 12345678 + - List of integers passed as an array. + - Path to binary file. Example: my_binary.bin + template_value: my_binary.bin + required: [address] + + - type: object + required: [writeIFR] + properties: + writeIFR: + type: object + title: Write IFR + description: The startAddress will be the address into the IFR region, length will be in number of bytes to write to IFR region. The data to write to IFR region at the given address will immediately follow the header + properties: + type: + type: [string, number] + title: IFR type + description: IFR type to be written. + enum: [CFPA, CFPA_AND_CMPA] + template_value: CFPA + file: + type: string + title: Binary file. + format: file + skip_in_template: True + values: + type: [string, number, array] + title: 32-bit binary values delimited by comma to be programmed or a list with multiple values as integer or 32-bit binary values. + skip_in_template: True + value: + type: [string, number] + title: Binary value + skip_in_template: True + data: + type: [string, number, array] + title: Data to be loaded + description: > + The data to be loaded, it could be defined in following formats: + - 32-bit value. Value will be converted to binary in little endian format. Example: '0xB38AA899' or '0b111000' + - Array of 32-bit binary values delimited by comma to be loaded. Individual 32-bit values will be stored in little endian format. Example: 0x1234, 0x5678, 0, 12345678 + - List of integers passed as an array. + - Path to binary file. Example: my_binary.bin + template_value: ifr_data.bin + required: [type] + + - type: object + required: [loadCMAC] + properties: + loadCMAC: + type: object + title: Load CMAC + description: If set, then the data to write immediately follows the range header. The length field contains the actual data length. ROM is calculating cmac from loaded data and storing on address known by ROM decided based on startAddress. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be CMAC loaded. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be CMAC loaded. + format: number + template_value: 0 + file: + type: string + title: Binary file + description: Binary file to be loaded. + format: file + template_value: my_cmac_binary.bin + required: [address, file] + + - type: object + required: [copy] + properties: + copy: + type: object + title: Copy + description: Used for copying data from one place to another. 32 bytes fixed size. + properties: + addressFrom: + type: [string, number] + title: Address From + description: Address of memory block to be copied. + format: number + template_value: 0x0 + memoryIdFrom: + type: [string, number] + title: Memory ID From + description: ID of memory block to be copied. + format: number + template_value: 0 + size: + type: [string, number] + title: Size + description: Size of memory block to be copied. + format: number + template_value: 4096 + addressTo: + type: [string, number] + title: Address To + description: Address of memory where block to be copied. + format: number + template_value: 0x2000_0000 + memoryIdTo: + type: [string, number] + title: Memory ID To + description: ID of memory block where to be copied. + format: number + template_value: 0 + required: [addressFrom, size, addressTo] + + - type: object + required: [loadHashLocking] + properties: + loadHashLocking: + type: object + title: Load with HASH locking + description: If set, then the data to write immediately follows the range header. The length field contains the actual data length. ROM is calculating hash of the data and storing the value in the last 64 bytes of the loaded data, which are reserved for it. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be loaded. + format: number + template_value: 0 + file: + type: string + title: Binary file + description: Binary file to be loaded. + format: file + template_value: my_hashlocking_binary.bin + required: [address, file] + + - type: object + required: [loadKeyBlob] + properties: + loadKeyBlob: + type: object + title: Load Key Blob + description: Wrapped key blob immediately follows the range key blob header. The length field contains the actual data length. + properties: + offset: + type: [string, number] + title: Offset + description: Offset of the key blob. + format: number + template_value: 0x0 + wrappingKeyId: + type: string + title: Wrapping key ID + description: Wrapping ID of key blob. + enum: [NXP_CUST_KEK_INT_SK, NXP_CUST_KEK_EXT_SK] + template_value: 0 + file: + type: string + title: Binary file + description: Binary file to be loaded. + format: file + template_value: my_keyblob.bin + plainInput: + type: [string, boolean] # boolean covers auto-conversion: no -> False + title: Key Blob as plain text + description: Indicates whether key is provided as plaintext or not. If it's in plaintext this option also indicates whether it's as binary or hex + enum: ["no", bin, hex] + template_value: "no" + required: [offset, wrappingKeyId, file] + + - type: object + required: [configureMemory] + properties: + configureMemory: + type: object + title: Configure memory + description: Configure memory. + properties: + configAddress: + type: [string, number] + title: Address + description: Configuration address. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be configured. + format: number + template_value: 0 + required: [configAddress] + + - type: object + required: [fillMemory] + properties: + fillMemory: + type: object + title: Fill memory + description: Used for filling of the memory range by same repeated int32 pattern. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be filled. + format: number + template_value: 0x0 + size: + type: [string, number] + title: Size + description: Size of memory block to be filled. + format: number + template_value: 4096 + pattern: + type: [string, number] + title: Pattern + description: Pattern which will be used to fill memory. + format: number + template_value: 0xA5A5A5A5 + required: [address, size, pattern] + + - type: object + required: [checkFwVersion] + properties: + checkFwVersion: + type: object + title: Check firmware version + description: Checks FW version value specified in command for specified counter ID. FW version value in command must be greater than value programmed in OTP to be accepted, otherwise rollback is detected and receive SB fails + properties: + value: + type: [string, number] + title: Value - Firmware version + description: Firmware version to be compared. + format: number + template_value: 0x0000_0001 + counterId: + type: string + title: Counter ID + description: ID of FW counter to be checked. + enum: + [ + none, + nonsecure, + secure, + radio, + snt, + bootloader, + radio_lp, + ] + template_value: secure + required: [value, counterId] + + - type: object + required: [reset] + properties: + reset: + type: object + title: Reset + description: Resets the target + properties: {} + + - type: object + required: [checkLifecycle] + properties: + checkLifecycle: + type: object + title: Check Lifecycle + description: Checks if the device is in the expected lifecycle state. The command will fail if the device is not in the specified state. + properties: + lifecycle: + type: string + title: Lifecycle State + description: The expected lifecycle state of the device. + enum: + [ + NXP_BLANK, + NXP_FAB, + DEVELOP, + NXP_PROVISIONED, + DEVELOP2, + IN_FIELD, + IN_FIELD_RETURN, + NXP_FA, + IN_FIELD_LOCKED, + NXP_DEV, + BRICKED + ] + template_value: IN_FIELD + required: [lifecycle] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb40.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb40.yaml new file mode 100644 index 0000000..08920ea --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sb40.yaml @@ -0,0 +1,93 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +sb4_output: + type: object + title: Basic Settings + properties: + containerOutputFile: + type: string + title: SB4 filename + description: Generated SB4 container filename. + template_value: my_new.sb4 + required: [containerOutputFile] + +sb4_description: + type: object + title: Secure Binary v4.0 Settings + properties: + description: + type: string + title: Description + description: Description up to 16 characters, longer will be truncated. Stored in SB4.0 manifest. + template_value: My SB file +sb4: + type: object + title: Secure Binary v4.0 Settings + properties: + containerKeyBlobEncryptionKey: + type: string + title: Part Common Key + description: Path to PCK/NPK 256 or 128 bit key in plain hex string format or path to binary file or hex string. + template_value: my_pck.txt + format: file-or-hex-value-or-config-string + kdkAccessRights: + type: number + title: KDK access rights + description: Accepted values are 0, 1, 2 and 3. Value used as key properties for key derivation process, more details can be found in CSSv2 manual. + enum: [0, 1, 2, 3] + template_value: 0 + allOf: + - if: + properties: + isEncrypted: + enum: [true, null] + then: + required: [containerKeyBlobEncryptionKey] + else: + required: [] + + +image_version: + type: object + title: AHAB Container format to add to ECC + PQC sign. + properties: + imageVersion: + type: [number, string] + title: Image version. + description: | + Image version used for rollback protection in SB4 format. While primarily designed for dual boot scenarios in MBI (Master Boot Image), this field provides security through firmware version validation. + + **Rollback Protection Mechanism:** + The image version must be equal to or greater than the version stored in fuses or PFR (Protected Flash Region) to ensure proper rollback protection. + + **Version Calculation (e.g., MCXN556s series):** + The firmware version is calculated by combining the image version with the fuse version: + + fw_version = (imageVersion << 8) | fuse_version + + + **Validation Process:** + During rollback protection, the calculated firmware version is checked against the 'SECURE_FW_VERSION' value stored in the CFPA (Customer Field Programmable Area) page. Only firmware with versions equal to or higher than the stored value will be allowed to execute. + format: number + template_value: 0 + +sb4_test: + type: object + title: Secure Binary v4.0 Testing Settings + skip_in_template: true + properties: + isEncrypted: + type: boolean + title: Enable NXP Container encryption + description: If false, generated SB4.0 blocks are not encrypted, only for testing, ROM won't accept unencrypted SB4.0 file. If option is missing, SB4.0 file is automatically encrypted. + template_value: true + skip_in_template: true + timestamp: + type: [string, number] + title: SB4 file force timestamp + description: For testing purposes. This option can override real timestamp of SB4 file. + format: number + template_value: 1234567890 + skip_in_template: true diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbc.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbc.yaml new file mode 100644 index 0000000..3f8e3ad --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbc.yaml @@ -0,0 +1,181 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +common: + type: object + title: Common DevHSM settings + properties: + oemRandomShare: + type: string + title: OEM Random Share input + description: > + Path to a file containing 16B of random seed data. If not specified, random seed will be generated. + template_value: oem_seed.bin + format: optional_file + initialReset: + type: boolean + title: Initial device reset + description: Reset the device before starting the DevHSM operation + template_value: false + workspace: + type: string + title: Development/debug workspace + description: Path to a folder where to store intermediate artifacts for development/debugging purposes + template_value: wsp + format: dir_name + bufferAddress: + type: [string, number] + format: number + title: Communication buffer address + description: Address to override default communication buffer address + template_value: + containerOutputFile: + type: string + title: SBc filename + description: Generated SBc container filename. + template_value: my_new.sbc + format: file_name + +sbc_description: + type: object + title: Secure Binary C Settings + properties: + description: + type: string + title: Description + description: Description up to 16 characters, longer will be truncated. Stored in SBc manifest. + template_value: This is description of generated SB file. + +sbc_test: + type: object + title: Secure Binary C Testing Settings + properties: + timestamp: + type: [string, number] + title: SBc file force timestamp + description: For testing purposes. This option can override real timestamp of SBc file. + format: number + template_value: 1234567890 + +sbc_commands: + type: object + title: Secure Binary C Commands Settings + required: [commands] + properties: + commands: + type: array + title: SBc Commands + description: Secure Binary C commands block, list of all possible options - Modify it according to your application + items: + oneOf: + - type: object + required: [erase] + properties: + erase: + type: object + title: Erase + description: Performs a flash erase of the given address range. The erase will be rounded up to the sector size. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be erased. + format: number + template_value: 0x0 + size: + type: [string, number] + title: Size + description: Size of memory block to be erased. + format: number + template_value: 4096 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be erased. + format: number + template_value: 0 + required: [address, size] + + - type: object + required: [load] + properties: + load: + type: object + title: Load + description: If set, then the data to write immediately follows the range header. The length field contains the actual data length + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be loaded. + format: number + template_value: 0 + file: + type: string + title: Binary file. + description: Binary file to be loaded. + format: file + template_value: my_binary.bin + values: + type: string + title: Binary values. + description: Binary values delimited by comma to be loaded. + template_value: 0x1234, 0x5678, 0, 12345678 + required: [address] + + - type: object + required: [execute] + properties: + execute: + type: object + title: Execute + description: Address is the jump-to address. No further processing of SB after jump, ROM do not expect to return. + properties: + address: + type: [string, number] + title: Address + description: Jump-to address to start execute code. + format: number + template_value: 0x0 + required: [address] + + - type: object + required: [loadKeyBlob] + properties: + loadKeyBlob: + type: object + title: Load Key Blob + description: Wrapped key blob immediately follows the range key blob header. The length field contains the actual data length. + properties: + offset: + type: [string, number] + title: Offset + description: Offset of the key blob. + format: number + template_value: 0x0 + wrappingKeyId: + type: string + title: Wrapping key ID + description: Wrapping ID of key blob. + enum: [NXP_CUST_KEK_EXT_SK] + template_value: 0 + file: + type: string + title: Binary file + description: Binary file to be loaded. + format: file + template_value: my_keyblob.bin + plainInput: + type: string + title: Key Blob as plain text + description: Indicates whether key is provided as plaintext or not. If it's in plaintext this option also indicates whether it's as binary or hex + enum: ["true", bin, hex] + template_value: "true" + required: [offset, wrappingKeyId, file] \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbx.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbx.yaml new file mode 100644 index 0000000..a84acd5 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_sbx.yaml @@ -0,0 +1,197 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +sbx_output: + type: object + title: Basic Settings + properties: + containerOutputFile: + type: string + title: SBx filename + description: Generated SBx container filename. + template_value: my_new.sbx + required: [containerOutputFile] + +sbx_description: + type: object + title: Secure Binary X Settings + properties: + description: + type: string + title: Description + description: Description up to 16 characters, longer will be truncated. Stored in SBx manifest. + template_value: This is description of generated SB file. + +sbx: + type: object + title: Secure Binary X Settings + properties: + image_type: + type: string + title: image type + description: SecureBinaryXType + enum: ["NXP_PROVISIONING", "OEM_PROVISIONING", "OEM"] + template_value: "OEM_PROVISIONING" + +sbx_test: + type: object + title: Secure Binary X Testing Settings + properties: + isEncrypted: + type: boolean + title: Enable NXP Container encryption + description: If false, generated SBx.1 blocks are not encrypted, only for testing, ROM won't accept unencrypted SBx.1 file. If option is missing, SBx.1 file is automatically encrypted. + template_value: true + timestamp: + type: [string, number] + title: SBx file force timestamp + description: For testing purposes. This option can override real timestamp of SBx file. + format: number + template_value: 1234567890 + +signer: + type: object + title: Certificate Settings + properties: + signer: + type: string + title: Signer + description: Signature provider configuration in format 'type=;=;=' or a ISK Certificate private key used to sign certificate. Only valid for OEM and NXP_PROVISIONING image types + template_value: type=file;file_path=my_prv_key.pem + + if: + properties: + image_type: + enum: ["NXP_PROVISIONING", "OEM"] + then: + required: [signer] + +sbx_commands: + type: object + title: Secure Binary X Commands Settings + required: [commands] + properties: + commands: + type: array + title: SBx Commands + description: Secure Binary X commands block, list of all possible options - Modify it according to your application + items: + oneOf: + - type: object + required: [erase] + properties: + erase: + type: object + title: Erase + description: Performs a flash erase of the given address range. The erase will be rounded up to the sector size. + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be erased. + format: number + template_value: 0x0 + size: + type: [string, number] + title: Size + description: Size of memory block to be erased. + format: number + template_value: 4096 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be erased. + format: number + template_value: 0 + required: [address, size] + + - type: object + required: [load] + properties: + load: + type: object + title: Load + description: If set, then the data to write immediately follows the range header. The length field contains the actual data length + properties: + address: + type: [string, number] + title: Address + description: Address of memory block to be loaded. + format: number + template_value: 0x0 + memoryId: + type: [string, number] + title: Memory ID + description: ID of memory block to be loaded. + format: number + template_value: 0 + file: + type: string + title: Binary file. + description: Binary file to be loaded. + format: file + template_value: my_binary.bin + values: + type: string + title: Binary values. + description: Binary values delimited by comma to be loaded. + template_value: 0x1234, 0x5678, 0, 12345678 + required: [address] + + - type: object + required: [execute] + properties: + execute: + type: object + title: Execute + description: Address is the jump-to address. No further processing of SB after jump, ROM do not expect to return. + properties: + address: + type: [string, number] + title: Address + description: Jump-to address to start execute code. + format: number + template_value: 0x0 + required: [address] + + - type: object + required: [programIFR] + properties: + programIFR: + type: object + title: Program IFR + description: The startAddress will be the address into the IFR region, length will be in number of bytes to write to IFR region. The data to write to IFR region at the given address will immediately follow the header + properties: + address: + type: [string, number] + title: Address (IFR region index) + description: Index of IFR region to be programmed. + format: number + template_value: 0x0 + file: + type: string + title: Binary file + description: Binary file to be programmed. + format: file + template_value: my_binary.bin + value: + type: [string, number] + title: Binary value + description: Binary value to be programmed, at least 4 bytes. Value will be converted to binary little endian format. + template_value: "0xB38AA899" + values: + type: [string, number] + title: Binary values. + description: 32-bit binary values delimited by comma to be programmed. + template_value: 0x1234, 0x5678, 0, 12345678 + required: [address] + + - type: object + required: [reset] + properties: + reset: + type: object + title: Reset + description: Resets the target + properties: {} diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_shadow_regs.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_shadow_regs.yaml new file mode 100644 index 0000000..62e7425 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_shadow_regs.yaml @@ -0,0 +1,11 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +sr_registers: + type: object + required: [registers] + properties: + registers: + type: object + title: Shadow registers Settings diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_she_scec.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_she_scec.yaml new file mode 100644 index 0000000..e0ed06e --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_she_scec.yaml @@ -0,0 +1,129 @@ +# Copyright 2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +key_info: + type: object + title: SHE Configuration for using SCEc + properties: + key: + type: string + title: Key for SCEc operation + description: AES-128 key used in SHE (Secure Hardware Extension) SCEc operation + template_value: ~/keys/new_key.txt + key_id: + type: [number, string] + title: Key Identifier + description: Unique identifier for the SCEc key slot + enum: [ + "MASTER_ECU_KEY", + "BOOT_MAC_KEY", + "BOOT_MAC", + "RAM_KEY", + "USER_KEY_1", + "USER_KEY_2", + "USER_KEY_3", + "USER_KEY_4", + "USER_KEY_5", + "USER_KEY_6", + "USER_KEY_7", + "USER_KEY_8", + "USER_KEY_9", + "USER_KEY_10", + "USER_KEY_11", + "USER_KEY_12", + "USER_KEY_13", + "USER_KEY_14", + "USER_KEY_15", + "USER_KEY_16", + "USER_KEY_17", + ] + template_value: USER_KEY_1 + uid: + type: [number, string] + title: SHE Unique Identifier + description: Unique identifier for the SHE device + template_value: 0x12345678 + auth_key: + type: string + title: Authentication Key + description: Authentication AES-128 key for SHE (Secure Hardware Extension) SCEc operation + template_value: ~/keys/auth_key.txt + auth_key_id: + type: [number, string] + title: Authentication Key Identifier + description: Specifies which key to use for authentication. For most keys, you can use either MASTER_ECU_KEY or the key's own ID. For BOOT_MAC, you can only use MASTER_ECU_KEY or BOOT_MAC_KEY. + template_value: MASTER_ECU_KEY + counter: + type: [number, string] + title: Counter Value + description: Counter used in SHE (Secure Hardware Extension) SCEc operation + template_value: 1 + required: [key, key_id] + +flags: + type: object + title: SHE-SCEc key flags + properties: + write_protection: + type: boolean + title: Write Protection Flag + description: Enable or disable write protection for the SHE-SCEc key. This flag should be set with caution. Setting this flag is an irreversible step and will prevent the device from being reset to factory state + template_value: false + boot_protection: + type: boolean + title: Boot Protection Flag + description: If set, the key cannot be used if the MAC value calculated in the SECURE_BOOT step did not match the BOOT_MAC value stored in secure Flash. In other words, if secure boot fails, the keys marked BOOT_PROT remain locked, and they cannot be used during application execution. + template_value: false + debugger_protection: + type: boolean + title: Debugger Protection Flag + description: If set, the key cannot be used if a debugger is (or has ever been) connected to the MCU since it was last reset. + template_value: false + key_usage: + type: boolean + title: Key Usage Flag + description: This flag determines if a key is used for encryption/decryption or for CMAC generation/verification. If the flag is set, the key is used for CMAC generation/verification. If the flag is clear, the key is used for encryption/decryption. + template_value: false + wildcard: + type: boolean + title: Wildcard Key Flag + description: If set, the key cannot be updated by supplying a special wildcard UID (i.e. UID=0). + template_value: false + verify_only: + type: boolean + title: Verify Only Flag + description: If set, the key cannot be used by the GENERATE_MAC command and can only be used by the VERIFY_MAC command. If KEY_USAGE==0, then this attribute has no effect + template_value: false + + allOf: + # boot_protection + - if: + properties: + key_id: + enum: ["BOOT_MAC_KEY", "BOOT_MAC"] + then: + properties: + boot_protection: + enum: [false] + description: "The 'boot_protection' flag can not be set to true for BOOT_MAC_KEY, or BOOT_MAC keys" + # key_usage + - if: + properties: + key_id: + enum: ["MASTER_ECU_KEY", "BOOT_MAC_KEY", "BOOT_MAC"] + then: + properties: + key_usage: + enum: [false] + description: "The 'key_usage' flag can not be set to true for MASTER_ECU_KEY, BOOT_MAC_KEY, or BOOT_MAC keys" + # verify_only + - if: + properties: + key_id: + enum: ["MASTER_ECU_KEY", "BOOT_MAC_KEY", "BOOT_MAC"] + then: + properties: + verify_only: + enum: [false] + description: "The 'verify_only' flag can not be set to true for MASTER_ECU_KEY, BOOT_MAC_KEY, or BOOT_MAC keys" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_signed_msg.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_signed_msg.yaml new file mode 100644 index 0000000..459c790 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_signed_msg.yaml @@ -0,0 +1,563 @@ +# Copyright 2023-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +--- +family: + type: object + required: + - family + properties: + family: + type: string + title: MCU family + description: + Family identifier including the chip revision. If revision is not + present, latest revision is used as default. + template_value: mimxrt1189 + revision: + type: string + title: MCU revision + description: Revision of silicon + template_value: latest + +signed_message: + type: object + required: + - output + - srk_set + - fuse_version + - sw_version + - srk_table + - signer + - used_srk_id + - srk_revoke_mask + - message + properties: + output: + type: string + title: Output file name + description: Output Signed Message file name + format: file_name + template_value: signed_message.bin + + container_version: + type: number + title: Container version + description: + Force container version, if not specified the default version is used. + This configuration option is valid only for chips that supports both AHAB container versions. Possible options <2, 1> + minimal: 1 + maximal: 2 + template_value: 2 + skip_in_template: True + + srk_set: + type: string + template_title: Settings of Signed Message + title: Super Root Key (SRK) set + description: Defines which set is used to authenticate the signed message. + enum: [none, oem, nxp] + template_value: oem + used_srk_id: + type: [number, string] + title: Used SRK + description: Which key from SRK set is being used. + format: number + template_value: 0 + srk_revoke_mask: + type: [number, string] + title: SRK revoke mask + description: + Bitmask to indicate which SRKs to revoke. Bit set to 1 means revoke + key. Bit 0 = revoke SRK_0, bit 1 = revoke SRK_1 etc. + format: number + template_value: 0x00 + fuse_version: + type: [number, string] + title: Fuse version + description: + The value must be equal or greater than the version stored in fuses + to allow loading this container. + format: number + template_value: 0 + sw_version: + type: [number, string] + title: Software version + description: + Number used by Privileged Host Boot Companion (PHBC) to select between + multiple images with same Fuse version field. + format: number + template_value: 0 + + check_all_signatures: + type: string + title: Check all signatures + description: "This option overrides a fuse to select verification mode.\n + - default: Apply default fuse policy.\n + - check_all_signatures: Force verification of all present signatures." + enum: [default, check_all_signatures] + template_value: default + skip_in_template: True + + signer: + type: string + title: Signed Message container signer + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for sign the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + signer_#2: + type: string + title: Signed Message container signer for second signature (PQC only) + description: + Signature provider configuration in format 'type=;=;=' or a + private key used for second sign (PQC only) of the container header. Header can be signed by SRK. + The referenced SRK must not have been revoked. + template_value: type=file;file_path=my_prv_key.pem + skip_in_template: True + + srk_table: + type: object + title: SRK Table + template_title: Configuration of Signed Message SRK table + description: "SRK (Super Root key) table definition." + required: [srk_array] + properties: + flag_ca: + type: boolean + title: CA Flag + description: + "CA Flag is used by HAB to indicate if the SRK is allowed to sign other keys. + In AHAB CA Flag only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing process itself. + This option exists only for compatibility with systems where fuses are already programmed. In most cases, this should remain false." + template_value: false + hash_algorithm: + type: string + title: Hash Algorithm + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: + [default, sha256, sha384, sha512, sha3_256, sha3_384, sha3_512, sm3] + template_value: default + rsa_exponent_legacy_size: + type: boolean + title: RSA exponent legacy size (4 bytes) + description: + "Force RSA exponent to use legacy 4-byte size instead of actual exponent size. + This option provides backward compatibility with older SPSDK versions that always used 4 bytes for RSA exponents. + Only enable this if you need compatibility with containers generated by older SPSDK versions." + template_value: false + default: false + skip_in_template: true + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK records. All SRKs must be of the same + type. Supported signing algorithms are: RSA-PSS, ECDSA, Dilithium or SM2. Supported hash algorithms: + sha256, sha384, sha512, sha3_256, sha3_384, sha3_512, sm3. Supported key sizes/curves: prime256v1, sec384r1, sec512r1, + rsa2048, rsa4096, dilithium3, sm2. Certificate may be of Certificate Authority. Dilithium algorithms are supported just + in new type of AHAB container" + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + srk_table_#2: + type: object + title: Second SRK Table + template_title: Configuration of AHAB SRK table in case that the double signing (ECC + PQC) + required: [srk_array] + skip_in_template: True + properties: + flag_ca: + type: boolean + title: CA Flag + description: + "CA Flag is used by AHAB to indicate if the SRK is allowed to sign other keys. + In AHAB CA Flag only affects the final SRKH (Super Root Key Hash) value burned into chip fuses. It is not used in the AHAB signing process itself. + This option exists only for compatibility with systems where fuses are already programmed. In most cases, this should remain false." + template_value: false + hash_algorithm: + type: string + title: Hash Algorithm + description: "Hash algorithm used for SRK records. If not specified, default algorithm based on key type will be used." + enum: + [ + default, + sha256, + sha384, + sha512, + sha3_256, + sha3_384, + sha3_512, + sm3, + ] + template_value: default + srk_array: + type: array + title: Super Root Key (SRK) table + description: + "Table containing the used SRK Dilithium records. All SRKs must be of the same + type. Supported signing algorithms are: Dilithium level 3. Supported hash algorithms: + sha3_256, sha3_384, sha3_512. Certificate may be of Certificate Authority." + minItems: 4 + maxItems: 4 + items: + type: string + title: SRK key + description: Path to SRK Key file. + format: file + template_value: + - my_srk_public_key0.pub + - my_srk_public_key1.pub + - my_srk_public_key2.pub + - my_srk_public_key3.pub + certificate: + type: string + title: The AHAB certificate + template_title: Optional configuration of AHAB Container Certificate (if not used, erase the section) + description: + The file that contains AHAB certificate. It could be used already prepared binary form signed by SRK, or it is possible to + use configuration YAML file of certificate and the AHAB export process it will export it itself. + format: file + template_value: my_ahab_certificate.bin + + iv_path: + type: string + title: IV file path + description: + "Used only for encrypted messages. Fixed size at 256 bits. If defined the encryption is used for this Signed message. + The HEX format is accepted." + format: file-or-hex-value + template_value: my_IV.txt + + message: + type: object + template_title: Settings of Message + required: [command] + properties: + cert_version: + type: [number, string] + title: Certificate version + description: Certificate version + format: number + template_value: 0x00 + cert_permission: + type: [number, string] + title: Certificate permission + description: Certificate permission, to be used in future. The stated permission must allow the operation requested by the signed message. + format: number + template_value: 0x00 + issue_date: + type: string + pattern: ^\d{4}-\d{2}$ + title: Issue date + description: "Optional Issue date of message, if not defined the current date is used. The format must be following: 'YYYY-MM'" + template_value: 2022-10 + uuid: + type: string + title: Device UUID + description: + Unique identifier of the chip. It could be retrieve by BLHOST command from chip or also the debug authentication protocol + could provide this value. Hex string format (hexadecimal string without '0x'). In case that the restriction on UUID is not needed + the field could be omitted. + template_value: "0000000000000000" + command: + oneOf: + - type: object + required: [RETURN_LIFECYCLE_UPDATE_REQ] + properties: + RETURN_LIFECYCLE_UPDATE_REQ: + type: [number, string] + title: Life Cycle + description: Value of life cycle to be moved on. The value 16 is used for OEM keys (FIELD_RETURN_OEM) and 32 for NXP keys(FIELD_RETURN_NXP). + template_value: 0x10 + + - type: object + template_title: The 'Write secure fuse request' is message for NXP use, not usable for OEM + required: [WRITE_SEC_FUSE_REQ] + properties: + WRITE_SEC_FUSE_REQ: + type: object + title: Secure Fuse + description: Description of secure fuse to write (burn) + required: [id, data] + properties: + id: + type: [number, string] + title: Fuse ID + description: Fuse ID (address), maximal 16 bit value is allowed. + template_value: 0x0 + flags: + type: [number, string] + title: Fuse flags + description: Fuse flags, maximal 8 bit value is allowed. + template_value: 0x0 + data: + type: array + title: Fuse data + description: Fuse data, maximal 32 bit value is allowed in each item. + minItems: 1 + items: + type: [number, string] + format: number + template_value: ["0xA5A5A5A5", "0x01"] + + - type: object + template_title: The 'Key store reprovisioning enable' + required: [KEYSTORE_REPROVISIONING_ENABLE_REQ] + properties: + KEYSTORE_REPROVISIONING_ENABLE_REQ: + type: object + title: Key store reprovisioning enable + description: + This message is sent to enable the re-provisioning of a key store. User must send this signed + message before trying to create a new key store in a chip that has already been provisioned. + Once this command is successfully sent a new key store can be created through the key store + open message. + required: [monotonic_counter, user_sab_id] + properties: + monotonic_counter: + type: [number, string] + title: Monotonic counter value + description: Current monotonic counter value. Can be retrieve with SAB Get Info API + template_value: 0x0 + user_sab_id: + type: [number, string] + title: User SAB id + description: User SAB id that will do the re-provisioning. Can be retrieve with SAB Get Info API + template_value: 0x0 + + - type: object + template_title: The 'Key exchange' + required: [KEY_EXCHANGE_REQ] + properties: + KEY_EXCHANGE_REQ: + type: object + title: Key exchange + description: + This message is used to perform a combined key agreement and key derivation operation. The + derived key will be stored in key storage as a new key. Only symmetric keys can be created with + this operation. Key attributes are set in the command, like others key creation APIs (Generate + key, Import key). + required: + - key_store_id + - key_exchange_algorithm + - salt_flags + - derived_key_grp + - derived_key_size_bits + - derived_key_type + - derived_key_lifetime + - derived_key_usage + - derived_key_permitted_algorithm + - derived_key_lifecycle + - derived_key_id + - private_key_id + properties: + key_store_id: + type: [number, string] + title: Key store ID + description: + Key store ID where to store the derived key. It must be the key store ID + related to the key management handle set in the command API + format: number + template_value: 0x0 + key_exchange_algorithm: + type: string + title: Key exchange algorithm + description: | + ECDH HKDF SHA256 KEY IMPORT 0x09020109 + ECDH HKDF SHA384 KEY IMPORT 0x0902010A + ECDH HKDF SHA ANY KEY IMPORT 0x090201FF + ECDH HKDF SHA256 0x89020109 + ECDH HKDF SHA384 0x8902010A + ECDH HKDF SHA ANY 0x890201FF + enum: + - ECDH HKDF SHA256 KEY IMPORT + - ECDH HKDF SHA384 KEY IMPORT + - ECDH HKDF SHA ANY KEY IMPORT + - ECDH HKDF SHA256 + - ECDH HKDF SHA384 + - ECDH HKDF SHA ANY + - HKDF SHA256 + - HKDF SHA384 + template_value: ECDH HKDF SHA256 KEY IMPORT + + salt_flags: + type: [number, string] + title: Salt Flags + description: + "Bit field indicating the requested operations:\n + Bit 0: Salt in step #1 (HKDF-extract) of HMAC based two-step key derivation process:\n + - 0: Use zeros salt\n + - 1:Use peer public key hash as salt\n + Bit 1: In case of ELE import, salt used to derive OEM_IMPORT_WRAP_SK and OEM_IMPORT_CMAC_SK:\n + - 0: Zeros string\n + - 1: Device SRKH.\n + Bit 2 to 15: Reserved" + format: number + template_value: 0x0 + derived_key_grp: + type: [number, string] + title: Derived key group + description: + Derived key group. 100 groups are available per key store. It must be a + value in the range [0; 99]. Keys belonging to the same group can be managed through the Manage + key group command + format: number + template_value: 0x0 + derived_key_size_bits: + type: number + title: Derived key size bits + description: Derived key size bits + enum: [128, 192, 224, 256, 384, 512] + template_value: 256 + derived_key_type: + type: string + title: Derived key type + description: "\n + Key type Value Key size in bits\n + AES 0x2400 128/192/256\n + HMAC 0x1100 224/256/384/512\n + OEM_IMPORT_MK_SK 0x9200 128/192/256 " + enum: [AES, HMAC, OEM_IMPORT_MK_SK] + template_value: AES + derived_key_lifetime: + type: string + title: Derived key lifetime + description: "\n + VOLATILE 0x00 Standard volatile key.\n + PERSISTENT 0x01 Standard persistent key.\n + PERMANENT 0xFF Standard permanent key.\n" + enum: [VOLATILE, PERSISTENT, PERMANENT] + template_value: PERSISTENT + derived_key_usage: + type: array + title: Derived key usage + description: + "Permission usage list. List of possible permissions:\n + Cache 0x00000004 Permission to cache the key in the ELE internal secure memory. + This usage is set by default by ELE FW for all keys generated or imported.\n + Encrypt 0x00000100 Permission to encrypt a message with the key. It could be cipher + encryption, AEAD encryption or asymmetric encryption operation.\n + Decrypt 0x00000200 Permission to decrypt a message with the key. It could be + cipher decryption, AEAD decryption or asymmetric decryption operation.\n + Sign message 0x00000400 Permission to sign a message with the key. It could be + a MAC generation or an asymmetric message signature operation.\n + Verify message 0x00000800 Permission to verify a message signature with the key. + It could be a MAC verification or an asymmetric message signature verification operation.\n + Sign hash 0x00001000 Permission to sign a hashed message with the key + with an asymmetric signature operation. Setting this permission automatically + sets the Sign Message usage.\n + Verify hash 0x00002000 Permission to verify a hashed message signature with + the key with an asymmetric signature verification operation.\n + Setting this permission automatically sets the Verify Message usage.\n + Derive 0x00004000 Permission to derive other keys from this key." + inItems: 0 + maxItems: 8 + items: + type: string + enum: + [ + Cache, + Encrypt, + Decrypt, + Sign message, + Verify message, + Sign hash, + Verify hash, + Derive, + ] + template_value: [Cache, Derive] + derived_key_permitted_algorithm: + type: string + title: Derived key permitted algorithm + description: "\n + HKDF SHA256 (HMAC two-step) 0x08000109\n + HKDF SHA384 (HMAC two-step) 0x0800010A" + enum: [HKDF SHA256, HKDF SHA384] + template_value: HKDF SHA256 + derived_key_lifecycle: + type: string + title: Derived key lifecycle + description: "\n + CURRENT 0x00 Key is usable in current lifecycle.\n + OPEN 0x01 Key is usable in open lifecycle.\n + CLOSED 0x02 Key is usable in closed lifecycle.\n + CLOSED and LOCKED 0x04 Key is usable in closed and locked lifecycle." + enum: [CURRENT, OPEN, CLOSED, LOCKED] + template_value: CURRENT + derived_key_id: + type: [number, string] + title: Derived key ID + description: "It could be:\n + - Wanted key identifier of the generated key: only supported by persistent and permanent keys\n + - 0x00000000 to let the FW chose the key identifier: supported by all keys (all persistence levels)" + format: number + template_value: 0x0 + private_key_id: + type: [number, string] + title: Private key ID + description: Identifier in the ELE key storage of the private key to use with the peer public key during the key agreement process + format: number + template_value: 0x0 + input_peer_public_key_digest: + type: [number, string] + title: Input peer public key digest + description: The algorithm used to generate the digest must be SHA256 + template_value: "0x0000000000000000000000000000000000000000000000000000000000000000" + input_user_fixed_info_digest: + type: [number, string] + title: Input user fixed info digest + description: The algorithm used to generate the digest must be SHA256 + template_value: "0x0000000000000000000000000000000000000000000000000000000000000000" + oem_private_key: + type: string + title: OEM Private Key for ECDH + description: + "Path to OEM P256 private key file (PEM format) used for ECDH key agreement. + This key will be used with NXP_PROD_KA_PUB to derive the shared secret and subsequent keys. + If provided along with nxp_prod_ka_pub, automatic ECDH key derivation will be performed." + format: file + template_value: oem_p256_private_key.pem + nxp_prod_ka_pub: + type: [number, string] + title: NXP Production Key Agreement Public Key + description: "NXP production key agreement public key. + Used together with oem_private_key for ECDH key derivation." + format: file + template_value: nxp_prod_ka.pub + srkh: + type: [number, string] + title: Super Root Key Hash + description: Optional Super root key hash is used if Salt flags that requires in Exchange keys algorithms. + template_value: "0x00000000000000000000000000000000" + + - type: object + template_title: The 'Debug Authentication request' is message for DAT process, do not use it individually + required: [DAT_AUTHENTICATION_REQ] + properties: + DAT_AUTHENTICATION_REQ: + type: object + title: Debug Authentication response + description: Debug authentication response for DAT procedure + required: [challenge_vector] + properties: + challenge_vector: + type: [number, string] + title: Challenge vector + description: Challenge vector 32 bytes got's from the DAC. + template_value: 0x1234567812345678123456781234567812345678123456781234567812345678 + authentication_beacon: + type: [number, string] + title: Authentication beacon + description: Authentication beacon, keep it 0 till it will be implemented on HW. + template_value: 0x0 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tlv_blob.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tlv_blob.yaml new file mode 100644 index 0000000..958b7d2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tlv_blob.yaml @@ -0,0 +1,286 @@ +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +--- +output_file: + type: object + title: Basic Settings + properties: + output: + type: string + title: Output Image name + description: The path for result binary file. + format: file_name + template_value: tlv.bin + required: [output] + +tlv: + type: object + template_title: Settings of TLV + required: [command] + properties: + command: + oneOf: + - type: object + required: [KEY_IMPORT] + properties: + KEY_IMPORT: + type: object + title: Key import TLV + description: + This TLV is designed to import a symmetric key or a private key of an asymmetric key pair. The imported key must be encrypted + (except specific cases like SRKH). The key used to decrypt the imported key must have the following attributes; + - DECRYPT usage; + - A wrapping key algorithm as permitted algorithm (detailed in next sections). + User must import symmetric key or private key from an asymmetric key pair. For RSA asymmetric + private keys, it must be the concatenation of private exponent followed by the modulus. + To be valid, all key attributes of the imported key must be coherent. If attributes are invalid, an error is returned. + allOf: + - required: + - key_id + - permitted_algorithm + - key_usage + - key_type + - key_size_bits + - key_lifetime + - key_lifecycle + - oem_mk_sk_key_id + - key_wrapping_algorithm + - oneOf: + - required: + - wrapped_key + - signature + - required: + - import_key + - oem_import_mk_sk_key + + properties: + key_id: + type: [number, string] + title: Key ID + description: + Key store ID where to store the imported key. It must be the key store ID + related to the key management handle set in the command API. If set to 0, the actual ID is determined by ELE. + format: number + template_value: 0x0 + permitted_algorithm: + type: string + title: Permitted algorithm + description: "Permitted algorithm of the imported key. Supports hash, MAC, cipher, AEAD, signature, and key exchange algorithms." + enum: + # Hash Algorithms + - MD5 + - SHA1 + - SHA224 + - SHA256 + - SHA384 + - SHA512 + - SHA3_224 + - SHA3_256 + - SHA3_384 + - SHA3_512 + - SHAKE256 + # MAC Algorithms + - HMAC SHA256 + - HMAC SHA384 + - CMAC + # Cipher Algorithms + - ECB NO PADDING + - CBC NO PADDING + - CTR + - CFB + - OFB + - ALL CIPHER + # AEAD Algorithms + - CCM + - GCM + - CHACHA20_POLY1305 + - ALL AEAD + # Signature Algorithms + - ECDSA SHA224 + - ECDSA SHA256 + - ECDSA SHA384 + - ECDSA SHA512 + - RSA PKCS1 V1.5 SHA224 + - RSA PKCS1 V1.5 SHA256 + - RSA PKCS1 V1.5 SHA384 + - RSA PKCS1 V1.5 SHA512 + - RSA PKCS1 V1.5 SHA ANY + - RSA PKCS1 PSS MGF1 SHA224 + - RSA PKCS1 PSS MGF1 SHA256 + - RSA PKCS1 PSS MGF1 SHA384 + - RSA PKCS1 PSS MGF1 SHA512 + - RSA PKCS1 PSS MGF1 SHA ANY + - RSA PKCS1 ALL + - ED25519PH + - ED448PH + - PURE EDDSA + - ALL EDDSA + # Public Key Attestation + - CMAC ATTESTATION + - ECDSA SHA224 ATTESTATION + - ECDSA SHA256 ATTESTATION + - ECDSA SHA384 ATTESTATION + - ECDSA SHA512 ATTESTATION + # Asymmetric Encryption/Decryption + - RSA PKCS1 V1.5 CRYPT + - RSA PKCS1 OAEP SHA1 + - RSA PKCS1 OAEP SHA224 + - RSA PKCS1 OAEP SHA256 + - RSA PKCS1 OAEP SHA384 + - RSA PKCS1 OAEP SHA512 + # Key Exchange + - ECDH HKDF SHA256 KEY IMPORT + - ECDH HKDF SHA384 KEY IMPORT + - ECDH HKDF SHA ANY KEY IMPORT + - ECDH HKDF SHA256 + - ECDH HKDF SHA384 + - ECDH HKDF SHA ANY + template_value: SHA256 + key_usage: + type: array + title: Derived key usage + description: + "Permission usage list. List of possible permissions:\n + Cache 0x00000004 Permission to cache the key in the ELE internal secure memory. + This usage is set by default by ELE FW for all keys generated or imported.\n + Encrypt 0x00000100 Permission to encrypt a message with the key. It could be cipher + encryption, AEAD encryption or asymmetric encryption operation.\n + Decrypt 0x00000200 Permission to decrypt a message with the key. It could be + cipher decryption, AEAD decryption or asymmetric decryption operation.\n + Sign message 0x00000400 Permission to sign a message with the key. It could be + a MAC generation or an asymmetric message signature operation.\n + Verify message 0x00000800 Permission to verify a message signature with the key. + It could be a MAC verification or an asymmetric message signature verification operation.\n + Sign hash 0x00001000 Permission to sign a hashed message with the key + with an asymmetric signature operation. Setting this permission automatically + sets the Sign Message usage.\n + Verify hash 0x00002000 Permission to verify a hashed message signature with + the key with an asymmetric signature verification operation.\n + Setting this permission automatically sets the Verify Message usage.\n + Derive 0x00004000 Permission to derive other keys from this key." + inItems: 0 + maxItems: 8 + items: + type: string + enum: + [ + Cache, + Encrypt, + Decrypt, + Sign message, + Verify message, + Sign hash, + Verify hash, + Derive, + ] + template_value: [Cache, Derive] + key_type: + type: string + title: Import key type + description: "\n + Key type Value Key size in bits\n + AES 0x2400 128/192/256\n + HMAC 0x1100 224/256/384/512\n + Derived key 0x1200 256/384\n + OEM_IMPORT_MK_SK 0x9200 128/192/256\n + ECC NIST 0x7112 256/384/521\n + RSA 0x7001 2048/3072/4096" + enum: + [AES, HMAC, Derived key, OEM_IMPORT_MK_SK, ECC NIST, RSA] + template_value: AES + key_size_bits: + type: number + title: Import key size bits + description: Import key size bits + enum: [128, 192, 224, 256, 384, 512, 521, 2048, 3072, 4096] + template_value: 256 + key_lifetime: + type: string + title: Imported key lifetime + description: "\n + ELE_KEY_IMPORT_VOLATILE 0xC0020000 Standard volatile key.\n + ELE_KEY_IMPORT_PERSISTENT 0xC0020001 Standard persistent key.\n + ELE_KEY_IMPORT_PERMANENT 0xC00200FF Standard permanent key.\n" + enum: + [ + ELE_KEY_IMPORT_VOLATILE, + ELE_KEY_IMPORT_PERSISTENT, + ELE_KEY_IMPORT_PERMANENT, + ] + template_value: ELE_KEY_IMPORT_PERSISTENT + key_lifecycle: + type: string + title: Imported key lifecycle + description: "\n + CURRENT 0x00 Key is usable in current lifecycle.\n + OPEN 0x01 Key is usable in open lifecycle.\n + CLOSED 0x02 Key is usable in closed lifecycle.\n + OPENED and CLOSED 0x03 Key is usable in opened and closed lifecycle.\n + CLOSED and LOCKED 0x04 Key is usable in closed and locked lifecycle." + enum: [CURRENT, OPEN, CLOSED, OPEN_CLOSED, LOCKED] + template_value: CURRENT + oem_mk_sk_key_id: + type: [number, string] + title: OEM_IMPORT_MK_SK key ID + description: + Key store ID where is stored the OEM_IMPORT_MK_SK key. It must be the key store ID + related to the key management handle set in the command API + format: number + template_value: 0x0 + key_wrapping_algorithm: + type: string + title: Imported key wrapping algorithm + description: "\n + RFC3394 - RFC 3394 wrapping\n + AES_CBC - AES-CBC wrapping (padding: ISO7816-4 padding)" + enum: [RFC3394, AES_CBC] + template_value: RFC3394 + iv: + type: [number, string] + title: Initial vector + description: IV to use for CBC wrapping. Not used if 'wrapping algorithm' not equal 0x02. + template_value: "0x00000000000000000000000000000000" + signing_algorithm: + type: string + title: Wrapped key signing algorithm + description: "Algorithm used to sign the blob itself. Field “Signature” of this blob. It must be: 0x01 (CMAC)" + enum: [CMAC] + template_value: CMAC + wrapped_key: + type: [number, string] + title: Wrapped key + description: + "Private key data in encrypted format as defined by the 'Wrapping Algorithm'. + Key used to do the encryption must be OEM_IMPORT_WRAP_SK derived from OEM_IMPORT_MK_SK. + Instead of 'wrapped_key' & 'signature' it could be used 'import_key' & 'oem_import_mk_sk_key'." + template_value: "0x00000000" + signature: + type: [number, string] + title: Signature + description: + "Signature of all previous fields of this blob including + the signature tag (0x5E) and signature length fields. Key used to do the signature must be + OEM_IMPORT_CMAC_SK derived from OEM_IMPORT_MK_SK. + Instead of 'wrapped_key' & 'signature' it could be used 'import_key' & 'oem_import_mk_sk_key'." + template_value: "0x00000000000000000000000000000000" + import_key: + type: [number, string] + title: Raw import key + description: + "Raw private key that will be wrapped and encrypted by OEM_IMPORT_MK_SK key that must be also provided. + Instead of 'import_key' & 'oem_import_mk_sk_key' it could be used 'wrapped_key' & 'signature'." + template_value: raw_key.pem + oem_import_mk_sk_key: + type: [number, string] + title: OEM_IMPORT_MK_SK Key + description: + "OEM_IMPORT_MK_SK key used to wrap and encrypt the raw key. + Instead of 'import_key' & 'oem_import_mk_sk_key' it could be used 'wrapped_key' & 'signature'." + template_value: "0x00000000000000000000000000000000" + srkh: + type: [number, string] + title: Super Root Key Hash + description: Optional Super root key hash is used if Salt flags that requires in Exchange keys algorithms. + template_value: "0x00000000000000000000000000000000" diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tz.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tz.yaml new file mode 100644 index 0000000..a31a838 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_tz.yaml @@ -0,0 +1,160 @@ +# Copyright 2021-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +tz: + type: object + required: [tzpOutputFile, trustZonePreset] + properties: + tzpOutputFile: + type: string + title: Optional name of output file for TZ binary + description: The name of output binary file with Trust Zone data. + format: file_name + template_value: my_tz_file.bin + + trustZonePreset: + type: object + title: Customization of standard preset values + description: Trust Zone preset dictionary, with trust zone configuration. + +tz_v2: + type: object + required: [tzpOutputFile, trustZoneRecords] + properties: + tzpOutputFile: + type: string + title: Optional name of output file for TZ binary + description: The name of output binary file with Trust Zone data. + format: file_name + template_value: my_tz_file.bin + + trustZoneRecords: + type: array + title: List of Trust Zone configuration Records + description: > + Trust Zone preset dictionary, with trust zone configuration. + + The ROM executes following read/write sequence for every data record: + + 1. Reads DATA from ADDRESS + + 2. Calculates RESULT = (DATA AND ~MASK) OR (VALUE AND MASK) + + 3. Writes Result/Value into Address + + 4. Reads DATA from ADDRESS + + 5. Compare values (DATA AND MASK) and (VALUE AND MASK) + + 6. Repeats steps 4 and 5 + + 7. If compared values are not equal, the boot process fails + + + Many peripherals have registers, which combines control and status bits. In some cases these registers requires specific handling. For example registers, where reading register can delete some status bits or read value is different from value, which was written. In this case user can skip some steps in the sequence above (steps 1-7) to avoid unwanted behavior. + 32-bit platforms have peripheral registers address aligned to word boundary (bits bit1:bit0 are always zero). Therefore, these two bits together with mask value can be utilized to define, which steps will be skipped during memory address/register modification. + There are three ways how user can modify read/write data sequence: + + + Modification of read/write Data Sequence: + + Mask = 0: If Mask is set to 0, the read and mask with all zero bits, prior to value is modified, doesn't make any sense because all bits are cleared. Therefore, these steps are skipped (steps 1-2) and Value is directly written into destination address. + + b0 = 1: If bit0 in address is set to "1", the readback operation is skipped (steps 4-7) + + b1 = 1: If bit1 in address is set to "1", the write operation is skipped (steps 1-3) + + All possible combinations are summarized in Table below: + + + | Mode | skip_write | skip_readback | mask | Operations with register | Skipped steps | + + |--------------------|------------|---------------|----------|--------------------------|---------------| + + | read-modify-write | False | False | non-zero | read+write+read+read | none | + + | + readback | | | | | | + + | write + readback | False | False | 0x0 | write+read+read | 1-2 | + + | read-modify-write | False | True | non-zero | read+write | 4-7 | + + | write | False | True | 0x0 | write | 3-7 | + + + Usage Examples + -------------- + Read-modify-write + Readback Sequence + + This sequence is standard sequence and can be used to modify part or whole register/memory address. + For example, set SAU->RNR (0xE000EDD8) to 0x7 the TZ-M preset data is: + + Address Mask Value + 0xE000EDD8 0xFF 0x7 + + + Write+Readback Sequence + + In case user wants to configure whole register/memory address the mask can be set to 0x0. In this case steps 1-2 are skipped, and value is directly written into register. Following readback verifies that register/memory address contains desired value. + Let consider the same example as above. Then preset data is + + Address Mask Value + 0xE000EDD8 0x0 0x7 + + + Configuring special peripheral/core register + + Let’s consider setting bit3 in SCB->AIRCR (0xE000ED0C) register. This register contains specific bitfield VECTKEY/VECTKEYSTAT (bits 31-16). When register is read, this bitfield contains value 0xFA05 while when register is written, this bitfield needs to be set to 0x05FA. This fact doesn’t allow to use standard read-modify-write + readback sequence. But this register can be modified by read-modify-write sequence: + + Address Mask Value + 0xE000ED0D 0xFFFF0008 0x05FA0008 + + + If validation of written value is required, it can be done by additional read only sequence: + + Address Mask Value + 0xE000ED0E 0xFFFF0008 0xFA050008 + + This complex example shows that TZ-M preset data can be used not only to configure some registers or memory addresses, but it can be also used to verify that certain register or memory address contains desired value. + + minItems: 1 + items: + type: object + required: [address, value] + properties: + address: + type: [number, string] + title: Memory or Register Address + description: Hexadecimal or decimal address of register for Trust Zone configuration + format: number + template_value: "0xE000EDD8" + mask: + type: [number, string] + title: Mask for register write/read operation + description: Bit mask to control which bits of the register will be modified during Trust Zone configuration + format: number + template_value: "0x00000007" + value: + type: [number, string] + title: Value for register write/read operation + description: Value to be written to the specified address with the given mask + format: number + template_value: "0x00000007" + skip_write: + type: boolean + title: Skip Write Operation + description: Flag to control whether write operation (steps 1-3) should be skipped during Trust Zone configuration + default: false + template_value: false + skip_readback: + type: boolean + title: Skip Readback Operation + description: Flag to control whether readback verification (steps 4-7) should be skipped during Trust Zone configuration + default: false + template_value: false + + + + + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_wpc.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_wpc.yaml new file mode 100644 index 0000000..eacc8c2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_wpc.yaml @@ -0,0 +1,137 @@ +# Copyright 2024-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +el2go: + type: object + properties: + url: + type: string + title: "EdgeLock2Go URL" + description: "URL pointing to the root of EL2GO server" + template_value: "https://api.edgelock2go.com" + qi_id: + type: [number, string] + title: "Customer Qi ID" + description: "Customer's (product line) Qi ID registered in EL2GO" + template_value: 123456 + api_key: + type: string + title: "EL2GO API Key" + description: "REST API key used for user authentication in EL2GO. + You may use: + 1) path to a file with the key on the first line: ~/.el2go/wpc_token.txt (~ is interpreted as your HOME) + 2) environment variable with the key: $MY_EL2GO_KEY + 3) environment variable containing a path to the key file: $MY_KEY_FILE + 4) directly your API key in plain text (not recommended)" + template_value: abcxyz123 + timeout: + type: number + title: "Timeout for EL2GO API" + description: "Timeout for EL2GO API in seconds. Default is 60 seconds" + template_value: 60 + required: [url, qi_id, api_key] + +mboot: + type: object + description: Select one of the communication interfaces. For specification details please see 'blhost --help' + properties: + port: + type: string + title: Serial line interface + template_value: com1 + usb: + type: string + title: USB interface + template_value: 0x1fc9:0x014f + sdio: + type: string + title: SDIO Interface + template_value: /dev/mcu-sdio + lpcusbsio: + type: string + title: USBSIO Interface + template_value: spi0 + can: + type: string + title: CAN Interface + template_value: can1 + plugin: + type: string + title: Plugin Interface + template_value: identifier=,param1=value1,param2=value2 + oneOf: + - required: [port] + - required: [usb] + - required: [sdio] + - required: [lpcusbsio] + - required: [can] + - required: [plugin] + +model: + type: object + properties: + model_dir: + type: string + format: dir + title: "Model directory" + description: "Path to directory containing the model (config.yaml)" + template_value: + required: [model_dir] + +full_config: + type: object + properties: + family: + type: string + title: "Target family" + description: "Name of the target family" + template_value: mwct2xxxs + service_type: + type: string + title: "Name of the WPC service adapter" + description: "Name of the WPC service adapter" + service_parameters: + type: object + title: "Parameters for the WPC service adapter" + description: "Parameters for the WPC service adapter" + properties: {} + target_type: + type: string + title: "Name of the target adapter" + description: "Name of the target adapter" + target_parameters: + type: object + title: "Parameters for the target adapter" + description: "Parameters for the target adapter" + properties: {} + required: + [service_type, service_parameters, target_type, target_parameters, family] + +service_config: + type: object + properties: + service_type: + type: string + title: "Name of the WPC service adapter" + description: "Name of the WPC service adapter" + service_parameters: + type: object + title: "Parameters for the WPC service adapter" + description: "Parameters for the WPC service adapter" + properties: {} + required: [service_type, service_parameters] + +target_config: + type: object + properties: + target_type: + type: string + title: "Name of the target adapter" + description: "Name of the target adapter" + target_parameters: + type: object + title: "Parameters for the target adapter" + description: "Parameters for the target adapter" + properties: {} + required: [target_type, target_parameters] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_xmcd.yaml b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_xmcd.yaml new file mode 100644 index 0000000..bd69633 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/jsonschemas/sch_xmcd.yaml @@ -0,0 +1,35 @@ +# Copyright 2022-2025 NXP +# +# SPDX-License-Identifier: BSD-3-Clause + +memory_type: + type: object + required: [mem_type] + properties: + mem_type: + type: string + title: Memory type + description: Specify type of memory used by XMCD description. + enum: [flexspi_ram, semc_sdram, xspi_ram] + template_value: flexspi_ram + +config_type: + type: object + required: [config_type] + properties: + config_type: + type: string + title: Configuration type + description: Specify type of configuration used by XMCD description. + enum: [full, simplified] + template_value: simplified + +xmcd: + type: object + properties: + xmcd_settings: + type: object + title: Settings of XMCD + description: External memory configuration settings for selected MCU. + + required: [xmcd_settings] diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/readme.md b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/readme.md new file mode 100644 index 0000000..e0a64f3 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/data/readme.md @@ -0,0 +1,230 @@ +# NXP Secure Provisioning SDK Database + The data folder in package contains all data that is used by SPSDK tool. + +## Organization of database + - common: Folder that contains common data for the general operation of SPSDK as defaults for all devices. + - devices: Folder with all supported devices by SPSDK. the name of folder is unique name of supported family. Each family folder must contains at least 'database.yaml' file + with correct format. + - jsonschemas: Folder with JSON SCHEMAS used by individual SPSDK tools. Format of file depends on each tool, some of tool is using standard JSON SCHEMA format, rest is + contains chunks of JSON SCHEMAs organized as a big dictionary. + +## Glossary + - SPSDK_Database: The base SPSDK class to handle with database. It has Singleton behavior so it could created any time without duplicate load of database. + - SPSDK_Database cache: See chapter "Database caching" + - Device: Name of the device. The exact name of the device is specified by name of the folder in 'devices' folder. + - Revision: Revision of the device. Each device has to have at least one revision. + - Feature: Device feature. By feature is organized the whole database to support individual tools. Example of features: mbi (Master BOot Image), tp (Trust Provisioning) etc. The whole list contains the SPSDK_Database class. + + +## Device data composition + The device data for the using by SPSDK are organized by family chip revisions, the database method 'get_device_features()' is designed as a main way to get data from database. + +### Mandatory fields in device 'database.yaml' for fully defined devices + - revisions: The dictionary with all supported revisions. In case that the revision doesn't contains any changes to standard features it enough to define empty dictionary + - latest: The name of latest revision of the device. + - features: The dictionary with all supported features by device. The final device feature is composed from the defaults from 'common/database_defaults.yaml' updated by information in '{device_name}/database.yaml' + +Example of newly created device: +``` +revisions: + rev0: {} + rev1: + features: + feature1: + key1: override_value_for_this_revision + rev2: + features: + feature1: + key1: override_value_for_this_revision + feature2: + key1: override_value_for_this_revision + +latest: rev2 +features: +feature1: +key1: value +feature2: +key1: value +``` + +### Mandatory fields in device 'database.yaml' for alias defined devices + - alias: The name of a device that is used as origin. + +In aliased devices is possible to define also all definitions from 'Mandatory fields in device 'database.yaml' for fully defined devices' chapter. +To define a new revision in aliased device the key word 'alias' must be used also in newly defined revision: + +Example of created a new device as a alias of existing device. In example there is also created new revision. +``` +alias: origin_device +revisions: + new_rev: + alias: origin_device_revision + features: + feature1: + key1: override_value_for_this_revision + +latest: new_rev +``` + +### Steps to create final revision +The SPSDK database flow to get the final data for requested revision. + +**The code without alias devices performs the following steps:** +1. Load device features +2. Load default features +3. For all defined device features do following: + 1. Get default feature values + 2. Updated default feature values by device feature values +4. For all defined device revisions update gotten feature data by revision updates + +Here is example of simple data to show creating of final revision data + +**Default database file => common/default_database.yaml** +``` +revisions: {} +latest: latest + +features: + feature1: + key1: value_default + feature2: + key1: value_default + feature3: {} +``` + +**Device 1 database file => devices/device1/database.yaml** +``` +revisions: + rev1: {} + rev2: + features: + feature1: + key2: rev2_value +latest: rev2 + +features: + feature1: + key2: value +``` + +**Device 2 database file => devices/device2/database.yaml** +``` +revisions: + rev1: + features: + feature1: + key1: rev1_value +latest: rev1 + +features: + feature1: + key1: value + feature2: {} +``` + +--- +--- +**The final revisions data for device 1:** +``` +rev1: + features: + feature1: + key1: value_default + key2: value +rev2: + features: + feature1: + key1: value_default + key2: rev2_value +``` + +**The final revisions data for device 2:** +``` +rev1: + features: + feature1: + key1: rev1_value + feature2: + key1: value_default +``` + +--- +--- +**The code with alias device do following steps:** +1. Load origin device +2. Load device features +3. If the device features are present, all origin revision are updated by them +4. If the device revisions are present, update the revision data from step 3 by them +5. If there is a new revision defined (must contains alias key), then is copied from aliased revision and update by possible new revision values +6. If a new latest revision field is available, also this one is updated + +**Here is example of new aliased device from previous data with new created revision:** +``` +alias: device1 + +revisions: + new_rev: + alias: rev2 + features: + feature1: + key2: new_rev_value +latest: new_rev +``` +**The final revisions data for new aliased device:** +``` +rev1: + features: + feature1: + key1: value_default + key2: value +rev2: + features: + feature1: + key1: value_default + key2: rev2_value +new_rev: + features: + feature1: + key1: value_default + key2: new_rev_value +``` + +### Revision data access in code +The revision class contains few basic methods to get data from database including type hints and type validation. +Each "get_" has two mandatory parameters: +- feature: Name of the feature to be data gets from +- key: What is union of simple string key or list of strings that is used as a path to get into nested values + +**List of supported "get_" methods:** +- get_value: Get general value without type checking +- get_bool: Get boolean +- get_int: Get integer +- get_str: Get string +- get_dict: Get dictionary +- get_list: Get list +- get_file_path: Get file path. Path is relative to device folder. In case of aliased device and non existing file in device folder, + it automatically used device path of aliased device. The method also check if the file exists. + + +## Database Caching +By default, the SPSDK database is cached on the local machine to improve load performance. Each SPSDK instance on the machine has its own independent cache. + An invalidation mechanism is also in place to detect changes in the original data and update the cache accordingly. If necessary, the cache can be disabled + by setting the environment variable "SPSDK_CACHE_DISABLED_{version}" to True, where {version} represents the current version of SPSDK. + +You can now specify a custom path for the SPSDK cache by setting the system environment variable "SPSDK_CACHE_FOLDER". This allows you to control where the cache is stored on your system. + +The database itself also maintains a simple cache for opened configuration files to prevent multiple loads during the application's runtime. The content of these runtime configuration files is checked upon exit of SPSDK, and + the main cache is updated if new files are found. + +## Support for Restricted Data +The database also supports a mechanism to load restricted data (usually chips and features under an NDA deal). The structure of the restricted data folders/files + must adhere to the standard database. If the restricted data is used, the database performs the following steps: +- Checks if "database_defaults.yaml" is present in the restricted data and uses it instead of the standard one if available. +- Checks if "database.yaml" is present in the restricted device data and uses it instead of the standard one if available. This check is performed for each device. +- If the restricted data contains a file with the same name as a standard database folder, the restricted file is used instead of the standard one. + +## Support for Database Add-On Data +Add-ons are designed to add any customer data to the standard/restricted database. The structure of the add-on data folders/files must adhere to the standard database. + If the add-on data is used, the database performs the following steps: +- Checks if "database.yaml" is present in the add-on device data and updates the loaded database with these add-ons. +- Add-ons also allow the addition of new data files. Files with the same names as those in the restricted/standard database are ignored. diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/py.typed b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/py.typed new file mode 100644 index 0000000..e69de29 diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_ebnf_grammar.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_ebnf_grammar.txt new file mode 100644 index 0000000..50d8ba6 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_ebnf_grammar.txt @@ -0,0 +1,174 @@ +/* BD file grammar in EBNF form */ +command_file ::= pre_section_block* section_block* + +pre_section_block ::= options_block +| constants_block +| sources_block +| keyblob_block + +options_block ::= OPTIONS '{' option_def* '}' + +option_def ::= IDENT '=' const_expr ';' + +constants_block ::= CONSTANTS '{' constant_def* '}' + +constant_def ::= IDENT '=' bool_expr ';' + +sources_block ::= SOURCES '{' source_def* '}' + +source_def ::= IDENT '=' source_value ( '(' option_list? ')' )? ';' + +source_value ::= STRING_LITERAL +| EXTERN '(' int_const_expr ')' + +option_list ::= IDENT '=' const_expr (',' IDENT '=' const_expr )* + +keyblob_block ::= KEYBLOB '(' int_const_expr ')' '{' keyblob_contents '}' + +keyblob_contents ::= '(' option_list* ')' + +section_block ::= SECTION '(' int_const_expr section_options? ')' section_contents + +section_options ::= ';' option_list? + +section_contents ::= '{' statement* '}' +| '<=' source_name ';' + +statement ::= basic_stmt ';' +| from_stmt +| if_stmt +| keywrap_stmt + +basic_stmt ::= load_stmt +| load_ifr_stmt +| call_stmt +| jump_sp_stmt +| mode_stmt +| message_stmt +| erase_stmt +| enable_stmt +| reset_stmt +| encrypt_stmt +| keystore_stmt + +load_stmt ::= LOAD load_opt load_data load_target + +load_opt ::= IDENT +| int_const_expr +| empty + +load_data ::= int_const_expr +| STRING_LITERAL +| IDENT +| section_list +| section_list FROM IDENT +| BINARY_BLOB + +load_target ::= '>' '.' +| '>' address_or_range + +section_list ::= section_ref (',' section_ref )* + +section_ref ::= '~' SECTION_NAME +| SECTION_NAME + +erase_stmt ::= ERASE address_or_range +| ERASE ALL + +address_or_range ::= int_const_expr ( '..' int_const_expr)? + +symbol_ref ::= IDENT'?' ':' IDENT + +load_ifr_stmt ::= LOAD IFR int_const_expr '>' int_const_expr + +call_stmt ::= call_type call_target call_arg? + +call_type ::= CALL +| JUMP + +call_target ::= int_const_expr +| symbol_ref +| IDENT + +call_arg ::= '(' int_const_expr? ')' + +jump_sp_stmt ::= JUMP_SP int_const_expr call_target call_arg? + +from_stmt ::= FROM IDENT '{' in_from_stmt* '}' + +in_from_stmt ::= basic_stmt ';' +| if_stmt + +mode_stmt ::= MODE int_const_expr + +message_stmt ::= message_type STRING_LITERAL + +message_type ::= INFO +| WARNING +| ERROR + +keystore_stmt ::= KEYSTORE_TO_NV mem_opt address_or_range +| KEYSTORE_FROM_NV mem_opt address_or_range + +mem_opt ::= IDENT +| '@' int_const_expr +| empty + +if_stmt ::= IF bool_expr '{' statement* '}' else_stmt? + +else_stmt ::= ELSE '(' statement* ')' +| ELSE if_stmt + +keywrap_stmt ::= KEYWRAP '(' int_const_expr ')' '{' statement* '}' + +encrypt_stmt ::= ENCRYPT '(' int_const_expr ')' '{' statement* '}' + +enable_stmt ::= ENABLE AT_INT_LITERAL int_const_expr + +reset_stmt ::= RESET + +ver_check_stmt ::= VERSION_CHECK sec_or_nsec int_const_expr + +sec_or_nsec ::= SEC +| NSEC + +const_expr ::= STRING_LITERAL +| bool_expr + +int_const_expr ::= expr + +bool_expr ::= bool_expr '<' bool_expr +| bool_expr '<=' bool_expr +| bool_expr '>' bool_expr +| bool_expr '>=' bool_expr +| bool_expr '==' bool_expr +| bool_expr '!=' bool_expr +| bool_expr '&&' bool_expr +| bool_expr '||' bool_expr +| '(' bool_expr ')' +| int_const_expr +| '!' bool_expr +| DEFINED '(' IDENT ')' +| IDENT '(' source_name ')' + +expr ::= expr '+' expr +| expr '-' expr +| expr '*' expr +| expr '/' expr +| expr '%' expr +| expr '<<' expr +| expr '>>' expr +| expr '&' expr +| expr '|' expr +| expr '^' expr +| expr '.' INT_SIZE +| '(' expr ')' +| INT_LITERAL +| IDENT +| SYMBOL_REF +| unary_expr +| SIZEOF '(' SYMBOL_REF ')' +| SIZEOF '(' IDENT ')' + +unary_expr ::= '+' expr +| '-' expr diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_grammer.txt b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_grammer.txt new file mode 100644 index 0000000..c8718ba --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/spsdk/sbfile/sb2/bd_grammer.txt @@ -0,0 +1,210 @@ +/* BD file grammar in BNF form */ +command_file ::= pre_section_block section_block + +pre_section_block ::= pre_section_block options_block +| pre_section_block constants_block +| pre_section_block sources_block +| pre_section_block keyblob_block +| empty + +options_block ::= OPTIONS '{' option_def '}' + +option_def ::= option_def IDENT '=' const_expr ';' +| empty + +constants_block ::= CONSTANTS '{' constant_def '}' + +constant_def ::= constant_def IDENT '=' bool_expr ';' +| empty + +sources_block ::= SOURCES '{' source_def '}' + +source_def ::= source_def IDENT '=' source_value ';' +| source_def IDENT '=' source_value '(' source_attr_list ')' ';' +| empty + +source_value ::= STRING_LITERAL +| EXTERN '(' int_const_expr ')' + +source_attr_list ::= option_list +| empty + +option_list ::= IDENT '=' const_expr ',' option_list +| IDENT '=' const_expr + +keyblob_block ::= KEYBLOB '(' int_const_expr ')' '{' keyblob_contents '}' + +# ----------------------------- Original keyblob grammar ------------- +# keyblob_contents ::= keyblob_contents '(' keyblob_options_list ')' +# | empty + +# keyblob_options_list ::= keyblob_options +# | empty + +# keyblob_options ::= IDENT '=' const_expr ',' keyblob_options +# | IDENT '=' const_expr + +# ----------------------------- New keyblob grammar ------------------ +keyblob_contents ::= '(' keyblob_options ')' + +keyblob_options ::= IDENT '=' const_expr ',' keyblob_options +| IDENT '=' const_expr + +section_block ::= section_block SECTION '(' int_const_expr section_options ')' section_contents +| empty + +section_options ::= ';' option_list +| ';' +| empty + +section_contents ::= '{' statement '}' +| '<=' source_name ';' + +statement ::= statement basic_stmt ';' +| statement from_stmt +| statement if_stmt +| statement encrypt_block +| statement keywrap_block +| empty + +basic_stmt ::= load_stmt +| load_ifr_stmt +| call_stmt +| jump_sp_stmt +| mode_stmt +| message_stmt +| erase_stmt +| enable_stmt +| reset_stmt +| keystore_stmt + +load_stmt ::= LOAD load_opt load_data load_target + +load_opt ::= IDENT +| int_const_expr +| empty + +load_data ::= int_const_expr +| STRING_LITERAL +| SOURCE_NAME +| section_list +| section_list FROM SOURCE_NAME +| BINARY_BLOB + +load_target ::= '>' '.' +| '>' address_or_range +| empty + +section_list ::= section_list ',' section_ref +| section_ref + +section_ref ::= '~' SECTION_NAME +| SECTION_NAME + +erase_stmt ::= ERASE address_or_range +| ERASE ALL + +address_or_range ::= int_const_expr +| int_const_expr '..' int_const_expr + +symbol_ref ::= SOURCE_NAME'?' ':' IDENT + +load_ifr_stmt ::= LOAD IFR int_const_expr '>' int_const_expr + +call_stmt ::= call_type call_target call_arg + +call_type ::= CALL +| JUMP + +call_target ::= int_const_expr +| symbol_ref +| IDENT + +call_arg ::= '(' ')' +| '(' int_const_expr ')' +| empty + +jump_sp_stmt ::= JUMP_SP int_const_expr call_target call_arg + +from_stmt ::= FROM IDENT '{' in_from_stmt '}' + +in_from_stmt ::= in_from_stmt basic_stmt ';' +| in_from_stmt if_stmt +| empty + +mode_stmt ::= MODE int_const_expr + +message_stmt ::= message_type STRING_LITERAL + +message_type ::= INFO +| WARNING +| ERROR + +keystore_stmt ::= KEYSTORE_TO_NV mem_opt address_or_range +| KEYSTORE_FROM_NV mem_opt address_or_range + +mem_opt ::= IDENT +| '@' int_const_expr +| empty + +if_stmt ::= IF bool_expr '{' statement '}' else_stmt + +else_stmt ::= ELSE '(' statement ')' +| ELSE if_stmt +| empty + +keywrap_block ::= KEYWRAP '(' int_const_expr ')' '{' LOAD BINARY_BLOB GT int_const_expr SEMICOLON '}' + +encrypt_block ::= ENCRYPT '(' int_const_expr ')' '{' load_stmt '}' + +enable_stmt ::= ENABLE AT_INT_LITERAL int_const_expr + +reset_stmt ::= RESET + +ver_check_stmt ::= VERSION_CHECK sec_or_nsec int_const_expr + +sec_or_nsec ::= SEC +| NSEC + +const_expr ::= STRING_LITERAL +| bool_expr + +int_const_expr ::= expr + +bool_expr ::= bool_expr '<' bool_expr +| bool_expr '<=' bool_expr +| bool_expr '>' bool_expr +| bool_expr '>=' bool_expr +| bool_expr '==' bool_expr +| bool_expr '!=' bool_expr +| bool_expr '&&' bool_expr +| bool_expr '||' bool_expr +| '(' bool_expr ')' +| int_const_expr +| '!' bool_expr +| DEFINED '(' IDENT ')' +| IDENT '(' source_name ')' + +expr ::= expr '+' expr +| expr '-' expr +| expr '*' expr +| expr '/' expr +| expr '%' expr +| expr '<<' expr +| expr '>>' expr +| expr '&' expr +| expr '|' expr +| expr '^' expr +| expr '.' INT_SIZE +| '(' expr ')' +| INT_LITERAL +| IDENT +| SYMBOL_REF +| unary_expr +| SIZEOF '(' SYMBOL_REF ')' +| SIZEOF '(' IDENT ')' + +unary_expr ::= '+' expr +| '-' expr + +empty ::= diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/INSTALLER b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/INSTALLER new file mode 100644 index 0000000..5c69047 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/INSTALLER @@ -0,0 +1 @@ +uv \ No newline at end of file diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/METADATA b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/METADATA new file mode 100644 index 0000000..f3bb97a --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/METADATA @@ -0,0 +1,266 @@ +Metadata-Version: 2.4 +Name: textual +Version: 8.2.7 +Summary: Modern Text User Interface framework +License: MIT +License-File: LICENSE +Author: Will McGugan +Author-email: will@textualize.io +Requires-Python: >=3.9,<4.0 +Classifier: Development Status :: 5 - Production/Stable +Classifier: Environment :: Console +Classifier: Intended Audience :: Developers +Classifier: License :: OSI Approved :: MIT License +Classifier: Operating System :: MacOS +Classifier: Operating System :: Microsoft :: Windows :: Windows 10 +Classifier: Operating System :: Microsoft :: Windows :: Windows 11 +Classifier: Operating System :: POSIX :: Linux +Classifier: Programming Language :: Python :: 3 +Classifier: Programming Language :: Python :: 3.9 +Classifier: Programming Language :: Python :: 3.10 +Classifier: Programming Language :: Python :: 3.11 +Classifier: Programming Language :: Python :: 3.12 +Classifier: Programming Language :: Python :: 3.13 +Classifier: Programming Language :: Python :: 3.14 +Classifier: Typing :: Typed +Provides-Extra: syntax +Requires-Dist: markdown-it-py[linkify] (>=2.1.0) +Requires-Dist: mdit-py-plugins +Requires-Dist: platformdirs (>=3.6.0,<5) +Requires-Dist: pygments (>=2.19.2,<3.0.0) +Requires-Dist: rich (>=14.2.0) +Requires-Dist: tree-sitter (>=0.25.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-bash (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-css (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-go (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-html (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-java (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-javascript (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-json (>=0.24.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-markdown (>=0.3.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-python (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-regex (>=0.24.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-rust (>=0.23.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-sql (>=0.3.11) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-toml (>=0.6.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-xml (>=0.7.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: tree-sitter-yaml (>=0.6.0) ; (python_version >= "3.10") and (extra == "syntax") +Requires-Dist: typing-extensions (>=4.4.0,<5.0.0) +Project-URL: Bug Tracker, https://github.com/Textualize/textual/issues +Project-URL: Documentation, https://textual.textualize.io/ +Project-URL: Homepage, https://github.com/Textualize/textual +Project-URL: Repository, https://github.com/Textualize/textual +Description-Content-Type: text/markdown + + + +[![Discord](https://img.shields.io/discord/1026214085173461072)](https://discord.gg/Enf6Z3qhVr) +[![Supported Python Versions](https://img.shields.io/pypi/pyversions/textual)](https://pypi.org/project/textual/) +[![PyPI version](https://badge.fury.io/py/textual.svg?)](https://badge.fury.io/py/textual) +![OS support](https://img.shields.io/badge/OS-macOS%20Linux%20Windows-red) + + + +![textual-splash](https://github.com/user-attachments/assets/4caeb77e-48c0-4cf7-b14d-c53ded855ffd) + +# Textual + +clock + +Build cross-platform user interfaces with a simple Python API. Run your apps in the terminal *or* a web browser. + +Textual's API combines modern Python with the best of developments from the web world, for a lean app development experience. +De-coupled components and an advanced [testing](https://textual.textualize.io/guide/testing/) framework ensure you can maintain your app for the long-term. + +Want some more examples? See the [examples](https://github.com/Textualize/textual/tree/main/examples) directory. + +```python +""" +An App to show the current time. +""" + +from datetime import datetime + +from textual.app import App, ComposeResult +from textual.widgets import Digits + + +class ClockApp(App): + CSS = """ + Screen { align: center middle; } + Digits { width: auto; } + """ + + def compose(self) -> ComposeResult: + yield Digits("") + + def on_ready(self) -> None: + self.update_clock() + self.set_interval(1, self.update_clock) + + def update_clock(self) -> None: + clock = datetime.now().time() + self.query_one(Digits).update(f"{clock:%T}") + + +if __name__ == "__main__": + app = ClockApp() + app.run() +``` + +> [!TIP] +> Textual is an asynchronous framework under the hood. Which means you can integrate your apps with async libraries — if you want to. +> If you don't want or need to use async, Textual won't force it on you. + + + + + +## Widgets + +Textual's library of [widgets](https://textual.textualize.io/widget_gallery/) covers everything from buttons, tree controls, data tables, inputs, text areas, and more… +Combined with a flexible [layout](https://textual.textualize.io/how-to/design-a-layout/) system, you can realize any User Interface you need. + +Predefined themes ensure your apps will look good out of the box. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + + ![buttons](https://github.com/user-attachments/assets/2ac26387-aaa3-41ed-bc00-7d488600343c) + + + +![tree](https://github.com/user-attachments/assets/61ccd6e9-97ea-4918-8eda-3ee0f0d3770e) + +
    + + ![datatables](https://github.com/user-attachments/assets/3e1f9f7a-f965-4901-a114-3c188bd17695) + + + +![inputs](https://github.com/user-attachments/assets/b02aa203-7c37-42da-a1bb-2cb244b7d0d3) + +
    + +![listview](https://github.com/user-attachments/assets/963603bc-aa07-4688-bd24-379962ece871) + + + +![textarea](https://github.com/user-attachments/assets/cd4ba787-5519-40e2-8d86-8224e1b7e506) + +
    + + + + +## Installing + +Install Textual via pip: + +``` +pip install textual textual-dev +``` + +See [getting started](https://textual.textualize.io/getting_started/) for details. + + + + +## Demo + + +Run the following command to see a little of what Textual can do: + +``` +python -m textual +``` + +Or try the [textual demo](https://github.com/textualize/textual-demo) *without* installing (requires [uv](https://docs.astral.sh/uv/)): + +```bash +uvx --python 3.12 textual-demo +``` + + + +## Dev Console + +devtools + + +How do you debug an app in the terminal that is also running in the terminal? + +The `textual-dev` package supplies a dev console that connects to your application from another terminal. +In addition to system messages and events, your logged messages and print statements will appear in the dev console. + +See [the guide](https://textual.textualize.io/guide/devtools/) for other helpful tools provided by the `textual-dev` package. + + + +## Command Palette + + +Textual apps have a *fuzzy search* command palette. +Hit `ctrl+p` to open the command palette. + +It is easy to extend the command palette with [custom commands](https://textual.textualize.io/guide/command_palette/) for your application. + + +![Command Palette](https://github.com/user-attachments/assets/94d8ec5d-b668-4033-a5cb-bf820e1b8d60) + + + +# Textual ❤️ Web + +textual-serve + + +Textual apps are equally at home in the browser as they are the terminal. Any Textual app may be served with `textual serve` — so you can share your creations on the web. +Here's how to serve the demo app: + +``` +textual serve "python -m textual" +``` + +In addition to serving your apps locally, you can serve apps with [Textual Web](https://github.com/Textualize/textual-web). + +Textual Web's firewall-busting technology can serve an unlimited number of applications. + +Since Textual apps have low system requirements, you can install them anywhere Python also runs. Turning any device into a connected device. +No desktop required! + + + + + +## Join us on Discord + +Join the Textual developers and community on our [Discord Server](https://discord.gg/Enf6Z3qhVr). + diff --git a/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/RECORD b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/RECORD new file mode 100644 index 0000000..70ddeb2 --- /dev/null +++ b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/RECORD @@ -0,0 +1,270 @@ +textual-8.2.7.dist-info/INSTALLER,sha256=5hhM4Q4mYTT9z6QB6PGpUAW81PGNFrYrdXMj4oM_6ak,2 +textual-8.2.7.dist-info/METADATA,sha256=r1Da-UtMgQhjGBX_b4tBj4KSnSOZREXxlNmTla-Q-04,9077 +textual-8.2.7.dist-info/RECORD,, +textual-8.2.7.dist-info/REQUESTED,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0 +textual-8.2.7.dist-info/WHEEL,sha256=kJCRJT_g0adfAJzTx2GUMmS80rTJIVHRCfG0DQgLq3o,88 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b/tools/production/dist/service-tui-v0.2.0-windows/service_tui/_internal/textual-8.2.7.dist-info/licenses/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Will McGugan + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 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